Fast throughput rate: 1 MSPS
Specified for V
Low power at max throughput rate
4 mW max at 1 MSPS with 3 V supplies
9.25 mW max at 1 MSPS with 5 V supplies
Fully differential analog input
Wide input bandwidth
70 dB SINAD at 100 kHz input frequency
Flexible power/serial clock speed management
No pipeline delays
High speed serial interface
SPI®/QSPI™/MICROWIRE™/DSP compatible
Power-down mode: 1 μA max
8-lead SOT-23 and MSOP packages
APPLICATIONS
Transducer interface
Battery-powered systems
Data acquisition systems
Portable instrumentation
Motor control
GENERAL DESCRIPTION
The AD7440/AD7450A1 are 10-bit and 12-bit high speed, low
power, successive approximation (SAR) analog-to-digital
converters with a fully differential analog input. These parts
operate from a single 3 V or 5 V power supply and use
advanced design techniques to achieve very low power
dissipation at throughput rates up to 1 MSPS. The SAR
architecture of these parts ensures that there are no pipeline
delays.
The parts contain a low noise, wide bandwidth, differential
t
rack-and-hold amplifier (T/H) that can handle input
frequencies up to 3.5 MHz. The reference voltage is applied
externally to the V
3.5 V depending on the power supply and what suits the
application. The value of the reference voltage determines the
common-mode voltage range of the part. With this truly
differential input structure and variable reference input, the
user can select a variety of input ranges and bias points.
The conversion process and data acquisition are controlled
CS
usin
g
and the serial clock, allowing the device to interface
with microprocessors or DSPs. The input signals are sampled
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
of 3 V and 5 V
DD
pin and can be varied from 100 mV to
REF
AD7440/AD7450A
FUNCTIONAL BLOCK DIAGRAM
V
DD
V
IN+
V
IN–
V
REF
AD7440/AD7450A
T/H
GND
on the falling edge of CS; the conversion is also initiated at this
point. The SAR architecture of these parts ensures that there are
no pipeline delays. The AD7440 and the AD7450A use advanced design techniques to achieve very low power dissipation
at high throughput rates.
PRODUCT HIGHLIGHTS
1. Operation with either 3 V or 5 V power supplies.
2. H
igh throughput with low power consumption.
With a 3 V supply, the AD7440/AD7450A offer 4 mW
max power consumption for 1 MSPS throughput.
ble power/serial clock speed management.
The conversion rate is determined by the serial clock,
allowing the power to be reduced as the conversion time
is reduced through the serial clock speed increase. These
parts also feature a shutdown mode to maximize power
efficiency at lower throughput rates.
hanges to General Description .......................................................1
C
Changes to Table 1 footnotes .............................................................3
Changes to Table 2 footnotes .............................................................5
Changes to Table 3 footnotes .............................................................7
Rev. C | Page 2 of 28
Page 3
AD7440/AD7450A
www.BDTIC.com/ADI
AD7440–SPECIFICATIONS
Table 1. VDD = 2.7 V to 3.6 V, f
V
= 2.5 V; V
REF
CM
1
= V
; TA = T
REF
Parameter Test Conditions/Comments B Version Unit
DYNAMIC PERFORMANCE fIN = 100 kHz
Signal-to-(Noise + Distortion) (SINAD)
Total Harmonic Distortion (THD)2 –82 dB typ –74 dB max
Peak Harmonic or Spurious Noise
Intermodulation Distortion (IMD)2 fa = 90 kHz, fb = 110 kHz
Second-Order Terms –83 dB typ
Third-Order Terms –83 dB typ
Aperture Delay
Aperture Jitter
2
2
Full Power Bandwidth2, 3 @ –3 dB 20 MHz typ
@ –0.1 dB 2.5 MHz typ
DC ACCURACY
Resolution 10 Bits
Integral Nonlinearity (INL)2 ±0.5 LSB max
Differential Nonlinearity (DNL)2 Guaranteed no missed codes to 10 bits ±0.5 LSB max
Zero-Code Error
Positive Gain Error
Negative Gain Error
2
2
2
ANALOG INPUT
Full-Scale Input Span 2 × V
Absolute Input Voltage
V
VCM = V
IN+
V
VCM = V
IN–
DC Leakage Current ±1 μA max
Input Capacitance When in track-and-hold 30/10 pF typ
REFERENCE INPUT
V
Input Voltage
REF
DC Leakage Current ± 1 μA max
V
Input Capacitance When in track-and-hold 10/30 pF typ
REF
LOGIC INPUTS
Input High Voltage, V
Input Low Voltage, V
2.4 V min
INH
0.8 V max
INL
Input Current, IIN Typically 10 nA, VIN = 0 V or VDD ±1 μA max
Input Capacitance, CIN 7 10 pF max
LOGIC OUTPUTS
Output High Voltage, VOH VDD = 4.75 V to 5.25 V; I
V
Output Low Voltage, VOL I
Floating-State Leakage Current ±1 μA max
Floating-State Output Capacitance
Output Coding Twos complement
= 18 MHz, fS = 1 MSPS, V
SCLK
MIN
to T
2
, unless otherwise noted. Temperature range for B Version: –40°C to +85°C.
MAX
2
61 dB min
–82 dB typ –76 dB max
5 ns typ
50 ps typ
±2.5 LSB max
±1 LSB max
±1 LSB max
REF
= 4.75 V to 5.25 V (±1% tolerance for
V
DD
specified performance)
= 2.7 V to 3.6 V (±1% tolerance for specified
V
DD
performance)
= 2.7 V to 3.6 V; I
DD
= 200 μA 0.4 V max
SINK
7
10 pF max
= 2.0 V; VDD = 4.75 V to 5.25 V, f
REF
4
V
VCM ± V
REF
VCM ± V
REF
2.5
2.0
= 200 μA 2.8 V min
SOURCE
= 200 μA 2.4 V min
SOURCE
= 18 MHz, fS = 1 MSPS,
SCLK
– V
V
IN+
IN–
/2 V
REF
/2 V
REF
5
V
6
V
Rev. C | Page 3 of 28
Page 4
AD7440/AD7450A
www.BDTIC.com/ADI
Parameter Test Conditions/Comments B Version Unit
CONVERSION RATE
Conversion Time 888 ns with an 18 MHz SCLK 16 SCLK cycles
Track-and-Hold Acquisition Time
Step input 290 ns max
Throughput Rate 1 MSPS max
POWER REQUIREMENTS
VDD Range: 3 V + 20%/–10%; 5 V ± 5% 2.7/5.25 V min/V max
8
I
DD
Normal Mode (Static) SCLK on or off 0.5 mA typ
Normal Mode (Operational) VDD = 4.75 V to 5.25 V 1.95 mA max
V
Full Power-Down Mode SCLK on or off 1 μA max
Power Dissipation
Normal Mode (Operational) VDD = 5 V, 1.55 mW typ for 100 kSPS
V
Full Power-Down Mode VDD = 5 V, SCLK on or off 5 μW max
V
1
Common-mode voltage. The input signal can be centered on a dc common-mode voltage in the range specified in Figure 28 and Figure 29.
2
See the Terminology section.
3
Analog inputs with slew rates exceeding 27 V/μs (full-scale input sine wave > 3.5 MHz) within the acquisition time can cause the converter to return an
incorrect result.
4
Because the input spans of V
5
The AD7440 is functional with a reference input from 100 mV and for VDD = 5 V; the reference can range up to 3.5 V.
6
The AD7440 is functional with a reference input from 100 mV and for VDD = 3 V; the reference can range up to 2.2 V.
7
Guaranteed by characterization.
8
Measured with a midscale dc input.
9
See the Power vs. Throughput section.
IN+
and V
2
are both V
IN–
Sine wave input 200 ns max
= 2.7 V to 3.6 V 1.45 mA max
DD
9
= 3 V, 0.6 mW typ for 100 kSPS
DD
= 3 V, SCLK on or off 3 μW max
DD
and are 180° out of phase, the differential voltage is 2 × V
REF
9
9.25 mW max
4 mW max
.
REF
Rev. C | Page 4 of 28
Page 5
AD7440/AD7450A
www.BDTIC.com/ADI
AD7450A–SPECIFICATIONS
Table 2. VDD = 2.7 V to 3.6 V, f
V
= 2.5 V; V
REF
1
= V
CM
; T = T to T, unless otherwise noted. Temperature range for B Version: –40°C to +85°C.
REFAMINMAX
Parameter Test Conditions/Comments B Version Unit
DYNAMIC PERFORMANCE fIN = 100 kHz
Signal-to-(Noise + Distortion) (SINAD)
Total Harmonic Distortion (THD)2 VDD = 4.75 V to 5.25 V, –86 dB typ –76 dB max
V
Peak Harmonic or Spurious Noise
V
Intermodulation Distortion (IMD)2 fa = 90 kHz, fb = 110 kHz
Second-Order Terms –89 dB typ
Third-Order Terms –89 dB typ
Aperture Delay
Aperture Jitter
Full Power Bandwidth
2
2
2, 3
@ –3 dB 20 MHz typ
@ –0.1 dB 2.5 MHz typ
DC ACCURACY
Resolution 12 Bits
Integral Nonlinearity (INL)2 ±1 LSB max
Differential Nonlinearity (DNL)2 Guaranteed no missed codes to 12 bits ±0.95 LSB max
Zero-Code Error
Positive Gain Error
Negative Gain Error
2
2
2
ANALOG INPUT
Full-Scale Input Span 2 × V
Absolute Input Voltage
V
VCM = V
IN+
V
VCM = V
IN–
DC Leakage Current ±1 μA max
Input Capacitance When in track-and-hold 30/10 pF typ
REFERENCE INPUT
V
Input Voltage
REF
DC Leakage Current ±1 μA max
V
Input Capacitance When in track-and-hold 10/30 pF typ
REF
LOGIC INPUTS
Input High Voltage, V
Input Low Voltage, V
2.4 V min
INH
0.8 V max
INL
Input Current, IIN Typically 10 nA, VIN = 0 V or VDD ±1 μA max
Input Capacitance, C
7
10 pF max
IN
LOGIC OUTPUTS
Output High Voltage, VOH V
V
Output Low Voltage, V
OL
Floating-State Leakage Current ±1 μA max
Floating-State Output Capacitance
Output Coding Twos complement
= 18 MHz, fS = 1 MSPS, V
SCLK
2
2
70 dB min
= 2.7 V to 3.6 V, –84 dB typ –74 dB max
DD
VDD = 4.75 V to 5.25 V, –86 dB typ –76 dB max
= 2.7 V to 3.6 V, –84 dB typ –74 dB max
DD
5 ns typ
50 ps typ
±6 LSB max
±2 LSB max
±2 LSB max
= 4.75 V to 5.25 V
V
DD
(±1% tolerance for specified performance)
= 2.7 V to 3.6 V
V
DD
(±1% tolerance for specified performance)
= 4.75 V to 5.25 V; I
DD
= 2.7 V to 3.6 V; I
DD
I
= 200 μA 0.4 V max
SINK
7
10 pF max
= 2.0 V; VDD = 4.75 V to 5.25 V, f
REF
4 V
REF
VCM ± V
REF
VCM ± V
REF
= 200 μA 2.8 V min
SOURCE
= 200 μA 2.4 V min
SOURCE
= 18 MHz, fS = 1 MSPS,
SCLK
– V
V
IN+
IN–
/2 V
REF
/2 V
REF
5
2.5
6
2.0
V
V
Rev. C | Page 5 of 28
Page 6
AD7440/AD7450A
www.BDTIC.com/ADI
Parameter Test Conditions/Comments B Version Unit
CONVERSION RATE
Conversion Time 888 ns with an 18 MHz SCLK 16 SCLK cycles
Track-and-Hold Acquisition Time
Step input 290 ns max
Throughput Rate 1 MSPS max
POWER REQUIREMENTS
VDD Range: 3 V + 20%/–10%; 5 V ± 5% 2.7/5.25 V min/V max
8
I
DD
Normal Mode (Static) SCLK on or off 0.5 mA typ
Normal Mode (Operational) VDD = 4.75 V to 5.25 V 1.95 mA max
V
Full Power-Down Mode SCLK on or off 1 μA max
Power Dissipation
Normal Mode (Operational) VDD = 5 V, 1.55 mW typ for 100 kSPS9 9.25 mW max
V
Full Power-Down VDD = 5 V, SCLK on or off 5 μW max
V
1
Common-mode voltage. The input signal can be centered on a dc common-mode voltage in the range specified in Figure 28 and Figure 29.
2
See the Terminology section.
3
Analog inputs with slew rates exceeding 27 V/μs (full-scale input sine wave > 3.5 MHz) within the acquisition time can cause the converter to return an
incorrect result.
4
Because the input spans of V
5
The AD7450A is functional with a reference input from 100 mV and for VDD = 5 V; the reference can range up to 3.5 V.
6
The AD7450A is functional with a reference input from 100 mV and for VDD = 3 V; the reference can range up to 2.2 V.
7
Guaranteed by characterization.
8
Measured with a midscale dc input.
9
See the Power vs. Throughput section.
IN+
and V
2
are both V
IN–
Sine wave input 200 ns max
= 2.7 V to 3.6 V 1.45 mA max
DD
= 3 V, 0.6 mW typ for 100 kSPS
DD
= 3 V, SCLK on or off 3 μW max
DD
and are 180° out of phase, the differential voltage is 2 × V
REF
9
4 mW max
.
REF
Rev. C | Page 6 of 28
Page 7
AD7440/AD7450A
S
A
S
A
www.BDTIC.com/ADI
TIMING SPECIFICATIONS
Guaranteed by characterization. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of
1.6 V. See Figure 2, Figure 3, and the Serial Interface section.
Table 3. V
V
= 2.5 V; V
REF
Parameter Limit at T
2
f
10 kHz min
SCLK
18 MHz max
t
CONVER T
888 ns max
t
60 ns min
QUIET
t1 10 ns min
t2 10 ns min
3
t
20 ns max
3
3
t
4
t
5
t
6
t
7
4
t
10 ns min SCLK falling edge to SDATA three-state enabled
8
35 ns max SCLK falling edge to SDATA three-state enabled
t
POWER-UP
1
Common-mode voltage.
2
Mark/space ratio for the SCLK input is 40/60 to 60/40.
3
Measured with the load circuit of Figure 4 and defined as the time required for the output to cross 0.8 V or 2.4 V with VDD = 5 V or 0.4 V or 2.0 V for VDD = 3 V.
4
t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 4. The measured number is then extrapolated
back to remove the effects of charging or discharging the 25 pF capacitor. This means that the time, t8, quoted in the Timing Specifications is the true bus relinquish
time of the part and is independent of the bus loading.
5
See Power-Up Time section.
= 2.7 V to 3.6 V, f
DD
1
= V
CM
16 × t
40 ns max Data access time after SCLK falling edge
0.4 t
0.4 t
10 ns min SCLK edge to data valid hold time
5
1 μs max Power-up time from full power-down
= 18 MHz, fS = 1 MSPS, V
SCLK
; TA = T
REF
, T
MIN
t
SCLK
to T
MIN
Unit Description
MAX
, unless otherwise noted.
MAX
SCLK
= 2.0 V; VDD = 4.75 V to 5.25 V, f
REF
= 1/f
SCLK
Minimum quiet time between the end of a serial read and the next falling edge of
CS
Minimum
CS
falling edge to SCLK falling edge setup time
Delay from
ns min SCLK high pulse width
SCLK
ns min SCLK low pulse width
SCLK
pulse width
CS
falling edge until SDATA three-state disabled
= 18 MHz, fS = 1 MSPS,
SCLK
CS
CS
SCLK
DAT
CS
SCLK
DAT
t
t
2
1234513141516
t
3
0000DB11DB10DB2DB1DB0
4 LEADING ZEROSTHREE-STATE
t
4
CONVERT
t
5
t
7
B
Figure 2. AD7450A Serial Interface Timing Diagram
t
t
2
1234513141516
t
3
0000DB9DB8DB000
4 LEADING ZEROS2 TRAILING ZEROS
t
4
CONVERT
t
5
t
7
B
Figure 3. AD7440 Serial Interface Timing Diagram
Rev. C | Page 7 of 28
t
1
t
6
t
8
t
QUIET
03051-A-002
t
1
t
6
t
8
t
QUIET
THREE-STATE
03051-A-003
Page 8
AD7440/AD7450A
www.BDTIC.com/ADI
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 4.
Parameter Rating
VDD to GND –0.3 V to +7 V
V
to GND –0.3 V to VDD + 0.3 V
IN+
V
to GND –0.3 V to VDD + 0.3 V
IN–
Digital Input Voltage to GND –0.3 V to +7 V
Digital Output Voltage to GND –0.3 V to VDD + 0.3 V
V
to GND –0.3 V to VDD + 0.3 V
REF
Input Current to Any Pin Except Supplies1±10 mA
Operating Temperature Range
Commercial (B Version) –40°C to +85°C
Storage Temperature Range –65°C to +150°C
Junction Temperature 150°C
θJA Thermal Impedance
MSOP 205.9°C/W
SOT-23 211.5°C/W
θJC Thermal Impedance
MSOP 43.74°C/W
SOT-23 91.99°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) 215°C
Infrared (15 sec) 220°C
ESD 1 kV
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
1
Transient currents of up to 100 mA do not cause SCR latch up.
Figure 4. Load Circuit for Digital Output Timing Specifications
TO OUTPUT
PIN
25pF
C
L
1.6mAI
200μAI
OL
OH
1.6V
03051-A-004
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. C | Page 8 of 28
Page 9
AD7440/AD7450A
V
www.BDTIC.com/ADI
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
V
DD
SCLK
SDATA
CS
1
AD7440/
2
AD7450A
3
TOP VIEW
(Not to Scale)
4
V
8
REF
7
V
IN+
6
V
IN–
5
GND
03051-A-005
Figure 5. Pin Configuration for 8-Lead SOT-23
Table 5. Pin Function Descriptions
Mnemonic Function
V
REF
Reference Input for the AD7440/AD7450A. An external reference must be applied to this input. For a 5 V power supply, the
eference is 2.5 V (±1%) for specified performance. For a 3 V power supply, the reference is 2 V (±1%) for specified
r
performance. This pin should be decoupled to GND with a capacitor of at least 0.1 μF. See the Reference section for more
details.
V
Positive Terminal for Differential Analog Input.
IN+
V
Negative Terminal for Differential Analog Input.
IN–
GND
CS
Analog Ground. Ground reference point for all circuitry on the AD7440/AD7450A. All analog input signals and any external
eference signal should be referred to this GND voltage.
r
Chip Select. Active low logic input. This input provides the dual func
and framing the serial data transfer.
SDATA
Serial Data. Logic output. The conversion result from the AD7440/AD7450A is pr
The bits are clocked out on the falling edge of the SCLK input. The data stream of the AD7450A consists of four leading zeros
followed by the 12 bits of conversion data, which are provided MSB first; the data stream of the AD7440 consists of four
leading zeros, followed by the 10 bits of conversion data, followed by two trailing zeros. In both cases, the output coding is
twos complement.
SCLK
Serial Clock. Logic input. SCLK provides the serial clock for ac
clock source for the conversion process.
VDD
Power Supply Input. V
is 3 V (+20%/–10%) or 5 V (±5%). This supply should be decoupled to GND with a 0.1 μF capacitor and
DD
a 10 μF tantalum capacitor in parallel.
1
REF
AD7440/
2
V
IN+
AD7450A
3
V
IN–
TOP VIEW
(Not to Scale)
GND
4
Figure 6. Pin Configuration for 8-Lead MSOP
8
7
6
5
V
DD
SCLK
SDATA
CS
03051-A-006
tion of initiating a conversion on the AD7440/AD7450A
ovided on this output as a serial data stream.
cessing data from the part. This clock input is also used as the
Rev. C | Page 9 of 28
Page 10
AD7440/AD7450A
V
www.BDTIC.com/ADI
TERMINOLOGY
Signal-to-(Noise + Distortion) Ratio
This is the measured ratio of signal to (noise + distortion) at the
output of the ADC. The signal is the rms amplitude of the
fundamental. Noise is the sum of all nonfundamental signals
up to half the sampling frequency (f
ratio is dependent on the number of quantization levels in the
digitization process; the more levels, the smaller the quantization noise. The theoretical signal-to-(noise + distortion) ratio
for an ideal N-bit converter with a sine wave input is given by
the following:
Signal-to-(Noise + Distortion) = (6.02
Thus for a 12-bit converter, this is 74 dB; and for a 10-bit
co
nverter, this is 62 dB.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of harmonics to the
fundamental. For the AD7440/AD7450A, it is defined as
THD
where V
V
, V5, and V6 are the rms amplitudes of the second to the sixth
4
=
is the rms amplitude of the fundamental and V2, V3,
1
2
log20)dB(
harmonics.
Peak Harmonic or Spurious Noise
Peak harmonic (spurious noise) is the ratio of the rms value of
the next largest component in the ADC output spectrum (up to
f
/2 and excluding dc) to the rms value of the fundamental.
S
Normally, the value of this specification is determined by the
largest harmonic in the spectrum, but for ADCs where the
harmonics are buried in the noise floor, it is a noise peak.
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies,
fa and fb, any active device with nonlinearities creates distortion
products at the sum and difference frequencies of mfa ± nfb where
m, n = 0, 1, 2, 3, and so on. Intermodulation distortion terms are
those for which neither m nor n is equal to 0. For example, the
second-order terms include (fa + fb) and (fa – fb), while the thirdorder terms include (2fa + fb), (2fa – fb),
(fa + 2fb), and (fa – 2fb).
The AD7440/AD7450A is tested using the CCIF standard of two
i
nput frequencies near the top end of the input bandwidth. In this
case, the second-order terms are distanced in frequency from the
original sine waves, while the third-order terms are at a frequency
close to the input frequencies. As a result, the second- and thirdorder terms are specified separately. The calculation of the
intermodulation distortion is as per the THD specification, where it
is the ratio of the rms sum of the individual distortion products to
the rms amplitude of the sum of the fundamentals, expressed in dB.
/2), excluding dc. The
S
2
2
2
4
3
1
N + 1.76)dB.
2
2
6
5
VVVVV
++++
Aperture Delay
This is the amount of time from the leading edge of the
sampling clock until the ADC actually takes the sample.
Aperture Jitter
This is the sample-to-sample variation in the effective point in
time at which the actual sample is taken.
Full Power Bandwidth
The full power bandwidth of an ADC is the input frequency at
which the amplitude of the reconstructed fundamental is
reduced by 0.1 dB or 3 dB for a full-scale input.
Common-Mode Rejection Ratio (CMRR)
The common-mode rejection ratio is the ratio of the power
in the ADC output at full-scale frequency, f, to the power of a
100 mV p-p sine wave applied to the common-mode voltage of
V
and V
IN+
CMRR (dB) = 10 log (Pf/P
Pf is t
power at frequency f
of frequency fS as follows:
IN–
fs)
he power at the frequency f in the ADC output; Pfs is the
in the ADC output.
S
Integral Nonlinearity (INL)
This is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function.
Differential Nonlinearity (DNL)
This is the difference between the measured and the ideal
1 LSB change between any two adjacent codes in the ADC.
Zero-Code Error
This is the deviation of the midscale code transition
(111...111 to 000...000) from the ideal V
IN+
− V
(i.e., 0 LSB).
IN–
Positive Gain Error
This is the deviation of the last code transition (011...110 to
011...111) from the ideal V
IN+
(i.e., +V
IN–
− 1 LSB), after
REF
– V
the zero code error has been adjusted out.
Negative Gain Error
This is the deviation of the first code transition (100...000 to
100...001) from the ideal VIN+ − VIN– (i.e., –VREF + 1 LSB),
after the zero code error has been adjusted out.
Track- a n d-Hold Acqui s i t ion Time
The track-and-hold acquisition time is the minimum time
required for the track-and-hold amplifier to remain in track
mode for its output to reach and settle to within 0.5 LSB of the
applied input signal.
Rev. C | Page 10 of 28
Page 11
AD7440/AD7450A
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Power Supply Rejection Ratio (PSRR)
The power supply rejection ratio is the ratio of the power in
the ADC output at full-scale frequency, f, to the power of a
100 mV p-p sine wave applied to the ADC V
frequency f
1 MHz.
. The frequency of this input varies from 1 kHz to
S
supply of
DD
PSRR (dB) = 10
e power at frequency f in the ADC output; Pfs is the
Figure 7. AD7450A SINAD vs. Analog Input Frequency for Various
Supply Voltages
0
–10
–20
–30
–40
–50
–60
CMRR (dB)
–70
–80
–90
–100
10100010010000
Figure 8. CMRR vs. Frequency for V
0
100mV p-p SINEWAVE ON V
NO DECOUPLING ON V
–20
–40
–60
PSRR (dB)
–80
–100
–120
0100 200 300 400 500 600 700 800 900 1000
SUPPLY RIPPLE FREQUENCY (kHz)
VDD = 3V
FREQUENCY (kHz)
DD
DD
VDD = 3V
= 5V
V
DD
= 5V
V
DD
= 5 V and 3 V
DD
03051-A-008
03051-A-009
Figure 9. PSRR vs. Supply Ripple Frequency without Supply Decoupling
–140
0100200300400500
Figure 10. AD7450A Dynamic Performance with V
FREQUENCY (kHz)
DD
03051-A-010
= 5 V
1.0
0.8
0.6
0.4
0.2
0
–0.2
DNL ERROR (LSB)
–0.4
–0.6
–0.8
–1.0
01024204830724096
Figure 11. Typical DNL for the AD7450A for V
1.0
0.8
0.6
0.4
0.2
0
–0.2
INL ERROR (LSB)
–0.4
–0.6
–0.8
–1.0
01024204830724096
Figure 12. Typical INL for the AD7450A for V
CODE
CODE
DD
DD
= 5 V
= 5 V
03051-A-011
03051-A-012
Rev. C | Page 12 of 28
Page 13
AD7440/AD7450A
www.BDTIC.com/ADI
3.0
2.5
2.0
1.5
1.0
0.5
CHANGE IN DNL (LSB)
0
–0.5
–1.0
00.51.01.52.02.53.03.5
Figure 13. Change in DNL vs. V
POSITIVE DNL
NEGATIVE DNL
V
(V)
REF
for the AD7450A for VDD = 5 V
REF
03051-A-013
2.5
2.0
1.5
1.0
0.5
0
–0.5
CHANGE IN INL (LSB)
–1.0
–1.5
–2.0
00.51.01.52.0 2.22.5
Figure 16. Change in INL vs. V
POSITIVE INL
NEGATIVE INL
V
(V)
REF
for the AD7450A for VDD = 3 V
REF
03051-A-016
2.5
2.0
1.5
1.0
0.5
0
CHANGE IN DNL (LSB)
–0.5
–1.0
00.51.01.52.0 2.22.5
Figure 14. Change in DNL vs. V
5
4
3
2
1
0
–1
–2
CHANGE IN INL (LSB)
–3
–4
–5
00.51.01.52.52.03.03.5
Figure 15. Change in INL vs. V
POSITIVE DNL
NEGATIVE DNL
V
(V)
REF
for the AD7450A for VDD = 3 V
REF
POSITIVE INL
NEGATIVE INL
V
(V)
REF
for the AD7450A for VDD = 5 V
REF
8
7
6
VDD = 5V
5
4
3
= 3V
V
2
ZERO-CODE ERROR (LSB)
03051-A-014
DD
1
0
00.51.01.52.02.53.03.5
V
(V)
REF
03051-A-017
Figure 17. Change in Zero-Code Error vs. Reference Voltage for
V
= 5 V and 3 V for the AD7450A
DD
12.0
11.5
V
= 3V
DD
11.0
10.5
10.0
9.5
9.0
8.5
EFFECTIVE NUMBER OF BITS
8.0
7.5
03051-A-015
7.0
00.51.01.52.02.53.03.5
Figure 18. Change in ENOB vs. Reference Voltage for V
VDD = 5V
03051-A-018
V
(V)
REF
= 5 V and 3 V
DD
for the AD7450A
Rev. C | Page 13 of 28
Page 14
AD7440/AD7450A
www.BDTIC.com/ADI
10,000
V
= V
IN+
IN–
10,000 CONVERSIONS
9,000
f
= 1MSPS
S
8,000
7,000
6,000
5,000
4,000
3,000
2,000
1,000
0
204420452046204720482049
Figure 19. Histogram of 10,000 Conversions of a DC Input for the
AD7450A with V
0
–20
–40
–60
–80
SNR (dB)
–100
–120
–140
0100200300400500
Figure 20. AD7440 Dynamic Performance with V
10,000
CODES
CODE
= 5 V
DD
FREQUENCY (kHz)
8192 POINT FFT
f
SAMPLE
f
= 100kHz
IN
SINAD = +61.6dB
THD = –81.7dB
SFDR = –83.1dB
= 1MSPS
= 5 V
DD
0.5
0.4
0.3
0.2
0.1
0
–0.1
DNL ERROR (LSB)
–0.2
–0.3
–0.4
03051-A-019
–0.5
02565127681024
CODE
03051-A-021
Figure 21. Typical DNL for the AD7440 for VDD = 5 V
0.5
0.4
0.3
0.2
0.1
0
–0.1
INL ERROR (LSB)
–0.2
–0.3
–0.4
03051-A-020
–0.5
02565127681024
CODE
03051-A-022
Figure 22. Typical INL for the AD7440 for VDD = 5 V
Rev. C | Page 14 of 28
Page 15
AD7440/AD7450A
V
V
V
V
www.BDTIC.com/ADI
CIRCUIT INFORMATION
The AD7440/AD7450A are 10-bit and 12-bit fast, low power,
single-supply, successive approximation analog-to-digital
converters (ADCs). They can operate with a 5 V or 3 V power
supply and are capable of throughput rates up to 1 MSPS when
supplied with an 18 MHz SCLK. They require an external
reference to be applied to the V
pin, with the value of the
REF
reference chosen depending on the power supply and what suits
the application.
When they are operated with a 5 V supply, the maximum
eference that can be applied is 3.5 V. When they are operated
r
with a 3 V supply, the maximum reference that can be applied is
2.2 V (see the Reference section).
The AD7440/AD7450A have an on-chip differential track-and-
old amplifier, a successive approximation (SAR) ADC, and a
h
serial interface housed in either an 8-lead SOT-23 or an MSOP
package. The serial clock input accesses data from the part and
provides the clock source for the successive approximation
ADC. The AD7440/AD7450A feature a power-down option for
reduced power consumption between conversions. The powerdown feature is implemented across the standard serial interface
as described in the
Modes of Operation section.
CONVERTER OPERATION
The AD7440/AD7450A are successive approximation ADCs
based around two capacitive DACs. Figure 23 and Figure 24
w simplified schematics of the ADC in acquisition and
sho
conversion phase, respectively. The ADC is comprised of
control logic, an SAR, and two capacitive DACs. In
(acq
uisition phase), SW3 is closed, SW1 and SW2 are in
Position A, the comparator is held in a balanced condition,
and the sampling capacitor arrays acquire the differential
signal on the input.
B
IN+
A
A
IN–
B
C
S
SW1
SW2
C
S
V
REF
SW3
COMPARATOR
Figure 23. ADC Acquisition Phase
Figure 23
CAPACITIVE
DAC
CONTROL
LOGIC
CAPACITIVE
DAC
03051-A-023
When the ADC starts a conversion (Figure 24), SW3 opens and
SW1 and SW2 move to Position B, causing the comparator to
become unbalanced. Both inputs are disconnected once the
conversion begins. The control logic and the charge redistribution DACs are used to add and subtract fixed amounts of
charge from the sampling capacitor arrays to bring the comparator back into a balanced condition. When the comparator is
rebalanced, the conversion is complete. The control logic
generates the ADC’s output code. The output impedances of the
sources driving the V
and the V
IN+
pins must be matched;
IN–
otherwise, the two inputs have different settling times, resulting
in errors.
CAPACITIVE
DAC
B
IN+
A
A
IN–
B
C
S
SW1
SW2
C
S
V
REF
SW3
COMPARATOR
CONTROL
LOGIC
CAPACITIVE
DAC
03051-A-024
Figure 24. ADC Conversion Phase
ADC TRANSFER FUNCTION
The output coding for the AD7440/AD7450A is twos
complement. The designed code transitions occur at successive
LSB values (1 LSB, 2 LSBs, and so on). The LSB size of the
AD7450A is 2 × V
2 × V
/1024. The ideal transfer characteristic of the
REF
AD7440/AD7450A is shown in Figure 25.
011...111
011...110
000...001
000...000
111...111
ADC CODE
100...010
100...001
100...000
Figure 25. AD7440/AD7450A Ideal Transfer Characteristic
/4096, and the LSB size of the AD7440 is
REF
–V
REF
1LSB = 2×V
1LSB = 2
1 LSB
/4096 AD7450A
REF
×
V
/1024 AD7440
REF
0 LSB
ANALOG INPUT
(V
+V
– V
)
IN+
IN–
REF
– 1 LSB
03051-A-025
Rev. C | Page 15 of 28
Page 16
AD7440/AD7450A
www.BDTIC.com/ADI
TYPICAL CONNECTION DIAGRAM
Figure 26 shows a typical connection diagram for the
AD7440/AD7450A for both 5 V and 3 V supplies. In this setup,
the GND pin is connected to the analog ground plane of the
system. The V
decoupled reference source, depending on the power supply, to
set up the analog input range. The common-mode voltage has
to be set up externally and is the value on which the two inputs
are centered. The conversion result is output in a 16-bit word
with four leading zeros followed by the MSB of the 12-bit or
10-bit result. The 10-bit result of the AD7440 is followed by two
trailing zeros. For more details on driving the differential inputs
and setting up the common mode, refer to the Driving
Differential Inputs section.
V
REF
p-p
V
REF
p-p
*CM IS THE COMMON-MODE VOLTAGE.
ANALOG INPUT
The analog input of the AD7440/AD7450A is fully differential.
Differential signals have a number of benefits over singleended signals, including noise immunity based on the device’s
common-mode rejection, improvements in distortion performance, doubling of the device’s available dynamic range, and
flexibility in input ranges and bias points.
f
ully differential analog input of the AD7440/AD7450A.
COMMON-MODE
The amplitude of the differential signal is the difference
between the signals applied to the V
(i.e., V
IN+
two signals each of amplitude V
The amplitude of the differential signal is therefore –V
+V
peak-to-peak (2 × V
REF
common mode (CM).
pin is connected to either a 2.5 V or a 2 V
REF
3V/5V
SUPPLY
μ
F
SCLK
GND
CM*
CM*
0.1
0.1μF
V
DD
V
IN+
V
IN–
V
REF
μ
F
10
AD7440/
AD7450A
2V/2.5V
V
REF
Figure 26. Typical Connection Diagram
Figure 27 defines the
V
REF
p-p
V
REF
p-p
VOLTAGE
Figure 27. Differential Input Definitions
– V
). V
IN–
IN+
and V
are simultaneously driven by
IN–
REF
). This is true regardless of the
REF
V
IN+
V
IN–
and V
IN+
that are 180° out of phase.
SERIAL
INTERFACE
CS
AD7440/
AD7450A
pins
IN–
REF
03051-A-027
μC/μ
to
PSDATA
The common mode is the average of the two signals, that is,
+ V
(V
IN+
)/2 and is therefore the voltage that the two inputs
IN–
are centered on. This results in the span of each input being
CM ± V
range varies with V
/2. This voltage has to be set up externally, and its
REF
. As the value of V
REF
increases, the
REF
common-mode range decreases. When driving the inputs with
an amplifier, the actual common-mode range is determined by
the amplifier’s output voltage swing.
Figure 28 and Figure 29 show how the common-mode range
ically varies with V
typ
for both a 5 V and a 3 V power supply.
REF
The common mode must be in this range to guarantee the
functionality of the AD7440/AD7450A.
For ease of use, the common mode can be set up to equal V
resulting in the differential signal being ±V
centered on V
REF
REF
REF
,
.
When a conversion takes place, the common mode is rejected,
esulting in a virtually noise-free signal of amplitude –V
r
+V
, corresponding to the digital codes of 0 to 4096 in the
REF
REF
to
case of the AD7450A and 0 to 1024 in the AD7440.
4.5
4.0
3.5
3.0
2.5
03051-A-026
2.0
1.5
1.0
COMMON-MODE VOLTAGE (V)
0.5
0
00.51.01.52.02.53.03.5
COMMON-MODE RANGE
V
(V)
REF
Figure 28. Input Common-Mode Range vs. V
(V
= 5 V and V
2.5
2.0
1.5
1.0
COMMON-MODE VOLTAGE (V)
0.5
0
00.250.500.751.001.251.501.752.00
DD
COMMON-MODE RANGE
(Max) = 3.5 V)
REF
V
(V)
REF
Figure 29. Input Common-Mode Range vs. V
= 3 V and V
(V
DD
(Max) =2V)
REF
3.25V
1.75V
03051-A-028
REF
REF
2V
1V
03051-A-029
Rev. C | Page 16 of 28
Page 17
AD7440/AD7450A
www.BDTIC.com/ADI
Figure 30 shows examples of the inputs to V
different values of V
for VDD = 5 V. It also gives the maximum
REF
and minimum common-mode voltages for each reference value
according to
Figure 28.
REFERENCE = 2V
COMMON-MODE (CM)
COMMON-MODE (CM)
CM
CM
CM
CM
MAX
MIN
MIN
MAX
= 1.25V
= 3.75V
= 1V
= 4V
REFERENCE = 2.5V
Figure 30. Examples of the Analog Inputs to V
Different Values of V
for VDD = 5 V
REF
V
V
V
V
Analog Input Structure
Figure 31 shows the equivalent circuit of the analog input
structure of the AD7440/AD7450A. The four diodes provide
ESD protection for the analog inputs. Care must be taken to
ensure that the analog input signals never exceed the supply
rails by more than 300 mV. This causes these diodes to become
forward biased and start conducting into the substrate. These
diodes can conduct up to 10 mA without causing irreversible
damage to the part. The capacitors, C1 in
ty
pically 4 pF and can primarily be attributed to pin
capacitance. The resistors are lumped components made up of
the on resistance of the switches. The value of these resistors is
typically about 100 Ω. The capacitors, C2, are the ADC’s
sampling capacitors and have a capacitance of 16 pF typically.
and V
IN+
IN–
2V p-p
IN+
IN–
2.5V p-p
IN+
IN+
and V
Figure 31, are
IN–
for
For ac applications, removing high frequency components from
e analog input signal through the use of an RC low-pass filter
th
on the relevant analog input pins is recommended. In applications where harmonic distortion and signal-to-noise ratio are
critical, the analog input should be driven from a low impedance source. Large source impedances significantly affect the
ac performance of the ADC. This may necessitate the use of an
input buffer amplifier. The choice of op amp is a function of the
particular application.
When no amplifier is used to drive the analog input, the source
pedance should be limited to low values. The maximum
im
source impedance depends on the amount of total harmonic
03051-A-030
for
IN–
distortion (THD) that can be tolerated. The THD increases as
the source impedance increases, and performance degrades.
Figure 32 shows a graph of THD vs. the analog input signal
requency for different source impedances for V
f
0
TA = 25°C
V
= 5V
DD
–20
–40
THD (dB)
–60
–80
–100
101001000
RIN = 510
RIN = 10
INPUT FREQUENCY (kHz)
Figure 32. THD vs. Analog Input Frequency for Various Source Impedances
Figure 33 shows a graph of the THD vs. the analog input
frequency for V
C2
sampling at 1 MSPS with an SCLK of 18 MHz. In this case, the
of 5 V ± 5% and 3 V + 20%/–10%, while
DD
source impedance is 10 Ω.
–50
TA = 25°C
–55
= 2.7V
V
V
DD
V
= 3.6V
DD
= 4.75V
DD
= 5.25V
V
DD
03051-A-033
C2
03051-A-031
–60
–65
–70
THD (dB)
–75
–80
–85
–90
101001000
INPUT FREQUENCY (kHz)
Figure 33. THD vs. Analog Input Frequency for 3 V and 5 V Supply Voltages
Rev. C | Page 17 of 28
Page 18
AD7440/AD7450A
www.BDTIC.com/ADI
DRIVING DIFFERENTIAL INPUTS
Differential operation requires V
simultaneously with two equal signals that are 180° out of
phase. The common mode must be set up externally and has a
range determined by V
, the power supply, and the particular
REF
amplifier used to drive the analog inputs (see Figure 28 and
Figure 29). Differential modes of operation with either an ac or
dc in
put provide the best THD performance over a wide
frequency range. Because not all applications have a signal
preconditioned for differential operation, there is often a need
to perform single-ended-to-differential conversion.
Differential Amplifier
An ideal method of applying differential drive to the
AD7440/AD7450A is to use a differential amplifier such as the
AD8138. This part can be used as a single-ended-to-differential
amplifier or as a differential-to-differential amplifier. In both
cases, the analog input needs to be bipolar. It also provides
common-mode level shifting and buffering of the bipolar input
signal.
Figure 34 shows how the AD8138 can be used as a
gle-ended-to-differential amplifier. The positive and negative
sin
outputs of the AD8138 are connected to the respective inputs
on the ADC via a pair of series resistors to minimize the effects
IN+
and V
to be driven
IN–
+2.5V
GND
–2.5V
51Ω
R
1
G
V
OCM
R
2
G
RF1
AD8138
R
2
F
of switched capacitance on the front end of the ADCs. The RC
low-pass filter on each analog input is recommended in ac
applications to remove high frequency components of the
analog input. The architecture of the AD8138 results in outputs
that are very highly balanced over a wide frequency range
without requiring tightly matched external components.
If the analog input source being used has zero impedance, all
fo
ur resistors (R
1, RG2, RF1, and RF2) should be the same. If
G
the source has a 50 Ω impedance and a 50 Ω termination, for
example, the value of R
2 should be increased by 25 Ω to
G
balance this parallel impedance on the input and thus ensure
that both the positive and negative analog inputs have the same
gain (see
ma
Figure 34). The outputs of the amplifier are perfectly
tched, balanced differential outputs of identical amplitude
and are exactly 180° out of phase.
The AD8138 is specified with +3 V, +5 V, and ±5 V power
pplies, but the best results are obtained with a ±5 V supply.
su
The AD8132 is a lower cost device that could also be used in
this configuration with slight differences in characteristics to
the AD8138 but with similar performance and operation.
R
*
S
C*
R
*
S
C*
3.75V
2.5V
1.25V
V
IN+
AD7440/
AD7450A
V
IN–
3.75V
2.5V
1.25V
V
REF
*MOUNT AS CLOSE TO THE AD7440/AD7450A AS POSSIBLE
AND ENSURE HIGH PRECISION R
–50Ω; C–1nF
R
S
1 = RF1 = RF2 = 499Ω; RG2 = 523Ω
R
G
Figure 34. Using the AD8138 as a Single-Ended-to-Differential Amplifier
AND CS ARE USED.
S
EXTERNAL
(2.5V)
V
REF
03051-A-034
Rev. C | Page 18 of 28
Page 19
AD7440/AD7450A
V
www.BDTIC.com/ADI
Op Amp Pair
An op amp pair can be used to directly couple a differential
signal to the AD7440/AD7450A. The circuit configurations
shown in Figure 35 and Figure 36 show how a dual op amp can
b
e used to convert a single-ended signal into a differential
signal for both a bipolar and unipolar input signal, respectively.
The voltage applied to Point A sets up the common-mode
vol
tage. In both diagrams, it is connected in some way to the
reference, but any value in the common-mode range can be
input here to set up the common mode. The AD8022 is a
suitable dual op amp that could be used in this configuration
to provide differential drive to the AD7440/AD7450A.
Take care when choosing the op amp; the selection depends on
t
he required power supply and system performance objectives.
The driver circuits in Figure 35 and Figure 36 are optimized for
dc co
upling applications requiring best distortion performance.
The circuit configuration shown in Figure 35 converts a
polar, single-ended signal into a differential signal.
uni
The differential op amp driver circuit in Figure 36 is configured
to
convert and level shift a single-ended, ground-referenced
(bipolar) signal to a differential signal centered at the V
REF
level
of the ADC.
2× V
p-p
REF
REF
GND
Figure 35. Dual Op Amp Circuit to Convert a Single-Ended Unipolar Signal
2× V
p-p
REF
GND
Figure 36. Dual Op Amp Circuit to Convert a Single-Ended Bipolar Signal into
220Ω
390Ω
220Ω
220Ω
A
10kΩ
o a Differential Signal
int
220Ω
390Ω
220Ω
220Ω
220Ω
A
20kΩ
a D
ifferential Signal
V+
V–
V+
V–
V+
V–
V+
V–
10kΩ
27Ω
27Ω
27Ω
27Ω
V
IN+
V
IN–
V
IN+
V
IN–
V
DD
AD7440/
AD7450A
V
EXTERNAL
V
V
DD
AD7440/
AD7450A
V
EXTERNAL
V
REF
0.1μF
REF
REF
0.1μF
REF
03051-A-036
03051-A-035
RF Transformer
An RF transformer with a center tap offers a good solution for
generating differential inputs in systems that do not need to
be dc-coupled. Figure 37 shows how a transformer is used for
sin
gle-ended-to-differential conversion. It provides the benefits
of operating the ADC in the differential mode without contributing additional noise and distortion. An RF transformer also
has the benefit of providing electrical isolation between the
signal source and the ADC. A transformer can be used for most
ac applications. The center tap is used to shift the differential
signal to the common-mode level required; in this case, it is
connected to the reference so the common-mode level is the
value of the reference.
3.75V
2.5V
R
R
R
Figure 37. Using an RF Transformer
1.25V
V
IN+
V
3.75V
2.5V
1.25V
AD7440/
AD7450A
IN–
V
REF
EXTERNAL
V
REF
C
to Generate Differential Inputs
03051-A-037
DIGITAL INPUTS
The digital inputs applied to the device are not limited by the
maximum ratings, which limit the analog limits. Instead the
digital inputs applied,
restricted by the V
CS
and SCLK, can go to 7 V and are not
+ 0.3 V limits as on the analog input.
DD
The main advantage of the inputs not being restricted to the
+ 0.3 V limit is that power supply sequencing issues are
V
DD
avoided. If
CS
and SCLK are applied before VDD, there is no risk
of latch-up as there would be on the analog inputs if a signal
greater than 0.3 V was applied prior to V
DD
.
REFERENCE
An external reference source is required to supply the reference
to the device. This reference input can range from 100 mV to
3.5 V. With a 5 V power supply, the specified reference is 2.5 V
and the maximum reference is 3.5 V. With a 3 V power supply,
the specified reference is 2 V and the maximum reference is
2.2 V. In both cases, the reference is functional from 100 mV.
Ensure that, when choosing the reference value for a particular
a
pplication, the maximum analog input range (V
never greater than V
+ 0.3 V to comply with the maximum
DD
ratings of the device. The following two examples calculate the
maximum V
AD7440/AD7450A at a V
input that can be used when operating the
REF
of 5 V and 3 V, respectively.
DD
max) is
IN
Rev. C | Page 19 of 28
Page 20
AD7440/AD7450A
www.BDTIC.com/ADI
Example 1
VIN max = VDD + 0.3
V
max = V
IN
= 5 V, then VIN max = 5.3 V.
If V
DD
Therefore
V
3 ×
REF
V
max = 3.5 V
REF
Thus, when operating at V
from 100 mV to a maximum value of 3.5 V. When V
V
max = 3.17 V.
REF
Example 2
VIN max = VDD + 0.3
V
max = V
IN
If V
= 3 V, then VIN max = 3.3 V.
DD
Therefore,
3 × V
REF
V
max = 2.2 V
REF
Thus, when operating at V
from 100 mV to a maximum value of 2.2 V. When V
max = 2 V.
V
REF
These examples show that the maximum reference applied to
th
e AD7440/AD7450A is directly dependent on the value
applied to V
The value of the reference sets the analog input span and the
ommon-mode voltage range. Errors in the reference source
c
result in gain errors in the AD7440/AD7450A transfer function
and add to specified full-scale errors on the part. A 0.1 μF
capacitor should be used to decouple the V
Figure 38 shows a typical connection diagram for the V
Tabl e 6 lists examples of suitable voltage references.
When supplied with a 5 V power supply, the AD7440/AD7450A
can handle a single-ended input. The design of these devices is
optimized for differential operation, so with a single-ended
input, performance degrades. Linearity degrades by typically
0.2 LSB, the full-scale errors degrade typically by 1 LSB, and ac
performance is not guaranteed.
To operate the AD7440/AD7450A in single-ended mode, the
V input is coupled to the signal source, while the V
IN+IN–
biased to the appropriate voltage corresponding to the midscale
code transition. This voltage is the common mode, which is a
fixed dc voltage (usually the reference). The V
IN+
around this value and should have a voltage span of 2 × V
make use of the full dynamic range of the part. The input signal
therefore has peak-to-peak values of common mode ±V
the analog input is unipolar, an op amp in a noninverting unity
gain configuration can be used to drive the V
pin. The ADC
IN+
operates from a single supply, so it is necessary to level shift
ground-based bipolar signals to comply with the input
requirements. An op amp can be configured to rescale and level
shift the ground-based bipolar signal, so it is compatible with
the selected input range of the AD7440/AD7450A (
0.1μF
5V
2.5V
0V
V
IN+
AD7440/
AD7450A
V
IN–
o the AD7440/AD7450A
R
+2.5V
–2.5V
0V
R
V
IN
R
R
EXTERNAL
(2.5V)
V
REF
Figure 39. Applying a Bipolar Single-Ended Input t
03051-A-038
input is
input swings
to
REF
. If
REF
Figure 39).
V
REF
03051-A-039
Rev. C | Page 20 of 28
Page 21
AD7440/AD7450A
www.BDTIC.com/ADI
SERIAL INTERFACE
Figure 2 and Figure 3 show detailed timing diagrams for the
s
erial interface of the AD7450A and the AD7440, respectively.
The serial clock provides the conversion clock and also controls
the transfer of data from the devices during conversion.
initiates the conversion process and frames the data transfer.
CS
The falling edge of
puts the track-and-hold into hold mode
and takes the bus out of three-state. The analog input is sampled
and the conversion is initiated at this point. The conversion
requires 16 SCLK cycles to complete.
Once 13 SCLK falling edges have occurred, the track-and-hold
g
oes back into track on the next SCLK rising edge, as shown at
Point B in
e
dge, the SDATA line goes back into three-state. If the rising
edge of
Figure 2 and Figure 3. On the 16th SCLK falling
CS
occurs before 16 SCLKs have elapsed, the conversion
terminates and the SDATA line goes back into three-state.
The conversion result from th
e AD7440/AD7450A is provided
on the SDATA output as a serial data stream. The bits are
clocked out on the falling edge of the SCLK input. The data
stream of the AD7450A consists of four leading zeros followed
by 12 bits of conversion data provided MSB first; the data
stream of the AD7440 consists of four leading zeros, followed
by the 10 bits of conversion data followed by two trailing zeros,
which is also provided MSB first. In both cases, the output
coding is twos complement.
CS
Sixteen serial clock cycles are required to perform a conversion
CS
and access data from the AD7440/AD7450A.
going low
provides the first leading zero to be read in by the DSP or
microcontroller. The remaining data is then clocked out on the
subsequent SCLK falling edges beginning with the second
leading zero. Thus, the first falling clock edge on the serial clock
provides the second leading zero. The final bit in the data
transfer is valid on the 16th falling edge, having been clocked
out on the previous (15th) falling edge. Once the conversion is
complete and the data has been accessed after the 16 clock
cycles, it is important to ensure that before the next conversion
is initiated, enough time is left to meet the acquisition and
quiet time specifications (see Timing Examples 1 and 2). To
achieve 1 MSPS with an 18 MHz clock for V
= 3 V and 5 V, an
DD
18-clock burst performs the conversion and leaves enough time
before the next conversion for the acquisition and quiet time.
In applications with a slower SCLK, it may be possible to read in
da
ta on each SCLK rising edge; that is, the first rising edge of
SCLK after the
CS
falling edge would have the leading zero
provided and the 15th SCLK edge would have DB0 provided.
CS
10ns
t
2
SCLK
1234513141516
12.5(1/F
SCLK
Figure 40. Serial Interface Timing Example
t
CONVERT
t
5
)
1/THROUGHPUT
BC
t
6
t
8
t
ACQUISITION
t
QUIET
03051-A-040
Rev. C | Page 21 of 28
Page 22
AD7440/AD7450A
www.BDTIC.com/ADI
Timing Example 1
Having F
cycle time of
= 18 MHz and a throughput rate of 1 MSPS gives a
SCLK
roughput = 1/1,000,000 = 1 μs
1/Th
Timing Example 2
Having F
= 5 MHz and a throughput rate of 315 kSPS gives a
SCLK
cycle time of
roughput = 1/315,000 = 3.174 μs
1/Th
A cycle consists of
+ 12.5(1/F
t
2
Therefore, if t
10 ns + 12.5(1/18 MH
= 296 ns
t
ACQ
SCLK
= 10 ns
2
) + t
ACQ
z) + t
= 1 μs
ACQ
= 1 μs
This 296 ns satisfies the requirement of 290 ns for t
From Figure 40, t
2.5(1/F
SCLK
comprises
ACQ
) + t8 + t
QUIET
where t8 = 35 ns. This allows a value of 122 ns for t
satisfying the minimum requirement of 60 ns.
ACQ
QUIET
A cycle consists of
+ 12.5(1/F
t
2
Therefore, if t
10 ns + 12.5(1/5 MH
= 664 ns
t
ACQ
.
This 664 ns satisfies the requirement of 290 ns for t
From Figure 40, t
2.5(1/F
SCLK
,
where t8 = 35 ns. This allows a value of 129 ns for t
SCLK
is 10 ns
2
ACQ
) + t8 + t
) + t
= 3.174 μs
ACQ
z) + t
comprises
QUIET
= 3.174 μs
ACQ
ACQ
QUIET,
.
satisfying the minimum requirement of 60 ns.
As in this example and with other slower clock values, the signal
ay already be acquired before the conversion is complete, but
m
it is still necessary to leave 60 ns minimum t
QUIET
between
conversions. In Timing Example 2, the signal should be fully
acquired at approximately Point C in Figure 40.
Rev. C | Page 22 of 28
Page 23
AD7440/AD7450A
S
A
www.BDTIC.com/ADI
MODES OF OPERATION
The operational mode of the AD7440/AD7450A is selected by
CS
controlling the logic state of the
signal during a conversion.
There are two possible modes of operation, normal and powerdown. The point at which
CS
is pulled high after the conversion
has been initiated determines whether or not the device enters
power-down mode. Similarly, if already in power-down,
CS
controls whether the devices return to normal operation or
remain in power-down. These modes of operation are designed
to provide flexible power management options. These options
can be chosen to optimize the power dissipation/throughput
rate ratio for differing application requirements.
NORMAL MODE
This mode is intended for fastest throughput rate performance.
The user does not have to worry about any power-up times with
the AD7440/AD7450A remaining fully powered up all the time.
Figure 41 shows the general diagram of the operation of the
AD7440/AD7450A in this mode. The conversion is initiated on
the falling edge of
section. To ensure the part remains fully powered up,
remain low until at least 10 SCLK falling edges have elapsed
after the falling edge of
CS
SCLK
SDATA
CS
, as described in the Serial Interface
CS
.
110
4 LEADING ZEROS + CONVERSION RESULT
Figure 41. Normal Mode Operation
16
CS
must
03051-A-041
POWER-DOWN MODE
This mode is intended for use in applications where slower
hroughput rates are required; either the ADC is powered down
t
between each conversion, or a series of conversions may be
performed at a high throughput rate and the ADC is then
powered down for a relatively long duration between these
bursts of conversions. When the AD7440/AD7450A are in the
power-down mode, all analog circuitry is powered down. To
enter power-down mode, the conversion process must be
interrupted by bringing
falling edge of SCLK and before the 10th falling edge of SCLK,
as shown in Figure 42.
CS
SCLK
DAT
Figure 42. Entering Power-Down Mode
CS
Once
has been brought high in this window of SCLKs, the
part enters power-down, the conversion that was initiated by
the falling edge of
three-state. The time from the rising edge of
three-state enabled is never greater than t
Specifications). If
falling edge, the part remains in normal mode and does not
power down. This avoids accidental power-down due to glitches
CS
on the
line.
CS
high anywhere after the second
1
2
CS
is terminated, and SDATA goes back into
CS
is brought high before the second SCLK
10
THREE-STATE
CS
to SDATA
(refer to the Timing
8
03051-A-042
CS
If
is brought high any time after the 10th SCLK falling edge,
ut before the 16th SCLK falling edge, the part remains
b
powered up but the conversion terminates and SDATA goes
back into three-state. Sixteen serial clock cycles are required to
complete the conversion and access the complete conversion
CS
result.
lo
may idle high until the next conversion or may idle
w until sometime prior to the next conversion. Once a data
transfer is complete, when SDATA has returned to three-state,
another conversion can be initiated after the quiet time, t
has elapsed by again bringing
PART BEGINS
CS
SCLK
SDATA
TO POWER UP
A
1
CS
low.
t
POWER-UP
101611016
INVALID DATAVALID DATA
QUIET
Figure 43. Exiting Power-Down Mode
Rev. C | Page 23 of 28
In order to exit this mode of operation and power up the
AD7440/AD7450A again, a dummy conversion is performed.
On the falling edge of
continues to power up as long as
CS
, the device begins to power up and
CS
is held low until after the
falling edge of the 10th SCLK. The device is fully powered up
after 1 μs has elapsed and, as shown in
Figure 43, valid data
results from the next conversion.
,
THIS PART IS FULLY POWERED
UP WITH V
FULLY ACQUIRED
IN
03153-A-031
Page 24
AD7440/AD7450A
www.BDTIC.com/ADI
If CS is brought high before the 10th falling edge of SCLK, the
AD7440/AD7450A again goes back into power-down. This
CS
avoids accidental power-up due to glitches on the
inadvertent burst of eight SCLK cycles while
although the device may begin to power up on the falling edge
CS
of
, it again powers down on the rising edge of CS as long as
it occurs before the 10th SCLK falling edge.
POWER-UP TIME
The power-up time of the AD7440/AD7450A is typically 1 μs,
which means that with any frequency of SCLK up to 18 MHz,
one dummy cycle is always sufficient to allow the device to
power up. Once the dummy cycle is complete, the ADC is fully
powered up and the input signal is acquired properly. The quiet
time, t
bus goes back into three-state after the dummy conversion to
the next falling edge of
When running at the maximum throughput rate of 1 MSPS, the
AD7440/AD74
±0.5 LSB in one dummy cycle, 1 μs. When powering up from
the power-down mode with a dummy cycle, as in
rack-and-hold, which was in hold mode while the part was
t
powered down, returns to track mode after the first SCLK edge
the part receives after the falling edge of
Point A in Figure 43.
Although at any SCLK frequency one dummy cycle is sufficient
to
power up the device and acquire V
full dummy cycle of 16 SCLKs must always elapse to power up
the device and acquire V
the device and acquire the input signal.
For example, if a 5 MHz SCLK frequency was applied to the
AD
dummy cycle, 3.2 μs, the part would be powered up and V
acquired fully. However, after 1 μs with a 5 MHz SCLK, only
five SCLK cycles would have elapsed. At this stage, the ADC
would be fully powered up and the signal acquired. So in this
case, the
edge and brought low again after a time, t
conversion.
When power supplies are first applied to the device, the ADC
ma
Because of this, it is best to allow a dummy cycle to elapse to
ensure the part is fully powered up before attempting a valid
conversion. Likewise, if the user wants the part to power up in
power-down mode, the dummy cycle may be used to ensure the
device is in power-down by executing a cycle such as the one
shown in
, must still be allowed from the point at which the
QUIET
CS
.
50A power up and acquire a signal within
CS
. This is shown as
, it does not mean that a
IN
fully; 1 μs is sufficient to power up
IN
C, the cycle time would be 3.2 μs (1/(5 MHz) × 16). In one
CS
can be brought high after the 10th SCLK falling
QUIET
y power up in either power-down mode or normal mode.
Figure 42.
line or an
CS
is low. So
Figure 43, the
, to initiate the
IN
Once supplies are applied to the AD7440/AD7450A, the power-
p time is the same as that when powering up from power-
u
down mode. It takes about 1 μs to power up fully if the part
powers up in normal mode. It is not necessary to wait 1 μs
before executing a dummy cycle to ensure the desired mode of
operation. Instead, the dummy cycle can occur directly after
power is supplied to the ADC. If the first valid conversion is
then performed directly after the dummy conversion, ensure
that adequate acquisition time has been allowed.
As mentioned earlier, when powering up from the power-down
ode, the part returns to track mode upon the first SCLK edge
m
applied after the falling edge of
powers up initially after supplies are applied, the track-and-hold
is already in track mode. Assuming the user has the facility to
monitor the ADC supply current, this means the ADC powers
up in the desired mode of operation, and thus a dummy cycle is
not required to change mode. A dummy cycle is therefore not
required to place the track-and-hold into track mode.
CS
. However, when the ADC
POWER VS. THROUGHPUT RATE
By using the power-down mode on the AD7440/AD7450A
when not converting, the average power consumption of the
ADC decreases at lower throughput rates. Figure 44 shows how,
a
s the throughput rate is reduced, the device remains in its
power-down state longer and the average power consumption is
reduced accordingly for both 5 V and 3 V power supplies.
For example, if the AD7440/AD7450A are operated in
ntinuous sampling mode with a throughput rate of 100 kSPS
co
and an SCLK of 18 MHz, and the device is placed in powerdown mode between conversions, the power consumption is
calculated as follows:
Power Dissipation during Normal Operation = 9
(for V
If the power-up time is one dummy cycle (1 μs), and the
r
AD7440/AD7450A can be said to dissipate 9.25 mW for 2 μs
during each conversion cycle.
If the throughput rate = 100 kSPS, the cycle time = 10 μs and
t
(2/10) × 9.25 mW = 1.85 mW.
For the same scenario, if V
during normal operation is 4 mW max.
The AD7440/AD7450A can now be said to dissipate 4 mW for
2 μs
1
= 5 V)
DD
emaining conversion time is another cycle (1 μs), the
he average power dissipated during each cycle is
= 3 V, the power dissipation
DD
1
during each conversion cycle.
This figure assumes a very short time to enter power-down mode. This
increases as the burst of clocks used to enter this mode is increased.
.25 mW max
1
Rev. C | Page 24 of 28
Page 25
AD7440/AD7450A
www.BDTIC.com/ADI
Thus, the average power dissipated during each cycle with a
throughput rate of 100 kSPS is (2/10) × 4 mW = 0.8 mW.
This is how the power numbers in Figure 44 are calculated.
For throughput rates above 320 kSPS, it is recommended to
r
educe the serial clock frequency for best power performance.
100
10
1
POWER (mW)
0.1
0.01
Figure 44. Power vs. Throughput Rate for Power-Down Mode
50100150200250300
0350
VDD = 5V
V
DD
THROUGHPUT (kSPS)
= 3V
03051-A-044
MICROPROCESSOR AND DSP INTERFACING
The serial interface on the AD7440/AD7450A allows the parts
to be directly connected to many different microprocessors.
This section explains how to interface the AD7440/AD7450A
with some of the more common microcontroller and DSP serial
interface protocols.
AD7440/AD7450A to ADSP-21xx
The ADSP-21xx family of DSPs is interfaced directly to the
AD7440/AD7450A without any glue logic required.
The SPORT control register should be set up as follows:
Table 7.
Parameter Description
TFSW = RFSW = 1 Alternate framing
INVRFS = INVTFS = 1 Active low frame signal
DTYPE = 00 Right-justify data
SLEN = 1111 16-bit data-words
ISCLK = 1 Internal serial clock
TFSR = RFSR = 1 Frame every word
IRFS = 0
ITFS = 1
To implement power-down mode, SLEN should be set to 1001
to issue an 8-bit SCLK burst.
The connection diagram is shown in Figure 45. The ADSP-21xx
has the TFS and RFS of the SPORT tied together, with TFS set
as an output and RFS set as an input. The DSP operates in
alternate framing mode and the SPORT control register is set
up as described. The frame synchronization signal generated on
the TFS is tied to
CS
and, as with all signal processing
applications, equidistant sampling is necessary. However in this
example, the timer interrupt is used to control the sampling rate
of the ADC; under certain conditions, equidistant sampling
may not be achieved.
The timer registers, for example, are loaded with a value that
provides an interrupt at the required sample interval. When an
interrupt is received, a value is transmitted with TFS/DT (ADC
control word). The TFS is used to control the RFS and therefore
the reading of data. The frequency of the serial clock is set in
the SCLKDIV register. When the instruction to transmit with
TFS is given (AX0 = TX0), the state of the SCLK is checked.
The DSP waits until the SCLK has gone high, low, and high
again before starting transmission. If the timer and SCLK values
are chosen such that the instruction to transmit occurs on or
near the rising edge of SCLK, then the data may be transmitted
or it may wait until the next clock edge.
AD7440/
AD7450A*
SCLK
SDATA
CS
*ADDITIONAL PINS REMOVED FOR CLARITY
Figure 45. Interfacing to the ADSP-21xx
ADSP-21xx*
SCLK
DR
RFS
TFS
For example, the ADSP-2111 has a master clock frequency of
1
6 MHz. If the SCLKDIV register is loaded with the value 3, an
SCLK of 2 MHz is obtained and eight master clock periods
elapse for every SCLK period. If the timer registers are loaded
with the value 803, then 100.5 SCLKs occur between interrupts
and subsequently between transmit instructions. This situation
results in nonequidistant sampling as the transmit instruction is
occurring on a SCLK edge. If the number of SCLKs between
interrupts is a whole integer figure of N, equidistant sampling is
implemented by the DSP.
03051-A-045
Rev. C | Page 25 of 28
Page 26
AD7440/AD7450A
www.BDTIC.com/ADI
AD7440/AD7450A to TMS320C5x/C54x
The serial interface on the TMS320C5x/C54x uses a continuous
serial clock and frame synchronization signals to synchronize
the data transfer operations with peripheral devices like the
AD7440/AD7450A. The
between the TMS320C5x/C54x and the AD7440/AD7450A
without any glue logic required. The serial port of the
TMS320C5x/C54x is set up to operate in burst mode with
internal CLKx (Tx serial clock) and FSx (Tx frame sync). The
serial port control register (SPC) must have the following setup:
FO = 0, FSM = 1, MCM = 1, and TxM = 1. The format bit, FO,
may be set to 1 to set the word length to eight bits to implement
the power-down mode on the AD7440/AD7450A. The connection diagram is shown in
a
pplications, it is imperative that the frame synchronization
signal from the TMS320C5x/C54x provide equidistant
sampling.
AD7440/
AD7450A*
SCLK
SDATA
CS
*ADDITIONAL PINS REMOVED FOR CLARITY
Figure 46. Interfacing to the TMS320C5x/C54
AD7440/AD7450A to DSP56xxx
The connection diagram in Figure 47 shows how the device can
be connected to the synchronous serial interface (SSI) of the
DSP56xxx family of DSPs from Motorola. The SSI is operated in
synchronous mode (SYN bit in CRB = 1) with internally
generated 1-word frame sync for both Tx and Rx (Bits FSL1 = 0
and FSL0 = 0 in CRB). Set the word length to 16 by setting Bits
WL1 = 1 and WL0 = 0 in CRA. To implement power-down
mode on the AD7440/AD7450A, the word length can be
changed to 8 bits by setting Bits WL1 = 0 and WL0 = 0 in CRA.
For signal processing applications, it is imperative that the
frame synchronization signal from the DSP56xxx provide
equidistant sampling.
AD7440/
AD7450A*
SCLK
SDATA
CS
CS
input allows easy interfacing
Figure 46. For signal processing
TMS320C5x/
C54x*
CLKx
CLKR
DR
FSx
FSR
DSP56xxx*
SCLK
SRD
SR2
03051-A-046
GROUNDING AND LAYOUT HINTS
The printed circuit board that houses the AD7440/AD7450A
hould be designed so that the analog and digital sections are
s
separated and confined to certain areas of the board. This
facilitates the use of ground planes that can be easily separated.
A minimum etch technique is generally best for ground planes
as it gives the best shielding. Digital and analog ground planes
should be joined in only one place, a star ground point
established as close to the GND pin on the AD7440/AD7450A
as possible. Avoid running digital lines under the devices
because this couples noise onto the die. The analog ground
plane should be allowed to run under the AD7440/AD7450A to
avoid noise coupling. The power supply lines to the
AD7440/AD7450A should use as large a trace as possible to
provide low impedance paths and reduce the effects of glitches
on the power supply line.
Fast switching signals like clocks should be shielded with digital
round to avoid radiating noise to other sections of the board,
g
and clock signals should never run near the analog inputs.
Avoid crossover of digital and analog signals. Traces on
opposite sides of the board should run at right angles to each
other. This reduces the effects of feedthrough through the
board. A microstrip technique is by far the best but is not
always possible with a double-sided board.
In this technique, the component side of the board is dedicated
to ground planes while signals are placed on the solder side.
Good decoupling is also important. All analog supplies should
be decoupled with 10 μF tantalum capacitors in parallel with
0.1 μF capacitors to GND. To achieve the best from these
decoupling components, they must be placed as close as
possible to the device.
EVALUATING THE AD7440/AD7450A
PERFORMANCE
The evaluation board package includes a fully assembled and
tested evaluation board, documentation, and software for
controlling the board from a PC via the evaluation board
controller. The evaluation board controller can be used in
conjunction with the AD7440/AD7450A evaluation board, as
well as many other Analog Devices evaluation boards ending
with the CB designator, to demonstrate and evaluate the ac and
dc performance of the AD7440/AD7450A.
The software allows the user to perform ac (fast Fourier
transform) and dc (histogram of codes) tests on the device. See
the AD7440/AD7450A application note that accompanies the
evaluation kit for more information.
*ADDITIONAL PINS REMOVED FOR CLARITY
Figure 47. Interfacing to the DSP56xxx
03051-A-047
Rev. C | Page 26 of 28
Page 27
AD7440/AD7450A
www.BDTIC.com/ADI
OUTLINE DIMENSIONS
2.90 BSC
2
1.95
BSC
56
0.65 BSC
2.80 BSC
1.45 MAX
SEATING
PLANE
0.22
0.08
8°
4°
0°
0.60
0.45
0.30
1.60 BSC
PIN 1
INDICATOR
1.30
1.15
0.90
0.15 MAX
847
13
0.38
0.22
COMPLIANT TO JEDEC STANDARDS MO-178-BA
Figure 48. 8-Lead Small Outline Transistor Package [SOT-23]
(RT-8)
Dim
ensions shown in millimeters
3.20
3.00
2.80
8
5
4
SEATING
PLANE
5.15
4.90
4.65
1.10 MAX
0.23
0.08
8°
0°
0.80
0.60
0.40
3.20
3.00
2.80
PIN 1
0.95
0.85
0.75
0.15
0.00
COPLANARITY
1
0.65 BSC
0.38
0.22
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 49. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dim
ensions shown in millimeters
Rev. C | Page 27 of 28
Page 28
AD7440/AD7450A
www.BDTIC.com/ADI
ORDERING GUIDE
Package
Model Temperature Range Linearity Error (LSB)1
AD7440BRT-REEL7 –40°C to +85°C ±0.5 8-lead SOT-23 RT-8 CTB
AD7440BRT-R2 –40°C to +85°C ±0.5 8-lead SOT-23 RT-8 CTB
AD7440BRTZ-REEL7
AD7440BRTZ-R2
2
2
–40°C to +85°C ±0.5 8-lead SOT-23 RT-8 C3J
–40°C to +85°C ±0.5 8-lead SOT-23 RT-8 C3J
AD7440BRM –40°C to +85°C ±0.5 8-lead MSOP RM-8 CTB
AD7440BRM-REEL7 –40°C to +85°C ±0.5 8-lead MSOP RM-8 CTB
AD7440BRMZ
2
–40°C to +85°C ±0.5 8-lead MSOP RM-8 C3J
AD7450ABRT-REEL7 –40°C to +85°C ±1 8-lead SOT-23 RT-8 CSB
AD7450ABRT-R2 –40°C to +85°C ±1 8-lead SOT-23 RT-8 CSB
AD7450ABRTZ-REEL7
2
–40°C to +85°C ±1 8-lead SOT-23 RT-8 C4N
AD7450ABRM –40°C to +85°C ±1 8-lead MSOP RM-8 CSB
AD7450ABRM-REEL7 –40°C to +85°C ±1 8-lead MSOP RM-8 CSB
AD7450ABRMZ
Linearity error here refers to integral nonlinearity error.
2
Z = Pb-free part.
3
This can be used as a standalone evaluation board or in conjunction with the evaluation board controller for evaluation/demonstration purposes.
4
Evaluation board controller. This board is a complete unit allowing a PC to control and communicate with all Analog Devices’ evaluation boards ending in the CB
designator. For a complete evaluation kit, order the ADC evaluation board (that is, the EVAL-AD7450ACB or EVAL-AD7440CB), the EVAL-CONTROL BRD2, and a 12 V ac
transformer. See the AD7440/AD7450A application note that accompanies the evaluation kit for more information.