Datasheet AD745 Datasheet (Analog Devices)

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Page 1

Ultralow Noise,

FREQUENCY – Hz

OPEN-LOOP GAIN – dB

PHASE MARGIN – Degrees

120

100

–20

100 1k 10k 100k 1M

10M 100M

120

100

–20

PHASE

GAIN

OFFSET

NULL

1 2

3 4

AD745

TOP VIEW

OUTPUT OFFSET

NULL

– IN

+IN

–V

NC = NO CONNECT

2 3 4 5

AD745

TOP VIEW

NC NC

OFFSET

NULL

– IN

+IN OUTPUT

OFFSET NULL

–V

FEATURES ULTRALOW NOISE PERFORMANCE

2.9 nV/ÏHz at 10 kHz

0.38 mV p-p, 0.1 Hz to 10 Hz

6.9 fA/ÏHz Current Noise at 1 kHz EXCELLENT AC PERFORMANCE

12.5 V/ms Slew Rate 20 MHz Gain Bandwidth Product THD = 0.0002% @ 1 kHz Internally Compensated for Gains of +5 (or –4) or

Greater

EXCELLENT DC PERFORMANCE

0.5 mV max Offset Voltage 250 pA max Input Bias Current 2000 V/mV min Open Loop Gain Available in Tape and Reel in Accordance with

EIA-481A Standard

APPLICATIONS Sonar Photodiode and IR Detector Amplifiers Accelerometers Low Noise Preamplifiers High Performance Audio

PRODUCT DESCRIPTION

The AD745 is an ultralow noise, high speed, FET input operational amplifier. It offers both the ultralow voltage noise and high speed generally associated with bipolar input op amps and the very low input currents of FET input devices. Its 20 MHz bandwidth and 12.5 V/µs slew rate makes the AD745 an ideal amplifier for high speed applications demanding low noise and high dc precision. Furthermore, the AD745 does not exhibit an output phase reversal.

1000

100

SOURCE

OP37 &

RESISTOR

( — )

High Speed, BiFET Op Amp

AD745

CONNECTION DIAGRAMS

8-Pin Plastic Mini-DIP (N) &

8-Pin Cerdip (Q) Packages

The AD745’s guaranteed, tested maximum input voltage noise of 4 nV/√

Hz at 10 kHz is unsurpassed for a FET-input monolithic op amp, as is its maximum 1.0 µV p-p noise in a 0.1 Hz to 10 Hz bandwidth. The AD745 also has excellent dc performance with 250 pA maximum input bias current and 0.5 mV maximum offset voltage.

The internal compensation of the AD745 is optimized for higher gains, providing a much higher bandwidth and a faster slew rate. This makes the AD745 especially useful as a preamplifier where low level signals require an amplifier that provides both high amplification and wide bandwidth at these higher gains. The AD745 is available in five performance grades. The AD745J and AD745K are rated over the commercial temperature range of 0°C to +70°C. The AD745A and AD745B are rated over the industrial temperature range of –40°C to +85°C. The AD745S is rated over the military temperature range of –55°C to +125°C and is available processed to MIL-STD-883B, Rev. C.

The AD745 is available in 8-pin plastic mini-DIP, 8-pin cerdip, 16-pin SOIC, or in chip form.

16-Pin SOIC (R) Package

REV. C

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

INPUT NOISE VOLTAGE – nV/ Hz

100

AD745 & RESISTOR

OP37 & RESISTOR

RESISTOR NOISE ONLY

1k 10k 100k

SOURCE RESISTANCE – Ω

(– – –)

AD745 + RESISTOR

( )

1M 10M

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703

Page 2

AD745–SPECIFICA TIONS

(@ +258C and 615 V dc, unless otherwise noted)

Model AD745J/A

Conditions Min Typ Max Units

INPUT OFFSET VOLTAGE

Initial Offset 0.25 1.0/0.8 mV Initial Offset T vs. Temp. T vs. Supply (PSRR) 12 V to 18 V vs. Supply (PSRR) T

INPUT BIAS CURRENT

MIN MIN

MIN

to T to T

to T

MAX MAX

MAX

90 96 dB

2 µV/°C

88 dB

1.5 mV

Either Input VCM = 0 V 150 400 pA Either Input

@ T

MAX

Either Input VCM = +10 V 250 600 pA

VCM = 0 V 8.8/25.6 nA

Either Input, VS = ±5 V VCM = 0 V 30 200 pA

INPUT OFFSET CURRENT VCM = 0 V 40 150 pA

Offset Current

@ T

MAX

VCM = 0 V 2.2/6.4 nA

FREQUENCY RESPONSE

Gain BW, Small Signal G = –4 20 MHz Full Power Response VO = 20 V p-p 120 kHz Slew Rate G = –4 12.5 V/µs Settling Time to 0.01% 5 µs Total Harmonic f = 1 kHz

Distortion

G = –4 0.0002 %

INPUT IMPEDANCE

Differential 1 × 1010i20 ΩipF Common Mode 3 × 1011i18 ΩipF

INPUT VOLTAGE RANGE

Differential Common-Mode Voltage +13.3, –10.7 V Over Max Operating Range

–10 +12 V

±20 V

Common-Mode

Rejection Ratio VCM = ±10 V 80 95 dB

MIN

to T

MAX

78 dB

INPUT VOLTAGE NOISE 0.1 to 10 Hz 0.38 µV p-p

f = 10 Hz 5.5 nV/√Hz f = 100 Hz 3.6 nV/√Hz f = 1 kHz 3.2 5.0 nV/√Hz

f = 10 kHz 2.9 4.0 nV/√Hz INPUT CURRENT NOISE f = 1 kHz 6.9 fA/√Hz OPEN LOOP GAIN VO = ±10 V

≥ 2 kΩ 1000 4000 V/mV

LOAD

to T

MIN

MAX

= 600 Ω 1200 V/mV

LOAD

800 V/mV

OUTPUT CHARACTERISTICS

Voltage R

Current Short Circuit 20 40 mA

≥ 600 Ω +13, –12 V

LOAD

≥ 600 Ω +13.6, –12.6 V

LOAD

to T

MIN

MAX

≥ 2 kΩ±12 +13.8, –13.1 V

LOAD

+12, –10 V

POWER SUPPLY

Rated Performance ±15 V Operating Range ±4.8 ±18 V Quiescent Current 8 10.0 mA

TRANSISTOR COUNT # of Transistors 50

NOTES

Input offset voltage specifications are guaranteed after 5 minutes of operations at TA = +25°C.

Test conditions: +VS = 15 V, –VS = 12 V to 18 V and +VS = 12 V to +18 V, –VS = 15 V.

Bias current specifications are guaranteed maximum at either input after 5 minutes of operation at TA = +25°C. For higher temperature, the current doubles every 10°C.

Gain = –4, RL = 2 kΩ, CL = 10 pF.

Defined as voltagc between inputs, such that neither exceeds ±10 V from common.

The AD745 does not exhibit an output phase reversal when the negative common-mode limit is exceeded.

All min and max specifications are guaranteed. Specifications subject to change without notice.

–2–

REV. C

Page 3

AD745

ABSOLUTE MAXIMUM RATINGS

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18 V

Internal Power Dissipation

Plastic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 W

Cerdip Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 W

SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 W

Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±V

Output Short-Circuit Duration . . . . . . . . . . . . . . . . Indefinite

Differential Input Voltage . . . . . . . . . . . . . . . . . . +V

and –V

Storage Temperature Range (Q) . . . . . . . . . –65°C to +150°C

Storage Temperature Range (N, R) . . . . . . . –65°C to +125°C

Operating Temperature Range

AD745J/K . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C

AD745A/B . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C

AD745S . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C

Lead Temperature Range (Soldering 60 sec) . . . . . . . . +300°C

NOTES

Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

8-Pin Plastic Package: θJA = 100°C/W, θJC = 50°C/W 8-Pin Cerdip Package: θ 8-Pin Plastic SOIC Package: θJA = 100°C/W, θJC = 30°C/W

= 110°C/W, θJC = 30°C/W

METALIZATION PHOTOGRAPH

Dimensions shown in inches and (mm).

ESD SUSCEPTIBILITY

An ESD classification per method 3015.6 of MIL-STD-883C has been performed on the AD745, which is a class 1 device. Using an IMCS 5000 automated ESD tester, the two null pins will pass at voltages up to 1000 volts, while all other pins will pass at voltages exceeding 2500 volts.

ORDERING GUIDE

Package

Model Temperature Range Option*

AD745JN 0°C to +70°C N-8 AD745AN –40°C to +85°C N-8 AD745JR-16 0°C to +70°C R-16

*N = Plastic DIP; R = Small Outline IC.

REV. C

–3–

Page 4

AD745

100

10k

LOAD RESISTANCE – Ω

OUTPUT VOLTAGE SWING – Volts p-p

200 100

0.1

0.01 10k 100k 1M 10M 100M

FREQUENCY – Hz

OUTPUT IMPEDANCE – Ω

CLOSED-LOOP GAIN = –5

–60 –40 –20020

40 60 80 100 120 140

GAIN BANDWIDTH PRODUCT – MHz

TEMPERATURE – C

–Typical Characteristics

(@ + 258C, VS = 615 V unless otherwise noted)

R = 10kΩ

LOAD

INPUT VOLTAGE SWING – Volts

SUPPLY VOLTAGE VOLTS

–V

10 15 20

–

Figure 1. Input Voltage Swing vs. Supply Voltage

QUIESCENT CURRENT – mA

R = 10kΩ

LOAD

OUTPUT VOLTAGE SWING – Volts

POSITIVE

SUPPLY

NEGATIVE

SUPPLY

5101520

SUPPLY VOLTAGE VOLTS

–

Figure 2. Output Voltage Swing vs. Supply Voltage

–6

–7

–8

–9

–10

–11

INPUT BIAS CURRENT – Amps

Figure 3. Output Voltage Swing vs. Load Resistance

–12

510

SUPPLY VOLTAGE ± VOLTS

15 20

Figure 4. Quiescent Current vs. Supply Voltage

300

200

100

INPUT BIAS CURRENT – pA

–9 –6 –3 3 6 9 COMMON-MODE VOLTAGE – Volts

Figure 7. Input Bias Current vs. Common-Mode Voltage

0–12

–60 –40 –20020 40 60

TEMPERATURE – °C

80 100 120 140

Figure 5. Input Bias Current vs. Temperature

CURRENT LIMIT – mA

0 – 60 – 40

+ OUTPUT CURRENT

– OUTPUT CURRENT

0 20 40 60 80 100 120 140

– 20

TEMPERATURE – °C

Figure 8. Short Circuit Current Limit vs. Temperature

Figure 6. Output Impedance vs. Frequency

Figure 9. Gain Bandwidth Product vs. Temperature

–4–

REV. C

Page 5

10 15 20

120

130

140

150

100

OPEN-LOOP GAIN – dB

SUPPLY VOLTAGE ± VOLTS

RL = 2kΩ

1.0

100

100 1k 10k 100k

FREQUENCY – Hz

CURRENT NOISE SPECTRAL DENSITY – fA/ Hz

Typical Characteristics–

AD745

120

100

OPEN-LOOP GAIN – dB

–20

100 1k 10k 100k 1M

GAIN

FREQUENCY – Hz

PHASE

10M 100M

120

100

–20

Figure 10. Open-Loop Gain and Phase vs. Frequency

120

110

100

Vcm = ±10V

COMMON-MODE REJECTION – dB

10k 100k 1M 10M100

FREQUENCY – Hz

Figure 13. Common-Mode Rejection vs. Frequency

CLOSED-LOOP GAIN = +5

SLEW RATE – Volts/µs

PHASE MARGIN – Degrees

–60 –40 –20 0 20 40 60 80 100 120 140

TEMPERATURE – °C

Figure 11. Slew Rate vs. Temperature

120

100

POWER SUPPLY REJECTION – dB

100 1k 10k 100k 1M 10M 100M

– SUPPLY

FREQUENCY – Hz

+ SUPPLY

Figure 14. Power Supply Rejection vs. Frequency

Figure 12. Open-Loop Gain vs. Supply Voltage

OUTPUT VOLTAGE – Volts p-p

10k 100k 1M 10M

R = 2kΩ

FREQUENCY – Hz

Figure 15. Large Signal Frequency Response

TOTAL HARMONIC DISTORTION (THD) – dB

Figure 16. Total Harmonic Distortion vs. Frequency

–40

–60

–80

GAIN = +10

–100

GAIN = +100

–120

–140

10 100 1k 10k 100k

GAIN = –4

FREQUENCY – Hz

1.0

0.1

0.01

0.001

0.0001

0.00001

100

1.0

TOTAL HARMONIC DISTORTION (THD) – %

NOISE VOLTAGE (reffered to input) – nV/

0.1

CLOSED-LOOP GAIN = +5

10 100 1k 10k 100k 1M 10M

Figure 17. Input Noise Voltage Spectral Density

FREQUENCY – Hz

Figure 18. Input Noise Current Spectral Density

REV. C

–5–

Page 6

AD745

–Typical Characteristics

TOTAL UNITS = 760

66 60

48 42

36 30 24

NUMBER OF UNITS

6 0

–15

–10

INPUT OFFSET VOLTAGE DRIFT – µV/ C

1050–5

Figure 19. Distribution of Offset Voltage Drift. T

SQUARE

WAVE INPUT

499Ω

= +25°C to +125°C

AD745

–V

2kΩ

20pF

0.1µF

10pF

648 594 540 486 432 378 324 270 216

NUMBER OF UNITS

162 108

2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.42.6

INPUT VOLTAGE NOISE @ 10kHz – nV/√ Hz

Figure 20. Typical Input Noise Voltage Distribution @ 10 kHz

OUT

 100

 90

 10  0%

TOTAL UNITS = 4100



2µs

0.1µF

Figure 21. Offset Null Configuration, 8-Pin Package Pinout

 100

 90

 10  0%

1µF

AD745

–V



50mV

1µF

ADJUST

0.1µF

1MΩ



500nS

2MΩ

Figure 22a. Gain of 5 Follower, 8-Pin Package Pinout

20pF

2kΩ

0.1 µF

0.1µF

SQUARE

WAVE INPUT

499Ω

AD745

–V

Figure 23a. Gain of 4 Inverter, 8-Pin Package Pinout

10pF

OUT

Figure 22b. Gain of 5 Follower Large Signal Pulse Response



 100

 90

 10  0%



2µs

Figure 23b. Gain of 4 Inverter Large Signal Pulse Response

Figure 22c. Gain of 5 Follower Small Signal Pulse Response



 100

 90

 10  0%



50mV

500nS

Figure 23c. Gain of 4 Inverter Small Signal Pulse Response

–6–

REV. C

Page 7

AD745

OP AMP PERFORMANCE JFET VS. BIPOLAR

The AD745 offers the low input voltage noise of an industry standard bipolar op amp without its inherent input current errors. This is demonstrated in Figure 24, which compares input voltage noise vs. input source resistance of the OP37 and the AD745 op amps. From this figure, it is clear that at high source impedance the low current noise of the AD745 also provides lower total noise. It is also important to note that with the AD745 this noise reduction extends all the way down to low source impedances. The lower dc current errors of the AD745 also reduce errors due to offset and drift at high source impedances (Figure 25).

1000

SOURCE

100

INPUT NOISE VOLTAGE – nV/ Hz

100 1k

SOURCE

AD745 & RESISTOR

OP37 & RESISTOR

RESISTOR NOISE ONLY

10k

SOURCE RESISTANCE – Ω

(– – –)

OP37 & RESISTOR

( — )

AD745 + RESISTOR

100k

(

)

10M

Figure 24. Total Input Noise Spectral Density @ 1 kHz vs. Source Resistance

100

DESIGNING CIRCUITS FOR LOW NOISE

An op amp’s input voltage noise performance is typically divided into two regions: flatband and low frequency noise. The AD745 offers excellent performance with respect to both. The figure of 2.9 nV/Ï

Hz @ 10 kHz is excellent for a JFET input amplifier. The 0.1 Hz to 10 Hz noise is typically 0.38 µV p-p. The user should pay careful attention to several design details in order to optimize low frequency noise performance. Random air currents can generate varying thermocouple voltages that appear as low frequency noise: therefore sensitive circuitry should be well shielded from air flow. Keeping absolute chip temperature low also reduces low frequency noise in two ways: first, the low frequency noise is strongly dependent on the ambient temperature and increases above +25°C. Secondly, since the gradient of temperature from the IC package to ambient is greater, the noise generated by random air currents, as previously mentioned, will be larger in magnitude. Chip temperature can be reduced both by operation at reduced supply voltages and by the use of a suitable clip-on heat sink, if possible. Low frequency current noise can be computed from the



= 2qIB∆f

magnitude of the dc bias current below approximately 100 Hz with a 1/f power spectral density.



For the AD745 the typical value of current noise is 6.9 fA/√ at 1 kHz. Using the formula, Johnson noise of a resistor, expressed as a current, one can see

that the current noise of the AD745 is equivalent to that of a

3.45 × 10

Ω source resistance.

= 4kT/R∆f



and increases



, to compute the

At high frequencies, the current noise of a FET increases proportionately to frequency. This noise is due to the “real” part of the gate input impedance, which decreases with frequency. This noise component usually is not important, since the voltage noise of the amplifier impressed upon its input capacitance is an apparent current noise of approximately the same magnitude.

In any FET input amplifier, the current noise of the internal bias circuitry can be coupled externally via the gate-to-source capacitances and appears as input current noise. This noise is totally correlated at the inputs, so source impedance matching will tend to cancel out its effect. Both input resistance and input capacitance should be balanced whenever dealing with source capacitances of less than 300 pF in value.

ADOP37G

1.0

INPUT OFFSET VOLTAGE – mV

0.1 100

1k 10k 100k

SOURCE RESISTANCE – Ω

AD745 KN

1M 10M

Figure 25. Input Offset Voltage vs. Source Resistance

REV. C

LOW NOISE CHARGE AMPLIFIERS

As stated, the AD745 provides both low voltage and low current noise. This combination makes this device particularly suitable in applications requiring very high charge sensitivity, such as capacitive accelerometers and hydrophones. When dealing with a high source capacitance, it is useful to consider the total input charge uncertainty as a measure of system noise.

Charge (Q) is related to voltage and current by the simply stated fundamental relationships:

Q = CV and I =

As shown, voltage, current and charge noise can all be directly

related. The change in open circuit voltage (∆V) on a capacitor will equal the combination of the change in charge (∆Q/C) and the change in capacitance with a built-in charge (Q/∆C).

–7–

Page 8

AD745

1pA 10pA

100pA 1nA

10nA

5.2 x 10

INPUT BIAS CURRENT

RESISTANCE IN Ω

Figures 26 and 27 show two ways to buffer and amplify the output of a charge output transducer. Both require using an amplifier which has a very high input impedance, such as the AD745. Figure 26 shows a model of a charge amplifier circuit. Here, amplification depends on the principle of conservation of charge at the input of amplifier A1, which requires that the charge on capacitor C yielding an output voltage of ∆Q/C

be transferred to capacitor CF, thus

. The amplifiers input

voltage noise will appear at the output amplified by the noise gain (1 + (C

)) of the circuit.

S/CF

R 2

Figure 26. A Charge Amplifier Circuit

C *

Figure 28 shows that these two circuits have an identical frequency response and the same noise performance (provided that C “T” network is used to increase the effective resistance of R

= R1/ R2). One feature of the first circuit is that a

S/CF

and improve the low frequency cutoff point by the same factor.

–100 –110

–120

–130 –140 –150 –160 –170 –180 –190 –200

DECIBELS REFERENCED TO 1V/

–210 –220

0.01

0.1 1 10 100 FREQUENCY – Hz

10k 100k

TOTAL OUTPUT NOISE

NOISE DUE TO R ALONE

NOISE DUE TO I ALONE

Figure 28. Noise at the Outputs of the Circuits of Figures 26 and 27. Gain = 10, C

However, this does not change the noise contribution of R

= 3000 pF, RB = 22 M

Ω

which, in this example, dominates at low frequencies. The graph of Figure 29 shows how to select an R

large enough to

minimize this resistor’s contribution to overall circuit noise. When the equivalent current noise of R

the noise of

larger.

IB2qI

()

, there is diminishing return in making

((Ï4 kT)/R) equals

*OPTIONAL, SEE TEXT

Figure 27. Model for A High Z Follower with Gain

The second circuit, Figure 27, is simply a high impedance follower with gain. Here the noise gain (1 + (R1/R2)) is the same as the gain from the transducer to the output. Resistor R in both circuits, is required as a dc bias current return.

There are three important sources of noise in these circuits. Amplifiers A1 and A2 contribute both voltage and current noise, while resistor R

contributes a current noise of:

= 4 k

∆f

where:

k = Boltzman’s Constant = 1.381 × 10

–23

Joules/Kelvin

T = Absolute Temperature, Kelvin (0°C = +273.2 Kelvin)

∆

f = Bandwidth – in Hz (Assuming an Ideal “Brick Wall”

Filter) This must be root-sum-squared with the amplifier’s own

current noise.

Figure 29. Graph of Resistance vs. Input Bias Current Where the Equivalent Noise

of the Bias Current

IB2qI

Ï4 kT/R

()

, Equals the Noise

To maximize dc performance over temperature, the source resistances should be balanced on each input of the amplifier. This is represented by the optional resistor R

in Figures 26 and

27. As previously mentioned, for best noise performance care should be taken to also balance the source capacitance designated by C to C

in Figure 27. At values of CB over 300 pF, there is a

diminishing impact on noise; capacitor C

The value for CB in Figure 26 would be equal

can then be simply a

large mylar bypass capacitor of 0.01 µF or greater.

–8–

REV. C

Page 9

AD745

HOW CHIP PACKAGE TYPE AND POWER DISSIPATION AFFECT INPUT BIAS CURRENT

As with all JFET input amplifiers, the input bias current of the AD745 is a direct function of device junction temperature, I

approximately doubling every 10°C. Figure 30 shows the relationship between bias current and junction temperature for the AD745. This graph shows that lowering the junction temperature will dramatically improve I

–6

–7

V = 15V

–8

–9

–10

INPUT BIAS CURRENT – Amps

–11

–12

–60

–20 0

–40

JUNCTION TEMPERATURE – °C

T = +25°C

20 40 60 80 100 120 140

Figure 30. Input Bias Current vs. Junction Temperature

The dc thermal properties of an IC can be closely approximated by using the simple model of Figure 31 where current represents power dissipation, voltage represents temperature, and resistors represent thermal resistance (θ in °C/watt).

WHERE:

= DEVICE DISSIPATION

= AMBIENT TEMPERATURE

= JUNCTION TEMPERATURE

= THERMAL RESISTANCE – JUNCTION TO CASE

= THERMAL RESISTANCE – CASE TO AMBIENT

Figure 31. Device Thermal Model

From this model TJ = TA+θJA PIN. Therefore, IB can be determined in a particular application by using Figure 30 together with the published data for θ The user can modify θ

by use of an appropriate clip-on heat

sink such as the Aavid #5801. θ

and power dissipation.

is also a variable when using

the AD745 in chip form. Figure 32 shows bias current vs. supply voltage with θ used to predict bias current after θ

as the third variable. This graph can be

has been computed. Again

bias current will double for every 10°C. The designer using the AD745 in chip form (Figure 33) must also be concerned with both θ

and θCA, since θJC can be affected by the type of die

mount technology used. Typically, θ

’s will be in the 3°C to 5°C/watt range; therefore,

for normal packages, this small power dissipation level may be ignored. But, with a large hybrid substrate, θ proportionately more of the total θ

will dominate

300

T = +25°C

200

100

INPUT BIAS CURRENT – pA

SUPPLY VOLTAGE – ±Volts

= 165°C/W

= 115°C/W

= 0°C/W

Figure 32. Input Bias Current vs. Supply Voltage for Various Values of

CASE

(J TO DIE MOUNT)

(DIE MOUNT TO CASE)

Figure 33. Breakdown of Various Package Thermal Resistance

REDUCED POWER SUPPLY OPERATION FOR LOWER I

Reduced power supply operation lowers IB in two ways: first, by lowering both the total power dissipation and, second, by reducing the basic gate-to-junction leakage (Figure 32). Figure 34 shows a 40 dB gain piezoelectric transducer amplifier, which operates without an ac coupling capacitor, over the –40°C to +85°C temperature range. If the optional coupling capacitor, C1, is used, this circuit will operate over the entire –55°C to +125°C temperature range.

100Ω 10kΩ

C1*

10 Ω

TRANSDUCER

*OPTIONAL DC BLOCKING CAPACITOR **OPTIONAL, SEE TEXT

CT**

+5V

AD745

–5V

10 Ω

Figure 34. A Piezoelectric Transducer

REV. C

–9–

Page 10

AD745

100Ω

1900Ω

C1*

*OPTIONAL, SEE TEXT ** 1 VOLT PER MICROPASCAL

10 Ω

AD745

R4*

B&K TYPE 8100 HYDROPHONE

INPUT SENSITIVITY = –179dB RE. 1V/µPa**

OUTPUT

TWO HIGH PERFORMANCE ACCELEROMETER AMPLIFIERS

Two of the most popular charge-out transducers are hydrophones and accelerometers. Precision accelerometers are typically calibrated for a charge output (pC/g).* Figures 35a and 35b show two ways in which to configure the AD745 as a low noise charge amplifier for use with a wide variety of piezoelectric accelerometers. The input sensitivity of these circuits will be determined by the value of capacitor C1 and is equal to:

∆Q

∆V

OUT

The ratio of capacitor C1 to the internal capacitance (CT) of the transducer determines the noise gain of this circuit (1 + C

/C1).

The amplifiers voltage noise will appear at its output amplified by this amount. The low frequency bandwidth of these circuits will be dependent on the value of resistor R1. If a “T” network is used, the effective value is: R1 (1 + R2/R3).

*pC = Picocoulombs g = Earth’s Gravitational Constant

1250pFC1

110MΩ

(5x22MΩ)

9kΩ

1kΩ

A dc servo loop (Figure 35b) can be used to assure a dc output <10 mV, without the need for a large compensating resistor when dealing with bias currents as large as 100 nA. For optimal low frequency performance, the time constant of the servo loop (R4C2 = R5C3) should be:

Time Constant ≥10 R11+

 



R2 R3

 



A LOW NOISE HYDROPHONE AMPLIFIER

Hydrophones are usually calibrated in the voltage-out mode. The circuit of Figures 36a can be used to amplify the output of a typical hydrophone. If the optional ac coupling capacitor C

used, the circuit will have a low frequency cutoff determined by an RC time constant equal to:

Time Constant =

2π×C

×100 Ω

where the dc gain is 1 and the gain above the low frequency cutoff (1/(2π C

(100 Ω))) is equal to (1 + R2/R3). The circuit

of Figure 36b uses a dc servo loop to keep the dc output at 0 V and to maintain full dynamic range for I

’s up to 100 nA. The

time constant of R7 and C1 should be larger than that of R1 and C

for a smooth low frequency response.

B&K MODEL

4370 OR

EQUIVALENT

Figure 35a. A Basic Accelerometer Circuit

B&K MODEL

4370 OR

EQUIVALENT

Figure 35b. An Accelerometer Circuit Employing a DC Servo Amplifier

AD745

1250pFC1

1kΩ

2.2µF

9kΩ

18MΩ

R4 R5

18MΩ

2.2µF

110MΩ

(5x22MΩ)

AD711

AD745

OUTPUT = 0.8mV/pC

*pC = PICOCOULOMBS g = EARTH'S GRAVITATIONAL CONSTANT

OUTPUT

0.8mV/pC

Figure 36a. A Low Noise Hydrophone Amplifier

The transducer shown has a source capacitance of 7500 pF. For smaller transducer capacitances (≤300 pF), lowest noise can be achieved by adding a parallel RC network (R4 = R1, C1 = C in series with the inverting input of the AD745.

1900Ω

100Ω

B&K TYPE

8100

HYDROPHONE

10 Ω

R4*

DC OUTPUT ≤ 1mV FOR I (AD745) ≤ 100nA

C1*

AD745

10 Ω

100kΩ

1MΩ

*OPTIONAL, SEE TEXT

0.27µF

AD711K

OUTPUT

16MΩ

Figure 36b. A Hydrophone Amplifier Incorporating a DC Servo Loop

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Page 11

Design Considerations for I-to-V Converters

3 POLE

LOW

PASS

FILTER

TOP VIEW

AD1862

20 BIT D/A

CONVERTER

AD745

DIGITAL

COMMON

DIGITAL INPUTS

ANALOG COMMON

0.01

µF

–12V

0.01

µF

+12V

–12V

0.01µF

3kΩ

2000pF

–12V

10µF

100pF

0.1µF

0.1µF OUTPUT

+12V0.01µF

+12V

1µF

There are some simple rules of thumb when designing an I-V converter where there is significant source capacitance (as with a photodiode) and bandwidth needs to be optimized. Consider the circuit of Figure 37. The high frequency noise gain (1 + C

S/CL

) is usually greater than five, so the AD745, with its higher slew rate and bandwidth is ideally suited to this application.

Here both the low current and low voltage noise of the AD745 can be taken advantage of, since it is desirable in some instances to have a large R

(which increases sensitivity to input current

noise) and, at the same time, operate the amplifier at high noise gain.

INPUT SOURCE: PHOTO DIODE, ACCELEROMETER, ECT.

AD745

Figure 37. A Model for an l-to-V Converter

In this circuit, the RF CS time constant limits the practical bandwidth over which flat response can be obtained, in fact:

fB≈

2πRFC

where:

= signal bandwidth

= gain bandwidth product of the amplifier

With C

≈ 1/(2 π RF CS) the net response can be adjusted to a

provide a two pole system with optimal flatness that has a corner frequency of f

. Capacitor CL adjusts the damping of the

circuit’s response. Note that bandwidth and sensitivity are directly traded off against each other via the selection of R example, a photodiode with C

= 300 pF and RF = 100 kΩ will

have a maximum bandwidth of 360 kHz when capacitor C

≈ 4.5 pF. Conversely, if only a 100 kHz bandwidth were

required, then the maximum value of R that of capacitor C

In either case, the AD745 provides impedance transformation,

still ≈ 4.5 pF.

would be 360 kΩ and

the effective transresistance, i.e., the I/V conversion gain, may be

Hz) as well as the high slew rate and

augmented with further gain. A wideband low noise amplifier such as the AD829 is recommended in this application.

This principle can also be used to apply the AD745 in a high performance audio application. Figure 38 shows that an I-V converter of a high performance DAC, here the AD1862, can be designed to take advantage of the low voltage noise of the AD745 (2.9 nV/Ï bandwidth provided by decompensation. This circuit, with component values shown, has a 12 dB/octave rolloff at 728 kHz, with a passband ripple of less than 0.001 dB and a phase deviation of less than 2 degrees @ 20 kHz.

. For

Figure 38. A High Performance Audio DAC Circuit

An important feature of this circuit is that high frequency energy, such as clock feedthrough, is shunted to common via a high quality capacitor and not the output stage of the amplifier, greatly reducing the error signal at the input of the amplifier and subsequent opportunities for intermodulation distortions.

√

BALANCED

2.9nV/

RTI NOISE VOLTAGE nV/

10 100 1000

UNBALANCED

√

INPUT CAPACITANCE – pF

Figure 39. RTI Noise Voltage vs. Input Capacitance

BALANCING SOURCE IMPEDANCES

As mentioned previously, it is good practice to balance the source impedances (both resistive and reactive) as seen by the inputs of the AD745. Balancing the resistive components will optimize dc performance over temperature because balancing will mitigate the effects of any bias current errors. Balancing input capacitance will minimize ac response errors due to the amplifier’s input capacitance and, as shown in Figure 39, noise performance will be optimized. Figure 40 shows the required external components for noninverting (A) and inverting (B) configurations.

REV. C

–11–

Page 12

AD745

C = C

R = R

FOR R >> R OR R

C = C II C

BFS

OUTPUT

AD745

NONINVERTING

CONNECTION

R = R II R

B1S

Figure 40. Optional External Components for Balancing Source Impedances

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

8-Pin Plastic Mini-DIP (N) Package

AD745

CONNECTION

OUTPUT

INVERTING

C1507–24–2/91

8-Pin Cerdip (Q) Package

0.005 (0.13) MIN 0.055 (1.35) MAX

0.405 (10.29) MAX

0.200

(5.08)

MAX

0.200 (5.08)

0.125 (3.18)

0.023 (0.58)

0.014 (0.36)

0.100 (2.54)

BSC

0.320 (8.13)

0.290 (7.37)

0.070 (1.78)

0.030 (0.76)

0.060 (1.52)

0.015 (0.38)

0.150 (3.81) MIN

0 - 15

SEATING PLANE

0.310 (7.87)

0.220 (5.59)

(7.87)

0.165 0.01 (4.19 0.25)

0.125 (3.18) MIN

0.015 (0.38)

0.008 (0.20)

0.31

O.018 0.003

(0.46 0.08)

0.39 (9.91) MAX

0.100 (2.54)

TYP

0.035 0.01 (0.89 0.25)

0.18 0.03

(4.57 0.76)

0.25

(6.35)

0.30 (7.62)

0.011 0.003 (0.28 0.08)

0 - 15

0.419 (10.64)

0.394 (10.01)

0.104 (2.64)

0.003 (2.36)

SEATING

PLANE

REF

16-Pin SOIC (R) Package

916

0.292 (7.42)

0.413 (10.49)

0.396 (10.11)

0.019 (0.483)

0.060

0.014 (0.356)

(1.27)

REF

0.300 (7.62)

0.011 (0.279)

0.004 (0.102)

0.0125 (0.32)

0.0091 (0.23)

0.0500 (1.27)

0.0157 (0.40)

0.0291 (0.74)

0.0098 (0.25)

0 - 8

x 45

SEE DETAIL ABOVE

PRINTED IN U.S.A.

–12–

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