Datasheet AD7441 Datasheet (Analog Devices)

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Page 1

Pseudo Differential Input, 1 MSPS,

10- and 12-Bit ADCs in an 8-Lead SOT-23

FEATURES

Fast throughput rate: 1 MSPS Specified for V

of 2.7 V to 5.25 V

Low power at max throughput rate:

4 mW max at 1 MSPS with V

9.25 mW max at 1 MSPS with V

= 3 V

= 5 V Pseudo differential analog input Wide input bandwidth:

70 dB SINAD at 100 kHz input frequency Flexible power/serial clock speed management No pipeline delays High speed serial interface:

SPI®-/QSPI™-/MICROWIRE™-/DSP-compatible Power-down mode: 1 µA max 8-lead SOT-23 and MSOP packages

APPLICATIONS

Transducer interface Battery-powered systems Data acquisition systems Portable instrumentation

GENERAL DESCRIPTION

The AD7441/AD74511 are, respectively, 10-bit and 12-bit high speed, low power, successive approximation (SAR) analog-todigital converters that feature a pseudo differential analog input. These parts operate from a single 2.7 V to 5.25 V power supply and achieve very low power dissipation at high throughput rates of up to 1 MSPS.

The AD7441/AD7451 contain a low noise, wide bandwidth, differential track-and-hold (T/H) amplifier that handles input frequencies up to 3.5 MHz. The reference voltage for these devices is applied externally to the V 100 mV to V

, depending on the power supply and what suits

the application.

The conversion process and data acquisition are controlled

using

and the serial clock, allowing the device to interface with microprocessors or DSPs. The input signals are sampled on the falling edge of CS when the conversion is initiated. The SAR architecture of these parts ensures that there are no pipeline delays.

Protected by U.S. Patent Number 6,681,332.

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

pin and can range from

REF

AD7441/AD7451

FUNCTIONAL BLOCK DIAGRAM

IN+

IN–

REF

AD7441/AD7451

T/H

GND

PRODUCT HIGHLIGHTS

1. Operation with 2.7 V to 5.25 V power supplies.

2. High throughput with low power consumption. With a 3 V

supply, the AD7441/AD7451 offer 4 mW maximum power consumption for a 1 MSPS throughput rate.

3. Pseudo differential analog input.

4. Flexible power/serial clock speed management. The

conversion rate is determined by the serial clock, allowing the power to be reduced as the conversion time is reduced through the serial clock speed increase. These parts also feature a shutdown mode to maximize power efficiency at lower throughput rates.

5. Variable voltage reference input.

6. No pipeline delays.

7. Accurate control of the sampling instant via a

once-off conversion control.

8. ENOB > 10 bits typically with 500 mV reference.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 Fax: 781.326.8703

www.analog.com

12-BIT

SUCCESSIVE

APPROXIMATION

ADC

CONTROL LOGIC

Figure 1.

SCLK SDATA CS

input and

03153-A-001

Page 2

AD7441/AD7451

TABLE OF CONTENTS

AD7451 Specifications..................................................................... 3

Analog Input Structure.............................................................. 14

AD7441 Specifications..................................................................... 5

Timing Specifications....................................................................... 7

Absolute Maximum Ratings............................................................ 8

ESD Caution.................................................................................. 8

Pin Configurations and Function Descriptions ........................... 9

Terminology .................................................................................... 10

Typical Performance Characteristics ........................................... 11

Theory of Operation ...................................................................... 13

Circuit Information.................................................................... 13

Converter Operation.................................................................. 13

ADC Transfer Function............................................................. 13

Typical Connection Diagram ................................................... 14

Analog Input............................................................................... 14

REVISION HISTORY

2/05—Rev. A to Rev. B

Changes to Ordering Guide...............................................................24

Digital Inputs .............................................................................. 15

Reference ..................................................................................... 15

Serial Interface............................................................................ 16

Modes of Operation ....................................................................... 18

Normal Mode.............................................................................. 18

Power-Down Mode.................................................................... 18

Power vs. Throughput Rate....................................................... 20

Microprocessor and DSP Interfacing ...................................... 20

Grounding and Layout Hints.................................................... 22

Evaluating Performance ............................................................ 22

Outline Dimensions....................................................................... 23

Ordering Guide .......................................................................... 24

2/04—Rev. 0 to Rev. A

Updated Format.................................................................... Universal

Changes to General Description .......................................................1

Changes to Table 1 Footnotes ............................................................4

Changes to Table 2 Footnotes ............................................................6

Changes to Table 3 Footnotes ............................................................7

Changes to Table 5 .............................................................................. 9

Updated Figures 7, 8, and 9.............................................................. 13

Changes to Figure 23.........................................................................16

Changes to Reference Section..........................................................17

Rev. B | Page 2 of 24

Page 3

AD7441/AD7451

AD7451 SPECIFICATIONS

VDD = 2.7 V to 5.25 V; f versions: −40°C to +85°C.

Table 1.

Parameter Test Conditions/Comments A Version B Version Unit

DYNAMIC PERFORMANCE fIN = 100 kHz

Signal-to-Noise Ratio (SNR)1 VDD = 2.7 V to 5.25 V 70 70 dB min Signal to (Noise + Distortion) (SINAD)1 VDD = 2.7 V to 3.6 V 69 69 db min V Total Harmonic Distortion (THD)1 V V Peak Harmonic or Spurious Noise1 V V Intermodulation Distortion (IMD)1 fa = 90 kHz; fb = 110 kHz

Second-Order Terms −80 −80 dB typ

Third-Order Terms −80 −80 dB typ Aperture Delay1 5 5 ns typ Aperture Jitter1 50 50 ps typ Full-Power Bandwidth @ −0.1 dB 2.5 2.5 MHz typ

DC ACCURACY

Resolution 12 12 Bits Integral Nonlinearity (INL)1 ±1.5 ±1 LSB max Differential Nonlinearity (DNL)1 Guaranteed no missed codes to 12 bits ±0.95 ±0.95 LSB max Offset Error1 ±3.5 ±3.5 LSB max Gain Error1 ±3 ±3 LSB max

ANALOG INPUT

Full-Scale Input Span V Absolute Input Voltage

IN+

VDD = 2.7 V to 3.6 V −0.1 to +0.4 −0.1 to +0.4 V

IN–

DC Leakage Current ±1 ±1 µA max Input Capacitance When in track and hold 30/10 30/10 pF typ

REFERENCE INPUT

Input Voltage

REF

DC Leakage Current ±1 ±1 µA max V

Input Capacitance When in track and hold 10/30 10/30 pF typ

REF

LOGIC INPUTS

Input High Voltage, V Input Low Voltage, V Input Current, IIN Typically 10 nA, VIN = 0 V or VDD ±1 ±1 µA max Input Capacitance, C

LOGIC OUTPUTS

Output High Voltage, VOH VDD = 4.75 V to 5.25 V; I

Output Low Voltage, VOL I Floating-State Leakage Current ±1 ±1 µA max Floating-State Output Capacitance5 10 10 pF max Output Coding

= 18 MHz; fS = 1 MSPS; V

SCLK

= 4.75 V to 5.25 V 70 70 dB min

= 2.7 V to 3.6 V; −78 dB typ −73 −73 dB max

= 4.75 V to 5.25 V; −80 dB typ −75 −75 dB max

= 2.7 V to 3.6 V; −80 dB typ −73 −73 dB max

= 4.75 V to 5.25 V; −82 dB typ −75 −75 dB max

1, 2

@ −3 dB 20 20 MHz typ

− V

IN+

= 4.75 V to 5.25 V −0.1 to +1.5 −0.1 to +1.5 V

±1% tolerance for specified performance

2.4 2.4 V min

INH

0.8 0.8 V max

INL

10 10 pF max

= 2.7 V to 3.6 V; I

= 200 µA 0.4 0.4 V max

SINK

= 2.5 V; TA = T

REF

IN–

SOURCE

to T

MIN

= 200 µA 2.8 2.8 V min

SOURCE

, unless otherwise noted. Temperature ranges for A, B

MAX

= 200 µA 2.4 2.4 V min

REF

2.54 V

2.5

Straight (natural) binary

REF

Straight (natural) binary

Rev. B | Page 3 of 24

Page 4

AD7441/AD7451

Parameter Test Conditions/Comments A Version B Version Unit

CONVERSION RATE

Conversion Time 888 ns with an 18 MHz SCLK 16 16 SCLK cycles Track-and-Hold Acquisition Time1 Sine wave input 250 250 ns max

Full-scale step input 290 290 ns max

Throughput Rate 1 1 MSPS max

POWER REQUIREMENTS

VDD 2.7/5.25 2.7/5.25 V min/max

6, 7

Normal Mode (Static) SCLK on or off 0.5 0.5 mA typ Normal Mode (Operational) VDD = 4.75 V to 5.25 V 1.95 1.95 mA max

Full Power-Down Mode SCLK on or off 1 1 µA max

Power Dissipation

Normal Mode (Operational) VDD = 5 V; 1.55 mW typ for 100 ksps6 9.25 9.25 mW max V Full Power-Down VDD = 5 V; SCLK on or off 5 5 µW max

See section. Terminology

Analog inputs with slew rates exceeding 27 V/µs (full-scale input sine wave > 3.5 MHz) within the acquisition time could cause the converter to return an incorrect

result.

A small dc input is applied to V

The AD7451 is functional with a reference input in the range of 100 mV to VDD.

Guaranteed by characterization.

See the Power vs. Throughput section.

Measured with a full-scale dc input.

to provide a pseudo ground for V

IN–

= 2.7 V to 3.6 V 1.45 1.45 mA max

= 3 V; 0.6 mW typ for 100 ksps6 4 4 mW max

= 3 V; SCLK on or off 3 3 µW max

IN+

Rev. B | Page 4 of 24

Page 5

AD7441/AD7451

AD7441 SPECIFICATIONS

VDD = 2.7 V to 5.25 V; f B version: −40°C to +85°C.

Table 2.

Parameter Test Conditions/Comments B Version Unit

DYNAMIC PERFORMANCE fIN = 100 kHz

Signal to (Noise + Distortion) (SINAD)1 61 dB min Total Harmonic Distortion (THD)1 2.7 V to 3.6 V; −77 dB typ −72 dB max

4.75 V to 5.25 V; −79 dB typ −73 dB max Peak Harmonic or Spurious Noise1 2.7 V to 3.6 V; −80 dB typ −72 dB max

4.75 V to 5.25 V; −82 dB typ −74 dB max Intermodulation Distortion (IMD)

Second-Order Terms −80 dB typ

Third-Order Terms −80 dB typ Aperture Delay1 5 ns typ Aperture Jitter1 50 ps typ Full-Power Bandwidth1, 2 @ −3 dB 20 MHz typ

@ −0.1 dB 2.5 MHz typ DC ACCURACY

Resolution 10 Bits Integral Nonlinearity (INL) Differential Nonlinearity (DNL)1 Guaranteed no missed codes to 10 bits ±0.5 LSB max Offset Error1 ±1 LSB max Gain Error1 ±1 LSB max

ANALOG INPUT

Full-Scale Input Span V Absolute Input Voltage

IN+

VDD = 2.7 V to 3.6 V −0.1 to +0.4 V

IN–

V DC Leakage Current ±1 µA max Input Capacitance When in track and hold 30/10 pF typ

REFERENCE INPUT

Input Voltage

REF

DC Leakage Current ±1 µA max V

Input Capacitance When in track and hold 10/30 pF typ

REF

LOGIC INPUTS

Input High Voltage, V Input Low Voltage, V Input Current, I

Input Capacitance, C

LOGIC OUTPUTS

Output High Voltage, VOH VDD = 4.75 V to 5.25 V ; I

Output Low Voltage, VOL I Floating-State Leakage Current ±1 µA max Floating-State Output Capacitance5 10 pF max Output Coding Straight (natural) binary

= 18 MHz; fS = 1 MSPS; V

SCLK

fa = 90 kHz, fb = 110 kHz

±0.5 LSB max

− V

IN+

= 4.75 V to 5.25 V −0.1 to +1.5 V

±1% tolerance for specified performance

2.4 V min

INH

0.8 V max

INL

Typically 10 nA, VIN = 0 V or V

10 pF max

= 2.7 V to 3.6 V; I

= 200 µA 0.4 V max

SINK

= 2.5 V; TA = T

REF

IN–

SOURCE

to T

MIN

= 200 µA 2.8 V min

SOURCE

, unless otherwise noted. Temperature range for

MAX

= 200 µA 2.4 V min

REF

2.5

±1 µA max

Rev. B | Page 5 of 24

Page 6

AD7441/AD7451

Parameter Test Conditions/Comments B Version Unit

CONVERSION RATE

Conversion Time 888 ns with an 18 MHz SCLK 16 SCLK cycles Track-and-Hold Acquisition Time1 Sine wave input 250 ns max Step input 290 ns max Throughput Rate 1 MSPS max

POWER REQUIREMENTS

VDD 2.7/5.25 V min/max

6, 7

Normal Mode (Static) SCLK on or off 0.5 mA typ Normal Mode (Operational) VDD = 4.75 V to 5.25 V 1.95 mA max V Full Power-Down Mode SCLK on or off 1 µA max

Power Dissipation

Normal Mode (Operational) VDD = 5 V; 1.55 mW typ for 100 ksps6 9.25 mW max V Full Power-Down VDD = 5 V; SCLK on or off 5 µW max

See the Terminology section.

Analog inputs with slew rates exceeding 27 V/µs (full-scale input sine wave > 3.5 MHz) within the acquisition time may cause the converter to return an incorrect

result.

A small dc input is applied to V

The AD7441 is functional with a reference input in the range 100 mV to VDD.

Guaranteed by characterization.

See the Power vs. Throughput section.

Measured with a full-scale dc input.

to provide a pseudo ground for V

IN–

= 2.7 V to 3.6 V 1.25 mA max

= 3 V; 0.6 mW typ for 100 ksps6 4 mW max

= 3 V; SCLK on or off 3 µW max

IN+

Rev. B | Page 6 of 24

Page 7

AD7441/AD7451

TIMING SPECIFICATIONS

VDD = 2.7 V to 5.25 V; f

Table 3.

Parameter Limit at T

10 kHz min

SCLK

CONVERT

60 ns min

QUIET

18 MHz max

16 × t

888 ns max

t1 10 ns min t2 10 ns min

20 ns max

t4 40 ns max Data access time after SCLK falling edge t5 0.4 t t6 0.4 t

SCLK

t7 10 ns min SCLK edge to data valid hold time

POWER-UP

10 ns min SCLK falling edge to SDATA three-state enabled 35 ns max SCLK falling edge to SDATA three-state enabled

1 µs max Power-up time from full power-down

Guaranteed by characterization. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. See , , and

the section.

Serial Interface

Mark/space ratio for the SCLK input is 40/60 to 60/40.

Measured with the load circuit of and defined as the time required for the output to cross 0.8 V or 2.4 V with VDD = 5 V and the time required for an output to

cross 0.4 V or 2.0 V for V

t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 4. The measured number is then extrapolated

back to remove the effects of charging or discharging the 25 pF capacitor. This means that the time, t time of the part and is independent of the bus loading.

See section. Power-Up Time

= 18 MHz; fS = 1 MSPS; V

SCLK

, T

MIN

MAX

SCLK

ns min SCLK high pulse width ns min SCLK low pulse width

Figure 4

= 3 V.

= 2.5 V; TA = T

REF

Unit Description

= 1/f

SCLK

Minimum quiet time between the end of a serial read and the next falling edge of Minimum CS

falling edge to SCLK falling edge set-up time

Delay from

MIN

to T

, unless otherwise noted.

MAX

pulse width

falling edge until SDATA three-state disabled

, quoted in the timing characteristics, is the true bus relinquish

Figure 2 Figure 3

SCLK

DAT

12345 13141516

0 0 0 0 DB11 DB10 DB2 DB1 DB0

4 LEADING ZEROS THREE-STATE

CONVERT

QUIET

03153-A-002

Figure 2. AD7451 Serial Interface Timing Diagram

SCLK

SDATA

12345 13141516

0 0 0 0 DB9 DB8 DB0 0 0

4 LEADING ZEROS 2 TRAILING ZEROS

Figure 3. AD7441 Serial Interface Timing Diagram

CONVERT

Rev. B | Page 7 of 24

QUIET

THREE-STATE

03153-A-003

Page 8

AD7441/AD7451

ABSOLUTE MAXIMUM RATINGS

Table 4. TA = 25°C, unless otherwise noted.

Parameter Rating

VDD to GND −0.3 V to +7 V V

to GND −0.3 V to VDD + 0.3 V

IN+

to GND −0.3 V to VDD + 0.3 V

IN–

Digital Input Voltage to GND −0.3 V to +7 V Digital Output Voltage to GND −0.3 V to VDD + 0.3 V V

to GND −0.3 V to VDD + 0.3 V

REF

Input Current to any Pin Except Supplies1±10 mA Operating Temperature Range

−40°C to +85°C

Commercial (A, B Version) Storage Temperature Range −65°C to +150°C Junction Temperature 150°C θJA Thermal Impedance 205.9°C/W (MSOP)

211.5°C/W (SOT-23)

θJC Thermal Impedance 43.74°C/W (MSOP)

Lead Temperature, Soldering

91.99°C/W (SOT-23)

Vapor Phase (60 sec) 215°C

Infrared (15 sec) 220°C ESD 1 kV

Transient currents of up to 100 mA do not cause SCR latch-up.

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Figure 4. Load Circuit for Digital Output Timing Specifications

TO OUTPUT

25pF

1.6mA I

200µAI

1.6V

03153-A-004

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Rev. B | Page 8 of 24

Page 9

AD7441/AD7451

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

SCLK

SDATA

AD7441/

AD7451

TOP VIEW

(Not to Scale)

REF

IN+

IN–

GND

Figure 5. 8-Lead SOT-23

Table 5. 8-Lead Pin Function Descriptions

Mnemonic Description

REF

Reference Input for the AD7441/AD7451. An external reference in the range of 100 mV to VDD must be applied to this input. The specified reference input is 2.5 V. This pin should be decoupled to GND with a capacitor of at least 0.1 µF.

Noninverting Analog Input.

IN+

IN–

GND

SDATA

Inverting Input. This pin sets the ground reference point for the V pseudo ground.

Analog Ground. Ground reference point for all circuitry on the AD7441/AD7451. All analog input signals and any external reference signal should be referred to this GND voltage.

Chip Select. Active low logic input. This input provides the dual function of initiating a conversion on the AD7441/AD7451 and framing the serial data transfer.

Serial Data, Logic Output. The conversion result from the AD7441/AD7451 is provided on this output as a serial data stream. The bits are clocked out on the falling edge of the SCLK input. The data stream of the AD7451 consists of four leading zeros followed by the 12 bits of conversion data that are provided MSB first; the data stream of the AD7441 consists of four leading zeros, followed by the 10 bits of conversion data, followed by two trailing zeros. In both cases, the output coding is straight (natural) binary.

SCLK

VDD

Serial Clock, Logic Input. SCLK provides the serial clock for accessing data from the part. This clock input is also used as the clock source for the conversion process.

Power Supply Input. VDD is 2.7 V to 5.25 V. This supply should be decoupled to GND with a 0.1 µF capacitor and a 10 µF tantalum capacitor.

REF

AD7441/

IN+

AD7451

IN–

TOP VIEW

(Not to Scale)

GND

03153-A-005

8 7 6 5

SCLK SDATA CS

03153-A-006

Figure 6. 8-Lead MSOP

input. Connect to ground or to a dc offset to provide a

IN+

Rev. B | Page 9 of 24

Page 10

AD7441/AD7451

TERMINOLOGY

Signal to (Noise + Distortion) Ratio (SINAD) This is the measured ratio of SINAD at the output of the ADC. The signal is the rms amplitude of the fundamental. Noise is the sum of all nonfundamental signals up to half the sampling frequency (f number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. The theoretical SINAD ratio for an ideal N-bit converter with a sine wave input is given by

Therefore, for 12-bit converters, the SINAD is 74 dB; for10-bit converters, 62 dB.

Total Harmonic Distortion (THD) Total harmonic distortion is the ratio of the rms sum of harmonics to the fundamental. In the AD7441/AD7451, THD is

where:

is the rms amplitude of the fundamental.

, V3, V4, V5 and V6 are the rms amplitudes of the second to the

sixth harmonics.

Peak Harmonic or Spurious Noise Peak harmonic (spurious noise) is defined as the ratio of the rms value of the next largest component in the ADC output spectrum (up to f fundamental. Normally, the value of this specification is determined by the largest harmonic in the spectrum, but for ADCs where the harmonics are buried in the noise floor, it is a noise peak.

Intermodulation Distortion With inputs consisting of sine waves at two frequencies, fa and fb, an active device with nonlinearities creates distortion products at sum and difference frequencies of mfa ± nfb where m, n = 0, 1, 2, 3 and so on. Intermodulation distortion terms are those in which neither m nor n are equal to zero. For example, the second-order terms include (fa + fb) and (fa − fb), while the third-order terms include (2fa + fb), (2fa − fb), (fa + 2fb) and (fa − 2fb).

/2), excluding dc. The ratio is dependent on the

Signal to (Noise + Distortion) = (6.02 N + 1.76) dB

22222

++++

VVVVV

THD

()

log20dB

/2, excluding dc) to the rms value of the

65432

specified separately. The calculation of the intermodulation distortion is as per the THD specification where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals expressed in dB.

Aperture Delay This is the amount of time from the leading edge of the sampling clock until the ADC actually takes the sample.

Aperture Jitter This is the sample to sample variation in the effective point in time at which the actual sample is taken.

Full Power Bandwidth The full power bandwidth of an ADC is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 0.1 dB or 3 dB for a full-scale input.

Integral Nonlinearity (INL) This is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function.

Differential Nonlinearity (DNL) This is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC.

Offset Error This is the deviation of the first code transition (000…000 to 000…001) from the ideal (i.e., AGND + 1 LSB).

Gain Error This is the deviation of the last code transition (111…110 to 111…111) from the ideal (i.e., V

− 1 LSB) after the offset

REF

error has been adjusted out.

Track-and-Hold Acquisition Time The track-and-hold acquisition time is the minimum time required for the track-and-hold amplifier to remain in track mode for its output to reach and settle to within 0.5 LSB of the applied input signal.

Power Supply Rejection Ratio (PSRR) The power supply rejection ratio is defined as the ratio of the power in the ADC output at full-scale frequency, f, to the power of a 100 mV p-p sine wave applied to the ADC V

supply of

frequency fs. The frequency of this input varies from 1 kHz to 1 MHz.

PSRR (dB) = 10 log (Pf/Pfs)

The AD7441/AD7451 is tested using the CCIF standard where two input frequencies near the top end of the input bandwidth are used. In this case, the second-order terms are usually distanced in frequency from the original sine waves while the third-order terms are usually at a frequency close to the input frequencies. As a result, the second- and third-order terms are

Rev. B | Page 10 of 24

Pf is the power at frequency f in the ADC output; Pfs is the power at frequency fs in the ADC output.

Page 11

AD7441/AD7451

TYPICAL PERFORMANCE CHARACTERISTICS

Default conditions: TA = 25°C, fS = 1 MSPS, f

= 4.75V

SINAD (dB)

10 100 1000

FREQUENCY (kHz)

= 3.6V

= 2.7V

= 18 MHz, VDD = 2.7 V to 5.25 V, V

SCLK

VDD = 5.25V

03153-A-007

= 2.5 V, unless otherwise noted.

REF

1.0

0.8

0.6

0.4

0.2

–0.2

DNL ERROR (LSB)

–0.4 –0.6

–0.8

–1.0

0 1024 2048 3072

CODE

03153-A-010

4096

Figure 7. SINAD vs. Analog Input Frequency for the AD7451 for

Various Supply Voltages

100mV p-p SINE WAVE ON V NO DECOUPLING ON V

–20

–40

–60

PSRR (dB)

–80

–100

–120

0 100 200 300 400 500 600 700 800 900 1000

SUPPLY RIPPLE FREQUENCY (kHz)

VDD = 3V

= 5V

03153-A-008

Figure 8. PSRR vs. Supply Ripple Frequency Without Supply Decoupling

–20

–40

–60

–80

SNR (dB)

–100

–120

–140

0 100 200

FREQUENCY (kHz)

8192 POINT FFT

SAMPLE

= 100kSPS

SINAD = 71dB THD = –82dB SFDR = –83dB

300 400

= 1MSPS

03153-A-009

500

Figure 10. Typical DNL for the AD7451 for V

= 5 V

1.0

0.8

0.6

0.4

0.2

–0.2

INL ERROR (LSB)

–0.4 –0.6

–0.8

–1.0

0 1024 2048 3072

Figure 11. Typical INL for the AD7451 for V

10,000

9,000

8,000

7,000

6,000

5,000

COUNTS

4,000

3,000

2,000

1,000

2046 2047 2048 2049 2050 2051

27 CODES 24 CODES

CODE

9949

CODES

= 5 V

03153-A-011

4096

03153-A-012

Figure 9. AD7451 Dynamic Performance for V

= 5 V

Figure 12. Histogram of 10,000 Conversions of a DC Input for the AD7451

Rev. B | Page 11 of 24

Page 12

AD7441/AD7451

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

CHANGE IN DNL (LSB)

–0.5

–1.0

01234

Figure 13. Change in DNL vs. V

CHANGE IN INL (LSB)

–1

–2

01234

Figure 14. Change in INL vs. V

EFFECTIVE NUMBER OF BITS

012345

VDD = 3V

= 5V

Figure 15. ENOB vs. V

–20

–40

–60

–80

POSITIVE DNL

NEGATIVE DNL

03153-A-013

(V)

REF

for VDD = 5 V

REF

POSITIVE DNL

NEGATIVE DNL

03153-A-014

(V)

REF

for VDD = 5 V

REF

03153-A-015

(V)

REF

for V

= 5 V and 3V

SNR (dB)

–100

–120

–140

0 100 200 300 400 500

(V)

REF

Figure 16. AD7441 Dynamic Performance

0.5

0.4

0.3

0.2

0.1

–0.1

DNL ERROR (LSB)

–0.2

–0.3

–0.4

–0.5

0 256 512 768 1024

CODE

Figure 17. Typical DNL for the AD7441

0.5

0.4

0.3

0.2

0.1

–0.1

INL ERROR (LSB)

–0.2

–0.3

–0.4

–0.5

0 256 512 768 1024

Figure 18. Typical INL for the AD7441

CODE

8192 POINT FFT

= 1MSPS

SAMPLE

= 100kSPS

SINAD = 61.7dB THD = –81.7dB SFDR = –82dB

03153-A-016

03153-A-017

03153-A-018

Rev. B | Page 12 of 24

Page 13

AD7441/AD7451

THEORY OF OPERATION

CIRCUIT INFORMATION

The AD7441/AD7451 are 10-bit and 12-bit, fast, low power, single-supply, successive approximation analog-to-digital converters (ADCs) with a pseudo differential analog input. They operate with a single 2.7 V to 5.25 V power supply and are capable of throughput rates up to 1 MSPS when supplied with an 18 MHz SCLK. They require an external reference to be applied to the V

REF

pin.

The AD7441/AD7451 have a successive approximation (SAR) ADC, an on-chip differential track-and-hold amplifier, and a serial interface housed in either an 8-lead SOT-23 or an MSOP package. The serial clock input accesses data from the part and provides the clock source for the successive approximation ADC. The AD7441/AD7451 feature a power-down option for reduced power consumption between conversions. The powerdown feature is implemented across the standard serial interface, as described in the Modes of Operation section.

CONVERTER OPERATION

The AD7441/AD7451 are successive approximation ADCs based around two capacitive DACs. Figure 19 and Figure 20 show simplified schematics of the ADC in the acquisition and conversion phase, respectively. The ADC is comprised of control logic, an SAR, and two capacitive DACs. In Figure 19 (acquisition phase), SW3 is closed; SW1 and SW2 are in Position A, the comparator is held in a balanced condition, and the sampling capacitor arrays acquire the differential signal on the input.

CAPACITIVE

DAC

IN+

IN–

SW1

SW2

REF

SW3

Figure 19. ADC Acquisition Phase

COMPARATOR

CONTROL

LOGIC

CAPACITIVE

DAC

03153-A-019

CAPACITIVE

DAC

IN+

IN–

SW1

SW2

REF

SW3

COMPARATOR

CONTROL

LOGIC

CAPACITIVE

DAC

03153-A-020

Figure 20. ADC Conversion Phase

ADC TRANSFER FUNCTION

The output coding for the AD7441/AD7451 is straight (natural) binary. The designed code transitions occur at successive LSB values (1 LSB, 2 LSB, and so on). The LSB size of the AD7451 is

/4096, and the LSB size of the AD7441 is V

REF

ideal transfer characteristic of the AD7441/AD7451 is shown in Figure 21.

1LSB = V

111...11

111...10

111...00

011...11

ADC CODE

000...10

000...01

000...00

1LSB = V

Figure 21. AD7441/AD7451 Ideal Transfer Characteristic

/4096 (AD7451)

REF

/1024 (AD7441)

REF

ANALOG INPUT

REF

– 1LSB1LSB

/1024. The

03153-A-021

When the ADC starts a conversion (Figure 20), SW3 opens and SW1 and SW2 move to Position B, causing the comparator to become unbalanced. Both inputs are disconnected once the conversion begins. The control logic and the charge redistribution DACs are used to add and subtract fixed amounts of charge from the sampling capacitor arrays to bring the comparator back into a balanced condition. When the comparator is rebalanced, the conversion is complete. The control logic generates the ADC’s output code. The output impedances of the sources driving the V

and the V

IN+

IN–

pins must be matched; otherwise the two inputs have different settling times, resulting in errors.

Rev. B | Page 13 of 24

Page 14

AD7441/AD7451

–

TYPICAL CONNECTION DIAGRAM

Figure 22 shows a typical connection diagram for the device. In this setup the GND pin is connected to the analog ground plane of the system. The V

pin is connected to the AD780, a 2.5 V

REF

decoupled reference source. The signal source is connected to the V connected to the V V

analog input via a unity gain buffer. A dc voltage is

IN+

pin to provide a pseudo ground for the

IN–

input. The VDD pin should be decoupled to AGND with a

IN+

10 µF tantalum capacitor in parallel with a 0.1 µF ceramic capacitor. The reference pin should be decoupled to AGND with a capacitor of at least 0.1 µF. The conversion result is output in a 16-bit word with 4 leading zeros followed by the MSB of the 12-bit or 10-bit result. The 10-bit result of the AD7441 is followed by 2 trailing zeros.

2.7V TO 5.25V

SCLK

GND

SUPPLY

SERIAL

INTERFACE

µC/µ

PSDATA

03153-A-022

AD7441/

AD7451

2.5V

AD780

0.1µF

0.1

IN+

IN–

REF

p-p

DC INPUT VOLTAGE

Figure 22. Typical Connection Diagram

ANALOG INPUT

The AD7441/AD7451 has a pseudo differential analog input. The V amplitude of V the part. A dc input is applied to the V this input provides an offset from ground or a pseudo ground for the V input signal ground from the ADC’s ground, allowing dc common-mode voltages to be cancelled.

input is coupled to the signal source and must have an

IN+

p-p to make use of the full dynamic range of -

REF

. The voltage applied to

IN–

input. Pseudo differential inputs separate the analog

IN+

2.5V

1.25V 0V

IN+

AD7441/

AD7451

IN–

REF

03153-A-023

1.25V

IN+

0.1µF

EXTERNAL V

(2.5V)

REF

Figure 23. Op Amp Configuration to Level Shift a Bipolar Input Signal

ANALOG INPUT STRUCTURE

Figure 24 shows the equivalent circuit of the analog input structure of the AD7441/AD7451. The four diodes provide ESD protection for the analog inputs. Care must be taken to ensure that the analog input signals never exceed the supply rails by more than 300 mV. This causes these diodes to become forward-biased and start conducting into the substrate. These diodes can conduct up to 10 mA without causing irreversible damage to the part. The capacitors, C1 in Figure 24, are typically 4 pF and can be attributed primarily to pin capacitance. The resistors are lumped components made up of the on resistance of the switches. The value of these resistors is typically about 100 Ω. The capacitors, C2, are the ADC’s sampling capacitors and have a capacitance of 16 pF typically.

For ac applications, removing high frequency components from the analog input signal through the use of an RC low-pass filter on the relevant analog input pins is recommended. In applications where harmonic distortion and the signal-to-noise ratio are critical, the analog input should be driven from a low impedance source. Large source impedances significantly affect the ac performance of the ADC, which may necessitate the use of an input buffer amplifier. The choice of the amp is a function of the particular application.

Because the ADC operates from a single supply, it is necessary to level shift ground-based bipolar signals to comply with the input requirements. An op amp (for example, the AD8021) can

IN+

be configured to rescale and level shift a ground based (bipolar) signal so that it is compatible with the input range of the

AD7441/AD7451. (See Figure 23.)

When a conversion takes place, the pseudo ground corresponds to 0, and the maximum analog input corresponds to 4096 for the AD7451 and 1024 for the AD7441.

IN–

03153-A-024

Figure 24. Equivalent Analog Input Circuit;

Conversion Phase—Switches Open;

Track Phase—Switches Closed

Rev. B | Page 14 of 24

Page 15

AD7441/AD7451

When no amplifier is used to drive the analog input, the source impedance should be limited to low values. The maximum source impedance depends on the amount of total harmonic distortion that can be tolerated. The THD increases as the source impedance increases and performance degrades. Figure 25 shows a graph of THD vs. analog input signal frequency for different source impedances.

TA = 25°C V

= 5V

–10

–20

–30

–40

–50

THD (dB)

–60

–70

–80

–90

–100

10k 100k 1M

INPUT FREQUENCY (Hz)

100

200

Ω

03153-A-025

Figure 25. THD vs. Analog Input Frequency for Various Source Impedances

Figure 26 shows a graph of THD vs. analog input frequency for various supply voltages, while sampling at 1 MSPS with an SCLK of 18 MHz. In this case the source impedance is 10 Ω.

–50

TA = 25°C

–55

–60

–65

= 2.7V

–70

THD (dB)

–75

–80

–85

–90

10 100 1000

Figure 26. THD vs. Analog Input Frequency for Various Supply Voltages

= 3.6V

= 4.75V

INPUT FREQUENCY (kHz)

= 5.25V

03153-A-026

DIGITAL INPUTS

The digital inputs applied to the AD7441/AD7451 are not limited by the maximum ratings that limit the analog inputs. Instead the digital inputs applied—that is, go to 7 V and are not restricted by the V

and SCLK—can

+ 0.3 V limits as on

the analog input. The main advantage of the inputs not being restricted to the V sequencing issues are avoided. If

, there is no risk of latch-up as there would be on the analog

inputs if a signal greater than 0.3 V were applied prior to V

+ 0.3 V limit is that power supply

or SCLK are applied before

REFERENCE

An external source is required to supply the reference to the AD7441/AD7451. This reference input can range from 100 mV

. The specified reference is 2.5 V for the power supply

to V

range 2.7 V to 5.25 V. The reference input chosen for an application should never be greater than the power supply. Errors in the reference source result in gain errors in the AD7441/AD7451 transfer function and add to the specified full-scale errors of the part. A capacitor of at least 0.1 µF should be placed on the V the AD7441/AD7451 include the AD780 and the ADR421. Figure 27 shows a typical connection diagram for the V

0.1µF

*ADDITIONAL PINS OMITTED FOR CLARITY

10nF 0.1µF

Figure 27. Typical V

pin. Suitable reference sources for

REF

AD780

TEMP

GND

NC = NO CONNECT

Connection Diagram for VDD = 5 V

REF

OPSEL

OUT

TRIM

2.5V

6 5

REF

AD7441/

AD7451*

0.1µF

pin.

REF

03153-A-027

Rev. B | Page 15 of 24

Page 16

AD7441/AD7451

SERIAL INTERFACE

Figure 2 and Figure 3 show detailed timing diagrams for the serial interface of the AD7451 and the AD7441, respectively. The serial clock provides the conversion clock and also controls the transfer of data from the device during conversion. initiates the conversion process and frames the data transfer. The falling edge of and takes the bus out of three-state. The analog input is sampled and the conversion initiated at this point. The conversion requires 16 SCLK cycles to complete.

Once 13 SCLK falling edges have occurred, the track-and-hold goes back into track mode on the next SCLK rising edge, as shown at Point B in Figure 2 and Figure 3. On the 16th SCLK falling edge, the SDATA line goes back into three-state.

If the rising edge of the conversion is terminated and the SDATA line goes back into three-state.

The conversion result from the AD7441/AD7451 is provided on the SDATA output as a serial data stream. The bits are clocked out on the falling edge of the SCLK input. The data stream of the AD7451 consists of four leading zeros, followed by 12 bits of conversion data, provided MSB first. The data stream of the AD7441 consists of 4 leading zeros, followed by the 10 bits of conversion data, followed by 2 trailing zeros, which is also provided MSB first. In both cases, the output coding is straight (natural) binary.

puts the track-and-hold into hold mode

occurs before 16 SCLKs have elapsed,

Sixteen serial clock cycles are required to perform a conversion

and to access data from the AD7441/AD7451. provides the first leading zero to be read in by the DSP or the microcontroller. The remaining data is then clocked out on the subsequent SCLK falling edges, beginning with the second leading zero. Thus, the first falling clock edge on the serial clock provides the second leading zero. The final bit in the data transfer is valid on the 16th falling edge, having been clocked out on the previous (15th) falling edge. Once the conversion is complete and the data has been accessed after the 16 clock cycles, it is important to ensure that, before the next conversion is initiated, enough time is left to meet the acquisition and quiet-time specifications (see the timing examples that follow). To achieve 1 MSPS with an 18 MHz clock, an 18-clock burst performs the conversion and leaves enough time before the next conversion for the acquisition and quiet time.

In applications with slower SCLKs, it could be possible to read in data on each SCLK rising edge; that is, the first rising edge of

SCLK after the provided and the 15th SCLK edge would have DB0 provided.

falling edge would have the leading zero

going low

Rev. B | Page 16 of 24

Page 17

AD7441/AD7451

Timing Example 1

Having F

= 18 MHz and a throughput rate of 1 MSPS gives a

SCLK

cycle time of

Timing Example 2

Having F

= 5 MHz and a throughput rate of 315 kSPS gives a

SCLK

cycle time of

1/Throughput = 1/1000000 = 1 µs

A cycle consists of

Therefore if t

+ 12.5 (1/F

= 10 ns, then

10 ns + 12.5 (1/18 MHz) + t

= 296 ns

ACQ

SCLK

) + t

ACQ

= 1 µs

ACQ

This 296 ns satisfies the requirement of 290 ns for t

From Figure 28, t

comprises

ACQ

2.5 (1/F

SCLK

) + t8 = t

QUIET

where t8 = 35 ns. This allows a value of 122 ns for t satisfying the minimum requirement of 60 ns.

ACQ

QUIET

1/Throughput = 1/315000 = 3.174 µs

A cycle consists of

+ 12.5 (1/F

Therefore if t

is 10 ns, then

10 ns + 12.5 (1/5 MHz) + t

This 664 ns satisfies the requirement of 290 ns for t

From Figure 28, t

comprises

ACQ

2.5 (1/F

where t8 = 35 ns. This allows a value of 129 ns for t

SCLK

= 664 ns

ACQ

SCLK

) + t

ACQ

) + t8 = t

= 3.174 µs

ACQ

QUIET

ACQ

QUIET

satisfying the minimum requirement of 60 ns.

As in this example and with other slower clock values, the signal may already be acquired before the conversion is complete, but it is still necessary to leave 60 ns minimum t

QUIET

between conversions. In Example 2, the signal should be fully acquired at approximately Point C in Figure 28.

SCLK

10ns

12345 13141516

12.5(1/F

SCLK

CONVERT

)

1/THROUGHPUT

B C

ACQUISITION

QUIET

03153-A-028

Figure 28. Serial Interface Timing Example

Rev. B | Page 17 of 24

Page 18

AD7441/AD7451

MODES OF OPERATION

The operating mode of the AD7441/AD7451 is selected by

controlling the logic state of the There are two operating modes: normal mode and power-down mode. The point at which

CS has been initiated determines whether the part enters powerdown mode. Similarly, if already in power-down, whether the device returns to normal operation or remains in

power-down. These modes provide flexible power management options that can optimize the power dissipation/throughput rate ratio for differing application requirements.

NORMAL MODE

This mode is intended for fastest throughput rate performance. The user does not have to worry about any power-up times with the AD7441/AD7451 remaining fully powered up all the time. Figure 29 shows the general diagram of the operation of the AD7441/AD7451 in this mode. The conversion is initiated on the falling edge of section. To ensure that the part remains fully powered up, must remain low until at least 10 SCLK falling edges have elapsed after the falling edge of

is brought high any time after the 10th SCLK falling edge, but before the 16th SCLK falling edge, the part remains powered up but the conversion is terminated and SDATA goes back into three-state. Sixteen serial clock cycles are required to complete the conversion and access the complete conversion

result.

may idle high until the next conversion or may idle low until sometime prior to the next conversion. Once a data transfer is complete—that is, when SDATA has returned to three-state—another conversion can be initiated after the quiet time, t

QUIET

SCLK

SDATA

, as described in the Serial Interface

, has elapsed by again bringing CS low.

110

4 LEADING ZEROS + CONVERSION RESULT

Figure 29. Normal Mode Operation

signal during a conversion.

is pulled high after the conversion

controls

03153-A-029

POWER-DOWN MODE

This mode is intended for use in applications where slower throughput rates are required; either the ADC is powered down between each conversion or a series of conversions may be performed at a high throughput rate and the ADC is then powered down for a relatively long duration between these bursts of conversions. When the AD7441/AD7451 is in powerdown mode, all analog circuitry is powered down. For the AD7441/AD7451 to enter power-down mode, the conversion

process must be interrupted by bringing the second falling edge of SCLK and before the 10th falling edge of SCLK, as shown in Figure 30.

Once

has been brought high in this window of SCLKs, the part enters power-down and the conversion that was initiated by the falling edge of

is terminated and SDATA goes back into three-state. The time from the rising edge of three-state enabled is never greater than t Specifications). If

is brought high before the second SCLK falling edge, the part remains in normal mode and does not power down. This avoids accidental power-down due to glitches

on the

line.

To exit power-down mode and power up the AD7441/AD7451 again, a dummy conversion is performed. On the falling edge of CS

the device begins to power up and continues to power up as

long as

is held low until after the falling edge of the 10th SCLK. The device is fully powered up after 1 µs has elapsed and, as shown in Figure 31, valid data results from the next conversion.

SCLK

DAT

Figure 30. Entering Power-Down Mode

high anywhere after

(see the Timing

THREE-STATE

to SDATA

03153-A-030

Rev. B | Page 18 of 24

Page 19

AD7441/AD7451

POWER-UP

10 16 1 10 16

THIS PART IS FULLY POWERED UP WITH V

FULLY ACQUIRED

SCLK

PART BEGINS TO POWER UP

SDATA

INVALID DATA VALID DATA

Figure 31. Exiting Power-Down Mode

is brought high before the 10th falling edge of SCLK, the

If AD7441/AD7451 again goes back into power-down. This avoids accidental power-up due to glitches on the inadvertent burst of eight SCLK cycles while

is low. So

line or an

although the device may begin to power up on the falling edge

, it again powers down on the rising edge of CS as long as

it occurs before the 10th SCLK falling edge.

Power-Up Time

The power-up time of the AD7441/AD7451 is typically 1 µs, which means that with any frequency of SCLK up to 18 MHz, one dummy cycle is always sufficient to allow the device to power up. Once the dummy cycle is complete, the ADC is fully powered up and the input signal is acquired properly. The quiet time, t

, must still be allowed—from the point at which the

QUIET

bus goes back into three-state after the dummy conversion to the next falling edge of

When running at the maximum throughput rate of 1 MSPS, the AD7441/AD7451 power up and acquire a signal within ±0.5 LSB in one dummy cycle, that is, 1 µs. When powering up from the power-down mode with a dummy cycle, as in Figure 31, the track-and-hold, which was in hold mode while the part was powered down, returns to track mode after the first SCLK

edge the part receives after the falling edge of

. This is shown

as Point A in Figure 31.

03153-A-031

For example, when a 5 MHz SCLK frequency is applied to the ADC, the cycle time is 3.2 µs (that is, 1/(5 MHz) × 16). In one dummy cycle, 3.2 µs, the part is powered up and VIN acquired fully. However after 1 µs with a 5 MHz SCLK, only five SCLK cycles elapse. At this stage, the ADC is fully powered up and the

signal acquired. So, in this case, the

can be brought high after the 10th SCLK falling edge and brought low again after a time, t

, to initiate the conversion.

QUIET

When power supplies are first applied to the AD7441/AD7451, the ADC can power up either in power-down mode or normal mode. For this reason, it is best to allow a dummy cycle to elapse to ensure that the part is fully powered up before attempting a valid conversion. Likewise, if the user wants the part to power up in power-down mode, then the dummy cycle can be used to ensure the device is in power-down mode by executing a cycle such as that shown in Figure 30. Once supplies are applied to the AD7441/AD7451, the power-up time is the same as that when powering up from power-down mode. It takes approximately 1 µs to power up fully in normal mode. It is not necessary to wait 1 µs before executing a dummy cycle to ensure the desired mode of operation. Instead, the dummy cycle can occur directly after power is supplied to the ADC. If the first valid conversion is then performed directly after the dummy conversion, care must be taken to ensure that adequate acquisition time has been allowed.

Although at any SCLK frequency one dummy cycle is sufficient to power up the device and acquire V

, it does not necessarily

mean that a full dummy cycle of 16 SCLKs must always elapse to power up the device and acquire V

fully; 1 µs is sufficient to

power up the device and acquire the input signal.

Rev. B | Page 19 of 24

As mentioned earlier, when powering up from the power-down mode, the part returns to track mode upon the first SCLK edge

applied after the falling edge of

. However, when the ADC powers up initially after supplies are applied, the track-and-hold is already in track mode. This means (assuming one has the facility to monitor the ADC supply current) that if the ADC powers up in the desired mode of operation, a dummy cycle is not required to change mode. Thus, a dummy cycle is also not required to place the track-and-hold into track.

Page 20

AD7441/AD7451

POWER VS. THROUGHPUT RATE

By using the power-down mode on the device when not converting, the average power consumption of the ADC decreases at lower throughput rates. Figure 32 shows how, as the throughput rate is reduced, the device remains in its power-down state longer and the average power consumption reduces accordingly. For example, if the AD7441/AD7451 are operated in continuous sampling mode with a throughput rate of 100 kSPS and an SCLK of 18 MHz, and the device is placed in the power-down mode between conversions, then the power consumption during normal operation equals 9.25 mW max (for V

If the power-up time is one dummy cycle (1 µs) and the remaining conversion time is another cycle (1 µs), then the AD7441/AD7451 can be said to dissipate 9.25 mW for 2 µs during each conversion cycle. (This power consumption figure assumes a very short time to enter power-down mode. This power figure increases as the burst of clocks used to enter power-down mode is increased). The AD7441/AD7451 consumes just 5 µW for the remaining 8 µs.

If the throughput rate = 100 kSPS, then the cycle time = 10 µs, and the average power dissipated during each cycle is

mW85.1mW25.9)10/2( =×

= 5 V).

MICROPROCESSOR AND DSP INTERFACING

The serial interface on the AD7441/AD7451 allows the part to be connected directly to a range of different microprocessors. This section explains how to interface the AD7441/AD7451 with some of the more common microcontroller and DSP serial interface protocols.

AD7441/AD7451 to ADSP-21xx

The ADSP-21xx family of DSPs is interfaced directly to the AD7441/AD7451 without any glue logic required. The SPORT control register should be set up as follows:

TFSW = RFSW = 1 Alternate framing

INVRFS = INVTFS = 1 Active low frame signal

DTYPE = 00 Right justify data

SLEN = 1111 16-bit data-words

ISCLK = 1 Internal serial clock

TFSR = RFSR = 1 Frame every word

IRFS = 0

ITFS = 1

For the same scenario, if V

= 3 V, the power dissipation

during normal operation is 4 mW max.

The AD7441/AD7451 can now be said to dissipate 4 mW for 2 µs during each conversion cycle.

The average power dissipated during each cycle with a throughput rate of 100 kSPS is therefore

(2/10) × 4 mW = 0.8 mW

This is how the power numbers in Figure 32 are calculated.

100

POWER (mW)

0.1

0.01 0 350

50 100 150 200 250 300

Figure 32. Power vs. Throughput Rate for Power-Down Mode

VDD = 5V

THROUGHPUT (kSPS)

= 3V

03051-A-044

For optimum power performance in throughput rates above 320 kSPS, it is recommended that the serial clock frequency be reduced.

To implement power-down mode, SLEN should be set to 1001 to issue an 8-bit SCLK burst.

The connection diagram is shown in Figure 33. ADSP-21xx has the TFS and RFS of the SPORT tied together, with TFS set as an output and RFS set as an input. The DSP operates in alternate framing mode, and the SPORT control register is set up as described. The frame synchronization signal generated on the

TFS is tied to

, and, as with all signal processing applications, equidistant sampling is necessary. However, in this example, the timer interrupt is used to control the sampling rate of the ADC and, under certain conditions, equidistant sampling cannot be achieved.

AD7441/ AD7451*

SCLK

SDATA

*ADDITIONAL PINS REMOVED FOR CLARITY

Figure 33. Interfacing to the ADSP-21xx

ADSP-21xx*

SCLK DR

RFS TFS

03153-A-033

Rev. B | Page 20 of 24

Page 21

AD7441/AD7451

The timer registers, for example, are loaded with a value that provides an interrupt at the required sample interval. When an interrupt is received, a value is transmitted with TFS/DT (ADC control word). The TFS is used to control the RFS and therefore the reading of data. The frequency of the serial clock is set in the SCLKDIV register. When the instruction to transmit with TFS is given, that is, AX0 = TX0, the state of the SCLK is checked. The DSP waits until the SCLK has gone high, low, and high before starting transmission. If the timer and SCLK values are chosen such that the instruction to transmit occurs on or near the rising edge of SCLK, then the data may be transmitted or it may wait until the next clock edge.

For example, the ADSP-2111 has a master clock frequency of 16 MHz. If the SCLKDIV register is loaded with the value 3, an SCLK of 2 MHz is obtained, and eight master clock periods elapse for every one SCLK period. If the timer registers are loaded with the value 803, 100.5 SCLKs occur between interrupts and subsequently between transmit instructions. This situation results in nonequidistant sampling because the transmit instruction is occurring on an SCLK edge. If the number of SCLKs between interrupts is a whole integer figure of N, equidistant sampling is implemented by the DSP.

AD7441/AD7451 to TMS320C5x/C54x

The serial interface on the TMS320C5x/C54x uses a continuous serial clock and frame synchronization signals to synchronize the data transfer operations with peripheral devices such as the AD7441/AD7451. The

input allows easy interfacing between the TMS320C5x/C54x and the AD7441/AD7451 without any glue logic required. The serial port of the TMS320C5x/C54x is set up to operate in burst mode with internal CLKX (Tx serial clock) and FSX (Tx frame sync). The serial port control register (SPC) must have the following setup: FO = 0, FSM = 1, MCM = 1, and TXM = 1. The format bit, FO, can be set to 1 to set the word length to 8 bits in order to implement the powerdown mode on the AD7441/AD7451. The connection diagram is shown in Figure 34. Note that for signal processing applications, the frame synchronization signal from the TMS320C5x/C54x must provide equidistant sampling.

AD7441/AD7451 to DSP56xxx

The connection diagram in Figure 35 shows how the AD7441/ AD7451 can be connected to the SSI (synchronous serial interface) of the DSP56xxx family of DSPs from Motorola. The SSI is operated in synchronous mode (SYN bit in CRB = 1) with internally generated 1-bit clock period frame sync for both Tx and Rx (Bit FSL1 = 1 and Bit FSL0 = 0 in CRB). Set the word length to 16 by setting bits WL1 = 1 and WL0 = 0 in CRA. To implement the power-down mode on the AD7441/AD7451, the word length can be changed to eight bits by setting bits WL1 = 0 and WL0 = 0 in CRA. Note that for signal processing applications, the frame synchronization signal from the DSP56xxx must provide equidistant sampling.

AD7441/ AD7451*

SCLK

SDATA

*ADDITIONAL PINS REMOVED FOR CLARITY

Figure 35. Interfacing to the DSP56xxx

DSP56xxx*

SCLK SRD

SR2

03153-A-035

AD7441/ AD7451*

SCLK

SDATA

*ADDITIONAL PINS REMOVED FOR CLARITY

Figure 34. Interfacing to the TMS320C5x/C54x

TMS320C5x/

C54x*

CLKx CLKR DR

FSx FSR

03153-A-034

Rev. B | Page 21 of 24

Page 22

AD7441/AD7451

GROUNDING AND LAYOUT HINTS

The printed circuit board that houses the AD7441/AD7451 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. This facilitates the use of ground planes that can be easily separated. A minimum etch technique is generally best for ground planes as it gives the best shielding. Digital and analog ground planes should be joined in only one place, a star ground point established as close to the GND pin on the AD7441/AD7451 as possible.

EVALUATING PERFORMANCE

The evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from a PC via the evaluation board controller. The evaluation board controller can be used in conjunction with the AD7441 and the AD7451 evaluation boards, as well as with many other Analog Devices evaluation boards ending with the CB designator, to demonstrate and evaluate the ac and dc performance of the AD7441 and the AD7451.

Avoid running digital lines under the device as this couples noise onto the die. The analog ground plane should be allowed to run under the AD7441/AD7451 to avoid noise coupling. The power supply lines to the AD7441/AD7451 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line.

Fast switching signals like clocks should be shielded with digital grounds to avoid radiating noise to other sections of the board, and clock signals should never run near the analog inputs. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This reduces the effects of feedthrough on the board. A microstrip technique is by far the best but is not always possible with a double-sided board.

In this technique the component side of the board is dedicated to ground planes while signals are placed on the solder side. Good decoupling is also important. All analog supplies should be decoupled with 10 µF tantalum capacitors in parallel with

0.1 µF capacitors to GND. To achieve the best from these decoupling components, they must be placed as close as possible to the device.

The software allows the user to perform ac (fast Fourier transform) and dc (histogram of codes) tests on the AD7441/AD7451. See the AD7441/AD7451 application note that accompanies the evaluation kit for more information.

Rev. B | Page 22 of 24

Page 23

AD7441/AD7451

OUTLINE DIMENSIONS

2.90 BSC

1.95 BSC

0.65 BSC

2.80 BSC

1.45 MAX

SEATING PLANE

0.22

0.08 8° 4° 0°

0.60

0.45

0.30

1.60 BSC

PIN 1

INDICATO

1.30

1.15

0.90

0.15 MAX

847

0.38

0.22

COMPLIANT TO JEDEC STANDARDS MO-178BA

Figure 36. 8-Lead Small Outline Transistor Package [SOT-23]

(RT-8)

Dimensions shown in millimeters

3.00 BSC

3.00

BSC

PIN 1

0.65 BSC

4.90

BSC

0.15

0.00

0.38

0.22

COPLANARITY

0.10 COMPLIANT TO JEDEC STANDARDS MO-187AA

1.10 MAX

SEATING PLANE

0.23

0.08

8° 0°

Figure 37. 8-Lead Mini Small Outline Package [MSOP]

(RM-8)

Dimensions shown in millimeters

0.80

0.60

0.40

Rev. B | Page 23 of 24

Page 24

AD7441/AD7451

ORDERING GUIDE

Model Temperature Range Linearity Error (LSB)1Package Description Package Option Branding

AD7451ART-R2 −40°C to +85°C ± 1.5 8-Lead SOT-23 RT-8 CSA AD7451ART-REEL7 −40°C to +85°C ± 1.5 8-Lead SOT-23 RT-8 CSA AD7451ARM −40°C to +85°C ± 1.5 8-Lead MSOP RM-8 CSA AD7451ARM-REEL7 −40°C to +85°C ± 1.5 8-Lead MSOP RM-8 CSA AD7451BRT-R2 −40°C to +85°C ± 1 8-Lead SOT-23 RT-8 C05 AD7451BRT-REEL7 −40°C to +85°C ± 1 8-Lead SOT-23 RT-8 C05 AD7451BRM −40°C to +85°C ± 1 8-Lead MSOP RM-8 C05 AD7451BRM-REEL7 −40°C to +85°C ± 1 8-Lead MSOP RM-8 C05 AD7441BRT-R2 −40°C to +85°C ± 0.5 8-Lead SOT-23 RT-8 C0F AD7441BRT-REEL7 −40°C to +85°C ± 0.5 8-Lead SOT-23 RT-8 C0F AD7441BRM −40°C to +85°C ± 0.5 8-Lead MSOP RM-8 C0F AD7441BRM-REEL7 −40°C to +85°C ± 0.5 8-Lead MSOP RM-8 C0F EVAL-AD7451CB2

EVAL-AD7441CB

EVAL-CONTROL BRD2

Evaluation Board

Controller Board

Linearity error here refers to integral nonlinearity error.

This can be used as a standalone evaluation board or in conjunction with the evaluation board controller for evaluation/demonstration purposes.

The evaluation board controller is a complete unit allowing a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators.

To order a complete evaluation kit, you must order the ADC evaluation board (EVAL-AD7451CB or EVAL-AD7441CB), the EVAL-CONTROL BRD2, and a 12 V ac transformer. See the AD7451/AD7441 application note that accompanies the evaluation kit for more information.

C03153-0-2/05(B)

Rev. B | Page 24 of 24

Datasheet AD7441 Datasheet (Analog Devices)

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

PRODUCT HIGHLIGHTS

AD7451 SPECIFICATIONS

AD7441 SPECIFICATIONS

TIMING SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

TERMINOLOGY

TYPICAL PERFORMANCE CHARACTERISTICS

THEORY OF OPERATION

CIRCUIT INFORMATION

CONVERTER OPERATION

ADC TRANSFER FUNCTION

TYPICAL CONNECTION DIAGRAM

ANALOG INPUT

ANALOG INPUT STRUCTURE

DIGITAL INPUTS

REFERENCE

SERIAL INTERFACE

Timing Example 1

Timing Example 2

MODES OF OPERATION

NORMAL MODE

POWER-DOWN MODE

Power-Up Time

POWER VS. THROUGHPUT RATE

MICROPROCESSOR AND DSP INTERFACING

AD7441/AD7451 to ADSP-21xx

AD7441/AD7451 to TMS320C5x/C54x

AD7441/AD7451 to DSP56xxx

GROUNDING AND LAYOUT HINTS

EVALUATING PERFORMANCE

OUTLINE DIMENSIONS

ORDERING GUIDE