Datasheet AD743SQ-883B, AD743KR-16-REEL, AD743KR-16, AD743KN, AD743JR-16-REEL Datasheet (Analog Devices)
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Ultralow Noise
a
FEATURES
ULTRALOW NOISE PERFORMANCE
2.9 nV/√Hz at 10 kHz
0.38 V p-p, 0.1 Hz to 10 Hz
6.9 fA/√Hz Current Noise at 1 kHz
EXCELLENT DC PERFORMANCE
0.5 mV Max Offset Voltage
250 pA Max Input Bias Current
1000 V/mV min Open-Loop Gain
AC PERFORMANCE
2.8 V/s Slew Rate
4.5 MHz Unity-Gain Bandwidth
THD = 0.0003% @ 1 kHz
Available in Tape and Reel in Accordance with
EIA-481A Standard
APPLICATIONS
Sonar Preamplifiers
High Dynamic Range Filters (>140 dB)
Photodiode and IR Detector Amplifiers
Accelerometers
PRODUCT DESCRIPTION
The AD743 is an ultralow noise precision, FET input, monolithic
operational amplifier. It offers a combination of the ultralow
voltage noise generally associated with bipolar input op amps
and the very low input current of a FET-input device. Furthermore, the AD743 does not exhibit an output phase reversal
when the negative common-mode voltage limit is exceeded.
The AD743’s guaranteed, maximum input voltage noise of
4.0nV/√Hz at 10 KHz is unsurpassed for a FET-input monolithic
op amp, as is the maximum 1.0 µV p-p, 0.1 Hz to 10 Hz noise.
The AD743 also has excellent dc performance with 250 pA
maximum input bias current and 0.5 mV maximum offset voltage.
The AD743 is specifically designed for use as a preamp in
capacitive sensors, such as ceramic hydrophones. It is available
in five performance grades. The AD743J is rated over the
commercial temperature range of 0°C to 70°C.
The AD743 is available in 8-Lead plastic mini-DIP, and
16-pin SOIC.
PRODUCT HIGHLIGHTS
1. The low offset voltage and low input offset voltage drift of
the AD743 coupled with its ultralow noise performance
mean that the AD743 can be used for upgrading many
applications now using bipolar amplifiers.
BiFET Op Amp
AD743
CONNECTION DIAGRAMS
8-Lead Plastic Mini-DIP (N)
1
NULL
2
–IN
3
+IN
–V
4
S
NC = NO CONNECT
AD743
TOP VIEW
8
8
NC
+V
7
6
OUT
NULL
5
2. The combination of low voltage and low current noise make
the AD743 ideal for charge sensitive applications such as
accelerometers and hydrophones.
3. The low input offset voltage and low noise level of the
AD743 provide >140 dB dynamic range.
4. The typical 10 kHz noise level of 2.9 nV/√Hz permits a three
op amp instrumentation amplifier, using three AD743s, to be
built which exhibits less than 4.2 nV/√Hz noise at 10 KHz
and which has low input bias currents.
1000
R
SOURCE
100
10
INPUT NOISE VOLTAGE – nV/ Hz
1
R
SOURCE
AD743 & RESISTOR
OR
OP27 & RESISTOR
RESISTOR NOISE ONLY
100
1k
SOURCE RESISTANCE – Ω
Input Noise Voltage vs. Source Resistance
16-Lead SOIC (R) Package
1
NC
OFFSET
S
E
O
(– – –)
10k 100k
2
NULL
3
–IN
4
NC
+IN
5
–V
6
S
7
NC
8
NC
NC = NO CONNECT
OP27 &
RESISTOR
( — )
AD743 + RESISTOR
AD743
)
(
1M
16 NC
15
14
13
12
11
10
10M
8
9
NC
NC
+V
S
OUTPUT
OFFSET
NULL
NC
NC
REV. D
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 2002
AD743–SPECIFICATIONS
(@ 25ⴗC and ⴞ15 V dc, unless otherwise noted)
Model Conditions Min Typ Max Min Typ Max Unit
AD743J AD743K
INPUT OFFSET VOLTAGE
1
Initial Offset 0.25 1.0/0.8 0.1 0.5/0.25 mV
Initial Offset T
vs. Temp. T
vs. Supply (PSRR) 12 V to 18 V
vs. Supply (PSRR) T
INPUT BIAS CURRENT
3
MIN
MIN
MIN
to T
to T
to T
MAX
MAX
MAX
2
90 96 100 106 dB
21µV/°C
88 98 100 dB
1.5 1.0/0.50 mV
Either Input VCM = 0 V 150 400 150 250 pA
Either Input
@ T
MAX
Either Input V
VCM = 0 V 8.8/25.6 5.5/16 nA
= 10 V 250 600 250 400 pA
CM
Either Input, VS = ±5 V VCM = 0 V 30 200 30 125 pA
INPUT OFFSET CURRENT VCM = 0 V 40 150 30 75 pA
Offset Curren
@ T
MAX
VCM = 0 V 2.2/6.4 1.1/3.2 nA
FREQUENCY RESPONSE
Gain BW, Small Signal G = –1 4.5 4.5 MHz
Full Power Response VO = 20 V p-p 25 25 kHz
Slew Rate, Unity Gain G = –1 2.8 2.8 V/µs
Settling Time to 0.01% 6 6 µs
Total Harmonic f = 1 kHz
Distortion4 (Figure 16) G = –1 0.0003 0.0003 %
INPUT IMPEDANCE
Differential 1 ⫻ 1010||20 1 ⫻ 1010||20 Ω||pF
Common Mode 3 ⫻ 1011||18 3 ⫻ 1011||18 Ω||pF
INPUT VOLTAGE RANGE
Differential
Common-Mode Voltage +13.3, –10.7 +13.3, –10.7 V
Over Max Operating Range
5
6
–10 +12 –10 +12 V
±20 ±20 V
Common-Mode
Rejection Ratio VCM = ±10 V 80 95 90 102 dB
T
MIN
to T
MAX
78 88 dB
INPUT VOLTAGE NOISE 0.1 Hz to 10 Hz 0.38 0.38 1.0 µV p-p
f = 10 Hz 5.5 5.5 10.0 nV/√Hz
f = 100 Hz 3.6 3.6 6.0 nV/√Hz
f = 1 kHz 3.2 5.0 3.2 5.0 nV/√Hz
f = 10 kHz 2.9 4.0 2.9 4.0 nV/√Hz
INPUT CURRENT NOISE f = 1 kHz 6.9 6.9 fA/√Hz
OPEN LOOP GAIN VO = ±10 V
R
≥ 2 kΩ 1000 4000 2000 4000 V/mV
LOAD
T
to T
MIN
R
MAX
= 600 Ω 1200 1200 V/mV
LOAD
800 1800 V/mV
OUTPUT CHARACTERISTICS
Voltage R
≥ 600 Ω +13, –12 +13, –12 V
LOAD
R
≥ 600 Ω +13.6, –12.6 +13.6, –12.6 V
LOAD
T
to T
MIN
R
MAX
≥ 2 kΩ±12 +13.8, –13.1 ±12 +13.8, –13.1 V
LOAD
+12, –10 +12, –10 V
Current Short Circuit 20 40 20 40 mA
POWER SUPPLY
Rated Performance ±15 ±15 V
Operating Range ±4.8 ±18 ±4.8 ±18 V
Quiescent Current 8.1 10.0 8.1 10.0 mA
TRANSISTOR COUNT # of Transistors 50 50
NOTES
1
Input offset voltage specifications are guaranteed after 5 minutes of operation at TA = 25°C.
2
Test conditions: +VS = 15 V, –VS = 12 V to 18 V and +VS = 12 V to 18 V, –VS = 15 V.
3
Bias current specifications are guaranteed maximum at either input after 5 minutes of operation at TA = 25°C. For higher temperature, the current doubles every 10°C.
4
Gain = –1, RL = 2 kΩ, CL = 10 pF.
5
Defined as voltage between inputs, such that neither exceeds ±10 V from common.
6
Thc AD743 does not exhibit an output phase reversal when the negative common-mode limit is exceeded.
All min and max specifications are guaranteed.
Specifications subject to change without notice.
–2–
REV. D
AD743
ABSOLUTE MAXIMUM RATINGS
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18 V
Internal Power Dissipation
2
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± V
1
S
Output Short Circuit Duration . . . . . . . . . . . . . . . . Indefinite
Differential Input Voltage . . . . . . . . . . . . . . . . . . +V
and –V
S
S
Storage Temperature Range (N, R) . . . . . . . –65°C to +125°C
Operating Temperature Range
AD743J . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Lead Temperature Range (Soldering 60 seconds) . . . . . 300°C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; and functional operation of
the device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
8-pin plastic package: θJA = 100°C/Watt, θJC = 50°C/Watt
16-pin plastic SOIC package: θJA = 100°C/Watt, θJC = 30°C/Watt
ESD SUSCEPTIBILITY
An ESD classification per method 3015.6 of MIL-STD-883C
has been performed on the AD743. The AD743 is a class 1
device, passing at 1000 V and failing at 1500 V on null pins 1
and 5, when tested, using an IMCS 5000 automated ESD
tester. Pins other than null pins fail at greater than 2500 V.
ORDERING GUIDE
Package
Model Temperature Range Option
AD743JN 0°C to +70°C N-8
AD743KN
AD743JR-16 0°C to +70°C R-16
AD743KR-16
AD743SQ/883B
2
2
2
0°C to +70°C N-8
0°C to +70°C R-16
–55°C to +125°C Q-8
1
AD743JR-16-REEL 0°C to +70°C Tape & Reel
AD743KR-16-REEL20°C to +70°C Tape & Reel
1
N = Plastic DIP; R = Small Outline IC; Q = Cerdip.
2
Not for new design, obsolete april 2002
REV. D
–3–
AD743
–60 –40 –20 0 20 40 60 80 100 120 140
3.0
4.0
5.0
6.0
7.0
2.0
TEMPERATURE – °C
GAIN BANDWIDTH PRODUCT
– MHz
–Typical Performance Characteristics
(@ 25ⴗC, VS = 15 V)
20
R = 10kΩ
LOAD
15
– Volts
10
5
INPUT VOLTAGE SWING
0
0
51015
SUPPLY VOLTAGE ± VOLTS
+V
IN
–V
IN
TPC 1. Input Voltage Swing
vs. Supply Voltage
12
9
– mA
6
QUIESCENT CURRENT
3
0
0510
SUPPLY VOLTAGE ± VOLTS
15 20
20
R = 10kΩ
LOAD
15
10
5
OUTPUT VOLTAGE SWING – Volts
0
20
0510
POSITIVE
SUPPLY
NEGATIVE
SUPPLY
SUPPLY VOLTAGE ± VOLTS
15
20
TPC 2. Output Voltage Swing vs.
Supply Voltage
–6
10
–7
10
–8
10
– Amps
–9
10
–10
10
INPUT BIAS CURRENT
–11
10
–12
10
–60 –40 –20
0
20 40 60 80 100
TEMPERATURE – °C
120
140
35
30
25
20
15
10
OUTPUT VOLTAGE SWING – Volts p-p
5
0
10
100
LOAD RESISTANCE – Ω
1k
TPC 3. Output Voltage Swing vs.
Load Resistance
200
100
10
1
OUTPUT IMPEDANCE – Ω
0.1
0.01
10k
100k 1M
FREQUENCY – Hz
10M
10k
100M
TPC 4. Quiescent Current vs.
Supply Voltage
300
200
100
INPUT BIAS CURRENT – pA
0
–9 –6 –3
COMMON MODE VOLTAGE – Volts
TPC 7. Input Bias Current vs.
Common-Mode Voltage
3
0–12 12
9
6
TPC 5. Input Bias Current vs.
Temperature
80
70
60
50
40
30
CURRENT LIMIT – mA
20
10
0
–40 –20 0 20 40 60 80 100 120 140
–60
+ OUTPUT
CURRENT
– OUTPUT
CURRENT
TEMPERATURE – °C
TPC 8. Short Circuit Current
Limit vs. Temperature
TPC 6. Output Impedance vs.
Frequency (Closed Loop Gain = –1)
TPC 9. Gain Bandwidth Product
vs. Temperature
REV. D–4–
AD743
100
80
60
40
20
OPEN-LOOP GAIN – dB
0
–20
100 1k 10k 100k
FREQUENCY – Hz
PHASE
GAIN
1M 10M 100M
TPC 10. Open-Loop Gain and
Phase vs. Frequency
120
100
V = ±10V
80
60
40
COMMON-MODE REJECTION – dB
20
0
100 1k 10k 100k 1M
CM
FREQUENCY – Hz
TPC 13. Common-Mode Rejection
vs. Frequency
100
60
80
40
20
0
–20
3.5
3.0
2.5
SLEW RATE – Volts/µs
PHASE MARGIN – Degrees
2.0
–60 –40 –20 0
20
TEMPERATURE – °C
40
TPC 11. Slew Rate vs.
Temperature (Gain = –1)
120
100
+ SUPPLY
FREQUENCY – Hz
POWER SUPPLY REJECTION – dB
80
60
40
20
0
100
– SUPPLY
1k 10k 100k
TPC 14. Power Supply Rejection
vs. Frequency
60 80 100 120 140
1M 10M 100M
150
140
– dB
130
120
OPEN-LOOP GAIN
100
80
05
SUPPLY VOLTAGE ± VOLTS
10 15 20
TPC 12. Open-Loop Gain vs.
Supply Voltage, R
35
30
25
20
– Volts p-p
15
R = 2kΩ
L
10
OUTPUT VOLTAGE
5
0
1k 10k
FREQUENCY – Hz
LOAD
= 2K
100k
TPC 15. Large Signal Frequency
Response
1M
–70
–80
–90
–100
–110
THD – dB
–120
–130
–140
GAIN = +10
GAIN = –1
10
100
1k 10k
FREQUENCY – Hz
TPC 16. Total Harmonic Distortion
vs. Frequency
REV. D
100k
100
– nV Hz
10
1.0
0.1
NOISE VOLTAGE (REFERRED TO INPUT)
1
10
CLOSED-LOOP GAIN = 1
CLOSED-LOOP GAIN = 10
100
1k 10k 100k
FREQUENCY – Hz
TPC 17. Input Noise Voltage
Spectral Density
–5–
1k
– fA/ Hz
100
10
CURRENT NOISE SPECTRAL DENSITY
1.0
1
1M
10M
10
FREQUENCY – Hz
100
1k
10k 100k
TPC 18. Input Noise Current
Spectral Density
AD743
NUMBER OF UNITS
69
63
57
51
45
39
33
27
21
15
9
3
2.5
2.7 2.9 3.1
INPUT VOLTAGE NOISE – nV
3.3
TPC 19. Typical Noise Distribution
@ 10 kHz (602 Units)
3.8
3.5
Hz
TPC 22b. Unity-Gain Follower
Small Signal Pulse Response
100pF
2kΩ
+V
V
IN
SQUARE WAVE
INPUT
2kΩ
2
3
S
7
AD743
4
–V
S
1µF
1µF
6
0.1µF
0.1µF
V
C
L
100pF
OUT
TPC 20. Offset Null Configuration
TPC 21. Unity-Gain Follower
TPC 23a. Unity-Gain Inverter
TPC 23b. Unity-Gain Inverter
Large Signal Pulse Response
TPC 22a. Unity-Gain Follower
Large Signal Pulse Response
TPC 23c. Unity-Gain Inverter
Small Signal Pulse Response
REV. D–6–
AD743
OP AMP PERFORMANCE: JFET VS. BIPOLAR
The AD743 is the first monolithic JFET op amp to offer the low
input voltage noise of an industry standard bipolar op amp
without its inherent input current errors. This is demonstrated
in Figure 1, which compares input voltage noise vs. input source
resistance of the OP27 and the AD743 op amps. From this
figure, it is clear that at high source impedance the low current
noise of the AD743 also provides lower total noise. It is also
important to note that with the AD743 this noise reduction
extends all the way down to low source impedances. The lower
dc current errors of the AD743 also reduce errors due to offset
and drift at high source impedances (Figure 2).
1000
R
SOURCE
100
– nV/ Hz
10
INPUT NOISE VOLTAGE
1
R
SOURCE
AD743 & RESISTOR
OR
OP27 & RESISTOR
RESISTOR NOISE ONLY
100
1k
SOURCE RESISTANCE – Ω
10k 100k
E
(– – –)
O
OP27 &
RESISTOR
( — )
AD743 + RESISTOR
)
(
1M
10M
Figure 1. Total Input Noise Spectral Density @ 1 kHz vs.
Source Resistance
100
ADOP27G
10
1.0
INPUT OFFSET VOLTAGE – mV
AD743 KN
0.1
100
1k 10k 100k
SOURCE RESISTANCE – Ω
1M 10M
Figure 2. Input Offset Voltage vs. Source Resistance
DESIGNING CIRCUITS FOR LOW NOISE
An op amp’s input voltage noise performance is typicaly divided
into two regions: flatband and low frequency noise. The AD743
offers excellent performance with respect to both. The figure of
2.9 nV/√Hz @ 10 kHz is excellent for JFET input amplifier.
The 0.1 Hz to 10 Hz noise is typically 0.38 µV p-p. The user
should pay careful attention to several design details in order to
optimize low frequency noise performance. Random air currents
can generate varying thermocouple voltages that appear as low
frequency noise: therefore sensitive circuitry should be well
shielded from air flow. Keeping absolute chip temperature low
also reduces low frequency noise in two ways: first, the low
frequency noise is strongly dependent on the ambient
temperature and increases above +25°C. Second, since the
gradient of temperature from the IC package to ambient is
greater, the noise generated by random air currents, as
previously mentioned, will be larger in magnitude. Chip
temperature can be reduced both by operation at reduced
supply voltages and by the use of a suitable clip-on heat sink, if
possible.
Low frequency current noise can be computed from the
magnitude of the dc bias current (~I
below approximately 100 Hz with a 1/f power spectral density.
n
=
2qIB∆f
) and increases
For the AD743 the typical value of current noise is 6.9 fA/√Hz
at 1 kHz. Using the formula, ~I
Johnson noise of a resistor, expressed as a current, one can see
that the current noise of the AD743 is equivalent to that of a
3.45 ⫻ 10
8
Ω source resistance.
n
=
4kT /R∆f ,
to compute the
At high frequencies, the current noise of a FET increases
proportionately to frequency. This noise is due to the “real” part
of the gate input impedance, which decreases with frequency.
This noise component usually is not important, since the voltage
noise of the amplifier impressed upon its input capacitance is an
apparent current noise of approximately the same magnitude.
In any FET input amplifier, the current noise of the internal
bias circuitry can be coupled externally via the gate-to-source
capacitances and appears as input current noise. This noise is
totally correlated at the inputs, so source impedance matching
will tend to cancel out its effect. Both input resistance and input
capacitance should be balanced whenever dealing with source
capacitances of less than 300 pF in value.
LOW NOISE CHARGE AMPLIFIERS
As stated, the AD743 provides both low voltage and low current
noise. This combination makes this device particularly suitable
in applications requiring very high charge sensitivity, such as
capacitive accelerometers and hydrophones. When dealing with
a high source capacitance, it is useful to consider the total input
charge uncertainty as a measure of system noise.
Charge (Q) is related to voltage and current by the simply stated
fundamental relationships:
Q = CV and I =
dQ
dt
As shown, voltage, current and charge noise can all be directly
related. The change in open circuit voltage (∆V) on a capacitor
will equal the combination of the change in charge (∆Q/C) and
the change in capacitance with a built in charge (Q/∆C).
REV. D
–7–
AD743
Figures 3 and 4 show two ways to buffer and amplify the output
of a charge output transducer. Both require using an amplifier
which has a very high input impedance, such as the AD743.
Figure 3 shows a model of a charge amplifier circuit. Here,
amplification depends on the principle of conservation of charge
at the input of amplifier A1, which requires that the charge on
capacitor C
output voltage of ∆Q/C
appear at the output amplified by the noise gain (1 + (C
be transferred to capacitor CF, thus yielding an
S
. The amplifiers input voltage noise will
F
S/CF
))
of the circuit.
Figure 3. A Charge Amplifier Circuit
Figure 5 shows that these two circuits have an identical
frequency response and the same noise performance (provided
that C
“T” network is used to increase the effective resistance of R
= R1/ R2). One feature of the first circuit is that a
S/CF
B
and improve the low frequency cutoff point by the same factor.
–100
–110
–120
Hz
–130
–140
–150
–160
–170
–180
–190
DECIBELS REFERENCED TO 1V/
–200
–210
–220
10M
100M
1 10 100
FREQUENCY – Hz
1k
10k 100k
TOTAL OUTPUT
NOISE
NOISE DUE TO
R ALONE
B
NOISE DUE TO
I ALONE
B
Figure 5. Noise at the Outputs of the Circuits of Figures
3 and 4. Gain = 10, C
However, this does not change the noise contribution of R
= 3000 pF, RB = 22 M
S
Ω
B
which, in this example, dominates at low frequencies. The graph
of Figure 6 shows how to select an R
large enough to minimize
B
this resistor’s contribution to overall circuit noise. When the
equivalent current noise of R
(
), there is diminishing return in making RB larger.
2qI
B
10
5.2 x 10
((√4kT)/R) equals the noise of I
B
B
Figure 4. Model for a High Z Follower with Gain
The second circuit, Figure 4, is simply a high impedance
follower with gain. Here the noise gain (1 + (R1/R2)) is the
same as the gain from the transducer to the output. Resistor R
,
B
in both circuits, is required as a dc bias current return.
There are three important sources of noise in these circuits.
Amplifiers A1 and A2 contribute both voltage and current noise,
while resistor R
contributes a current noise of:
B
~
N =
T
4k
∆f
R
B
where:
k = Boltzman’s Constant = 1.381 x 10
–23
Joules/Kelvin
T = Absolute Temperature, Kelvin (0°C = 273.2 Kelvin)
∆
f = Bandwidth – in Hz (Assuming an Ideal “Brick Wall”
Filter)
This must be root-sum-squared with the amplifier’s own current
noise.
9
5.2 x 10
Ω
8
5.2 x 10
RESISTANCE IN
7
5.2 x 10
6
5.2 x 10
1pA 10pA
100pA 1nA
INPUT BIAS CURRENT
10nA
Figure 6. Graph of Resistance vs. Input Bias Current
√4kT/R
where the Equivalent Noise
of the Bias Current
2qI
B
, Equals the Noise
To maximize dc performance over temperature, the source
resistances should be balanced on each input of the amplifier.
This is represented by the optional resistor R
in Figures 3 and
B
4. As previously mentioned, for best noise performance care should
be taken to also balance the source capacitance designated by C
The value for C
At values of C
noise; capacitor C
in Figure 3 would be equal to CS, in Figure 4.
B
over 300 pF, there is a diminishing impact on
B
can then be simply a large bypass of 0.01 µF
B
.
B
or greater.
REV. D–8–
AD743
HOW CHIP PACKAGE TYPE AND POWER DISSIPATION
AFFECT INPUT BIAS CURRENT
As with all JFET input amplifiers, the input bias current of the
AD743 is a direct function of device junction temperature, I
B
approximately doubling every 10°C. Figure 7 shows the
relationship between bias current and junction temperature for
the AD743. This graph shows that lowering the junction
temperature will dramatically improve I
–6
10
–7
10
10
10
–10
10
INPUT BIAS CURRENT – Amps
–11
10
–12
10
–8
–9
–60
–20 0
–40
JUNCTION TEMPERATURE – °C
V = ±15V
T = 25°C
20 40 60 80 100 120 140
.
B
S
+
A
Figure 7. Input Bias Current vs. Junction Temperature
The dc thermal properties of an IC can be closely approximated
by using the simple model of Figure 8 where current represents
power dissipation, voltage represents temperature, and resistors
represent thermal resistance (θ in °C/Watt).
T
θ
J
JC
θ
P
IN
WHERE:
P
= DEVICE DISSIPATION
IN
T
= AMBIENT TEMPERATURE
A
= JUNCTION TEMPERATURE
T
J
= THERMAL RESISTANCE – JUNCTION TO CASE
θ
JC
= THERMAL RESISTANCE – CASE TO AMBIENT
θ
CA
θ
CA
JA
T
A
Figure 8. A Device Thermal Model
From this model TJ = TA + θJA Pin. Therefore, IB can be
determined in a particular application by using Figure 7
together with the published data for θ
The user can modify θ
by use of an appropriate clip-on heat
JA
sink such as the Aavid #5801. θ
and power dissipation.
JA
is also a variable when using
JA
the AD743 in chip form. Figure 9 shows bias current vs. supply
voltage with θ
predict bias current after θ
as the third variable. This graph can be used to
JA
has been computed. Again bias
JA
current will double for every 10°C. The designer using the
AD743 in chip form (Figure 10) must also be concerned with
both θ
and θCA, since θJC can be affected by the type of die
JC
mount technology used.
Typically, θ
’s will be in the 3°C to 5°C/watt range; therefore,
JC
for normal packages, this small power dissipation level may be
ignored. But, with a large hybrid substrate, θ
proportionately more of the total θ
.
JA
will dominate
JC
300
= +25 C
T
A
200
θ
= 115 C/W
100
INPUT BIAS CURRENT – pA
0
51510
JA
SUPPLY VOLTAGE – Volts
θJA= 165 C/W
θ
JA
= 0 C/W
Figure 9. Input Bias Current vs. Supply Voltage for
Various Values of
θ
JA
Figure 10. A Breakdown of Various Package Thermal
Resistances
REDUCED POWER SUPPLY OPERATION FOR
LOWER I
B
Reduced power supply operation lowers IB in two ways: first, by
lowering both the total power dissipation and second, by
reducing the basic gate-to-junction leakage (Figure 32). Figure
34 shows a 40 dB gain piezoelectric transducer amplifier, which
operates without an ac coupling capacitor, over the –40°C to
+85°C temperature range. If the optional coupling capacitor is
used, this circuit will operate over the entire –55°C to +125°C
military temperature range.
Figure 11. A Piezoelectric Transducer
REV. D
–9–
AD743
AN INPUT-IMPEDANCE-COMPENSATED, SALLEN-KEY FILTER
The simple high pass filter of Figure 12 has an important source
of error which is often overlooked. Even 5 pF of input capacitance
in amplifier “A” will contribute an additional 1% of passband
amplitude error, as well as distortion, proportional to the C/V
characteristics of the input junction capacitance. The addition
of the network designated “Z” will balance the source
impedance–as seen by “A”–and thus eliminate these errors.
Figure 12. An Input Impedance Compensated
Sallen-Key Filter
TWO HIGH PERFORMANCE ACCELEROMETER AMPLIFIERS
Two of the most popular charge-out transducers are hydrophones
and accelerometers. Precision accelerometers are typically
calibrated for a charge output (pC/g).* Figures 13a and 13b
show two ways in which to configure the AD743 as a low noise
charge amplifier for use with a wide variety of piezoelectric
accelerometers. The input sensitivity of these circuits will be
determined by the value of capacitor C1 and is equal to:
∆Q
∆V
OUT
The ratio of capacitor C1 to the internal capacitance (CT) of the
transducer determines the noise gain of this circuit (1 + C
The amplifiers voltage noise will appear at its output amplified
by this amount. The low frequency bandwidth of these circuits
will be dependent on the value of resistor R1. If a “T” network
is used, the effective value is: R1 (1 + R2/R3).
OUT
=
C1
/C1).
T
Figure 13b. An Accelerometer Circuit Employing a
DC Servo Amplifier
A dc servo-loop (Figure 13b) can be used to assure a dc output
which is <10 mV, without the need for a large compensating
resistor when dealing with bias currents as large as 100 nA. For
optimal low frequency performance, the time constant of the
servo loop (R4C2 = R5C3) should be:
Time Constant ≥ 10 R11+
A LOW NOISE HYDROPHONE AMPLIFIER
R2
R3
C1
Hydrophones are usually calibrated in the voltage-out mode.
The circuits of Figures 14a and 14b can be used to amplify the
output of a typical hydrophone. Figure 14a shows a typical dc
coupled circuit. The optional resistor and capacitor serve to
counteract the dc offset caused by bias currents flowing through
resistor R1. Figure 14b, a variation of the original circuit, has a
low frequency cutoff determined by an RC time constant equal
to:
Time Constant =
2π×C
1
×100Ω
C
*pC = Picocoulombs
Figure 13a. A Basic Accelerometer Circuit
g = Earth's Gravitational Constant
Figure 14a. A Basic Hydrophone Amplifier
REV. D–10–
Figure 14b. An AC-Coupled, Low Noise
Hydrophone Amplifier
AD743
Where the dc gain is 1 and the gain above the low frequency
cutoff (1/(2πC
14a. The circuit of Figure 14c uses a dc servo loop to keep the
dc output at 0 V and to maintain full dynamic range for I
to 100 nA. The time constant of R7 and C2 should be larger
than that of R1 and C
The transducer shown has a source capacitance of 7500 pF. For
smaller transducer capacitances (≤300 pF), lowest noise can be
achieved by adding a parallel RC network (R4 = R1, C1 = C
in series with the inverting input of the AD743.
BALANCING SOURCE IMPEDANCES
As mentioned previously, it is good practice to balance the
source impedances (both resistive and reactive) as seen by the
inputs of the AD743. Balancing the resistive components will
optimize dc performance over temperature because balancing
will mitigate the effects of any bias current errors. Balancing
input capacitance will minimize ac response errors due to the
amplifier’s input capacitance and, as shown in Figure 15, noise
performance will be optimized. Figure 16 shows the required
external components for noninverting (A) and inverting (B)
configurations.
(100 Ω))) is the same as the circuit of Figure
C
’s up
B
for a smooth low frequency response.
T
)
T
Figure 14c. A Hydrophone Amplifier Incorporating a
DC Servo Loop
Figure 16. Optional External Components for Balancing Source Impedances
REV. D
Figure 15. RTI Voltage Noise vs. Input Capacitance
–11–
AD743
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Pin Plastic Mini-DIP (N)
C00830-0-2/02(D)
16-Pin SOIC (R) Package
Revision History
Location Page
Data Sheet changed from REV. C to REV. D.
Edits to PRODUCT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Edits to CONNECTION DIAGRAMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Deleted AD7435 column from SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Edits to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Deleted METALIZATION PHOTOGRAPH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Edits to REDUCE POWER SUPPLY OPERATION FOR LOWER I
Deleted 8-Pin Cerdip (Q) package Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
B
REV. D–12–
PRINTED IN U.S.A.
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