Page 1
Ultralow Noise
BiFET Op Amp
AD743
FEATURES
Ultralow Noise Performance
√
2.9 nV/
Hz at 10 kHz
0.38 V p-p, 0.1 Hz to 10 Hz
6.9 fA/
√
Hz Current Noise at 1 kHz
Excellent DC Performance
0.5 mV Max Offset Voltage
250 pA Max Input Bias Current
1000 V/mV Min Open-Loop Gain
AC Performance
2.8 V/s Slew Rate
4.5 MHz Unity-Gain Bandwidth
THD = 0.0003% @ 1 kHz
Available in Tape and Reel in Accordance with
EIA-481A Standard
APPLICATIONS
Sonar Preamplifiers
High Dynamic Range Filters (>140 dB)
Photodiode and IR Detector Amplifiers
Accelerometers
GENERAL DESCRIPTION
The AD743 is an ultralow noise, precision, FET input, monolithic
operational amplifier. It offers a combination of the ultralow voltage noise generally associated with bipolar input op amps and
the very low input current of a FET input device. Furthermore,
the AD743 does not exhibit an output phase reversal when the
negative common-mode voltage limit is exceeded.
The AD743’s guaranteed, maximum input voltage noise of
4.0 nV/√Hz at 10 kHz is unsurpassed for a FET input monolithic op amp, as is the maximum 1.0 µV p-p, 0.1 Hz to 10 Hz
noise. The AD743 also has excellent dc performance with 250 pA
maximum input bias current and 0.5 mV maximum offset voltage.
The AD743 is specifically designed for use as a preamp in capacitive sensors, such as ceramic hydrophones. The AD743J is rated
over the commercial temperature range of 0°C to 70°C.
The AD743 is available in a 16-lead SOIC and 8-lead PDIP.
PRODUCT HIGHLIGHTS
1. The low offset voltage and low input offset voltage drift of the
AD743 coupled with its ultralow noise performance mean
that the AD743 can be used for upgrading many applications
now using bipolar amplifiers.
CONNECTION DIAGRAMS
8-Lead PDIP (N) 16-Lead SOIC (R)
NULL
–IN
+IN
–V
1
2
3
4
S
AD743
TOP VIEW
NC = NO CONNECT
1
8
8
NC
+V
7
S
6
OUT
NULL
5
NC
OFFSET
NULL
–IN
NC
+IN
–V
NC
NC
AD743
2
3
4
5
6
S
7
TOP VIEW
8
NC = NO CONNECT
8
16
15
14
13
12
11
10
9
NC
NC
NC
+V
S
OUTPUT
OFFSET
NULL
NC
NC
2. The combination of low voltage and low current noise make
the AD743 ideal for charge sensitive applications such as
accelerometers and hydrophones.
3. The low input offset voltage and low noise level of the AD743
provide >140 dB dynamic range.
4. The typical 10 kHz noise level of 2.9 nV/√Hz permits a three
op amp instrumentation amplifier, using three AD743s, to be
built which exhibits less than 4.2 nV/√Hz noise at 10 kHz
and which has low input bias currents.
1000
)
z
H
/
(nV
E
IS
O
N
E
G
LTA
O
T V
U
P
IN
R
SOURCE
E
O
R
100
SOURCE
AD743 AND RESISTOR
OR
OP27 AND RESISTOR
10
RESISTOR NOISE ONLY
(– – –)
1
100 1k 10k 100k
SOURCE RESISTANCE (⍀)
OP27 AND
RESISTOR
( — )
AD743 AND
RESISTOR
(
)
1M 10M
Figure 1. Input Voltage Noise vs. Source Resistance
REV. E
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 www.analog.com
Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved.
Page 2
AD743–SPECIFICATIONS
(@ 25ⴗC and ⴞ15 V dc, unless otherwise noted.)
Parameter Conditions Min Typ Max Unit
INPUT OFFSET VOLTAGE
1
Initial Offset 0.25 1.0 mV
Initial Offset T
vs. Temperature T
MIN
MIN
to T
to T
vs. Supply (PSRR) 12 V to 18 V
vs. Supply (PSRR) T
INPUT BIAS CURRENT
3
MIN
to T
MAX
MAX
MAX
2
90 96 dB
2 µV/°C
88 dB
1.5 mV
Either Input VCM = 0 V 150 400 pA
Either Input @ T
MAX
Either Input V
VCM = 0 V 8.8 nA
= 10 V 250 600 pA
CM
Either Input, VS = ±5 V VCM = 0 V 30 200 pA
INPUT OFFSET CURRENT V
Offset Current @ T
MAX
= 0 V 40 150 pA
CM
VCM = 0 V 2.2 nA
FREQUENCY RESPONSE
Gain BW, Small Signal G = –1 4.5 MHz
Full Power Response V
= 20 V p-p 25 kHz
O
Slew Rate, Unity Gain G = –1 2.8 V/µs
Settling Time to 0.01% 6 µs
Total Harmonic Distortion
4
f = 1 kHz
(TPC 16) G = –1 0.0003 %
INPUT IMPEDANCE
Differential 1 10
10
储20 Ω储pF
Common Mode 3 1011储18 Ω储pF
INPUT VOLTAGE RANGE
Differential
Common-Mode Voltage +13.3, –10.7 V
Over Maximum Operating Range
Common-Mode Rejection Ratio V
5
6
= ±10 V 80 95 dB
CM
T
to T
MIN
MAX
–10 +12 V
78 dB
±20 V
INPUT VOLTAGE NOISE 0.1 Hz to 10 Hz 0.38 µV p-p
f = 10 Hz 5.5 nV/√Hz
f = 100 Hz 3.6 nV/√Hz
f = 1 kHz 3.2 5.0 nV/√Hz
f = 10 kHz 2.9 4.0 nV/√Hz
INPUT CURRENT NOISE f = 1 kHz 6.9 fA/√Hz
OPEN-LOOP GAIN V
= ±10 V,
O
≥ 2 kΩ 1000 4000 V/mV
R
LOAD
to T
T
R
MIN
LOAD
MAX
= 600 Ω 1200 V/mV
800 V/mV
OUTPUT CHARACTERISTICS
Voltage R
≥ 600 Ω +13, –12 V
LOAD
≥ 600 Ω +13.6, –12.6 V
R
LOAD
to T
T
R
MIN
LOAD
MAX
≥ 2 kΩ±12 +13.8, –13.1 V
+12, –10 V
Current Short Circuit 20 40 mA
POWER SUPPLY
Rated Performance ±15 V
Operating Range ±4.8 ± 18 V
Quiescent Current 8.1 10.0 mA
TRANSISTOR COUNT No. of Transistors 50
NOTES
1
Input offset voltage specifications are guaranteed after five minutes of operation at TA = 25°C.
2
Test conditions: +VS = 15 V, –VS = 12 V to 18 V; and +VS = 12 V to 18 V, –VS = 15 V.
3
Bias current specifications are guaranteed maximum at either input after 5 minutes of operation at TA = 25°C. For higher temperature, the current doubles every 10°C.
4
Gain = –1, RL = 2 kΩ, CL = 10 pF.
5
Defined as voltage between inputs, such that neither exceeds ±10 V from common.
6
The AD743 does not exhibit an output phase reversal when the negative common-mode limit is exceeded.
All min and max specifications are guaranteed.
Specifications subject to change without notice.
REV. E–2–
Page 3
AD743
ABSOLUTE MAXIMUM RATINGS
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18 V
Internal Power Dissipation
2
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±V
Output Short Circuit Duration . . . . . . . . . . . . . . . . Indefinite
Differential Input Voltage . . . . . . . . . . . . . . . . . . +V
Storage Temperature Range (N, R) . . . . . . . –65°C to +125°C
Operating Temperature Range
AD743J . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Lead Temperature Range (Soldering 60 sec) . . . . . . . . . 300°C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; and functional operation
of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2
8-lead PDIP: JA = 100°C/W, JC = 30°C/W.
16-lead SOIC: JA = 100°C/W, JC = 30°C/W.
1
ORDERING GUIDE
Temperature Package
Model Range Option*
S
AD743JN 0°C to 70°C N-8
and –V
S
S
AD743JR-16 0°C to 70°C R-16
AD743JR-16-REEL 0°C to 70°CTape and Reel
AD743JR-16-REEL7 0°C to 70°CTape and Reel
*N = PDIP; R = SOIC.
ESD SUSCEPTIBILITY
An ESD classification per method 3015.6 of MIL-STD-883C has
been performed on the AD743. The AD743 is a Class 1 device,
passing at 1000 V and failing at 1500 V on null Pins 1 and 5,
when tested, using an IMCS 5000 automated ESD tester. Pins
other than null pins fail at greater than 2500 V.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD743 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
REV. E
–3–
Page 4
AD743–Typical Performance Characteristics
0
(ⴞV)
0
k
(Hz)
0
(@ 25ⴗC, VS = 15 V)
20
R
= 10k⍀
LOAD
15
10
5
INPUT VOLTAGE SWING (V)
0
0510
SUPPLY VOLTAGE (ⴞV)
+V
IN
–V
IN
15 2
TPC 1. Input Voltage Swing vs.
Supply Voltage
12
9
6
3
QUIESCENT CURRENT (mA)
20
R
= 10k⍀
LOAD
15
10
50
OUTPUT VOLTAGE SWING (V)
0
0510
POSITIVE
SUPPLY
NEGATIVE
SUPPLY
SUPPLY VOLTAGE (ⴞV)
TPC 2. Output Voltage Swing
vs. Supply Voltage
–6
10
–7
10
–8
10
–9
10
–10
10
INPUT BIAS CURRENT (A)
–11
10
15 20
35
30
25
20
15
10
5
OUTPUT VOLTAGE SWING (V p-p)
0
10 100 1k
LOAD RESISTANCE (⍀)
TPC 3. Output Voltage Swing
vs. Load Resistance
200
100
10
1
0.1
OUTPUT IMPEDANCE (⍀)
10
0
0510
SUPPLY VOLTAGE
15 20
TPC 4. Quiescent Current vs.
Supply Voltage
300
200
100
INPUT BIAS CURRENT (pA)
0
–12 –9 3 6 9 12–6
–3 0
COMMON-MODE VOLTAGE (V)
TPC 7. Input Bias Current vs.
Common-Mode Voltage
–12
10
–60 –40 –20 0 20 40 60 80 100 120 140
TEMPERATURE (ⴗC)
TPC 5. Input Bias Current vs.
Temperature
80
70
60
50
40
30
CURRENT LIMIT (mA)
20
10
0
–60 –40 –20 0 20 40 60 80 100 120 14
+ OUTPUT
CURRENT
– OUTPUT
CURRENT
TEMPERATURE (ⴗC)
TPC 8. Short Circuit Current
Limit vs. Temperature
0.01
10k 100k 1M
FREQUENCY
10M 100M
TPC 6. Output Impedance vs.
Frequency (Closed-Loop Gain = –1)
7.0
6.0
5.0
4.0
3.0
GAIN BANDWIDTH PRODUCT (MHz)
2.0
–60 –40 –20 0 20 40 60 80 100 120 14
TEMPERATURE (ⴗC)
TPC 9. Gain Bandwidth Product
vs. Temperature
REV. E–4–
Page 5
AD743
k
k
k
100
80
60
40
20
OPEN-LOOP GAIN (dB)
0
–20
100 1k 10k 100k
GAIN
1M 10M 100M
FREQUENCY (Hz)
TPC 10. Open-Loop Gain and
Phase vs. Frequency
120
100
80
60
40
20
COMMON-MODE REJECTION (dB)
0
100 1k 10k
VCM = ⴞ10V
FREQUENCY (Hz)
TPC 13. Common-Mode
Rejection vs. Frequency
PHASE
100k 1M
100
80
60
40
20
PHASE MARGIN (Degrees)
0
–20
3.5
3.0
2.5
SLEW RATE (V/s)
2.0
TPC 11. Slew Rate vs. Temperature
(Gain = –1)
120
100
80
60
40
20
POWER SUPPLY REJECTION (dB)
TPC 14. Power Supply Rejection
vs. Frequency
–60 –40 –20 0 20 40 60 80 100 120 140
0
100 1k 10k 100k
TEMPERATURE (ⴗC)
+ SUPPLY
– SUPPLY
1M 10M 100M
FREQUENCY (Hz)
150
140
130
120
OPEN-LOOP GAIN (dB)
100
80
0510
SUPPLY VOLTAGE (ⴞV)
15 20
TPC 12. Open-Loop Gain vs.
Supply Voltage, R
35
30
25
20
15
10
OUTPUT VOLTAGE (V p-p)
5
0
10 100 1k
FREQUENCY (Hz)
LOAD
RL = 2k⍀
= 2 k
Ω
TPC 15. Large Signal Frequency
Response
10
–70
–80
–90
–100
–110
THD (dB)
–120
–130
–140
10 100 1k
GAIN = +10
GAIN = –1
10k 100
FREQUENCY (Hz)
TPC 16. Total Harmonic Distortion
vs. Frequency
REV. E
100
CLOSED-LOOP GAIN = ⴙ1
10
1
0.1
110100 1k 10k 100k 1M 10M
VOLTAGE NOISE (PREFERRED TO INPUT) (nV/ Hz)
CLOSED-LOOP GAIN = ⴙ10
FREQUENCY (Hz)
TPC 17. Input Voltage Noise
Spectral Density
–5–
1k
100
10
1
CURRENT NOISE SPECTRAL DENSITY (fA/ Hz)
110100 1k
FREQUENCY (Hz)
TPC 18. Input Current Noise
Spectral Density
10k 100
Page 6
AD743
69
63
57
51
45
39
33
27
NUMBER OF UNITS
21
15
9
3
2.5
2.7 2.9 3.1
INPUT VOLTAGE NOISE (nV/ Hz)
3.3
TPC 19. Typical Noise Distribution @ 10 kHz (602 Units)
3.8
3.5
TPC 23. Unity-Gain Follower Small
Signal Pulse Response
100pF
+V
0.1F
1F
2
3
AD743
–V
S
7
4
S
0.1F
1F
6
5
1
V
ADJUST
OS
TPC 20. Offset Null Configuration
+V
300⍀
V
IN
*
SQUARE WAVE
INPUT
S
7
2
AD743
3
4
–V
S
1F
*OPTIONAL, NOT REQUIRED
1F
6
0.1F
2k⍀
0.1F
TPC 21. Unity-Gain Follower
2k⍀
+V
2M⍀
1M⍀
2k⍀
V
IN
SQUARE WAVE
INPUT
2
3
7
AD743
4
–V
S
S
1F
1F
6
0.1F
0.1F
100pF
V
C
OUT
L
TPC 24. Unity-Gain Inverter
R
L
L
10pF
V
OUT
C
TPC 25. Unity-Gain Inverter Large Signal Pulse Response
TPC 22. Unity-Gain Follower Large Signal Pulse Response
TPC 26. Unity-Gain Inverter Small Signal Pulse Response
REV. E–6–
Page 7
AD743
OP AMP PERFORMANCE: JFET VS. BIPOLAR
The AD743 is the first monolithic JFET op amp to offer the low
input voltage noise of an industry-standard bipolar op amp without
its inherent input current errors. This is demonstrated in Figure 2,
which compares input voltage noise versus input source resistance of the OP27 and AD743 op amps. From this figure, it is
clear that at high source impedance the low current noise of the
AD743 also provides lower total noise. It is also important to
note that with the AD743 this noise reduction extends all the
way down to low source impedances. The lower dc current errors
of the AD743 also reduce errors due to offset and drift at high
source impedances (Figure 3).
1000
)
z
H
/
(nV
E
IS
O
N
E
G
LTA
O
T V
U
P
IN
R
SOURCE
E
O
R
100
SOURCE
AD743 AND RESISTOR
OR
OP27 AND RESISTOR
10
RESISTOR NOISE ONLY
(– – –)
1
100 1k 10k 100k
SOURCE RESISTANCE (⍀)
OP27 AND
RESISTOR
( — )
AD743 AND
RESISTOR
(
)
1M 10M
Figure 2. Total Input Noise Spectral Density @ 1 kHz
vs. Source Resistance
100
OP27
10
low frequency noise performance. Random air currents can generate varying thermocouple voltages that appear as low frequency
noise; therefore, sensitive circuitry should be well shielded from
air flow. Keeping absolute chip temperature low also reduces low
frequency noise in two ways. First, the low frequency noise is
strongly dependent on the ambient temperature and increases
above +25°C. Second, since the gradient of temperature from the
IC package to ambient is greater, the noise generated by random
air currents, as previously mentioned, will be larger in magnitude.
Chip temperature can be reduced both by operation at reduced
supply voltages and by the use of a suitable clip-on heat sink,
if possible.
Low frequency current noise can be computed from the magnitude of the dc bias current
˜
= 2 ∆
IqIf
nB
and increases below approximately 100 Hz with a 1/f power spectral
density. For the AD743, the typical value of current noise is
6.9 fA/√Hz at 1 kHz. Using the formula
˜
= 4 ∆
n
/IkTRf
to compute the Johnson noise of a resistor, expressed as a current,
one can see that the current noise of the AD743 is equivalent to
that of a 3.45 10
8
Ω source resistance.
At high frequencies, the current noise of a FET increases proportionately to frequency. This noise is due to the “real” part of
the gate input impedance, which decreases with frequency. This
noise component usually is not important, since the voltage noise
of the amplifier impressed upon its input capacitance is an apparent current noise of approximately the same magnitude.
In any FET input amplifier, the current noise of the internal
bias circuitry can be coupled externally via the gate-to-source
capacitances and appears as input current noise. This noise is
totally correlated at the inputs, so source impedance matching will tend to cancel out its effect. Both input resistance and
input capacitance should be balanced whenever dealing with
source capacitances of less than 300 pF in value.
1
INPUT OFFSET VOLTAGE (mV)
0.1
100
1k 10k 100k
SOURCE RESISTANCE (⍀)
AD743
1M 10M
Figure 3. Input Offset Voltage vs. Source Resistance
DESIGNING CIRCUITS FOR LOW NOISE
An op amp’s input voltage noise performance is typically divided
into two regions: flatband and low frequency noise. The AD743
offers excellent performance with respect to both. The figure of
2.9 nV/√Hz @ 10 kHz is excellent for a JFET input amplifier. The
0.1 Hz to 10 Hz noise is typically 0.38 µV p-p. The user should
pay careful attention to several design details in order to optimize
REV. E
–7–
LOW NOISE CHARGE AMPLIFIERS
As stated, the AD743 provides both low voltage and low current
noise. This combination makes this device particularly suitable
in applications requiring very high charge sensitivity, such as
capacitive accelerometers and hydrophones. When dealing with
a high source capacitance, it is useful to consider the total input
charge uncertainty as a measure of system noise.
Charge (Q) is related to voltage and current by the simply stated
fundamental relationships
==and
QCV I
dQ
dt
As shown, voltage, current, and charge noise can all be directly
related. The change in open circuit voltage (∆V) on a capacitor
will equal the combination of the change in charge (∆Q/C) and
the change in capacitance with a built in charge (Q/∆C).
Page 8
AD743
k
Figures 4 and 5 show two ways to buffer and amplify the output of
a charge output transducer. Both require using an amplifier that
has a very high input impedance, such as the AD743. Figure 4
shows a model of a charge amplifier circuit. Here, amplification depends on the principle of conservation of charge at the
input of amplifier A1, which requires that the charge on capaci-
be transferred to capacitor CF, thus yielding an output
tor C
S
voltage of ∆Q/CF. The amplifier’s input voltage noise will appear at
the output amplified by the noise gain (1 + (C
C
F
R
*
R1
B
R2
C
S
CB*
*OPTIONAL, SEE TEXT
A1
R1
*
R
B
=
R2
)) of the circuit.
S/CF
C
S
C
F
Figure 4. Charge Amplifier Circuit
R1
CB*
*
R2
R
C
*OPTIONAL, SEE TEXT
A2
B
R
S
B
Figure 5. Model for a High Z Follower with Gain
The circuit in Figure 5 is simply a high impedance follower with
gain. Here the noise gain (1 + (R1/R2)) is the same as the gain
from the transducer to the output. In both circuits, resistor R
is
B
required as a dc bias current return.
There are three important sources of noise in these circuits.
Amplifiers A1 and A2 contribute both voltage and current noise,
while resistor R
contributes a current noise of
B
˜
Nk
T
= 4 ∆
R
B
f
where
k = Boltzman’s Constant = 1.381 × 10
–23
joules/kelvin
T = Absolute Temperature, kelvin (0°C = 273.2 kelvin)
f = Bandwidth—in Hz (assuming an ideal “brick wall” filter)
This must be root-sum-squared with the amplifier’s own
current noise.
Figure 6 shows that these circuits in Figures 4 and 5 have an
identical frequency response and noise performance (provided
that C
network is used to increase the effective resistance of R
= R1/ R2). One feature of the first circuit is that a “T”
S/CF
and to
B
improve the low frequency cutoff point by the same factor.
–100
–110
–120
Hz
–130
–140
–150
–160
–170
–180
–190
DECIBELS REFERENCED TO 1V/
–200
–210
–220
0.01
0.1
110100
NOISE
DUE TO
ALONE
R
B
FREQUENCY (Hz)
NOISE
DUE TO
ALONE
I
B
1k
TOTAL
OUTPUT
NOISE
10k 100
Figure 6. Noise at the Outputs of the Circuits of
Figures 4 and 5. Gain = +10, C
= 3000 pF, RB = 22 M
S
Ω
However, this does not change the noise contribution of RB which,
in this example, dominates at low frequencies. The graph of
Figure 7 shows how to select an R
large enough to minimize
B
this resistor’s contribution to overall circuit noise. When the
equivalent current noise of R
((√4kT)/R equals the noise of I
B
B
(√2qIB), there is diminishing return in making RB larger.
10
5.2 ⴛ 10
9
5.2 ⴛ 10
8
5.2 ⴛ 10
RESISTANCE (⍀)
7
5.2 ⴛ 10
6
5.2 ⴛ 10
1pA 10pA 100pA 1nA 10nA
INPUT BIAS CURRENT
Figure 7. Graph of Resistance vs. Input Bias Current
√4kT/R
Where the Equivalent Noise
of the Bias Current
√2qI
B
, Equals the Noise
To maximize dc performance over temperature, the source
resistances should be balanced on each input of the amplifier.
This is represented by the optional resistor R
in Figures 4 and 5.
B
As previously mentioned, for best noise performance, care should
be taken to also balance the source capacitance designated by C
The value for C
At values of C
noise; capacitor C
in Figure 4 would be equal to CS in Figure 5.
B
over 300 pF, there is a diminishing impact on
B
can then be simply a large bypass of 0.01 µF
B
.
B
or greater.
REV. E–8–
Page 9
AD743
HOW CHIP PACKAGE TYPE AND POWER DISSIPATION AFFECT INPUT BIAS CURRENT
As with all JFET input amplifiers, the input bias current of
the AD743 is a direct function of device junction temperature,
approximately doubling every 10°C. Figure 8 shows the rela-
I
B
tionship between the bias current and the junction temperature
for the AD743. This graph shows that lowering the junction
= ±15V
S
.
B
temperature will dramatically improve I
–6
10
–7
10
–8
10
TA = 25ⴗC
–9
10
–10
10
INPUT BIAS CURRENT (A)
–11
10
–12
10
–60 –40 –20 0 20 40 60 80 100 120 140
JUNCTION TEMPERATURE (ⴗC)
V
Figure 8. Input Bias Current vs. Junction Temperature
The dc thermal properties of an IC can be closely approximated
by using the simple model of Figure 9, where current represents
power dissipation, voltage represents temperature, and resistors
represent thermal resistance ( in °C/W).
T
J
P
IN
P
= DEVICE DISSIPATION
IN
T
= AMBIENT TEMPERATURE
A
T
= JUNCTION TEMPERATURE
J
= THERMAL RESISTANCE—JUNCTION TO CASE
JC
= THERMAL RESISTANCE—CASE TO AMBIENT
CA
CA
JC
JA
T
A
Figure 9. Device Thermal Model
From this model, TJ = TA + JA PIN. Therefore, IB can be determined in a particular application by using Figure 8 together with
the published data for
modify
by using of an appropriate clip-on heat sink, such as
JA
the Aavid No. 5801.
and power dissipation. The user can
JA
is also a variable when using the AD743
JA
in chip form. Figure 10 shows the bias current versus the supply
voltage with
predict bias current after
as the third variable. This graph can be used to
JA
has been computed. Again, bias cur-
JA
rent will double for every 10°C. The designer using the AD743
in chip form (Figure 11) must also be concerned with both
and CA, since JC can be affected by the type of die mount
JC
technology used.
Typically,
will be in the 3°C/W to 5°C/W range; therefore,
JC
for normal packages, this small power dissipation level may be
ignored. But, with a large hybrid substrate,
proportionately more of the total
.
JA
will dominate
JC
300
= +25 C
T
A
200
= 115 C/W
100
INPUT BIAS CURRENT (pA)
0
51510
JA
SUPPLY VOLTAGE ( V)
= 165 C/W
JA
JA
= 0 C/W
Figure 10. Input Bias Current vs. Supply Voltage
for Various Values of
T
A
CASE
JA
T
J
A
(J TO
DIE MOUNT)
B
(DIE MOUNT
TO CASE)
A + B =
JC
Figure 11. Breakdown of Various Package Thermal
Resistances
REDUCED POWER SUPPLY OPERATION FOR LOWER I
B
Reduced power supply operation lowers IB in two ways: first, by
lowering both the total power dissipation and second, by reducing the basic gate-to-junction leakage (Figure 10). Figure 12
shows a 40 dB gain piezoelectric transducer amplifier, which
operates without an ac-coupling capacitor over the –40°C to
+85°C temperature range. If the optional coupling capacitor is
used, this circuit will operate over the entire –55°C to +125°C
military temperature range.
100⍀
C1*
8
10
⍀**
TRANSDUCER
C
T
10
*OPTIONAL DC BLOCKING CAPACITOR
**OPTIONAL, SEE TEXT
10k⍀
CT**
+5V
AD743
8
⍀
–5V
Figure 12. Piezoelectric Transducer
REV. E
–9–
Page 10
AD743
AN INPUT IMPEDANCE COMPENSATED, SALLEN-KEY FILTER
The simple high-pass filter of Figure 13 has an important source
of error which is often overlooked. Even 5 pF of input capacitance
in amplifier A will contribute an additional 1% of pass-band amplitude error, as well as distortion, proportional to the C/V characteristics
of the input junction capacitance. The addition of the network
designated Z will balance the source impedance—as seen by
A—and thus eliminate these errors.
+V
500k⍀
Z
1000pF1000pF
500k⍀
S
A
–V
S
1000pF
Z
1000pF
500k⍀
500k⍀
Figure 13. Input Impedance Compensated
Sallen-Key Filter
TWO HIGH PERFORMANCE ACCELEROMETER AMPLIFIERS
Two of the most popular charge-out transducers are hydrophones
and accelerometers. Precision accelerometers are typically calibrated for a charge output (pC/g).* Figures 14a and 14b show
two ways in which to configure the AD743 as a low noise charge
amplifier for use with a wide variety of piezoelectric accelerometers. The input sensitivity of these circuits will be determined
by the value of capacitor C1 and is equal to
Q
∆∆V
OUT
OUT
=
C
1
The ratio of capacitor C1 to the internal capacitance (CT) of the
transducer determines the noise gain of this circuit (1 + C
/C1).
T
The amplifier’s voltage noise will appear at its output amplified
by this amount. The low frequency bandwidth of these circuits
will be dependent on the value of resistor R1. If a T network is
used, the effective value is R1(1 + R2/R3).
C1
1250pF
R1
B AND K MODEL
4370 OR
EQUIVALENT
*pC = PICOCOULOMBS
g = EARTH’S GRAVITATIONAL CONSTANT
110M⍀
(5 ⴛ 22M⍀)
R3
1k⍀
AD743
R2
9k⍀
OUTPUT
0.8mV/pC*
Figure 14a. Basic Accelerometer Circuit
C1
1250pF
R1
110M⍀
(5 ⴛ 22M⍀)
B AND K MODEL
4370 OR
EQUIVALENT
1k⍀
R3
2.2F
AD711
C2
AD743
9k⍀
R4
18M⍀
R5
18M⍀
C3
2.2F
R2
OUTPUT
0.8mV/pC
Figure 14b. Accelerometer Circuit Using a DC
Servo Amplifier
A dc servo loop (Figure 14b) can be used to assure a dc output
which is <10 mV, without the need for a large compensating
resistor when dealing with bias currents as large as 100 nA. For
optimal low frequency performance, the time constant of the
servo loop (R4C2 = R5C3) should be
2
R
1
Time Cons R
10 1 1
Ctant ≥+
3
R
LOW NOISE HYDROPHONE AMPLIFIER
Hydrophones are usually calibrated in the voltage out mode.
The circuits of Figures 15a and 15b can be used to amplify the
output of a typical hydrophone. Figure 15a shows a typical
dc-coupled circuit. The optional resistor and capacitor serve
to counteract the dc offset caused by bias currents flowing through
resistor R1. Figure 15b, a variation of the original circuit, has a
low frequency cutoff determined by an RC time constant equal to
Time Cons t
B AND K TYPE 8100
HYDROPHONE
INPUT SENSITIVITY = –179 dB re. 1V/Pa**
*OPTIONAL, SEE TEXT
**1V PER MICROPASCAL
R3
100⍀
tan =
2 100πΩ
C1*
R4*
8
⍀
10
C
R1
T
8
⍀
10
1
C
××
C
R2
1900⍀
AD743
OUTPUT
Figure 15a. Basic Hydrophone Amplifier
REV. E–10–
Page 11
AD743
R2
1900⍀
R3
100⍀
R4*
C
C
B AND K TYPE 8100
HYDROPHONE
C
T
INPUT SENSITIVITY = –179 dB re. 1V/Pa**
*OPTIONAL, SEE TEXT
**1V PER MICROPASCAL
C1*
AD743
R1
8
⍀
10
Figure 15b. AC-Coupled, Low Noise
Hydrophone Amplifier
R2
1900⍀
R3
100⍀
B AND K
TYPE 8100
HYDROPHONE
R4*
8
10
C
T
⍀
10
1M⍀
C1*
AD743
C2
0.27F
R5
R1
8
100k⍀
⍀
R6
AD711K
OUTPUT
R7
16M⍀
OUTPUT
16M⍀
where the dc gain is 1 and the gain above the low frequency cutoff
(1/(2πC
(100 Ω))) is the same as the circuit of Figure 15a. The
C
circuit of Figure 15c uses a dc servo loop to keep the dc output
at 0 V and to maintain full dynamic range for I
up to 100 nA.
B
The time constant of R7 and C2 should be larger than that of
R1 and C
for a smooth low frequency response.
T
The transducer shown has a source capacitance of 7500 pF. For
smaller transducer capacitances (≤300 pF), the lowest noise can
be achieved by adding a parallel RC network (R4 = R1, C1 = C
)
T
in series with the inverting input of the AD743.
BALANCING SOURCE IMPEDANCES
As mentioned previously, it is good practice to balance the
source impedances (both resistive and reactive) as seen by the
inputs of the AD743. Balancing the resistive components will
optimize dc performance over temperature because balancing
will mitigate the effects of any bias current errors. Balancing
input capacitance will minimize ac response errors due to the
amplifier’s input capacitance and, as shown in Figure 16, noise
performance will be optimized. Figure 17 shows the required
external components for noninverting (A) and inverting (B)
configurations.
40
30
20
DC OUTPUT 1mV FOR IB (AD743) 100nA
*OPTIONAL, SEE TEXT
Figure 15c. Hydrophone Amplifier Incorporating a
DC Servo Loop
R1
C
B
R
S
R
S
A
NONINVERTING
CONNECTION
A
= C
C
B
S
RB = R
S
FOR
>> R1 OR R2
OUTPUT
R
B
R2
C
S
Figure 17. Optional External Components for Balancing Source Impedances
UNBALANCED
BALANCED
10
RTI VOLTAGE NOISE (nV/√Hz)
2.9nV/√Hz
10 100 1000
INPUT CAPACITORS (pF)
Figure 16. RTI Voltage Noise vs. Input Capacitance
C
F
R1
B
R
C
S
S
C
R
B
B
INVERTING
CONNECTION
B
= CF 储 C
C
B
RB = R1 储 R
OUTPUT
S
S
REV. E
–11–
Page 12
AD743
8-Lead Plastic Dual In-Line Package [PDIP]
(N-8)
Dimensions shown in inches and (millimeters)
0.375 (9.53)
0.365 (9.27)
0.355 (9.02)
8
1
0.100 (2.54)
0.180
(4.57)
MAX
0.150 (3.81)
0.130 (3.30)
0.110 (2.79)
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
COMPLIANT TO JEDEC STANDARDS MO-095AA
BSC
5
4
0.295 (7.49)
0.285 (7.24)
0.275 (6.98)
0.015
(0.38)
MIN
SEATING
PLANE
0.060 (1.52)
0.050 (1.27)
0.045 (1.14)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
OUTLINE DIMENSIONS
16-Lead Standard Small Outline Package [SOIC]
0.150 (3.81)
0.135 (3.43)
0.120 (3.05)
0.015 (0.38)
0.010 (0.25)
0.008 (0.20)
0.30 (0.0118)
0.10 (0.0039)
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MS-013AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
Wide Body
(R-16)
Dimensions shown in millimeters and (inches)
10.50 (0.4134)
10.10 (0.3976)
16
1
1.27 (0.0500)
BSC
0.51 (0.0201)
0.33 (0.0130)
9
7.60 (0.2992)
7.40 (0.2913)
8
2.65 (0.1043)
2.35 (0.0925)
SEATING
PLANE
10.65 (0.4193)
10.00 (0.3937)
0.32 (0.0126)
0.23 (0.0091)
0.75 (0.0295)
0.25 (0.0098)
8ⴗ
0ⴗ
C00830–0–7/03(E)
ⴛ 45ⴗ
1.27 (0.0500)
0.40 (0.0157)
Revision History
Location Page
7/03—Data Sheet changed from REV. D to REV. E.
Deleted K Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal
Changes to GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2/02—Data Sheet changed from REV. C to REV. D.
Edits to PRODUCT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Edits to CONNECTION DIAGRAMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Deleted AD7435 column from SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Edits to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Deleted METALLIZATION PHOTOGRAPH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Edits to REDUCE POWER SUPPLY OPERATION FOR LOWER I
Deleted 8-Pin CERDIP (Q) package drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
B
–12–
REV. E
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