Datasheet AD7401A Datasheet (ANALOG DEVICES)

V

V

V

Isolated Sigma-Delta Modulator

FEATURES

20 MHz maximum external clock rate
Second-order modulator
16 bits, no missing codes
±2 LSB INL typical at 16 bits
1 μV/°C typical offset drift
On-board digital isolator
On-board reference
±250 mV analog input range
Low power operation: 17 mA typical at 5.5 V

−40°C to +125°C operating range
16-lead SOIC package
Internal clock version: AD7400A
Safety and regulatory approvals

UL recognition

3750 V rms for 1 minute per UL 1577
CSA Component Acceptance Notice #5A
VDE Certificate of Conformity

DIN V VDE V 0884-10 (VDE V 0884-10):2006-12

V

= 891 V peak

IORM

APPLICATIONS

AC motor controls
Shunt current monitoring
Data acquisition systems
Analog-to-digital and opto-isolator replacements

AD7401A

GENERAL DESCRIPTION

The AD7401A1 is a second-order, sigma-delta (Σ-Δ) modulator
that converts an analog input signal into a high speed, 1-bit data
stream with on-chip digital isolation based on Analog Devices,
Inc., iCoupler® technology. The AD7401A operates from a 5 V
power supply and accepts a differential input signal of ±250 mV
(±320 mV full scale). The analog input is continuously sampled
by the analog modulator, eliminating the need for external
sample-and-hold circuitry. The input information is contained
in the output stream as a density of ones with a data rate up to
20 MHz. The original information can be reconstructed with
an appropriate digital filter. The serial I/O can use a 5 V or a 3 V
supply (V

The serial interface is digitally isolated. High speed CMOS,
combined with monolithic air core transformer technology,
means the on-chip isolation provides outstanding performance
characteristics, superior to alternatives such as optocoupler
devices. The part contains an on-chip reference. The AD7401A
is offered in a 16-lead SOIC and has an operating temperature
range of −40°C to +125°C.

DD2

).

FUNCTIONAL BLOCK DIAGRAM

DD1

+

IN

VIN–

1

Protected by U.S. Patents 5,952,849; 6,873,065; and 7,075,329. Other patents pending.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

REF

H

/

T

U

B

F

Σ-Δ ADC

CONTROL LOG IC

GND

UPDATE

WATC HDOG

1

Figure 1.

DD2

AD7401A

WATCHDOG

ENCODE DECODE

UPDATE

DECODE

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2008 Analog Devices, Inc. All rights reserved.

ENCODE

GND

MDAT

MCLKIN

2

07332-001

AD7401A

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Timing Specifications .................................................................. 5

Insulation and Safety-Related Specifications ............................ 6

Regulatory Information ............................................................... 6

DIN V VDE V 0884-10 (VDE V 0884-10) Insulation

Characteristics .............................................................................. 7

Absolute Maximum Ratings ............................................................ 8

ESD Caution .................................................................................. 8

Pin Configuration and Function Descriptions ............................. 9

Typical Performance Characteristics ........................................... 10

Terminology .................................................................................... 13

Theory of Operation ...................................................................... 14

Circuit Information .................................................................... 14

Analog Input ............................................................................... 14

Differential Inputs ...................................................................... 15

Current Sensing Applications ................................................... 15

Voltage Sensing Applications .................................................... 15

Digital Filter ................................................................................ 16

Applications Information .............................................................. 18

Grounding and Layout .............................................................. 18

Evaluating the AD7401A Performance ................................... 18

Insulation Lifetime ..................................................................... 18

Outline Dimensions ....................................................................... 19

Ordering Guide .......................................................................... 19

REVISION HISTORY

7/08—Revision 0: Initial Version

Rev. 0 | Page 2 of 20

AD7401A

SPECIFICATIONS

V

= 4.5 V to 5.5 V, V

DD1

16 MHz maximum,

= 3 V to 5.5 V, VIN+ = −200 mV to +200 mV, and VIN− = 0 V (single-ended); TA = −40°C to +125°C, f

DD2

1

tested with sinc3 filter, 256 decimation rate, as defined by Verilog code, unless otherwise noted.

MCLKIN

=

Table 1.

1, 2

Y Version

Parameter

STATIC PERFORMANCE

Resolution
Integral Nonlinearity (INL)

3

16 Bits Filter output truncated to 16 bits

±1.5 ±7 LSB
±2 ±13 LSB
±1.5 ±11 LSB
±2 ±46 LSB

Differential Nonlinearity (DNL)

3

Offset Error
Offset Drift vs. Temperature
Offset Drift vs. V
Gain Error

3

DD1

3

3

±0.9 LSB Guaranteed no missed codes to 16 bits,

±.025 ±0.5 mV

1 3.5 μV/°C

120 μV/V

0.07 ±1.5 mV

3

±1 mV
Gain Error Drift vs. Temperature
Gain Error Drift vs. V

DD1

3

3

23 μV/°C

110 μV/V

ANALOG INPUT

Input Voltage Range

±200 ±250 mV For specified performance; full range ±320 mV

Dynamic Input Current ±13 ±18 μA
±10 ±15 μA

0.08 μA
DC Leakage Current ±0.01 ±0.6 μA
Input Capacitance 10 pF

DYNAMIC SPECIFICATIONS VIN+ = 5 kHz

3

Signal-to-(Noise + Distortion) Ratio (SINAD)

76 82 dB VIN+ = ±200 V, TA = −40°C to +85°C,

71 82 dB VIN+ = ±250 V, TA = −40°C to +85°C,

72 82 dB VIN+ = ±200 V, TA = −40°C to +125°C,

82 dB VIN+ = ±250 V, TA = −40°C to +125°C,

Signal-to-Noise Ratio (SNR)

3

81 83 dB VIN+ = ±250 V, TA = −40°C to +125°C,

80 82 dB VIN+ = ±200 V, TA = −40°C to +125°C,

Total Harmonic Distortion (THD)3
Peak Harmonic or Spurious Noise (SFDR)
Effective Number of Bits (ENOB)3
Isolation Transient Immunity

LOGIC INPUTS

3

Input High Voltage, VIH 0.8 × V

−90 dB

3

−92 dB

13.3 12.3 Bits

25 30 kV/μs

V

DD2

Input Low Voltage, VIL 0.2 × V
Input Current, IIN ±0.5 μA
Floating State Leakage Current 1 μA
Input Capacitance, C

4

10 pF

IN

Unit Test Conditions/Comments Min Typ Max

V

+ = ±200 V, TA = −40°C to +85°C, f

V

DD2

IN

V

+ = ±250 V, TA = −40°C to +85°C, f

IN

V

+ = ±200 V, TA = −40°C to +125°C, f

IN

V

+ = ±250 V, TA = −40°C to +125°C, f

IN

f

= 20 MHz max,1 VIN+ = −250 mV to +250 mV

MCLKIN

f

= 20 MHz max,1 VIN+ = −250 mV to +250 mV

MCLKIN

f

= 20 MHz max,1 VIN+ = −250 mV to +250 mV

MCLKIN

V

+ = 500 mV, VIN− = 0 V, f

IN

V

+ = 400 mV, VIN− = 0 V, f

IN

V

+ = 0 V, VIN− = 0 V, f

IN

f

= 5 MHz to 20 MHz

MCLKIN

f

= 5 MHz to 20 MHz

MCLKIN

f

= 5 MHz to 20 MHz

MCLKIN

f

= 5 MHz to 20 MHz

MCLKIN

f

= 5 MHz to 20 MHz

MCLKIN

f

= 5 MHz to 20 MHz

MCLKIN

f

= 20 MHz max1, VIN+ = −250 mV to +250 mV

MCLKIN

MCLKIN

1

1

1

1

1

1

MCLKIN

MCLKIN

= 20 MHz max

MCLKIN

= 20 MHz max

MCLKIN

= 20 MHz max

= 20 MHz max
= 20 MHz max

= 20 MHz max

MCLKIN

= 20 MHz max

MCLKIN

1

1

1

1

1

1

1

Rev. 0 | Page 3 of 20

AD7401A

1, 2

Y Version

Parameter

Unit Test Conditions/Comments Min Typ Max

LOGIC OUTPUTS

Output High Voltage, VOH V

− 0.1 V IO = −200 μA

DD2

Output Low Voltage, VOL 0.4 V IO = +200 μA

POWER REQUIREMENTS

V

4.5 5.5 V

DD1

V

3 5.5 V

DD2

5

I

10 12 mA V

DD1

6

I

DD2

7 9 mA V

3 4 mA V

Power Dissipation

1

For f

> 16 MHz to 20 MHz, mark space ratio is 48/52 to 52/48, V

MCLK

2

All voltages are relative to their respective ground.

3

See the section. Terminology

4

Sample tested during initial release to ensure compliance.

5

See . Figure 15

6

See . Figure 17

93.5 mW V

= V

= 5 V ± 5%, and TA = −40°C to +85°C.

DD1

DD2

= 5.5 V

DD1

= 5.5 V

DD2

= 3.3 V

DD2

= V

DD1

= 5.5 V

DD2

Rev. 0 | Page 4 of 20

AD7401A

TIMING SPECIFICATIONS

V

= 4.5 V to 5.5 V, V

DD1

= 3 V to 5.5 V, TA = −40°C to +125°C, unless otherwise noted.

DD2

Table 2.

1

2, 3

Limit at T

20 MHz max Master clock input frequency

MIN

, T

MAX

Unit Description

Parameter

f

MCLKIN

5 MHz min Master clock input frequency

4

t

1

4

t

2

t3 0.4 × t
t

4

1

Sample tested during initial release to ensure compliance.

2

Mark space ratio for clock input is 40/60 to 60/40 for f

3

V

= V

= 5 V ± 5% for f

DD1

DD2

4

Measured with the load circuit of and defined as the time required for the output to cross 0.8 V or 2.0 V. Figure 2

25 ns max Data access time after MCLKIN rising edge
15 ns min Data hold time after MCLKIN rising edge

ns min Master clock low time

MCLKIN

0.4 × t

ns min Master clock high time

MCLKIN

> 16 MHz to 20 MHz.

MCLKIN

≤ 16 MHz and 48/52 to 52/48 for 16 MHz < f

MCLKIN

MCLKIN

< 20 MHz.

200µA I

TO OUTPUT

PIN

C

L

25pF

200µA I

Figure 2. Load Circuit for Digital Output Timing Specifications

OL

1.6V

OH

07332-002

t

4

MCLKIN

MDAT

t

1

Figure 3. Data Timing

t

2

t

3

07332-003

Rev. 0 | Page 5 of 20

AD7401A

INSULATION AND SAFETY-RELATED SPECIFICATIONS

Table 3.

Parameter Symbol Value Unit Conditions

Input-to-Output Momentary Withstand Voltage V
Minimum External Air Gap (Clearance) L(I01) 7.46 min mm

Minimum External Tracking (Creepage) L(I02) 8.1 min mm

Minimum Internal Gap (Internal Clearance) 0.017 min mm Insulation distance through insulation
Tracking Resistance (Comparative Tracking Index) CTI >175 V DIN IEC 112/VDE 0303 Part 1
Isolation Group IIIa Material Group (DIN VDE 0110, 1/89, Table I)

REGULATORY INFORMATION

Table 4.

1

UL

CSA VDE

Recognized Under 1577
Component Recognition Program

3750 V rms Isolation Voltage

File E214100 File 205078 File 2471900-4880-0001

1

In accordance with UL 1577, each AD7401A is proof tested by applying an insulation test voltage ≥ 4500 V rms for 1 second (current leakage detection limit = 7.5 μA).

2

In accordance with DIN V VDE V 0884-10, each AD7400A is proof tested by applying an insulation test voltage ≥1671V peak for 1 sec (partial discharge detection limit = 5 pC).

Approved under CSA Component

1

Acceptance Notice #5A
Reinforced insulation per

CSA 60950-1-03 and IEC 60950-1,
630 V rms maximum working
voltage

3750 min V 1-minute duration

ISO

Measured from input terminals to output
terminals, shortest distance through air

Measured from input terminals to output
terminals, shortest distance path along body

2

Certified according to DIN V VDE V 0884-10
(VDE V 0884-10):2006-12

2

Reinforced insulation per DIN V VDE V 0884-10 (VDE V
0884-10):2006-12, 891 V peak

Rev. 0 | Page 6 of 20

AD7401A

DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 INSULATION CHARACTERISTICS

This isolator is suitable for reinforced electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by
means of protective circuits.

Table 5.

Description Symbol Characteristic Unit

INSTALLATION CLASSIFICATION PER DIN VDE 0110

For Rated Mains Voltage ≤ 300 V rms I to IV
For Rated Mains Voltage ≤ 450 V rms I to II

For Rated Mains Voltage ≤ 600 V rms I to II
CLIMATIC CLASSIFICATION 40/105/21
POLLUTION DEGREE (DIN VDE 0110, TABLE 1) 2
MAXIMUM WORKING INSULATION VOLTAGE V
INPUT-TO-OUTPUT TEST VOLTAGE, METHOD B1

V

× 1.875 = VPR, 100% Production Test, tm = 1 sec, Partial Discharge < 5 pC VPR 1671 V peak

IORM

INPUT-TO-OUTPUT TEST VOLTAGE, METHOD A VPR

After Environmental Test Subgroup 1 1426 V peak

V

× 1.6 = VPR, tm = 60 sec, Partial Discharge < 5 pC

IORM

After Input and/or Safety Test Subgroup 2/ Safety Test Subgroup 3 1069 V peak

V

× 1.2 = VPR, tm = 60 sec, Partial Discharge < 5 pC

IORM

HIGHEST ALLOWABLE OVERVOLTAGE (TRANSIENT OVERVOLTAGE, tTR = 10 sec) VTR 6000 V peak
SAFETY-LIMITING VALUES (MAXIMUM VALUE ALLOWED IN THE EVENT OF A FAILURE, SEE Figure 4)

Case Temperature TS 150 °C

Side 1 Current IS1 265 mA

Side 2 Current IS2 335 mA
INSULATION RESISTANCE AT TS, VIO = 500 V RS >109 Ω

350

891 V peak

IORM

300

250

200

150

100

SAFETY-LIMITING CURRENT (mA)

50

0

0

Figure 4. Thermal Derating Curve, Dependence of Safety-Limiting Values

with Case Temperature per DIN V VDE V 0884-10

SIDE #2

SIDE #1

50 100 150 200

CASE TEMPERATURE (°C)

07332-004

Rev. 0 | Page 7 of 20

AD7401A

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted. All voltages are relative to
their respective ground.

Table 6.

Parameter Rating

V

to GND

DD1

V

DD2

Analog Input Voltage to GND
Digital Input Voltage to GND
Output Voltage to GND
Input Current to Any Pin Except

Supplies

to GND

1

1

2

1

2

2

−0.3 V to +6.5 V

−0.3 V to +6.5 V

−0.3 V to V

−0.3 V to V

−0.3 V to V

+ 0.3 V

DD1

+ 0.5 V

DD1

+ 0.3 V

DD2

±10 mA

Operating Temperature Range −40°C to +125°C
Storage Temperature Range o +150°C −65°C t
Junction Temperature 150°C
SOIC Package

θJA Thermal Impedance

θJC Thermal Impedance
Resistance (Input to Output), R
Capacitance (Input to Output), C

2

89.2°C/W

2

W 55.6°C/

10

I-O

3

I-O

12

Ω

yp 1.7 pF t

Pb mperature, Soldering -Free Te

Reflow 260°C
ESD 1.5 kV

1

Transient currents of up to 100 mA do not cause SCR to latch up.

2

EDEC 2S2P

3

f = 1 MHz.

standard board.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

Table 7. Maximum Continuous Working Voltage

1

Parameter Max Unit Constraint

AC Voltage,

565 V peak 50-year minimum lifetime

Bipolar Waveform
AC Voltage,

Unipolar Waveform

891 V peak

Maximum CSA/VDE
approved working
voltage

DC Voltage 891 V

Maximum CSA/VDE
approved working
voltage

1

Refers to continuous voltage magnitude imposed across the isolation

barrier. See the Insulation Lifetime section for more details.

ESD CAUTION

Rev. 0 | Page 8 of 20

AD7401A

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

V

1

DD1

VIN+

2

VIN–

3

4

NC

5

NC

NC

6

V

7

DD1

GND

8

1

NC = NO CONNECT

AD7401A

TOP VIEW

(Not to Scal e)

16

15

14

13

12

11

10

9

GND

2

NC

V

DD2

MCLKIN

NC

MDAT

NC

GND

2

07332-005

Figure 5. Pin Configuration

Table 8. Pin Function Descriptions

Pin No. Mnemonic Description

1, 7 V

Supply Voltage, 4.5 V to 5.5 V. This is the supply voltage for the isolated side of the AD7401A and is relative to GND1.

DD1

2 VIN+ Positive Analog Input. Specified range of ±250 mV.
3 VIN−
4 to 6, 10,

NC No Connect.

Negative Analog Input. Normally connected to GND1.

12, 15
8 GND
9, 16 GND

1

2

11 MDAT

Ground 1. This is the ground reference point for all circuitry on the isolated side.
Ground 2. This is the ground reference point for all circuitry on the nonisolated side.
Serial Data Output. The single bit modulator output is supplied to this pin as a serial data stream.

The bits are clocked out on the rising edge of the MCLKIN input and valid on the following MCLKIN rising edge.
13 MCLKIN Master Clock Logic Input. 20 MHz maximum. The bit stream from the modulator is valid on the rising edge of MCLKIN.
14 V

Supply Voltage. 3 V to 5.5 V. This is the supply voltage for the nonisolated side and is relative to GND2.

DD2

Rev. 0 | Page 9 of 20

AD7401A

–

–

TYPICAL PERFORMANCE CHARACTERISTICS

TA = 25°C, using 25 kHz brick-wall filter, unless otherwise noted.

100

90

80

70

60

50

PSRR (dB)

40

30

20

200mV p-p SI NE WAVE O N V
NO DECOUPLING

10

V

DD1

1MHz CUTOFF FILT ER

0

0 1000

MCLKIN = 5MHz

= V

= 5V

DD2

100 200 300 400 500 600 700 800 900

SUPPLY RIPPLE FREQUENCY (kHz)

MCLKIN = 16MHz

MCLKIN = 10MHz

DD1

Figure 6. PSRR vs. Supply Ripple Frequency Without Supply Decoupling

07332-006

90

–85

–80

–75

–70

SINAD (dB)

–65

–60

–55

–50

0.17 0.33

0.18 0.19 0.20 0.21 0.22 0.23 0.24 0.25 0.26 0.27 0. 28 0.29 0.30 0.31 0.32

± INPUT AMPLI TUDE (V)

MCLKIN = 10MHz

MCLKIN = 16MHz

Figure 9. SINAD vs. V

V

= V

DD1

IN

DD2

= 5V

07332-009

90

–85

–80

–75

MCLKIN = 10MHz

–70

SINAD (dB)

–65

–60

–55

–50

0 10k

1k 2k 3k 4k 5k 6k 7k 8k 9k

INPUT FREQ UENCY (Hz)

MCLKIN = 16MHz

MCLKIN = 5MHz

V

= V

= 5 V

DD1

DD2

V

= V

DD2

= 5V

07332-007

DD1

Figure 7. SINAD vs. Analog Input Frequency

20

0

–20

–40

–60

–80

(dB)

–100

–120

–140

–160

–180

03

5 10152025

FREQUENCY (kHz)

4096 POINT FFT

f

= 5kHz

IN

SINAD = 81.984dB
THD = –96.311dB
DECIMATIO N BY 256

0

07332-008

0.4

0.3

0.2

0.1

0

–0.1

–0.2

DNL ERRO R (LSB)

–0.3

–0.4

VIN+ = –200mV TO +200mV

– = 0V

V

IN

–0.5

0 60k

10k 20k 30k 40k 50k

Figure 10. Typical DNL (±200 mV Range)

0.8
VIN+ = –200mV TO +200mV

– = 0V

V

IN

0.6

0.4

0.2

INL ERROR (L SB)

0

–0.2

–0.4

06

10k 20k 30k 40k 50k

CODE

CODE

07332-010

0k

07332-011

Figure 8. Typical FFT (±200 mV Range)

Figure 11. Typical INL (±200 mV Range)

Rev. 0 | Page 10 of 20

AD7401A

250

V

= V

200

150

100

DD1

MCLKIN = 16MHz

= 4.5V

DD2

V

= V

DD1

DD2

MCLKIN = 5MHz

V

= V

DD1

MCLKIN = 16MHz

= 4.5V

DD2

= 5V

V

= V

DD1

MCLKIN = 10MHz

= 4.5V

DD2

V

= V

DD1

DD2

MCLKIN = 5MHz

= 5V

50

0

–50

OFFSET (µV)

–100

–150

–200

–250

V

= V

DD1

MCLKIN = 16MHz

–45

–35 –25 –15 –5 5 15 25 35 45 55 65 75 85 95 105

= 5.25V

DD2

V

= V

DD1

DD2

MCLKIN = 10MHz

= 5V

V

= V

DD1

MCLKIN = 10MHz

= 5.25V

DD2

V

= V

DD1

DD2

MCLKIN = 5MHz

= 5.25V

TEMPERATURE (° C)

Figure 12. Offset Drift vs. Temperature for Various Supply Voltages

200.5
V

= V

GAIN (mV)

200.4

200.3

200.2

200.1

200.0

199.9

= V

= V

= V

= V

DD2

DD2

DD2

DD2

DD2

= 4.5V

= 4.5V

= 5V

= 5.25V

= 5V

DD1

MCLKIN = 16MHz

V

DD1

MCLKIN = 5MHz

V

DD1

MCLKIN = 16MHz

V

DD1

MCLKIN = 16MHz

V

DD1

MCLKIN = 10MHz

V

= V

DD1

= V

= V

= V

DD2

DD2

DD2

DD2

= 4.5V

= 5V

= 5.25V

= 5.25V

DD1

MCLKIN = 10MHz

V
MCLKIN = 5MHz

V

DD1

MCLKIN = 10MHz

V

DD1

MCLKIN = 5MHz

199.8

199.7

199.6

199.5

–45

–35 –25 –15 –5 5 15 25 35 45 55 65 75 85 95 105

TEMPERATURE (° C)

Figure 13. Gain Error Drift vs. Temperature for Various Supply Voltages

0.0105
V

= V

DD1

0.0100

0.0095

= 5V

DD2

MCLKIN = 16MHz

T

= –40°C

A

MCLKIN = 16MHz

T

= +85°C

A

MCLKIN = 16MHz

T

= +105°C

A

0.0090

MCLKIN = 10MHz

T

(A)

DD1

I

0.0085

0.0080

= –40°C

A

MCLKIN = 10MHz

0.0075

0.0070

0.0065

0.0060

07332-012

MCLKIN = 5MHz

T

= +85°C

A

–0.33 0.33–0.28 –0.23 –0.18 –0.13 –0.08 –0.03 0.03 0.08 0.13 0.18 0.23 0.28

Figure 15. I

MCLKIN = 5MHz

VIN DC INPUT VOL TAGE (V)

vs. VIN at Various Temperatures

DD1

0.0070

0.0065

MCLKIN = 16MHz

T

A

T

A

= +85°C

= –40°C

MCLKIN = 10MHz

T

= +105°C

A

MCLKIN = 5MHz

T

= +105°C

A

V

= V

DD1

T

= 25°C

A

DD2

= 5V

07332-015

0.0060

0.0055

0.0050

(A)

0.0045

DD2

I

0.0040

0.0035

0.0030

MCLKIN = 10MHz

MCLKIN = 5MHz

0.0025

0.0020

07332-013

–0.225 –0.125 –0.025 0.075 0.175

–0.325

VIN DC INPUT VOLTAGE ( V)

Figure 16. I

vs. VIN DC Input Voltage

DD2

0.275

0.325–0.275 –0.175 –0.075 0.025 0.125 0.225

07332-016

0.0105

0.0100

MCLKIN = 16MHz

0.0095

0.0090

(A)

DD1

I

0.0085
MCLKIN = 10MHz

0.0080

0.0075

MCLKIN = 5MHz

0.0070

0.0065

–0.33 0.33–0.28 –0.23 –0.18 –0.13 –0.08 –0.03 0.03 0.08 0.13 0.18 0.23 0.28

VIN DC INPUT VOL TAGE (V)

Figure 14. I

vs. VIN DC Input Voltage

DD1

V

DD1

T

A

= V

= 25°C

DD2

= 5V

07332-014

Rev. 0 | Page 11 of 20

0.0065

0.0060

0.0055

0.0050

(A)

0.0045

DD2

I

0.0040

0.0035

0.0030

0.0025

0.0070

0.0020

V

= V

DD1

–0.325

= 5V

DD2

MCLKIN = 16MHz

T

= +105°C

= –40°C

MCLKIN = 10MHz

A

T

A

MCLKIN = 16MHz

T

= –40°C

A

MCLKIN = 10MHz

T

A

MCLKIN = 5MHz

T

= –40°C

A

MCLKIN = 5MHz

T

= +85°C

A

–0.225 –0.125 –0.025 0.075 0.175

VIN DC INPUT VOLTAGE ( V)

Figure 17. I

vs. VIN at Various Temperatures

DD2

MCLKIN = 10MHz

= +85°C

MCLKIN = 16MHz

T

A

T

= +105°C

A

MCLKIN = 5MHz

T

= +105°C

A

= +85°C

0.275

0.325–0.275 –0.175 –0.075 0.025 0.125 0.225

07332-017

AD7401A

8

V

= V

DD1

6

4

= 4.5V TO 5.25V

DD2

MCLKIN = 16M Hz

MCLKIN = 10MHz

2

0

(µA)

IN

I

MCLKIN = 5MHz

–2

–4

–6

–8

–0.35

–0.30

–0.25

–0.20

–0.15

0

–0.10

VIN– DC INPUT (V)

0.05

–0.05

0.10

0.15

0.20

0.25

0.30

0.35

07332-018

Figure 18. IIN vs. VIN− DC Input

0

–20

–40

–60

CMRR (dB)

MCLKIN = 10MHz

–80

V

= V

DD1

V

= V

DD1

DD2

MCLKIN = 5MHz

= 5 V

DD2

= 5V

1.0
V

= V

DD2

= 5V

DD1

50kHz BRICK-WALL FILTER

0.8

0.6

0.4

NOISE (mV)

MCLKIN = 5MHz

0.2

0

0.05

MCLKIN = 16MHz

0.10

0.15

0.20

0.25

0.30

07332-020

MCLKIN = 10MHz

0

–0.30

–0.25

–0.20

–0.15

–0.10

–0.05

DC INPUT (V)

V

IN

Figure 20. RMS Noise Voltage vs. VIN DC Input

–100

–120

0.1 1000

1 10 100

RIPPLE FREQUENCY (kHz)

MCLKIN = 16MHz

07332-019

Figure 19. CMRR vs. Common-Mode Ripple Frequency

Rev. 0 | Page 12 of 20

AD7401A

TERMINOLOGY

Differential Nonlinearity (DNL)

DNL is the difference between the measured and the ideal 1
LSB change between any two adjacent codes
in the ADC.

Integral Nonlinearity (INL)

INL is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function. The
endpoints of the transfer function are specified negative full
scale, −250 mV (V
and specified positive full scale, +250 mV (V

+ − VIN−), Code 7169 for the 16-bit level,

IN

+ − VIN−), Code

IN

58366 for the 16-bit level.

Offset Error

Offset error is the deviation of the midscale code (32768 for the
16-bit level) from the ideal V

+ − VIN− (that is, 0 V).

IN

Gain Error

The gain error includes both positive full-scale gain error and
negative full-scale gain error. Positive full-scale gain error is the
deviation of the specified positive full-scale code (58366 for the
16-bit level) from the ideal V

+ − VIN− (+250 mV) after the

IN

offset error is adjusted out. Negative full-scale gain error is the
deviation of the specified negative full-scale code (7169 for the
16-bit level) from the ideal V

+ − VIN− (−250 mV) after the

IN

offset error is adjusted out. Gain error includes reference error.

Signal-to-(Noise and Distortion) Ratio (SINAD)

SINAD is the measured ratio of signal-to-noise and distortion
at the output of the ADC. The signal is the rms amplitude of the
fundamental. Noise is the sum of all nonfundamental signals up
to half the sampling frequency (f

/2), excluding dc. The ratio is

S

dependent on the number of quantization levels in the digitization
process; the more levels, the smaller the quantization noise. The
theoretical signal-to-(noise and distortion) ratio for an ideal
N-bit converter with a sine wave input is given by

Signal-to-(Noise and Distortion) = (6.02N + 1.76) dB

Therefore, for a 12-bit converter, this is 74 dB.

Effective Number of Bits (ENOB)

ENOB is defined by

ENOB = (SINAD − 1.76)/6.02 bits

Total Harmonic Distortion (THD)

THD is the ratio of the rms sum of harmonics to the
fundamental. For the AD7401A, it is defined as

22222

++++

VVVVV

54

THD

log20(dB)

=

32

V

1

6

where:

V

is the rms amplitude of the fundamental.

1

V

, V3, V4, V5, and V6 are the rms amplitudes of the second

2

through the sixth harmonics.

Peak Harmonic or Spurious Noise

Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to f

/2, excluding dc) to the rms value of the

S

fundamental. Normally, the value of this specification is
determined by the largest harmonic in the spectrum, but
for ADCs where the harmonics are buried in the noise floor,
it is a noise peak.

Common-Mode Rejection Ratio (CMRR)

CMRR is defined as the ratio of the power in the ADC output
at ±250 mV frequency, f, to the power of a 250 mV p-p sine
wave applied to the common-mode voltage of V
of frequency, f

CMRR (dB) = 10 .log(Pf/Pf

, as

S

)

S

+ and VIN−

IN

where:

Pf is the power at frequency, f, in the ADC output.
Pf

is the power at frequency, fS, in the ADC output.

S

Power Supply Rejection Ratio (PSRR)

Variations in power supply affect the full-scale transition but
not the converter’s linearity. PSRR is the maximum change in
the specified full-scale (±250 mV) transition point due to a
change in power supply voltage from the nominal value (see
Figure 6).

Isolation Transient Immunity

The isolation transient immunity specifies the rate of rise/fall of
a transient pulse applied across the isolation boundary beyond
which clock or data is corrupted. The AD7401A was tested
using a transient pulse frequency of 100 kHz.

Rev. 0 | Page 13 of 20

AD7401A

A

L

A

THEORY OF OPERATION

CIRCUIT INFORMATION

The AD7401A isolated Σ-Δ modulator converts an analog input
signal into a high speed (20 MHz maximum), single-bit data
stream; the time average single-bit data from the modulators
is directly proportional to the input signal. Figure 23 shows a
typical application circuit where the AD7401A is used to provide
isolation between the analog input, a current sensing resistor,
and the digital output, which is then processed by a digital filter
to provide an N-bit word.

ANALOG INPUT

The differential analog input of the AD7401A is implemented
with a switched capacitor circuit. This circuit implements a
second-order modulator stage that digitizes the input signal
into a 1-bit output stream. The sample clock (MCLKIN)
provides the clock signal for the conversion process as well as
the output data-framing clock. This clock source is external
on the AD7401A. The analog input signal is continuously
sampled by the modulator and compared to an internal
voltage reference. A digital stream that accurately represents
the analog input over time appears at the output of the
converter (see Figure 21).

MODULATOR OUTPUT

+FS ANALOG INPUT

A differential input of 320 mV results in a stream of, ideally, all
1s. This is the absolute full-scale range of the AD7401A, and
200 mV is the specified full-scale range, as shown in Tab le 9 .

Table 9. Analog Input Range

Analog Input Voltage Input

Full-Scale Range +640 mV
Positive Full Scale +320 mV
Positive Typical Input Range +250 mV
Positive Specified Input Range +200 mV
Zero 0 mV
Negative Specified Input Range −200 mV
Negative Typical Input Range −250 mV
Negative Full Scale −320 mV

To reconstruct the original information, this output needs to be
digitally filtered and decimated. A sinc3 filter is recommended
because this is one order higher than that of the AD7401A modu­lator. If a 256 decimation rate is used, the resulting 16-bit word
rate is 62.5 kHz, assuming a 16 MHz external clock frequency.
Figure 22 shows the transfer function of the AD7401A relative
to the 16-bit output.

65535

–FS ANALOG INPUT

ANALOG INPUT

Figure 21. Analog Input vs. Modulator Output

A differential signal of 0 V results (ideally) in a stream of alter­nating 1s and 0s at the MDAT output pin. This output is high
50% of the time and low 50% of the time. A differential input of
200 mV produces a stream of 1s and 0s that are high 81.25% of
the time (for a +250 mV input, the output stream is high 89.06% of
the time). A differential input of −200 mV produces a stream of
1s and 0s that are high 18.75% of the time (for a −250 mV
input, the output stream is high 10.94% of the time).

ISO

TED

5V

AD7401A

V

DD1

Σ-Δ

IN

–

1

MOD/

ENCODER

DECODER

DECODER

ENCODER

INPUT

CURRENT

R

SHUNT

+

VIN+

V

GND

53248

07332-021

ADC CODE

SPECIFIE D RANGE

12288

0

–320mV –200mV +200mV +320mV

ANALOG INPUT

07332-022

Figure 22. Filtered and Decimated 16-Bit Transfer Characteristic

NONISOL

V

DD2

MDAT MDAT

MCLKIN

GND

2

5V/3V

TED

V

DD

SINC3 FILTER*

MCLK

GND

CS

SCLK

SDAT

*THIS FILTER IS IMPLEMENTED
WITHAN FPGA OR DSP.

07332-023

Figure 23. Typical Application Circuit

Rev. 0 | Page 14 of 20

AD7401A

V

V

DIFFERENTIAL INPUTS

The analog input to the modulator is a switched capacitor
design. The analog signal is converted into charge by highly
linear sampling capacitors. A simplified equivalent circuit
diagram of the analog input is shown in Figure 24. A signal
source driving the analog input must be able to provide the
charge onto the sampling capacitors every half MCLKIN cycle
and settle to the required accuracy within the next half cycle.

φA

1kΩ

1kΩ

MCLKIN

R

R

φB

φA

φB

φB φB

φA φA

C

AD7401A

2pF

2pF

7332-024

07332-025

+

IN

–

IN

Figure 24. Analog Input Equivalent Circuit

Because the AD7401A samples the differential voltage across
its analog inputs, low noise performance is attained with an
input circuit that provides low common-mode noise at each
input. The amplifiers used to drive the analog inputs play a
critical role in attaining the high performance available from the
AD7401A.

When a capacitive load is switched onto the output of an op
amp, the amplitude momentarily drops. The op amp tries to
correct the situation and, in the process, hits its slew rate limit.
This nonlinear response, which can cause excessive ringing,
can lead to distortion. To remedy the situation, a low-pass RC
filter can be connected between the amplifier and the input
to the AD7401A. The external capacitor at each input aids
in supplying the current spikes created during the sampling
process, and the resistor isolates the op amp from the transient
nature of the load.

The recommended circuit configuration for driving the
differential inputs to achieve best performance is shown in
Figure 25. A capacitor between the two input pins sources or
sinks charge to allow most of the charge that is needed by one
input to be effectively supplied by the other input. The series
resistor again isolates any op amp from the current spikes
created during the sampling process. Recommended values for
the resistors and capacitor are 22 Ω and 47 pF, respectively.

+

V

IN

–

V

IN

Figure 25. Differential Input RC Network

CURRENT SENSING APPLICATIONS

The AD7401A is ideally suited for current sensing applications
where the voltage across a shunt resistor is monitored. The load
current flowing through an external shunt resistor produces a
voltage at the input terminals of the AD7401A. The AD7401A
provides isolation between the analog input from the current
sensing resistor and the digital outputs. By selecting the appro­priate shunt resistor value, a variety of current ranges can be
monitored.

Choosing R

SHUNT

The shunt resistor values used in conjunction with the AD7401A
are determined by the specific application requirements in
terms of voltage, current, and power. Small resistors minimize
power dissipation, while low inductance resistors prevent any
induced voltage spikes, and good tolerance devices reduce
current variations. The final values chosen are a compromise
between low power dissipation and good accuracy. Low value
resistors have less power dissipated in them, but higher value
resistors may be required to utilize the full input range of the
ADC, thus achieving maximum SNR performance.

When the peak sense current is known, the voltage range of the
AD7401A (±200 mV) is divided by the maximum sense current
to yield a suitable shunt value. If the power dissipation in the
shunt resistor is too large, the shunt resistor can be reduced
and less of the ADC input range is used. Using less of the ADC
input range results in performance that is more susceptible to
noise and offset errors because offset errors are fixed and are
thus more significant when smaller input ranges are used.

R

must be able to dissipate the I2R power losses. If the

SHUNT

power dissipation rating of the resistor is exceeded, its value
may drift or the resistor may be damaged, resulting in an open
circuit. This can result in a differential voltage across the ter­minals of the AD401A in excess of the absolute maximum
ratings. If I

has a large high frequency component, take

SENSE

care to choose a resistor with low inductance.

VOLTAGE SENSING APPLICATIONS

The AD7401A can also be used for isolated voltage monitoring.
For example, in motor control applications, it can be used to
sense bus voltage. In applications where the voltage being moni­tored exceeds the specified analog input range of the AD7401A,
a voltage divider network can be used to reduce the voltage to
be monitored to the required range.

Rev. 0 | Page 15 of 20

AD7401A

(

)

DIGITAL FILTER

The overall system resolution and throughput rate is determined
by the filter selected and the decimation rate used. The higher
the decimation rate, the greater the system accuracy, as illus­trated in Figure 26. However, there is a tradeoff between accuracy
and throughput rate and, therefore, higher decimation rates
result in lower throughput solutions. Note that for a given
bandwidth requirement, a higher MCLKIN frequency can allow
for higher decimation rates to be used, resulting in higher SNR
performance.

90

80

70

60

50

40

SNR (dB)

30

20

10

0

Figure 26. SNR vs. Decimation Rate for Different Filter Types

10 100 1k1

DECIMATI ON RATE

A sinc3 filter is recommended for use with the AD7401A. This
filter can be implemented on an FPGA or a DSP.

3

DR

⎛

1

⎜

)(

zH

=

⎜

()

1

⎝

⎞

Z

−
⎟

−

1

⎟

Z

−

⎠

where DR is the decimation rate.

The following Verilog code provides an example of a sinc3 filter
implementation on a Xilinx® Spartan-II 2.5 V FPGA. This code
can possibly be compiled for another FPGA, such as an Altera®
device. Note that the data is read on the negative clock edge in
this case, although it can be read on the positive edge, if
preferred.

SINC3

SINC2

SINC1

07332-026

/*`Data is read on negative clk edge*/
module DEC256SINC24B(mdata1, mclk1, reset,
DATA);

input mclk1; /*used to clk filter*/
input reset; /*used to reset filter*/
input mdata1; /*ip data to be
filtered*/

output [15:0] DATA; /*filtered op*/
integer location;

integer info_file;
reg [23:0] ip_data1;
reg [23:0] acc1;
reg [23:0] acc2;
reg [23:0] acc3;
reg [23:0] acc3_d1;
reg [23:0] acc3_d2;
reg [23:0] diff1;
reg [23:0] diff2;
reg [23:0] diff3;
reg [23:0] diff1_d;
reg [23:0] diff2_d;
reg [15:0] DATA;
reg [7:0] word_count;
reg word_clk;

reg init;

/*Perform the Sinc ACTION*/
always @ (mdata1)

if(mdata1==0)
ip_data1 <= 0; /* change from a 0
to a -1 for 2's comp */
else
ip_data1 <= 1;

/*ACCUMULATOR (INTEGRATOR)
Perform the accumulation (IIR) at the speed
of the modulator.

MCLKIN

IP_DATA1

ACC1+ ACC2+

Z

+

Figure 27. Accumulator

Z

+

+

ACC3+

Z

07332-027

Rev. 0 | Page 16 of 20

AD7401A

W

Z = one sample delay
MCLKOUT = modulators conversion bit rate
*/

always @ (posedge mclk1 or posedge reset)
if (reset)
begin
/*initialize acc registers on reset*/
acc1 <= 0;
acc2 <= 0;
acc3 <= 0;
end
else
begin
/*perform accumulation process*/
acc1 <= acc1 + ip_data1;
acc2 <= acc2 + acc1;
acc3 <= acc3 + acc2;
end

/*DECIMATION STAGE (MCLKOUT/ WORD_CLK)
*/

always @ (negedge mclk1 or posedge reset)
if (reset)
word_count <= 0;
else
word_count <= word_count + 1;

word_clk <= word_count[7];
/*DIFFERENTIATOR ( including decimation

stage)
Perform the differentiation stage (FIR) at a
lower speed.

ACC3

ORD_CLK

DIFF1

+

–

–1

Z

Figure 28. Differentiator

DIFF2

+

–

–

–1

Z

DIFF3

+

–

–1

Z

Z = one sample delay
WORD_CLK = output word rate
*/

always @ (posedge word_clk or posedge reset)
if(reset)
begin
acc3_d2 <= 0;
diff1_d <= 0;
diff2_d <= 0;
diff1 <= 0;
diff2 <= 0;
diff3 <= 0;
end

else
begin
diff1 <= acc3 - acc3_d2;
diff2 <= diff1 - diff1_d;
diff3 <= diff2 - diff2_d;
acc3_d2 <= acc3;
diff1_d <= diff1;
diff2_d <= diff2;
end

/* Clock the Sinc output into an output
register always @ (word_count)

WORD_CLK

DATADIFF3

07332-029

Figure 29. Clocking Sinc Output into an Output Register

WORD_CLK = output word rate
*/

always @ (posedge word_clk)

07332-028

begin
DATA[15] <= diff3[23];

DATA[14] <= diff3[22];
DATA[13] <= diff3[21];
DATA[12] <= diff3[20];
DATA[11] <= diff3[19];
DATA[10] <= diff3[18];
DATA[9] <= diff3[17];
DATA[8] <= diff3[16];
DATA[7] <= diff3[15];
DATA[6] <= diff3[14];
DATA[5] <= diff3[13];
DATA[4] <= diff3[12];
DATA[3] <= diff3[11];
DATA[2] <= diff3[10];
DATA[1] <= diff3[9];
DATA[0] <= diff3[8];

end

endmodule

Rev. 0 | Page 17 of 20

AD7401A

APPLICATIONS INFORMATION

GROUNDING AND LAYOUT

Supply decoupling with a value of 100 nF is recommended on
both V

DD1

and V

. In applications involving high common-

DD2

mode transients, care should be taken to ensure that board
coupling across the isolation barrier is minimized. Further­more, the board layout should be designed so that any coupling
that occurs equally affects all pins on a given component side.
Failure to ensure this may cause voltage differentials between
pins to exceed the absolute maximum ratings of the device,
thereby leading to latch-up or permanent damage. Any decoupling
used should be placed as close to the supply pins as possible.

Series resistance in the analog inputs should be minimized to
avoid any distortion effects, especially at high temperatures. If
possible, equalize the source impedance on each analog input to
minimize offset. Beware of mismatch and thermocouple effects
on the analog input PCB tracks to reduce offset drift.

EVALUATING THE AD7401A PERFORMANCE

An AD7401A evaluation board is available with split ground
planes and a board split beneath the AD7401A package to
ensure isolation. This board allows access to each pin on the
device for evaluation purposes.

The evaluation board package includes a fully assembled and
tested evaluation board, documentation, and software for
controlling the board from the PC via the EVAL-CED1Z. The
software also includes a sinc3 filter implemented on an FPGA.
The evaluation board is used in conjunction with the EVAL­CED1Z board and can also be used as a standalone board. The
software allows the user to perform ac (fast Fourier transform)
and dc (histogram of codes) tests on the AD7401A. The soft­ware and documentation are on a CD that is shipped with the
evaluation board.

These tests subjected devices to continuous cross-isolation
voltages. To accelerate the occurrence of failures, the selected
test voltages were values exceeding those of normal use. The
time-to-failure values of these units were recorded and used
to calculate acceleration factors. These factors were then used
to calculate the time-to-failure under normal operating
conditions. The values shown in Tab le 7 are the lesser of the
following two values:

• The value that ensures at least a 50-year lifetime of

continuous use.

• The maximum CSA/VDE approved working voltage.

It should also be noted that the lifetime of the AD7401A varies
according to the waveform type imposed across the isolation
barrier. The iCoupler insulation structure is stressed differently
depending on whether the waveform is bipolar ac, unipolar ac,
or dc. Figure 30, Figure 31, and Figure 32 illustrate the different
isolation voltage waveforms.

RATED PEAK VOLTAGE

0V

Figure 30. Bipolar AC Waveform

7332-030

RATED PEAK VOLTAGE

0V

Figure 31. Unipolar AC Waveform

07332-031

RATED PEAK VOLTAGE

INSULATION LIFETIME

All insulation structures, subjected to sufficient time and/or
voltage, are vulnerable to breakdown. In addition to the testing
performed by the regulatory agencies, Analog Devices has
carried out an extensive set of evaluations to determine the
lifetime of the insulation structure within the AD7401A.

Rev. 0 | Page 18 of 20

0V

Figure 32. DC Waveform

07332-032

AD7401A

C

OUTLINE DIMENSIONS

10.50 (0.4134)

10.10 (0.3976)

9

7.60 (0.2992)

7.40 (0.2913)

8

10.65 (0.4193)

10.00 (0.3937)

2.65 (0.1043)

2.35 (0.0925)

SEATING
PLANE

8°
0°

0.33 (0.0130)

0.20 (0.0079)

0
0

.

7

.

2

5

(

0

5

(

0

.

0

2

9

5

)

0

0

9

8

)

.

1.27 (0.0500)

0.40 (0.0157)

45°

032707-B

0.30 (0.0 118)

0.10 (0.0039)

OPLANARITY

0.10

16

1

1.27 (0.0500)
BSC

0.51 (0.0201)

0.31 (0.0122)

CONTROLL ING DIMENS IONS ARE IN MILLIM ETERS; INCH DI MENSIONS
(IN PARENTHESES) ARE ROUNDED-O FF MIL LIMETE R EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRI ATE FOR USE IN DESIGN.

COMPLIANT TO JEDEC STANDARDS MS-013- AA

Figure 33. 16-Lead Standard Small Outline Package [SOIC_W]

Wide Body

(RW-16)

Dimensions shown in millimeters and (inches)

ORDERING GUIDE

Model Temperature Range Package Description Package Option

AD7401AYRWZ
AD7401AYRWZ-RL
EVAL-AD7401AEDZ
EVAL-CED1Z

1

Z = RoHS Compliant Part.

1

−40°C to +125°C 16-Lead Standard Small Outline Package (SOIC_W) RW-16

1

−40°C to +125°C 16-Lead Standard Small Outline Package (SOIC_W) RW-16

1

Evaluation Board

1

Development Board

Rev. 0 | Page 19 of 20

AD7401A

NOTES

©2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07332-0-7/08(0)

Rev. 0 | Page 20 of 20