Datasheet AD7401 Datasheet (ANALOG DEVICES)

V

V

Isolated Sigma-Delta Modulator

FEATURES

20 MHz maximum external clock rate
Second-order modulator
16 bits no missing codes
±2 LSB INL typical at 16 bits

3.5 μV/°C maximum offset drift
On-board digital isolator
On-board reference
Low power operation: 20 mA maximum at 5.25 V

−40°C to +105°C operating range
16-lead SOIC package
Safety and regulatory approvals

UL recognition

5000 V rms for 1 minute per UL 1577
CSA Component Acceptance Notice #5A
VDE Certificate of Conformity

DIN V VDE V 0884-10 (VDE V 0884-10):2006-12

V

= 891 V peak

IORM

APPLICATIONS

AC motor controls
Data acquisition systems
A/D + opto-isolator replacements

FUNCTIONAL BLOCK DIAGRAM

DD1

AD7401

GENERAL DESCRIPTION

The AD74011 is a second-order, sigma-delta (Σ-Δ) modulator
that converts an analog input signal into a high speed, 1-bit data
stream with on-chip digital isolation based on Analog Devices,
Inc. iCoupler® technology. The AD7401 operates from a 5 V
power supply and accepts a differential input signal of ±200 mV
(±320 mV full scale). The analog input is continuously sampled
by the analog modulator, eliminating the need for external
sample-and-hold circuitry. The input information is contained
in the output stream as a density of ones with a data rate up to
20 MHz. The original information can be reconstructed with an
appropriate digital filter. The serial I/O can use a 5 V or a 3 V
supply (V

The serial interface is digitally isolated. High speed CMOS,
combined with monolithic air core transformer technology,
means the on-chip isolation provides outstanding performance
characteristics, superior to alternatives such as optocoupler
devices. The part contains an on-chip reference. The AD7401
is offered in a 16-lead SOIC and has an operating temperature
range of −40°C to +105°C.

An internal clock version, AD7400, is also available.

1

Protected by U.S. Patents 5,952,849; 6,873,065; and 7,075,329.

DD2

).

DD2

VIN+

VIN–

REF

H

/

T

U

B

F

Σ-∆ ADC

CONTROL LOGIC

GND

1

Rev. D

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

UPDATE

ENCODE DECODE

WATCHDOG

DECODE

Figure 1.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2006–2011 Analog Devices, Inc. All rights reserved.

WATCHDOG

ENCODE

AD7401

UPDATE

GND

MDAT

MCLKIN

2

05851-001

AD7401

TABLE OF CONTENTS

Features.............................................................................................. 1

Applications....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Timing Specifications .................................................................. 4

Insulation and Safety-Related Specifications............................ 5

Regulatory Information............................................................... 5

DIN V VDE V 0884-10 (VDE V 0884-10) Insulation

Characteristics .............................................................................. 6

Absolute Maximum Ratings............................................................ 7

ESD Caution.................................................................................. 7

Pin Configuration and Function Descriptions............................. 8

REVISION HISTORY

7/11—Rev. C to Rev. D

Changes to Minimum External Air Gap (Clearance) Parameter,
Table 3 and Minimum External Tracking (Creepage) Parameter,

Table 3 ................................................................................................ 5

Changes to Figure 5; Pin 1 Description, Table 8; and Pin 7

Description, Table 8.......................................................................... 8

1/11—Rev. B to Rev. C

Changes to Features Section............................................................ 1

Changes to Input-to-Output Momentary Withstand Voltage

Parameter, Table 3, UL Column, Table 4, and Note 1, Table 4 .......... 5

Changes to Ordering Guide...................................................................18

Typical Performance Characteristics..............................................9

Terminology.................................................................................... 12

Theory of Operation ...................................................................... 13

Circuit Information.................................................................... 13

Analog Input............................................................................... 13

Differential Inputs...................................................................... 14

Digital Filter ................................................................................ 15

Applications Information.............................................................. 17

Grounding and Layout.............................................................. 17

Evaluating the AD7401 Performance...................................... 17



Insulation Lifetime..................................................................... 17

Outline Dimensions....................................................................... 18

Ordering Guide .......................................................................... 18

9/07—Rev. A to Rev. B

Updated VDE Certification Throughout ......................................1

Changes to Table 6.............................................................................7

12/06—Rev. 0 to Rev. A

Changes to Features and General Description ..............................1

Changes to Table 1.............................................................................3

Changes to Table 2.............................................................................4

Changes to Table 6.............................................................................7

Changes to Table 8.............................................................................8

Changes to Circuit Information Section ..................................... 13

Changes to Figure 27...................................................................... 15

1/06—Revision 0: Initial Version

Rev. D | Page 2 of 20

AD7401

SPECIFICATIONS

V

= 4.5 V to 5.25 V, V

DD1

f

= 16 MHz maximum, tested with Sinc3 filter, 256 decimation rate, as defined by Verilog code, unless otherwise noted.

MCLK

= 3 V to 5.5 V, VIN+ = −200 mV to +200 mV, and VIN− = 0 V (single-ended); TA = T

DD2

MIN

to T

MAX

,

Table 1.

Parameter Y Version

STATIC PERFORMANCE

Resolution
Integral Nonlinearity

3

16 Bits min Filter output truncated to 16 bits
±15 LSB max −40°C to +85°C; ±2 LSB typical; f

1, 2

Unit Test Conditions/Comments

= 20 MHz maximum4

MCLK

±25 LSB max >85°C to 105°C

±55 LSB max f

Differential Nonlinearity

Offset Error

3

3

±0.9 LSB max

±0.6 mV max f

= 20 MHz maximum4; VIN+ = −250 mV to +250 mV

MCLK

Guaranteed no missed codes to 16 bits;
f

= 20 MHz maximum4; VIN+ = −250 mV to +250 mV

MCLK

= 20 MHz maximum4; VIN+ = −250 mV to +250 mV

MCLK

±50 μV typ TA = 25°C
Offset Drift vs. Temperature

3.5 μV/°C max −40°C to +105°C
1 μV/°C typ
Offset Drift vs. V

DD1

120 μV/V typ
Gain Error3 ±1.6 mV max −40°C to +85°C
±2 mV max >85°C to 105°C
±1 mV typ f

= 20 MHz maximum4; VIN+ = −250 mV to +250 mV

MCLK

Gain Error Drift vs. Temperature 23 μV/°C typ −40°C to +105°C
Gain Error Drift vs. V

110 μV/V typ

DD1

ANALOG INPUT

Input Voltage Range

±200 mV min/mV max For specified performance; full range ±320 mV
Dynamic Input Current ±9 μA max VIN+ = 400 mV, VIN− = 0 V
DC Leakage Current ±0.5 μA max
Input Capacitance 10 pF typ

DYNAMIC SPECIFICATIONS VIN+ = 5 kHz, 400 mV p-p sine

Signal-to-(Noise + Distortion) Ratio (SINAD)3 70 dB min −40°C to +85°C; f
68 dB min −40°C to +85°C; f

= 9 MHz to 20 MHz4

MCLK

= 5 MHz to <9 MHz

MCLK

65 dB min >85°C to 105°C
65 dB min f

= 20 MHz maximum4; VIN+ = −250 mV to +250 mV

MCLK

81 dB typ
Signal-to-Noise Ratio (SNR) 80 dB min −40°C to +105°C; 82 dB typ

80 dB min f

Total Harmonic Distortion (THD)3 −92 dB typ f

= 20 MHz maximum4; VIN+ = −250 mV to +250 mV

MCLK

= 20 MHz maximum4; VIN+ = −250 mV to +250 mV

MCLK

Peak Harmonic or Spurious Noise (SFDR)3 −92 dB typ
Effective Number of Bits (ENOB)3 11.5 Bits
Isolation Transient Immunity3 25 kV/μs min

LOGIC INPUTS

Input High Voltage, VIH 0.8 × V
Input Low Voltage, VIL 0.2 × V

30 kV/μs typ

V min

DD2

V max

DD2

Input Current, IIN ±0.5 μA max
Input Capacitance, C

5

10 pF max

IN

Rev. D | Page 3 of 20

AD7401

T

Parameter Y Version

1, 2

Unit Test Conditions/Comments

LOGIC OUTPUTS

Output High Voltage, VOH V

− 0.1 V min IO = −200 μA

DD2

Output Low Voltage, VOL 0.4 V max IO = +200 μA

POWER REQUIREMENTS

V

4.5/5.25 V min/V max

DD1

V

3/5.5 V min/V max

DD2

6

I

12 mA max V

DD1

7

I

DD2

8 mA max V

4 mA max V

1

Temperature range is −40°C to +85°C.

2

All voltages are relative to their respective ground.

3

See the section. Terminology

4

For f

> 16 MHz to 20 MHz, mark space ratio is 48/52 to 52/48, V

MCLK

5

Sample tested during initial release to ensure compliance.

6

See . Figure 15

7

See . Figure 17

= V

= 5 V ± 5%, and TA = −40°C to +85°C.

DD1

DD2

= 5.25 V

DD1

= 5.5 V

DD2

= 3.3 V

DD2

TIMING SPECIFICATIONS

V

= 4.5 V to 5.25 V, V

DD1

Table 2.

Parameter Limit at T

2, 3

f

20 MHz max Master clock input frequency

MCLKIN

5 MHz min Master clock input frequency

4

t

1

4

t

2

t3 0.4 × t
t

4

1

Sample tested during initial release to ensure compliance

2

Mark space ratio for clock input is 40/60 to 60/40 for f

3

V

= V

= 5 V ± 5% for f

DD1

DD2

4

Measured with the load circuit of and defined as the time required for the output to cross 0.8 V or 2.0 V. Figure 2

= 3 V to 5.5 V, TA = T

DD2

, T

MIN

MAX

to T

MAX

, unless otherwise noted.1

MIN

Unit Description

25 ns max Data access time after MCLK rising edge
15 ns min Data hold time after MCLK rising edge

ns min Master clock low time

MCLKIN

0.4 × t

ns min Master clock high time

MCLKIN

> 16 MHz to 20 MHz.

MCLKIN

to 16 MHz and 48/52 to 52/48 for f

MCLKIN

> 16 MHz to 20 MHz.

MCLKIN

O OUTPUT

PIN

25pF

C

200µA I

L

200µA I

OL

1.6V

OH

05851-002

Figure 2. Load Circuit for Digital Output Timing Specifications

t

4

MCLKIN

MDAT

t

1

Figure 3. Data Timing

Rev. D | Page 4 of 20

t

2

t

3

05851-003

AD7401

INSULATION AND SAFETY-RELATED SPECIFICATIONS

Table 3.

Parameter Symbol Value Unit Conditions

Input-to-Output Momentary Withstand Voltage V
Minimum External Air Gap (Clearance) L(I01) 8.1 min mm

Minimum External Tracking (Creepage) L(I02) 7.46 min mm

Minimum Internal Gap (Internal Clearance) 0.017 min mm Insulation distance through insulation
Tracking Resistance (Comparative Tracking Index) CTI >175 V DIN IEC 112/VDE 0303 Part 1
Isolation Group IIIa Material Group (DIN VDE 0110, 1/89, Table I)

REGULATORY INFORMATION

Table 4.

UL1 CSA VDE2

Recognized under 1577
Component Recognition Program

5000 V rms Isolation Voltage

File E214100 File 205078 File 2471900-4880-0001

1

In accordance with UL 1577, each AD7401 is proof tested by applying an insulation test voltage ≥ 6000 V rms for 1 second (current leakage detection limit = 15 μA).

2

In accordance with DIN V VDE V 0884-10, each AD7401 is proof tested by applying an insulation test voltage ≥ 1671 V peak for 1 second (partial discharge detection

limit = 5 pC).

Approved under CSA Component

1

Acceptance Notice #5A
Reinforced insulation per CSA

60950-1-03 and IEC 60950-1, 630 V
rms maximum working voltage

5000 min V rms 1-minute duration

ISO

Measured from input terminals to output
terminals, shortest distance through air

Measured from input terminals to output
terminals, shortest distance path along body

Certified according to DIN V VDE V 0884-10 (VDE V 0884-

10):2006-122
Reinforced insulation per DIN V VDE V 0884-10 (VDE V 0884-

10):2006-12, 891V peak

Rev. D | Page 5 of 20

AD7401

DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS

This isolator is suitable for reinforced electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by
means of protective circuits.

Table 5.

Description Symbol Characteristic Unit

INSTALLATION CLASSIFICATION PER DIN VDE 0110

For Rated Mains Voltage ≤ 300 V rms I–IV
For Rated Mains Voltage ≤ 450 V rms I–II

For Rated Mains Voltage ≤ 600 V rms I–II
CLIMATIC CLASSIFICATION 40/105/21
POLLUTION DEGREE (DIN VDE 0110, TABLE I) 2
MAXIMUM WORKING INSULATION VOLTAGE V
INPUT-TO-OUTPUT TEST VOLTAGE, METHOD B1

V

× 1.875 = VPR, 100% Production Test, tm = 1 sec, Partial Discharge < 5 pC VPR 1671 V peak

IORM

INPUT-TO-OUTPUT TEST VOLTAGE, METHOD A VPR

After Environmental Test Subgroup 1 1426 V peak

V

× 1.6 = VPR, tm = 60 sec, Partial Discharge < 5 pC

IORM

After Input and/or Safety Test Subgroup 2/3 1069 V peak

V

× 1.2 = VPR, tm = 60 sec, Partial Discharge < 5 pC

IORM

HIGHEST ALLOWABLE OVERVOLTAGE (TRANSIENT OVERVOLTAGE, tTR = 10 sec) VTR 6000 V peak
SAFETY-LIMITING VALUES (MAXIMUM VALUE ALLOWED IN THE EVENT OF A FAILURE, ALSO SEE Figure 4)

Case Temperature TS 150 °C

Side 1 Current IS1 265 mA

Side 2 Current IS2 335 mA
INSULATION RESISTANCE AT TS, VIO = 500 V RS >109 Ω

350

891 V peak

IORM

300

250

200

150

100

SAFETY-LIMI TING CURRENT (mA)

50

0

0

Figure 4. Thermal Derating Curve, Dependence of Safety-Limiting Values

with Case Temperature per DIN V VDE V 0884-10

SIDE #2

SIDE #1

50 100 150 200

CASE TEMPE RATURE (°C)

5851-004

Rev. D | Page 6 of 20

AD7401

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted. All voltages are relative to
their respective ground.

Table 6.

Parameter Rating

V

to GND

DD1

V

DD2

to GND

1

2

Analog Input Voltage to GND
Digital Input Voltage to GND
Output Voltage to GND

2

1

2

−0.3 V to +6.5 V

−0.3 V to +6.5 V

−0.3 V to V

−0.3 V to V

−0.3 V to V

+ 0.3 V

DD1

+ 0.5 V

DD1

+ 0.3 V

DD2

Input Current to Any Pin Except Supplies1 ±10 mA
Operating Temperature Range −40°C to +105°C
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
SOIC Package

θJA Thermal Impedance 89.2°C/W

θJC Thermal Impedance 55.6°C/W
Resistance (Input to Output), R
Capacitance (Input to Output), C

10

I-O

2

1.7 pF typ

I-O

12

Ω

Pb-Free Temperature , Soldering

Reflow 260 (+0)°C
ESD 1.5 kV

1

Transient currents of up to 100 mA do not cause SCR to latch-up.

2

f = 1 MHz.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

Table 7. Maximum Continuous Working Voltage

1

Parameter Max Unit Constraint

AC Voltage,

565 V

50-year minimum lifetime

PK

Bipolar Waveform
AC Voltage,

891 V

Unipolar Waveform
DC Voltage 891 V

Maximum CSA/VDE

PK

approved working voltage
Maximum CSA/VDE

approved working voltage

1

Refers to continuous voltage magnitude imposed across the isolation

barrier. See the Insulation Lifetime section for more details.

ESD CAUTION

Rev. D | Page 7 of 20

AD7401

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

V

DD1

VIN+

2

VIN–

3

AD7401

4

NC

NC

NC

V

/NC

DD1

GND

TOP VIEW

(Not to Scale)

5

6

7

8

1

NC = NO CONNECT

16

15

14

13

12

11

10

9

GND

2

NC

V

DD2

MCLKIN

NC

MDAT

NC

GND

2

05851-005

Figure 5. Pin Configuration

Table 8. Pin Function Descriptions

Pin No. Mnemonic Description

1 V

Supply Voltage. 4.5 V to 5.25 V. This is the supply voltage for the isolated side of the AD7401 and is relative to GND1.

DD1

2 VIN+ Positive Analog Input. Specified range of ±200 mV.
3 VIN−
4 to 6, 10,

NC No Connect.

Negative Analog Input. Normally connected to GND1.

12, 15
7 V

/NC Supply Voltage. 4.5 V to 5.25 V. This is the supply voltage for the isolated side of the AD7401 and is relative to GND1.

DD1

No Connect (NC). If desired, Pin 7 may be allowed to float. It should not be tied to ground. The AD7401 will

operate normally provided that the supply voltage is applied to Pin 1.
8 GND
9, 16 GND

1

2

11 MDAT

Ground 1. This is the ground reference point for all circuitry on the isolated side.

Ground 2. This is the ground reference point for all circuitry on the nonisolated side.

Serial Data Output. The single bit modulator output is supplied to this pin as a serial data stream. The bits are

clocked out on the rising edge of the MCLKIN input and valid on the following MCLKIN rising edge.
13 MCLKIN Master Clock Logic Input. 20 MHz maximum. The bit stream from the modulator is valid on the rising edge of MCLKIN.
14 V

Supply Voltage. 3 V to 5.5 V. This is the supply voltage for the nonisolated side and is relative to GND2.

DD2

Rev. D | Page 8 of 20

AD7401

–

–

TYPICAL PERFORMANCE CHARACTERISTICS

TA = 25°C, using a 25 kHz brick wall filter, unless otherwise noted.

100

90

80

70

60

50

PSRR (dB)

40

30

20

200mV p-p SINE WAVE ON V
NO DECOUPL ING

10

V

DD1=VDD2

1MHz CUTOF F FILTER

0

0 1000

MCLKIN = 5MHz

=5V

100 200 300 400 500 600 700 800 900

SUPPLY RI PPLE F REQUENCY (kHz)

MCLKIN = 16MHz

MCLKIN = 10MHz

DD1

Figure 6. PSRR vs. Supply Ripple Frequency Without Supply Decoupling

90

–85

–80

–75

MCLKIN = 10MHz

–70

SINAD (dB)

–65

–60

–55

–50

0 10k

1k 2k 3k 4k 5k 6k 7k 8k 9k

INPUT FREQUENCY (Hz)

MCLKIN = 16MHz

MCLKIN = 5MHz

V

DD1=VDD2

V

DD1=VDD2

=5V

=5V

05851-006

05851-027

90

–85

–80

–75

–70

SINAD (dB)

–65

–60

–55

–50

0.17 0.33

0.18 0.19 0.20 0.21 0.22 0.23 0. 24 0.25 0.26 0.27 0.28 0.29 0.30 0.31 0.32

± INPUT AMPLITUDE (V)

MCLKIN = 10MHz

MCLKIN = 16MHz

Figure 9. SINAD vs. V

IN

V

DD1=VDD2

0.4

0.3

0.2

0.1

0

–0.1

–0.2

DNL ERRO R (LSB)

–0.3

–0.4

VIN+ = –200mV TO +200mV

– = 0V

V

IN

–0.5

0 60k

10k 20k 30k 40k 5 0k

CODE

=5V

05851-028

05851-043

Figure 7. SINAD vs. Analog Input Frequency

20

0

–20

–40

–60

–80

(dB)

–100

–120

–140

–160

–180

03

5 10152025

FREQUENCY (kHz)

4096 POINT FFT

f

= 5kHz

IN

SINAD = 81.984dB
THD = –96.311dB
DECIMATIO N BY 256

0

05851-042

0.8

0.6

0.4

0.2

INL ERROR (L SB)

–0.2

–0.4

Figure 8. Typical FFT (±200 mV Range)

Figure 10. Typical DNL (±200 mV Range)

VIN+ = –200mV TO +200mV

–=0V

V

IN

0

0 60k

10k 20k 30k 40k 50k

CODE

Figure 11. Typical INL (±200 mV Range)

05851-044

Rev. D | Page 9 of 20

AD7401

250

200

150

100

V

DD1=VDD2

MCLKIN = 16MHz

=4.5V

V

DD1=VDD2

MCLKIN = 5MHz

=4.5V

V

DD1=VDD2

MCLKIN = 16MHz

=5V

V

DD1=VDD2

MCLKIN = 10MHz

=4.5V

V

DD1=VDD2

MCLKIN = 5MHz

=5V

50

0

–50

OFFSET (µV)

–100

–150

–200

–250

V

DD1=VDD2

MCLKIN = 16MHz

–45

–35 –25 –15 –5 5 15 25 35 45 55 65 75 85 95 105

= 5.25V

V

DD1=VDD2

MCLKIN = 10MHz

=5V

V

DD1=VDD2

MCLKIN = 10MHz

= 5.25V

V

DD1=VDD2

MCLKIN = 5MHz

=5.25V

TEMPERATURE (°C)

Figure 12. Offset Drift vs. Temperature for Various Supply Voltages

200.5

GAIN (mV)

200.4

200.3

200.2

200.1

200.0

199.9

V

DD1=VDD2

MCLKIN = 16MHz

V

DD1=VDD2

MCLKIN = 5MHz

V

DD1=VDD2

MCLKIN = 16MHz

V

DD1=VDD2

MCLKIN = 16MHz

V

DD1=VDD2

MCLKIN = 10MHz

=4.5V

=4.5V

=5V

= 5.25V

=5V

V

DD1=VDD2

MCLKIN = 10MHz

V

DD1=VDD2

MCLKIN = 5MHz

V

DD1=VDD2

MCLKIN = 10MHz

V

DD1=VDD2

MCLKIN = 5MHz

=4.5V

=5V

= 5.25V

= 5.25V

199.8

199.7

199.6

199.5
–45

–35 –25 –15 –5 5 15 25 35 45 55 65 75 85 95 105

TEMPERATURE (°C)

Figure 13. Gain Error Drift vs. Temperature for Various Supply Voltages

0.0105

0.0100

MCLKIN = 16MHz

0.0095

0.0090

(A)

0.0085

DD1

I

MCLKIN = 10MHz

0.0080

0.0075
MCLKIN = 5MHz

0.0070

0.0065

–0.33 0.33–0.28 –0.23 –0.18 –0.13 –0.08 –0.03 0.03 0.08 0.13 0.18 0.23 0.28

VINDC INPUT VOLTAGE (V)

Figure 14. I

vs. VIN DC Input Voltage

DD1

V

DD1=VDD2

T

=25°C

A

=5V

0.0105

0.0100

0.0095

V

DD1=VDD2

=5V

MCLKIN = 16MHz

T

= –40°C

A

MCLKIN = 16MHz

T

= +85°C

A

MCLKIN = 16MHz

T

= +105°C

A

0.0090

MCLKIN = 10MHz

T

0.0085

(A)

DD1

0.0080

I

= –40°C

A

MCLKIN = 10MHz

0.0075

0.0070

0.0065

0.0060

05851-029

MCLKIN = 5MHz

T

= +85°C

A

–0.33 0.33–0.28 –0.23 –0.18 –0.13 –0.08 –0.03 0.03 0.08 0.13 0.18 0.23 0.28

Figure 15. I

MCLKIN = 5MHz

VINDC INPUT VOLTAGE (V)

vs. VIN at Various Temperatures

DD1

T

A

T

A

= +85°C

= –40°C

MCLKIN = 10MHz

T

= +105°C

A

MCLKIN = 5MHz

T

=+105°C

A

05851-034

0.0070

0.0065

MCLKIN = 16MHz

0.0060

0.0055

0.0050

(A)

0.0045

DD2

I

0.0040

0.0035

0.0030

MCLKIN = 10MHz

MCLKIN = 5MHz

0.0025

0.0020

05851-036

–0.225 –0.125 –0.025 0.075 0.175

–0.325

VINDC INPUT VOLTAGE (V)

Figure 16. I

vs. VIN DC Input Voltage

DD2

V

DD1=VDD2

T

=25°C

A

=5V

0.275

0.325–0.275 –0.175 –0.075 0.025 0.125 0.225

05851-037

0.0070
V

DD1=VDD2

0.0065

0.0060

0.0055

0.0050

(A)

0.0045

DD2

I

0.0040

0.0035

0.0030

0.0025

0.0020

–0.325

05851-033

=5V

MCLKIN = 16MHz

T

= +105°C

= –40°C

MCLKIN = 10MHz

T

A

A

= +85°C

MCLKIN = 10MHz

T

= +105°C

A

MCLKIN = 16MHz

T

= –40°C

A

MCLKIN = 10MHz

T

A

MCLKIN = 5MHz

T

= –40°C

A

MCLKIN = 5MHz

T

= +85°C

A

–0.225 –0.125 –0.025 0.075 0.175

VINDC INPUT VOLTAGE (V)

Figure 17. I

vs. VIN at Various Temperatures

DD2

MCLKIN = 16MHz

T

=+85°C

A

MCLKIN = 5MHz

T

= +105°C

A

0.275

0.325–0.275 –0.175 –0.075 0.025 0.125 0.225

05851-038

Rev. D | Page 10 of 20

AD7401

8

V

= V

DD2

–0.30

–0.25

= 4.5V TO 5.25V

MCLKIN = 10MHz

–0.20

–0.15

–0.10

VIN– DC INPUT (V)

Figure 18. I

vs. VIN− DC Input

IN

MCLKIN = 16M Hz

0

0.05

–0.05

MCLKIN = 5MHz

0.10

0.15

0.20

0.25

0.30

0.35

05851-030

DD1

6

4

2

0

(µA)

IN

I

–2

–4

–6

–8

–0.35

0

–20

–40

–60

CMRR (dB)

–80

MCLKIN = 10MHz

MCLKIN = 5MHz

V

DD1=VDD2

V

DD1=VDD2

=5V

=5V

1.0
V

= V

DD1

50kHz BRICK WALL FILT ER

0.8

0.6

0.4

NOISE (mV)

MCLKIN = 5MHz

0.2

0

–0.30

= 5V

DD2

MCLKIN = 10MHz

0

–0.25

–0.20

–0.15

–0.10

–0.05

DC INPUT (V)

V

IN

Figure 20. RMS Noise Voltage vs. V

MCLKIN = 16MHz

0.05

0.10

0.15

DC Input

IN

0.20

0.25

0.30

05851-032

–100

–120

0.1 1000

1 10 100

RIPPLE FREQUENCY (kHz)

MCLKIN = 16MHz

05851-031

Figure 19. CMRR vs. Common-Mode Ripple Frequency

Rev. D | Page 11 of 20

AD7401

TERMINOLOGY

Differential Nonlinearity

Differential nonlinearity is the difference between the measured
and the ideal 1 LSB change between any two adjacent codes in
the ADC.

Integral Nonlinearity

Integral nonlinearity is the maximum deviation from a straight
line passing through the endpoints of the ADC transfer function.
The endpoints of the transfer function are specified negative
full-scale, −200 mV (V
level, and specified positive full-scale, +200 mV (V
Code 53,248 for the 16-bit level.

Offset Error

Offset error is the deviation of the midscale code (Code 32,768
for the 16-bit level) from the ideal V

Gain Error

Gain error includes both positive full-scale gain error and
negative full-scale gain error. Positive full-scale gain error is the
deviation of the specified positive full-scale code (53,248 for the
16-bit level) from the ideal V
offset error is adjusted out. Negative full-scale gain error is the
deviation of the specified negative full-scale code (12,288 for
the 16-bit level) from the ideal V
offset error is adjusted out. Gain error includes reference error.

Signal-to-(Noise + Distortion) Ratio

This ratio is the measured ratio of signal-to-(noise + distortion)
at the output of the ADC. The signal is the rms amplitude of the
fundamental. Noise is the sum of all nonfundamental signals up
to half the sampling frequency (f
dependent on the number of quantization levels in the digitization
process; the more levels, the smaller the quantization noise. The
theoretical signal-to-(noise + distortion) ratio for an ideal N-bit
converter with a sine wave input is given by

Signal-to-(Noise + Distortion) = (6.02 N + 1.76) dB

Therefore, for a 12-bit converter, this is 74 dB.

Effective Number of Bits (ENOB)

The ENOB is defined by

ENOB = (SINAD − 1.76)/6.02

+ − VIN−), Code 12,288 for the 16-bit

IN

+ − VIN−),

IN

+ − VIN− (that is, 0 V).

IN

+ − VIN− (+200 mV) after the

IN

+ − VIN− (−200 mV) after the

IN

/2), excluding dc. The ratio is

S

Total Harmonic Distortion (THD)

THD is the ratio of the rms sum of harmonics to the
fundamental. For the AD7401, it is defined as

22222

++++

VVVVV

THD

log20)dB(

=

V

1

65432

where:

V

is the rms amplitude of the fundamental.

1

, V3, V4, V5, and V6 are the rms amplitudes of the second

V

2

through the sixth harmonics.

Peak Harmonic or Spurious Noise

Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to f

/2, excluding dc) to the rms value of the

S

fundamental. Normally, the value of this specification is
determined by the largest harmonic in the spectrum, but for
ADCs where the harmonics are buried in the noise floor, it is a
noise peak.

Common-Mode Rejection Ratio (CMRR)

CMRR is defined as the ratio of the power in the ADC output at
±200 mV frequency, f, to the power of a 200 mV p-p sine wave
applied to the common-mode voltage of V
frequency f

, expressed as

S

CMRR (dB) = 10log(Pf/Pf

)

S

+ and VIN− of

IN

where:

Pf is the power at frequency f in the ADC output.
Pf

is the power at frequency fS in the ADC output.

S

Power Supply Rejection Ratio (PSRR)

Variations in power supply affect the full-scale transition but
not converter linearity. PSRR is the maximum change in the
specified full-scale (±200 mV) transition point due to a change
in power supply voltage from the nominal value (see Figure 6).

Isolation Transient Immunity

The isolation transient immunity specifies the rate of rise/fall of
a transient pulse applied across the isolation boundary beyond
which clock or data is corrupted. (It was tested using a transient
pulse frequency of 100 kHz.)

Rev. D | Page 12 of 20

AD7401

THEORY OF OPERATION

CIRCUIT INFORMATION

The AD7401 isolated Σ-Δ modulator converts an analog input
signal into a high speed (20 MHz maximum), single-bit data
stream; the time average of the modulator’s single-bit data is
directly proportional to the input signal. Figure 23 shows a
typical application circuit where the AD7401 is used to provide
isolation between the analog input, a current sensing resistor,
and the digital output, which is then processed by a digital filter
to provide an N-bit word.

ANALOG INPUT

The differential analog input of the AD7401 is implemented
with a switched capacitor circuit. This circuit implements a
second-order modulator stage that digitizes the input signal
into a 1-bit output stream. The sample clock (MCLKIN)
provides the clock signal for the conversion process as well as
the output data-framing clock. This clock source is external on
the AD7401. The analog input signal is continuously sampled
by the modulator and compared to an internal voltage reference.
A digital stream that accurately represents the analog input over
time appears at the output of the converter (see Figure 21).

MODULATOR OUTPUT

+FS ANALOG INPUT

A differential input of 320 mV results in a stream of, ideally, all
1s. This is the absolute full-scale range of the AD7401, while
200 mV is the specified full-scale range, as shown in Tab le 9 .

Table 9. Analog Input Range

Analog Input Voltage Input

Full-Scale Range +640 mV
Positive Full-Scale +320 mV
Positive Specified Input Range +200 mV
Zero 0 mV
Negative Specified Input Range −200 mV
Negative Full-Scale −320 mV

To reconstruct the original information, this output needs to be
digitally filtered and decimated. A Sinc

3

filter is recommended
because this is one order higher than that of the AD7401 modu­lator. If a 256 decimation rate is used, the resulting 16-bit word
rate is 62.5 kHz, assuming a 16 MHz external clock frequency.
Figure 22 shows the transfer function of the AD7401 relative to
the 16-bit output.

65535

53248

–FS ANALOG INP UT

ANALOG I NPUT

Figure 21. Analog Input vs. Modulator Output

A differential signal of 0 V results (ideally) in a stream of 1s and
0s at the MDAT output pin. This output is high 50% of the time
and low 50% of the time. A differential input of 200 mV pro­duces a stream of 1s and 0s that are high 81.25% of the time. A
differential input of −200 mV produces a stream of 1s and 0s
that are high 18.75% of the time.

ISOLATED

5V

AD7401

V

DD1

Σ-∆

IN

–

1

MOD/

ENCODER

DECODER

DECODER

ENCODER

INPUT

CURRENT

R

SHUNT

+

VIN+

V

GND

5851-020

Figure 22. Filtered and Decimated 16-Bit Transfer Characteristic

NONISOLATED

5V/3V

V

DD2

MDAT MDAT

MCLKIN

GND

2

SPECIFIED RANGE

ADC CODE

12288

0

–320mV –200mV + 200mV +320mV

ANALOG INPUT

V

DD

SINC3FILTER

MCLK

GND

CS

SCLK

SDAT

5851-021

05851-019

Figure 23. Typical Application Circuit

Rev. D | Page 13 of 20

AD7401

V

V

DIFFERENTIAL INPUTS

The analog input to the modulator is a switched capacitor
design. The analog signal is converted into charge by highly
linear sampling capacitors. A simplified equivalent circuit
diagram of the analog input is shown in Figure 24. A signal
source driving the analog input must be able to provide the
charge onto the sampling capacitors every half MCLKIN cycle and
settle to the required accuracy within the next half cycle.

φA

1kΩ

+

IN

1kΩ

–

IN

Figure 24. Analog Input Equivalent Circuit

Because the AD7401 samples the differential voltage across its
analog inputs, low noise performance is attained with an input
circuit that provides low common-mode noise at each input.
The amplifiers used to drive the analog inputs play a critical role
in attaining the high performance available from the AD7401.

MCLKIN

φB

φA

φB

φB φB

φA φA

2pF

2pF

05851-022

When a capacitive load is switched onto the output of an op
amp, the amplitude momentarily drops. The op amp tries to
correct the situation and, in the process, hits its slew rate limit.
This nonlinear response, which can cause excessive ringing, can
lead to distortion. To remedy the situation, a low-pass RC filter
can be connected between the amplifier and the input to the
AD7401. The external capacitor at each input aids in supplying
the current spikes created during the sampling process, and the
resistor isolates the op amp from the transient nature of the load.

The recommended circuit configuration for driving the differ­ential inputs to achieve best performance is shown in Figure 25. A
capacitor between the two input pins sources or sinks charge to
allow most of the charge that is needed by one input to be
effectively supplied by the other input. The series resistor again
isolates any op amp from the current spikes created during the
sampling process. Recommended values for the resistors and
capacitor are 22 Ω and 47 pF, respectively.

R

+

V

IN

C

R

–

V

IN

Figure 25. Differential Input RC Network

AD7401

5851-023

Rev. D | Page 14 of 20

AD7401

W

DIGITAL FILTER

A Sinc3 filter is recommended for use with the AD7401. This
filter can be implemented on an FPGA or possibly a DSP. The
following Verilog code provides an example of a Sinc
implementation on a Xylinx® Spartan-II 2.5 V FPGA. This code
can possibly be compiled for another FPGA, such as an Altera®
device. Note that the data is read on the negative clock edge in
this case, although it can be read on the positive edge if preferred.
Figure 29 shows the effect of using different decimation rates
with various filter types.

/*`Data is read on negative clk edge*/
module DEC256SINC24B(mdata1, mclk1, reset,
DATA);

input mclk1; /*used to clk filter*/
input reset; /*used to reset filter*/
input mdata1; /*ip data to be
filtered*/

output [15:0] DATA; /*filtered op*/
integer location;

integer info_file;
reg [23:0] ip_data1;
reg [23:0] acc1;
reg [23:0] acc2;
reg [23:0] acc3;
reg [23:0] acc3_d1;
reg [23:0] acc3_d2;
reg [23:0] diff1;
reg [23:0] diff2;
reg [23:0] diff3;
reg [23:0] diff1_d;
reg [23:0] diff2_d;
reg [15:0] DATA;
reg [7:0] word_count;
reg word_clk;

reg init;

/*Perform the Sinc ACTION*/
always @ (mdata1)

if(mdata1==0)
ip_data1 <= 0; /* change from a 0
to a -1 for 2's comp */
else
ip_data1 <= 1;

/*ACCUMULATOR (INTEGRATOR)
Perform the accumulation (IIR) at the speed
of the modulator.

3

filter

MCLKIN

IP_DATA1

ACC1+ ACC2+

Z

+

Figure 26. Accumulator

Z

+

+

ACC3+

Z

05851-024

Z = one sample delay
MCLKIN = modulators conversion bit rate
*/

always @ (posedge mclk1 or posedge reset)
if (reset)
begin
/*initialize acc registers on reset*/
acc1 <= 0;
acc2 <= 0;
acc3 <= 0;
end
else
begin
/*perform accumulation process*/
acc1 <= acc1 + ip_data1;
acc2 <= acc2 + acc1;
acc3 <= acc3 + acc2;
end

/*DECIMATION STAGE (MCLKIN/ WORD_CLK)
*/

always @ (negedge mclk1 or posedge reset)
if (reset)
word_count <= 0;
else
word_count <= word_count + 1;

always @ (word_count)
word_clk <= word_count[7];

/*DIFFERENTIATOR (including decimation stage)
Perform the differentiation stage (FIR) at a

lower speed.

ACC3

ORD_CLK

DIFF1

+

–

–1

Z

Figure 27. Differentiator

DIFF2

+

–

–

–1

Z

DIFF3

+

–

–1

Z

05851-025

Z = one sample delay
WORD_CLK = output word rate
*/

Rev. D | Page 15 of 20

AD7401

always @ (posedge word_clk or posedge reset)
if(reset)
begin
acc3_d2 <= 0;
diff1_d <= 0;
diff2_d <= 0;
diff1 <= 0;
diff2 <= 0;

diff3 <= 0;
end

else
begin
diff1 <= acc3 - acc3_d2;
diff2 <= diff1 - diff1_d;
diff3 <= diff2 - diff2_d;
acc3_d2 <= acc3;
diff1_d <= diff1;
diff2_d <= diff2;
end

/* Clock the Sinc output into an output
register

WORD_CLK

DATADIFF3

05851-026

Figure 28. Clocking Sinc Output into an Output Register

WORD_CLK = output word rate
*/

always @ (posedge word_clk)
begin

DATA[15] <= diff3[23];
DATA[14] <= diff3[22];
DATA[13] <= diff3[21];
DATA[12] <= diff3[20];
DATA[11] <= diff3[19];
DATA[10] <= diff3[18];

DATA[9] <= diff3[17];
DATA[8] <= diff3[16];
DATA[7] <= diff3[15];
DATA[6] <= diff3[14];
DATA[5] <= diff3[13];
DATA[4] <= diff3[12];
DATA[3] <= diff3[11];
DATA[2] <= diff3[10];
DATA[1] <= diff3[9];
DATA[0] <= diff3[8];

end
endmodule

90

80

70

60

50

40

SNR (dB)

30

20

10

0

Figure 29. SNR vs. Decimation Rate for Different Filter Types

10 100 1k1

DECIMATION RATE

SINC

SINC

SINC

3

2

1

05851-035

Figure 29 shows a plot of SNR performance vs. decimation rate
with different filter types. Note that, for a given bandwidth
requirement, a higher MCLKIN frequency can allow higher
decimation rates to be used, resulting in higher SNR performance.

Rev. D | Page 16 of 20

AD7401

A

A

AKV

APPLICATIONS INFORMATION

GROUNDING AND LAYOUT

Supply decoupling with a value of 100 nF is strongly recom­mended on both V

pins does not affect performance significantly. In applications

V

DD1

DD1

and V

. Decoupling on one or both

DD2

involving high common-mode transients, care should be taken
to ensure that board coupling across the isolation barrier is
minimized. Furthermore, the board layout should be designed
so that any coupling that occurs equally affects all pins on a
given component side. Failure to ensure this may cause voltage
differentials between pins to exceed the absolute maximum
ratings of the device, thereby leading to latch-up or permanent
damage. Any decoupling used should be placed as close to the
supply pins as possible.

Series resistance in the analog inputs should be minimized to
avoid any distortion effects, especially at high temperatures. If
possible, equalize the source impedance on each analog input to
minimize offset. Beware of mismatch and thermocouple effects
on the analog input PCB tracks to reduce offset drift.

EVALUATING THE AD7401 PERFORMANCE

A simple standalone AD7401 evaluation board is available with
split ground planes and a board split beneath the AD7401
package to ensure isolation. This board allows access to each
pin on the device for evaluation purposes. External supplies and
all other circuitry (such as a digital filter) must be provided by
the user.

INSULATION LIFETIME

All insulation structures, subjected to sufficient time and/or
voltage, are vulnerable to breakdown. In addition to the testing
performed by the regulatory agencies, Analog Devices has
carried out an extensive set of evaluations to determine the
lifetime of the insulation structure within the AD7401.

These tests subjected populations of devices to continuous
cross-isolation voltages. To accelerate the occurrence of failures,
the selected test voltages were values exceeding those of normal
use. The time-to-failure values of these units were recorded and
used to calculate acceleration factors. These factors were then
used to calculate the time to failure under normal operating
conditions. The values shown in Tab le 7 are the lesser of the
following two values:

• The value that ensures at least a 50-year lifetime of

continuous use

• The maximum CSA/VDE approved working voltage

It should also be noted that the lifetime of the AD7401 varies
according to the waveform type imposed across the isolation
barrier. The iCoupler insulation structure is stressed differently
depending on whether the waveform is bipolar ac, unipolar ac,
or dc. Figure 30, Figure 31, and Figure 32 illustrate the different
isolation voltage waveforms.

R

TED PEAKVOLTAGE

0V

05851-039

Figure 30. Bipolar AC Waveform

TED PEAKVOLTAGE

R

0V

Figure 31. Unipolar AC Waveform

RATED P E

0V

OLTAGE

Figure 32. DC Waveform

05851-040

05851-041

Rev. D | Page 17 of 20

AD7401

C

OUTLINE DIMENSIONS

10.50 (0.4134)

10.10 (0.3976)

9

7.60 (0.2992)

7.40 (0.2913)

8

10.65 (0.4193)

10.00 (0.3937)

2.65 (0.1043)

2.35 (0.0925)

SEATING
PLANE

8°
0°

0.33 (0.0130)

0.20 (0.0079)

2

9

5

(

0

.

0

(

0

.

0

0

9

1.27 (0.0500)

0.40 (0.0157)

)

45°

)

8

03-27-2007-B

0

.

7

5

2

5

0

.

0.30 (0.0118)

0.10 (0.0039)

OPLANARITY

0.10

16

1

1.27 (0.0500)
BSC

0.51 (0.0201)

0.31 (0.0122)

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

COMPLIANT TO JEDEC STANDARDS MS-013-AA

Figure 33. 16-Lead Standard Small Outline Package [SOIC_W]

Wide Body

(RW-16)

Dimensions shown in millimeters and (inches)

ORDERING GUIDE

Model1 Temperature Range Package Description Package Option

AD7401YRW −40°C to +105°C 16-Lead Standard Small Outline Package [SOIC_W] RW-16
AD7401YRW-REEL −40°C to +105°C 16-Lead Standard Small Outline Package [SOIC_W] RW-16
AD7401YRW-REEL7 −40°C to +105°C 16-Lead Standard Small Outline Package [SOIC_W] RW-16
AD7401YRWZ −40°C to +105°C 16-Lead Standard Small Outline Package [SOIC_W] RW-16
AD7401YRWZ-REEL −40°C to +105°C 16-Lead Standard Small Outline Package [SOIC_W] RW-16
AD7401YRWZ-REEL7 −40°C to +105°C 16-Lead Standard Small Outline Package [SOIC_W] RW-16
EVAL-AD7401EDZ Evaluation Board
EVAL-CED1Z Development Board

1

Z = RoHS Compliant Part.

Rev. D | Page 18 of 20

AD7401

NOTES

Rev. D | Page 19 of 20

AD7401

NOTES

©2006–2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05851-0-7/11(D)

Rev. D | Page 20 of 20