Datasheet AD7394 Datasheet (ANALOG DEVICES)

+3 V/+5 V, Dual,

VDDV

FEATURES

Micropower: 100 μA/DAC

0.1 μA typical power shutdown
Single-supply 2.7 V to 5.5 V operation
12-bit resolution
Serial interface with Schmitt trigger inputs

APPLICATIONS

Automotive output span voltage
Portable communications
Digitally controlled calibration
PC peripherals

CLK

SDI

(DATA)

LDA
LDB

CS

Serial Input 12-Bit DAC

AD7394

FUNCTIONAL BLOCK DIAGRAM

REF

OP AMP

AGND

A

OP AMP

B

SHDN

EN

SHIFT

REGISTER

DGND MSB

DAC A

REGISTER

D

PR

12

D

DAC B

REGISTER

PR

DAC A

AD7394

DAC B

RS

Figure 1.

V

V

OUTA

OUTB

08528-001

GENERAL DESCRIPTION

The AD7394 is dual, 12-bit, voltage output digital-to-analog
converter designed to operate from a single 3 V supply. Built
using a CBCMOS process, this monolithic DAC offers the
user low cost and ease-of-use in a single-supply 3 V system.
Operation is guaranteed over the supply voltage range of 2.7 V
to 5.5 V making this device ideal for battery-operated
applications.

The full-scale output voltage is determined by the applied
external reference input voltage, V
input to V
to the positive supply, V

outputs allows for a full-scale voltage set equal

OUT

, or any value in between.

DD

A doubled-buffered serial data interface offers high speed,
microcontroller compatible inputs using the serial-data-in
(SDI), clock (CLK), and load strobe (

CS

A chip-select (

) pin simplifies the connection of multiple
DAC packages by enabling the clock input when active low.
Additionally, an

RS

input sets the output to zero scale or to 1/2

scale based on the logic level applied to the MSB pin. The power

SHDN

shutdown pin,

, reduces power dissipation to nanoamp
current levels. All digital inputs contain Schmitt-triggered logic
levels to minimize power dissipation and prevent false
triggering on the clock input.

. The rail-to-rail V

REF

LDA

and

LDB

REF

) pins.

The AD7394 is specified over the extended industrial (−40°C
to +85°C) temperature range and is available in a low profile

1.75 mm height SOIC surface mount package.

1.0
VDD = 3V

0.8

0.6

0.4

0.2

0

DNL (LSB)

–0.2

–0.4

–0.6

–0.8
–1.0

= 2.5V

V

REF

TA = –55°C, +25°C, +85°C
SUPERIMPOSED

0 500 1000 1500 2000 2500 3000 3500 4000

CODE (Decimal)

Figure 2. Differential Nonlinearity Error vs. Code

08528-002

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©1998–2010 Analog Devices, Inc. All rights reserved.

AD7394

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

AD7394 Electrical Characteristics ............................................. 3

Absolute Maximum Ratings ............................................................ 7

ESD Caution .................................................................................. 7

Pin Configuration and Function Descriptions ............................. 8

Typical Performance Characteristics ............................................. 9

Theory of Operation ...................................................................... 12

REVISION HISTORY

1/10—Rev. 0 to Rev. A

Updated Format .................................................................. Universal

Removed AD7395 ............................................................... Universal

Updated Outline Dimensions ....................................................... 18

Changes to Ordering Guide .......................................................... 19

4/98—Revision. 0: Initial Version

DAC Section ................................................................................ 12

Amplifier Section ....................................................................... 12

Reference Input ........................................................................... 12

Power Supply ............................................................................... 13

Power Supply Bypassing And Grounding ............................... 13

Input Logic Levels ...................................................................... 13

Digital Interface .......................................................................... 14

Reset (RS) Pin ............................................................................. 14

Power Shutdown (

Unipolar Output Operation ...................................................... 15

Outline Dimensions ....................................................................... 16

Ordering Guide .......................................................................... 16

SHDN

) ......................................................... 15

Rev. A | Page 2 of 16

AD7394

SPECIFICATIONS

AD7394 ELECTRICAL CHARACTERISTICS

@ V

Table 1.

Parameter Symbol Conditions 3 V ± 10% 5 V ± 10% Unit

STATIC PERFORMANCE

REFERENCE INPUT

ANALOG OUTPUT

LOGIC INPUTS

INTERFACE TIMING

AC CHARACTERISTICS

Data = 000H, f = 100 kHz −63 −63 dB typ

= 2.5 V, −40°C < TA < +85°C, unless otherwise noted.

REF IN

Resolution1 N 12 12 Bits
Relative Accuracy2 INL TA = +25°C ±1.5 ±1.5 LSB max
T

= –40°C, +85°C ±2.0 ±2.0 LSB max

A

Differential Nonlinearity2 DNL TA = +25°C, monotonic ±0.9 ±0.9 LSB max
Monotonic ±1 ±1 LSB max
Zero-Scale Error V
Full-Scale Voltage Error V
T
Full-Scale Tempco3 TCV

V

Range V

REF IN

Input Resistance R
Input Capacitance3 C

Output Current (Source) I
Output Current (Sink) I

Data = 000H 4.0 4.0 mV max

ZSE

TA = +25°C, +85°C, data = FFFH ±8 ±8 mV max

FSE

= −40°C, data = FFFH ±20 ±20 mV max

A

−30 −30 ppm/°C typ

FS

0/VDD 0/VDD V min/max

REF

2.5 2.5 MΩ typ4

REF

5 5 pF typ

REF

Data = 800H, ΔV

OUT

Data = 800H, ΔV

OUT

= 5 LSB 1 1 mA typ

OUT

= 5 LSB 3 3 mA typ

OUT

Capacitive Load3 CL No oscillation 100 100 pF typ

Logic Input Low Voltage VIL 0.5 0.8 V max
Logic Input High Voltage V

V

IH

− 0.6 4.0 V min

DD

Input Leakage Current IIL 10 10 μA max
Input Capacitance3 C

3, 5

10 10 pF max

IL

Clock Width High tCH 50 30 ns min
Clock Width Low tCL 50 30 ns min
Load Pulsewidth t

30 20 ns min

LDW

Data Setup tDS 10 10 ns min
Data Hold tDH 30 15 ns min
Clear Pulsewidth t
Load Setup t
Load Hold t

15 15 ns min

CLRW

30 15 ns min

LD1

40 20 ns min

LD2

Output Slew Rate SR Data = 000H to FFFH to 000H 0.05 0.05 V/μs typ
Settling Time6 t

To ±0.1% of full scale 70 60 μs typ

S

DAC Glitch Q Code 7FFH to 800H to 7FFH 65 65 nV/s typ
Digital Feedthrough Q
Feedthrough V

V

OUT/VREF

= 1.5 VDC +1 V p-p, 15 15 nV/s typ

REF

Rev. A | Page 3 of 16

AD7394

Parameter Symbol Conditions 3 V ± 10% 5 V ± 10% Unit

SUPPLY CHARACTERISTICS

Power Supply Range V
Shutdown Supply Current
Positive Supply Current IDD VIL = 0 V, no load 125/200 125/200 μA typ/max
Power Dissipation P
Power Supply Sensitivity PSS ΔVDD = ±5% 0.006 0.006 %/% max

1

One LSB = V

2

The first two codes (000H, 001H) are excluded from the linearity error measurement.

3

These parameters are guaranteed by design and not subject to production testing.

4

Typicals represent average readings measured at 25°C.

5

All input control signals are specified with tR = tF = 2 ns (10% to 90% of +3 V) and timed from a voltage level of 1.6 V.

6

The settling time specification does not apply for negative going transitions within the last three LSBs of ground.

/4096 V for the 12-bit AD7394.

REF

DNL < ± 1 LSB 2.7/5.5 2.7/5.5 V min/max

DD RANGE

SHDN

I

DD_SD

VIL = 0 V, no load 600 1000 μW max

DISS

= 0, VIL = 0 V, no load

0.1/1.5 0.1/1.5 μA typ/max

Rev. A | Page 4 of 16

AD7394

Timing Diagrams

SDI

CLK

t

CSS

CS

LDA, LDB

SDI

CLK

LDA, LDB

RS

V

OUT

t

LD1

tDSt

DH

t

CL

t

CH

FS

ZS

t

LDW

t

S

ERROR BAND

±1 LSB

Figure 3.

SHDN

I

DD

Figure 4.

t

SDR

D0D1D2D3D4D5D6D7D8D9D10D11

t

CSH

t

LD2

t

CLRW

t

S

08528-003

08528-004

Rev. A | Page 5 of 16

AD7394

Table 2. Control Logic Truth Table

CS

CLK

H X H X H H No effect Latched
L L H X H H No effect Latched
L H H X H H No effect Latched
L

↑+

L

↑+

L H H X H L No effect Transparent

L H X H H No effect Latched

↑+1
H X H X H

H X H X H L No effect Transparent
X X L H H X No effect Loaded with 800H
X X
X X L L H X No effect Loaded with all zeros
X X
X X X X L X No effect No affect

1

↑+ positive logic transition; ￬− negative logic transition; X don’t care.

2

Do not clock in serial data while level sensitive inputs

Table 3. AD7394 Serial Input Register Data Format, Data Is Loaded in MSB-First Format

MSB

B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

RS

SHDN LDA/LDB

MSB

Serial Shift Register Function DAC Register Function

H X H H Shift-register-data advanced one bit Latched
H X H L Shift-register-data advanced one bit Transparent

2

￬−

H H H No effect Latched with 800H

↑+

L H H No effect Latched all zeros

↑+

No effect Updated with current shift register contents

LDA

LDB

or

are logic low.

LSB

Rev. A | Page 6 of 16

AD7394

ABSOLUTE MAXIMUM RATINGS

Table 4.

Parameter Rating

VDD to GND –0.3 V to +7 V
V

to GND –0.3 V to VDD

REF

Logic Inputs to GND –0.3 V to +8 V
V

to GND –0.3 V to VDD + 0.3 V

OUT

I

Short Circuit to GND 50 mA

OUT

Package Power Dissipation (TJ max – TA)/θJA
Thermal Resistance θJA

14-Lead SOIC Package (R-14) 158°C/W
Maximum Junction Temperature (TJ max) 150°C
Operating Temperature Range −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Lead Temperature

R-14 (Vapor Phase, 60 sec) 215°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

Rev. A | Page 7 of 16

AD7394

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

AGND

1

V

2

OUTA

V

DGND

CLK

REF

CS

SDI

AD7394

3
4

TOP VIEW

(Not to Scale)

5
6
7

Figure 5. Pin Configuration

Table 5. Pin Function Descriptions

Pin No. Mnemonic Description

1 AGND Analog Ground.
2 V
3 V

DAC A Voltage Output.

OUTA

DAC Reference Voltage Input Terminal. Establishes DAC full-scale output voltage. Pin can be tied to VDD pin.

REF

4 DGND Digital Ground. Should be tied to analog GND.

CS

5

Chip Select, Active Low Input. Disables shift register loading when high. Does not affect LDA or LDB operation.
6 CLK Clock Input. Positive edge clocks data into shift register, MSB data bit first.
7 SDI Serial Data Input. Input data loads directly into the shift register.
8

Load DAC Register Strobe. Level sensitive active low. Transfers shift register data to DAC A register. Asynchronous

LDA

active low input. See Table 2 for operation.

9
10

RS

Load DAC Register Strobe. Level-sensitive active low. Transfers shift register data to DAC B register. Asynchronous

LDB

Resets DAC register to zero condition or half-scale, depending on MSB pin logic level. Asynchronous active low input.

active low input. See Table 2 for operation.

11 MSB

Digital Input. Logic High presets DAC registers to half-scale 800
logic low clears all DAC registers to zero (000H) when the RS pin is strobed.

12

Active Low Shutdown Control Input. Does not affect register contents as long as power is present on VDD. New data

SHDN

can be loaded into the shift register and DAC register during shutdown. When device is powered up the most

recent data loaded into the DAC register controls the DAC output.
13 VDD Positive Power Supply Input. Specified range of operation is 2.7 V to 5.5 V
14 V

DAC B Voltage Output.

OUTB

14

V

OUTB

13

V

DD

12

SHDN

11

MSB
LDB

10

RS

9

LDA

8

08528-005

(sets MSB bit to one) when the RS pin is strobed;

H

Rev. A | Page 8 of 16

AD7394

√

TYPICAL PERFORMANCE CHARACTERISTICS

1.5

1.0

0.5

0

INL (LSB)

–0.5

–1.0

–1.5

0 500 1000 1500 2000

TA = –55°C

TA = +25°C, + 85°C

Figure 6. Integral Nonlinearity Error vs. Code

CODE (Decimal)

VDD = 3V
V

= 2.5V

REF

2500 3000 3500 4000

08528-006

30

25

20

15

10

5

FSE (LSB)

0

–10

–15

–5

0

FULL SCALE ERROR

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

TOTAL UNADJUST E D

FULL SCALE ERROR

V

(V)

REF

Figure 9. Full-Scale Error vs. V

TA = 25°C

08528-011

REF

25

SS = 200 UNITS
T

= 25°C

A

V

= 2.7V

DD

20

V

= 2.5V

REF

15

10

FREQUENCY

5

0

–3 –2 –1 0 1

TOTAL UNADJUS TED ERROR (LS B)

08528-007

Figure 7. Total Unadjusted Error Histogram

0.6

0.5
VDD = 5.0V

= 25°C

(V)

T

A

CODE = 768

REF

H

08528-010

0.4

0.3

INL (LSB)

0.2

0.1

0

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

0

Figure 8. Integral Nonlinearity Error vs. V

V

REF

10

8

Hz)

6

4

2

OUTPUT NOISE DENSITY (µV/

0

FREQUENCY (Hz)

VDD = 5V
V

REF

= +25°C

T

A

Figure 10. Output Noise Density vs. Frequency

140

135

130

125

120

(µA)

DD

115

I

110

105

100

VDD = 3V

VIN 3V TO 0V

0 0.5 1.0 1.5 2.0 2.5 3.0

VIN (V)

VIN 0V TO 3V

Figure 11. Supply Current vs. Logic Input Voltage

= 2.5V

100k10 100 1k 10k1

08528-012

08528-013

Rev. A | Page 9 of 16

AD7394

5.0

4.5

4.0

3.5

3.0

2.5

LOGIC THRESHOLD (V)

2.0

1.5

1.0

V

FROM LOW TO HIGH

LOGIC

V

LOGIC

FROM HIGH TO LOW

VDD(V)

734562

8528-014

Figure 12. Logic Threshold vs. Supply Voltage

1800

A: IDD = 2.7V, CO DE = 555

1600

B: IDD = 2.7V, CO DE = 3FF
C: VDD = 5.5V, CO DE = 155

1400

D: VDD = 5.5V, CO DE = 3FF

1200

1000

(µA)

DD

800

I

600

400

200

0

CLOCK FREQ UENCY ( Hz )

H
H

H

H

D

C

B

A

10M10k 100k 1M1k

8528-015

Figure 13. Supply Current vs. Clock Frequency

80

70

60

= 5.0V, ±5%

V

50

40

PSRR (dB)

30

20

10

0

VDD = 3.0V, ±5%

1 10 100 1k 10k

FREQUENCY (Hz)

DD

TA = 25°C

Figure 14. Power Supply Rejection vs. Frequency

20

18

16

14

12

10

8

6

CURRENT SINKING (m A)

4

2

0

VDD = 5V

123456789100

Figure 15. I

ΔV

OUT

Sink Current vs. ΔV

OUT

(LSB)

V

DD

V

= 2.5V

REF

CODE = 800

= 3V

OUT

08528-016

H

08528-017

Rev. A | Page 10 of 16

AD7394

10

V

= 2.5V

REF

9

CODE = 800

8

7

6

5

4

3

CURRENT SOURCING ( mA)

2

1

0
–10 –9 0

H

VDD = 5V

VDD = 3V

–8 –7 –6 –5 –4 –3 –2 –1

Figure 16. I

ΔV

(LSB)

OUT

Source Current vs. ΔV

OUT

OUT

1.262

VDD = +5V
V

REF

= 2.5V

= 25°C

T

A

CODE = 800

5mV/DIV

(V)

V

1.257

1.252

OUT

1.247

TO 7FF

H

1.4

1.2

(mV)

1.0

OUT

0.8

0.6

0.4

NOMINAL CHANGE IN V

0.2

0

08528-018

CODE = 000

100 200 300 400 500 6000

HOURS OF O P E RATION (150° C)

H

CODE = FFF

H

08528-021

Figure 18. Long-Term Drift Accelerated by Burn-In

H

1.242

1.237

TIME (2µs/DIV)

08528-019

Figure 17. Midscale Transition Performance

Rev. A | Page 11 of 16

AD7394

V

THEORY OF OPERATION

The AD7394 is a pin compatible, dual, 12-bit digital-to-analog
converter. This single-supply operation device consumes less
than 200 microamps of current while operating from power
supplies in the 2.7 V to 5.5 V range, making it ideal for battery­operated applications. The AD7394 contains a voltage-switched,
12-bit, laser trimmed digital-to-analog converter, rail-to-rail
output op amps, two DAC registers, and a serial input shift
register. The external reference input has constant input
resistance independent of the digital code setting of the DAC.
In addition, the reference input can be tied to the same supply
voltage as V
0 to V
(SDI), clock (CLK), a chip select pin (

Register pins (

, resulting in a maximum output voltage span of

DD

. The serial interface consists of a serial data input

DD

CS

), and two load DAC

LDA

and

LDB

). A reset (RS) pin is available to
reset the DAC register to zero scale or midscale, depending on
the digital level applied to the MSB pin. This function is useful
for power-on reset or system failure recovery to a known state.
Additional power savings are accomplished by activating the
SHDN

pin resulting in a 1.5 mA maximum consumption sleep

mode.

DAC SECTION

The voltage switched R-2R DAC generates an output voltage
dependent on the external reference voltage connected to the
REF pin according to the following equation:

DV

×

V

OUT

where:

D is the decimal data word loaded into the DAC register.
N is the number of bits of DAC resolution.

For the 12-bit AD7394 operating from a 5.0 V reference
Equation 1 becomes:

V

OUT

Using Equation 3 the AD7394 provides a nominal midscale
voltage of 2.50 V for D = 2048, and a full-scale output of 4.998 V.
The LSB step size is = 5.0 × 1/4096 = 0.0012 V.

REF

= (1)

N

2

0.5

D

×

= (3)

4096

AMPLIFIER SECTION

The internal DAC’s output is buffered by a low power
consumption precision amplifier. The op amp has a 60 μs
typical settling time to 0.1% of full scale. There are slight
differences in settling time for negative slewing signals vs.
positive. Also, negative transition settling time to within the
last 6 LSBs of zero volts has an extended settling time. The
rail-to-rail output stage of this amplifier has been designed
to provide precision performance while operating near either
power supply. Figure 19 shows an equivalent output schematic
of the rail-to-rail-amplifier with its N-channel pull-down FETs
that will pull an output load directly to GND. The output
sourcing current is provided by a P-channel pull-up device
that can source current to GND terminated loads.

DD

P-CH

V

OUT

N-CH

AGND

08528-022

Figure 19. Equivalent Analog Output Circuit

The rail-to-rail output stage provides more than ±1 mA of
output current. The N-channel output pull-down MOSFET
shown in Figure 19 has a 35 Ω on resistance, which sets the
sink current capability near ground. In addition to resistive
load driving capability, the amplifier has also been carefully
designed and characterized for up to 100 pF capacitive load
driving capability.

REFERENCE INPUT

The reference input terminal has a constant input resistance
independent of digital code, which results in reduced glitches
on the external reference voltage source. The high 2.5 MΩ
input resistance minimizes power dissipation within the
AD7394 DAC. The V
from ground to the positive supply voltage V
simplest applications, which saves an external reference voltage
source, is connection of the V
supply. This connection results in a rail-to-rail voltage output
span maximizing the programmed range. The reference input
accepts ac signals as long as they are kept within the supply
voltage range, 0 < V
integral nonlinearity error performance are plotted in Figure 8.
The ratiometric reference feature makes the AD7394 an ideal
companion to ratiometric analog-to-digital converters such
as the AD7896.

input accepts input voltages ranging

REF

. One of the

DD

terminal to the positive VDD

REF

< VDD. The reference bandwidth and

REF

Rev. A | Page 12 of 16

AD7394

*

V

V

C

POWER SUPPLY

The very low power consumption of the AD7394 is a direct
result of a circuit design optimizing the use of a CBCMOS process.
By using the low power characteristics of CMOS for the logic,
and the low noise, tight matching of the complementary bipolar
transistors, excellent analog accuracy is achieved. One advan­tage of the rail-to-rail output amplifiers used in the AD7394 is
the wide range of usable supply voltage. The part is fully
specified and tested for operation from 2.7 V to 5.5 V.

POWER SUPPLY BYPASSING AND GROUNDING

Local supply bypassing consisting of a 10 μF tantalum
electrolytic in parallel with a 0.1 μF ceramic capacitor is
recommended in all applications (Figure 20).

2.7V TO 5.5

C

*

CS

LDA, LDB

CLK

SDI

RS

OPTIO NAL EXTERNAL
REFERENCE BYPASS

Figure 20. Recommended Supply Bypassing for the AD7394

REFV

DGND

DD

AD7394

AGND

0.1µF

10µF

V

V

OUTA

OUTB

08528-023

INPUT LOGIC LEVELS

All digital inputs are protected with a Zener-type ESD protection
structure (Figure 21) that allows logic input voltages to exceed

supply voltage. This feature can be useful if the user is

the V

DD

driving one or more of the digital inputs with a 5 V CMOS logic
input-voltage level while operating the AD7394 on a 3 V power
supply. If this mode of interface is used, make sure that the V
of the 5 V CMOS meets the V

input requirement of the

IL

AD7394 operating at 3 V. See Figure 12 for a graph of digital
logic input threshold vs. operating V

DD

LOGI

IN

GND

Figure 21. Equivalent Digital Input ESD Protection

supply voltage.

DD

08528-024

To minimize power dissipation from input logic levels that are
near the V

and VIL logic input voltage specifications, a Schmitt

IH

trigger design was used that minimizes the input buffer current
consumption compared to traditional CMOS input stages.
Figure 11 is a plot of incremental input voltage vs. supply current
showing that negligible current consumption takes place when
logic levels are in their quiescent state. The normal crossover
current still occurs during logic transitions. A secondary
advantage of this Schmitt trigger is the prevention of false
triggers that would occur with slow moving logic transitions
when a standard CMOS logic interface or opto isolators are

LDA, LDB, RS

CS

used. The logic inputs SDI, CLK,
SHDN

all contain the Schmitt trigger circuits.

,

, and

OL

Rev. A | Page 13 of 16

AD7394

DIGITAL INTERFACE

The AD7394 has a serial data input. A functional block diagram
of the digital section is shown in Figure 22, while Ta b le 2
contains the truth table for the logic control inputs. Three pins
control the serial data input register loading. Two additional
pins determine which DAC receives the data loaded into the
input shift register. Data at the SDI is clocked into the shift
register on the rising edge of the CLK. Data is entered in the

CS

MSB-first format. The active low chip select (
loading of data into the shift register from the SDI pin. Twelve
clock pulses are required to load the 12-bit AD7390 DAC shift
register. If additional bits are clocked into the shift register, for
example, when a microcontroller sends two 8-bit bytes, the

CS

MSBs are ignored ( ). When Tabl e 6

returns to logic high,
shift register loading is disabled. The load pins
control the flow of data from the shift register to the DAC register.
After a new value is clocked into the serial-input register, it is
transferred to the DAC register associated with its
logic control line. Note, if the user wants to load both DAC

registers with the current contents of the shift register, both
control lines
LDA

and

LDB

LDA

pins are level-sensitive and should be returned

and

LDB

should be strobed together. The

to logic high prior to any new data being sent to the input shift
register to avoid changing the DAC register values. See
for a complete set of conditions.

) pin enables

LDA

and

LDA

or

Tabl e 2

LDB

LDB

CS

CLK

SDI

EN

DAC A REGISTER

DPR

SHIFT

REGISTER

Q

Figure 22. Equivalent Digital Interface Logic

DAC B REGISTER

DPR

MSB

SRBDLADL

08528-025

RESET (RS) PIN

Forcing the asynchronous RS pin low sets the DAC register to
all zeros, or midscale, depending on the logic level applied to
the MSB pin. When the MSB pin is set to logic high, both DAC
registers are reset to midscale (that is, the DAC register’s MSB
bit is set to Logic 1 followed by all zeros). The reset function is
useful for setting the DAC outputs to zero at power-up or after
a power supply interruption. Test systems and motor controllers
are two of many applications that benefit from powering up to
a known state. The external reset pulse can be generated by the
microprocessor’s power-on reset signal, by an output from the

RS

microprocessor, or by an external resistor and capacitor.

has
a Schmitt trigger input, which results in a clean reset function
when using external resistor/capacitor generated pulses. See

for more information. Tabl e 2

Table 6. Typical Microcontroller Interface Formats1

MSB BYTE 1 LSB MSB BYTE 0 LSB

B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
X X X X D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
X X X X X X D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

1

D11 to D0: 12-bit AD7394 DAC data; X = don’t care; the MSB of byte 1 is the first bit that is loaded into the SDI input.

Rev. A | Page 14 of 16

AD7394

V

POWER SHUTDOWN (SHDN)

Maximum power savings can be achieved by using the power
shutdown control function. This hardware activated feature is

SHDN

controlled by the active low input

pin. This pin has a
Schmitt trigger input, which helps to desensitize it to slowly
changing inputs. By placing a logic low on this pin, the internal
consumption of the device is reduced to nano amp levels, guar­anteed to 1.5 μA maximum over the operating temperature
range. When the AD7394 has been programmed into the power
shutdown state, the present DAC register data is maintained
as long as V
command,

remains greater than 2.7 V. Once a wake-up

DD

SHDN

= 1, is given, the DAC voltage outputs return to
their previous values. It typically takes 80 microseconds for the
output voltage to fully stabilize. In the shutdown state the DAC
output amplifier exhibits an open circuit with a nominal output
resistance of 500 kΩ to ground. If the power shutdown feature is

SHDN

not needed, tie the

pin to the VDD voltage thereby

disabling this function.

UNIPOLAR OUTPUT OPERATION

This is the basic mode of operation for the AD7394. As shown
in Figure 23, the AD7394 has been designed to drive loads as
low as 5 kΩ in parallel with 100 pF. The code table for this
operation is shown in Table 7.

The circuit can be configured with an external reference plus
power supply, or powered from a single dedicated regulator or
reference depending on the application performance requirements.

+2.7V TO +5.5

R

0.01µF

EXT
REF

CONTROLLER

V

V

MICRO-

5

DIGITAL

Figure 23. AD7394 Unipolar Output Operation

DD

REF

DAC A

DAC B

DGND AGND

DIGITAL INTERFACE
CIRCUITRY OM ITTE D
FOR CLARIT Y .

75kΩ

75kΩ

0.1µF

100pF

100pF

Table 7. Unipolar Code Table

Output
Hexadecimal Number
in DAC Register

Decimal Number
in DAC Register

Voltage (V)

= 2.5 V]

[V

REF

FFF 4095 2.4994
801 2049 1.2506
800 2048
7FF 2047

1.2500

1.2494

000 0 0

V

V

10µF

OUTA

OUTB

8528-026

Rev. A | Page 15 of 16

AD7394

OUTLINE DIMENSIONS

8.75 (0.3445)

8.55 (0.3366)

BSC

8

7

6.20 (0.2441)

5.80 (0.2283)

1.75 (0.0689)

1.35 (0.0531)

SEATING
PLANE

8°
0°

0.25 (0.0098)

0.17 (0.0067)

0.50 (0.0197)

0.25 (0.0098)

1.27 (0.0500)

0.40 (0.0157)

45°

060606-A

4.00 (0.1575)

3.80 (0.1496)

0.25 (0.0098)

0.10 (0.0039)

COPLANARITY

0.10

14

1

1.27 (0.0500)

0.51 (0.0201)

0.31 (0.0122)

CONTROLLING DIME NSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLI M E TER EQUIVALENTS FOR
REFERENCE ONLYAND ARE NOT APP ROPRIATE FOR USE IN DESIGN.

COMPLIANT TO JEDEC STANDARDS MS-012-AB

Figure 24. 14-Lead Standard Small Outline Package [SOIC_N]

Narrow Body

(R-14)

Dimensions shown in millimeters and (inches)

ORDERING GUIDE

1, 2

Model

AD7394ARZ 12 −40°C to +85°C 14-Lead Standard Small Outline Package [SOIC_N] R-14
AD7394ARZ-REEL7

1

The AD7394 contains 709 transistors. The die size measures 70 mil × 99 mil.

2

Z = RoHS Compliant Part.

Res (LSB) Temperature Range Package Description Package Option

12 −40°C to +85°C 14-Lead Standard Small Outline Package [SOIC_N] R-14

©1998–2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D08528-0-1/10(A)

Rev. A | Page 16 of 16