Datasheet AD7390AR-REEL7, AD7390AN, AD7391SR, AD7391ARU-REEL, AD7391AR Datasheet (Analog Devices)

REV. A

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.

a

AD7390/AD7391

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © Analog Devices, Inc., 2002

3 V Serial-Input

Micropower 10-Bit and 12-Bit DACs

FUNCTIONAL BLOCK DIAGRAM

EN

AD7390

DAC REGISTER

12-BIT DAC

12

12

SERIAL REGISTER

REF

V

DD

CLR

LD

CLK

SDI

GND

V

OUT

FEATURES
Micropower—100 A
Single-Supply—2.7 V to 5.5 V Operation
Compact 1.75 mm Height SO-8 Package

and 1.1 mm Height TSSOP-8 Package
AD7390—12-Bit Resolution
AD7391—10-Bit Resolution
SPI and QSPI Serial Interface Compatible with Schmitt

Trigger Inputs

APPLICATIONS
Automotive 0.5 V to 4.5 V Output Span Voltage
Portable Communications
Digitally Controlled Calibration

GENERAL DESCRIPTION

The AD7390/AD7391 family of 10-bit and 12-bit voltage­output digital-to-analog converters is designed to operate
from a single 3 V supply. Built using a CBCMOS process,
these monolithic DACs offer the user low cost, and ease-of-use
in single-supply 3 V systems. Operation is guaranteed over the
supply voltage range of 2.7 V to 5.5 V consuming less than 100 µA
making this device ideal for battery operated applications.

The full-scale voltage output is determined by the external
reference input voltage applied. The rail-to-rail REF

IN

to

DAC

OUT

allows for a full-scale voltage set equal to the positive

supply V

DD

or any value in between.

A doubled-buffered serial-data interface offers high-speed,
3-wire, SPI and microcontroller compatible inputs using data

in (SDI), clock (CLK) and load strobe (LD) pins. Addition­ally, a CLR input sets the output to zero scale at power on or
upon user demand.

Both parts are offered in the same pinout to allow users to select
the amount of resolution appropriate for their application without
circuit card redesign.

The AD7390/AD7391 are specified over the extended industrial
(40°C to 85°C) temperature range. The AD7391AR is
specified for the 40°C to 125°C automotive temperature
range. The AD7390/AD7391s are available in plastic DIP, and
low profile 1.75 mm height SO-8 surface mount packages. The
AD7391ARU is available for ultracompact applications in a thin

1.1 mm TSSOP-8 package.

CODE – Decimal

1.00

1.00

0 4096512

DNL – LSB

1024 1536 2048 2560 3072 3584

0.75

0.00

0.25

0.50

0.75

0.50

0.25

AD7390

VDD = 3.0V
T

A

= 55C, +25C, +85C

SUPERIMPOSED

Figure 1. Differential Nonlinearity Error vs. Code

AD7390

VDD = 3.0V
V

REF

= 2.5V

+25C, +85C

CODE – Decimal

0 4096512 1024 1536 2048 2560 3072 2584

2.0

2.0

INL – LSB

1.5

0.0

0.5

1.0

1.5

1.0

0.5

55C

Figure 2. INL Error vs. Code and Temperature

REV. A

–2–

AD7390/AD7391–SPECIFICATIONS

Parameter Symbol Conditions 3 V  10% 5 V  10% Unit

STATIC PERFORMANCE

Resolution

1

N 12 12 Bits

Relative Accuracy

2

INL TA = 25°C ±1.6 ±1.6 LSB max
INL T

A

= 40°C, 85°C ±2.0 ±2 LSB max

Differential Nonlinearity

2

DNL TA = 25°C, Monotonic ±0.9 ±0.9 LSB max
DNL Monotonic ±1 ±1 LSB max

Zero-Scale Error V

ZSE

Data = 000

H

4.0 4.0 mV max

Full-Scale Voltage Error V

FSE

TA = 25°C, 85°C, Data = FFF

H

±8 ±8mV max

V

FSE

TA = 40°C, Data = FFF

H

±20 ±20 mV max

Full-Scale Tempco

3

TCV

FS

16 16 ppm/°C typ

REFERENCE INPUT

V

REF IN

Range V

REF

0/V

DD

0/V

DD

V min/max

Input Resistance R

REF

2.5 2.5 MΩ typ

4

Input Capacitance

3

C

REF

5 5 pF typ

ANALOG OUTPUT

Output Current (Source) I

OUT

Data = 800H, ∆V

OUT

= 5 LSB 1 1 mA typ

Output Current (Sink) I

OUT

Data = 800H, ∆V

OUT

= 5 LSB 3 3 mA typ

Capacitive Load

3

C

L

No Oscillation 100 100 pF typ

LOGIC INPUTS

Logic Input Low Voltage V

IL

0.5 0.8 V max

Logic Input High Voltage V

IH

V

DD

 0.6 V

DD

 0.6 V min

Input Leakage Current I

IL

10 10 µA max

Input Capacitance

3

C

IL

10 10 pF max

INTERFACE TIMING

3, 5

Clock Width High t

CH

50 30 ns min

Clock Width Low t

CL

50 30 ns min

Load Pulsewidth t

LDW

30 20 ns min

Data Setup t

DS

10 10 ns min

Data Hold t

DH

30 15 ns min

Clear Pulsewidth t

CLRW

15 15 ns min

Load Setup t

LD1

30 15 ns min

Load Hold t

LD2

40 20 ns min

AC CHARACTERISTICS

6

Output Slew Rate SR Data = 000H to FFFH to 000

H

0.05 0.05 V/µs typ

Settling Time t

S

To 0.1% of Full Scale 70 60 µs typ

DAC Glitch Q Code 7FF

H

to 800H to 7FF

H

65 65 nVs typ
Digital Feedthrough Q 15 15 nVs typ
Feedthrough V

OUT/VREFVREF

= 1.5 VDC  1 V p-p

,

63 63 dB typ

Data = 000H, f = 100 kHz

SUPPLY CHARACTERISTICS

Power Supply Range V

DD RANGE

DNL < ±1 LSB 2.7/5.5 2.7/5.5 V min/max

Positive Supply Current I

DD

VIL = 0 V, No Load, TA = 25°C55 55 µA typ

I

DD

VIL = 0 V, No Load 100 100 µA max

Power Dissipation P

DISS

VIL = 0 V, No Load 300 500 µW max

Power Supply Sensitivity PSS ∆VDD = ±5% 0.006 0.006 %/% max

NOTES

1

One LSB = V

REF

/4096 V for the 12-bit AD7390.

2

The first two codes (000H, 001H) are excluded from the linearity error measurement.

3

These parameters are guaranteed by design and not subject to production testing.

4

Typicals represent average readings measured at 25°C.

5

All input control signals are specified with

t

R

=

t

F

= 2 ns (10% to 90% of 3 V) and timed from a voltage level of 1.6 V.

6

The settling time specification does not apply for negative going transitions within the last 3 LSBs of ground.

Specifications subject to change without notice.

AD7390 ELECTRICAL CHARACTERISTICS

(@ V

REF IN

= 2.5 V, –40C < TA < +85C unless otherwise noted.)

REV. A

–3–

AD7390/AD7391

AD7391 ELECTRICAL CHARACTERISTICS

Parameter Symbol Conditions 3 V  10% 5 V  10% Unit

STATIC PERFORMANCE

Resolution

1

N 10 10 Bits

Relative Accuracy

2

INL TA = 25°C ±1.75 ±1.75 LSB max
INL T

A

= 40°C, 85°C, 125°C ±2.0 ±2.0 LSB max

INL T

A

= 55°C, S Grade ± 3 LSB max

Differential Nonlinearity

2

DNL Monotonic ±0.9 ±0.9 LSB max
DNL T

A

= 55°C, S Grade ± 2 LSB max

Zero-Scale Error V

ZSE

Data = 000

H

9.0 9.0 mV max

V

ZSE

TA = 55°C, S Grade 20 mV max

Full-Scale Error V

FSE

TA = 25°C, 85°C, 125°C, ±32 ±32 mV max
Data = 3FF

H

V

FSE

TA = 55°C, S Grade ± 55 mV max

Full-Scale Tempco

3

TCV

FS

16 16 ppm/°C typ

TCV

FS

TA = 55°C, S Grade 32 ppm/°C typ

REFERENCE INPUT

V

REF IN

Range V

REF

0/V

DD

0/V

DD

V min/max

Input Resistance R

REF

2.5 2.5 MΩ typ

4

Input Capacitance

3

C

REF

5 5 pF typ

ANALOG OUTPUT

Output Current (Source) I

OUT

Data = 800H, ∆V

OUT

= 5 LSB 1 1 mA typ

Output Current (Sink) I

OUT

Data = 800H, ∆V

OUT

= 5 LSB 3 3 mA typ

Capacitive Load

3

C

L

No Oscillation 100 100 pF typ

LOGIC INPUTS

Logic Input Low Voltage V

IL

0.5 0.8 V max

Logic Input High Voltage V

IH

V

DD

 0.6 V

DD

 0.6 V min

Input Leakage Current I

IL

10 10 µA max

Input Capacitance

3

C

IL

10 10 pF max

INTERFACE TIMING

3, 5

Clock Width High t

CH

50 30 ns

Clock Width Low t

CL

50 30 ns

Load Pulsewidth t

LDW

30 20 ns

Data Setup t

DS

10 10 ns

Data Hold t

DH

30 15 ns

Clear Pulsewidth t

CLRW

15 15 ns

Load Setup t

LD1

30 15 ns

Load Hold t

LD2

40 20 ns

AC CHARACTERISTICS

6

Output Slew Rate SR Data = 000H to 3FFH to 000

H

0.05 0.05 V/µs typ

Settling Time t

S

To 0.1% of Full Scale 70 60 µs typ

t

S

TA = –55°C, S Grade 100 µs typ

DAC Glitch Q Code 7FF

H

to 800H to 7FF

H

65 65 nVs typ
Digital Feedthrough Q 15 15 nVs typ
Feedthrough V

OUT/VREFVREF

= 1.5 VDC 1 V p-p, 63 63 dB typ

Data = 000H, f = 100 kHz

SUPPLY CHARACTERISTICS

Power Supply Range V

DD RANGE

DNL < ±1 LSB 2.7/5.5 2.7/5.5 V min/max

Positive Supply Current I

DD

VIL = 0 V, No Load, TA = 25°C55 55 µA typ

I

DD

VIL = 0 V, No Load 100 100 µA max

Power Dissipation P

DISS

VIL = 0 V, No Load 300 500 µW max

Power Supply Sensitivity PSS ∆VDD = ±5% 0.006 0.006 %/% max

NOTES

1

One LSB = V

REF

/1024 V for the 10-bit AD7391.

2

The first two codes (000H, 001H) are excluded from the linearity error measurement.

3

These parameters are guaranteed by design and not subject to production testing.

4

Typicals represent average readings measured at 25°C.

5

All input control signals are specified with tR = tF = 2 ns (10% to 90% of 3 V) and timed from a voltage level of 1.6 V.

6

The settling time specification does not apply for negative going transitions within the last 3 LSBs of ground.

Specifications subject to change without notice.

(@ V

REF IN

= 2.5 V, 40C < TA < 85C unless otherwise noted.)

REV. A

AD7390/AD7391

–4–

PIN DESCRIPTIONS

Pin No. Name Function

1 LD Load Strobe. Transfers shift register

data to DAC register while active low.
See truth table for operation.

2 CLK Clock Input. Positive edge clocks data

into shift register.

3 SDI Serial Data Input. Data loads directly

into the shift register.

4 CLR Resets DAC register to zero condition.

Active low input.
5 GND Analog and Digital Ground.
6V

OUT

DAC Voltage Output. Full-scale output

1 LSB less than reference input voltage REF.
7V

DD

Positive Power Supply Input. Specified

range of operation 2.7 V to 5.5 V.
8V

REF

DAC Reference Input Pin. Establishes

DAC full-scale voltage.

ABSOLUTE MAXIMUM RATINGS*

VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V, 8 V

V

REF

to GND . . . . . . . . . . . . . . . . . . . . . . 0.3 V, V

DD

 0.3 V

Logic Inputs to GND . . . . . . . . . . . . . . . . . . . . .0.3 V, 8 V

V

OUT

to GND . . . . . . . . . . . . . . . . . . . . 0.3 V, V

DD

 0.3 V
I

OUT

Short Circuit to GND . . . . . . . . . . . . . . . . . . . . . . 50 mA

Package Power Dissipation . . . . . . . . . . . . . (T

J MAX

 TA)/θ

JA

Thermal Resistance θ

JA

8-Lead Plastic DIP Package (N-8) . . . . . . . . . . . . . 103°C/W

8-Lead SOIC Package (SO-8) . . . . . . . . . . . . . . . . 158°C/W

TSSOP-8 Package (RU-8) . . . . . . . . . . . . . . . . . . . 240°C/W

Maximum Junction Temperature (T

J MAX

) . . . . . . . . . . 150°C

Operating Temperature Range . . . . . . . . . . 40°C to  85°C

AD7391AR . . . . . . . . . . . . . . . . . . . . . . . . 40°C to 125°C

Storage Temperature Range . . . . . . . . . . . 65°C to 150°C

Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . . . 300°C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
specification is not implied. Exposure to the above maximum rating conditions for
extended periods may affect device reliability.

DAC

REGISTER

RESET

LOAD

CLK

12-BIT AD7390*

SHIFT REGISTER

D

CLR

LD

CLK

SDI

12

*AD7391 HAS A 10-BIT SHIFT REGISTER

Figure 3. Digital Control Logic

PIN CONFIGURATIONS

TOP VIEW

(Not to
Scale)

1

2

3

4

8

7

6

5

TOP VIEW

(Not to Scale)

8

7

6

5

1

2

3

4

TOP VIEW

(Not to Scale)

8

7

6

5

1

2

3

4

LD

CLK

CLR

SDI

GND

V

REF

V

DD

V

OUT

TSSOP-8

SO-8

P-DIP-8

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD7390/AD7391 features proprietary ESD protection circuitry, permanent damage may occur
on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions
are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

ORDERING GUIDE

1

Temperature Package Package Top Number of Devices

Model Resolution Range Description Option Mark

2

Per Container

AD7390AN 12 40°C to  85°C 8-Lead P-DIP N-8 AD7390

2

50

AD7390AR 12 40°C to  85°C 8-Lead SOIC SO-8 AD7390

3

196

AD7390AR-REEL7 12 40°C to  85°C 8-Lead SOIC SO-8 AD7390

3

1000

AD7391AN 10 40°C to  85°C 8-Lead P-DIP N-8 AD7391

2

50

AD7391AR 10 40°C to  125°C 8-Lead SOIC SO-8 AD7391

3

196

AD7391SR 10 55°C to  125°C 8-Lead SOIC SO-8 AD7391

3

39

AD7391ARU-REEL 10 40°C to  85° C TSSOP-8 RU-8 AD7391A42500

NOTES

1

The AD7390 contains 588 transistors. The die size measures 70 mm  68 mm.

2

Line 1 contains ADI logo symbol and part number. Line 2 contains grade and date code YWW. Line 3 contains the letter G plus the 4-digit lot number.

3

Line 1 contains part number. Line 2 contains grade and date code YWW. Line 3 contains the letter G plus the 4-digit lot number and the ADI logo symbol.

4

Line 1 contains the date code YWW. Line 2 contains the 4-digit part number plus grade.

REV. A

AD7390/AD7391

–5–

DAC REGISTER LOAD

CLK

CLR

LD

CLK

SDI

AD7391AD7390

t

LD1

D11

t

LD1

D10 D9 D7 D5 D4 D3 D2 D1 D0

t

LD2

t

DS

t

DH

t

CL

t

CH

t

LDW

t

S

t

CLRW

t

S

0.1% FS

ERROR BAND

SDI

LD

FS

ZS

V

OUT

Figure 4. Timing Diagram

Table I. Control-Logic Truth Table

CLK CLR LD Serial Shift Register Function DAC Register Function

↑ H H Shift-Register-Data Advanced One-Bit Latched
X H L Disables Updated with Current Shift Register Contents
X L X No Effect Loaded with all Zeros
X ↑ H No Effect Latched with all Zeros
X ↑ L Disabled Previous SR Contents Loaded (Avoid usage of CLR

when LD is logic low, since SR data could be corrupted
if a clock edge takes place, while CLR returns high.)

↑ = Positive logic transition.
X = Don’t care.

Table II. AD7390 Serial Input Register Data Format, Data is Loaded in the MSB-First Format

MSB LSB

B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

AD7390 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Table III. AD7391 Serial Input Register Data Format, Data is Loaded in the MSB-First Format

MSB LSB

B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

AD7391 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

REV. A

AD7390/AD7391–Typical Performance Characteristics

–6–

TOTAL UNADJUSTED ERROR – LSB

FREQUENCY

25

0

5.0

10

5

20

15

5.8 6.6 7.3 8.1 8.9 9.7 10.5 11.212.0

SS = 100 UNITS
T

A

= 25C

V

DD

= 2.7V

V

REF

= 2.5V

TPC 1. AD7390 Total Unadjusted
Error Histogram

FREQUENCY – Hz

OUTPUT VOLTAGE NOISE – V

Hz

10

8

0

1 10 100k

100 1k 10k

6

4

2

12

14

16

VDD = 5V
V

REF

= 2.5V

T

A

= 25C

TPC 4. AD7390 Voltage Noise
Density vs. Frequency

TEMPERATURE – C

SUPPLY CURRENT – A

100

20

55 35 125

15 5 25 65 85 10545

90

60

50

40

30

80

70

SAMPLE SIZE = 300 UNITS

VDD = 5.0V, V

LOGIC

= 0V

VDD = 3.0V, V

LOGIC

= 0V

VDD = 3.6V, V

LOGIC

= 2.4V

TPC 7. AD7390 Supply Current
vs. Temperature

TOTAL UNADJUSTED ERROR – LSB

FREQUENCY

100

0

–10

40

20

80

60

–3.3 3.3 10 16 23 30 36 43 50

SS = 300 UNITS
T

A

= 25C

V

DD

= 2.7V

V

REF

= 2.5V

90

70

50

30

10

TPC 2. AD7391 Total Unadjusted
Error Histogram

VIN – V

0.0 0.5 3.0

1.0 1.5 2.0 2.5

SUPPLY CURRENT – A

100

95

50

70

65

60

55

90

75

80

85

V

LOGIC

FROM

3.0V TO 0V

V

LOGIC

FROM

0V TO 3.0V

T

A

= 25C

V

DD

= 3.0V

TPC 5. AD7390 Supply Current vs.
Logic Input Voltage

CLOCK FREQUENCY – Hz

SUPPLY CURRENT – A

1000

800

0

1k 10k 10M

100k 1M

600

400

200

a. VDD = 5.5V, CODE = 155

H

b. VDD = 5.5V, CODE = 3FF

H

c. VDD = 2.7V, CODE = 155

H

d

. VDD = 2.7V, CODE = 355

H

a

b

c

d

V

LOGIC

= 0V TO VDD TO 0V

V

REF

= 2.5V

T

A

= 25C

TPC 8. AD7391 Supply Current
vs. Clock Frequency

FULL-SCALE TEMPCO – ppm/ C

FREQUENCY

0

–33

12

6

24

18

–30 –26 –23 –20 –16 –13 –10 –6 –3300

SS = 100 UNITS
TA = 40C TO +85C

V

DD

= 2.7V

V

REF

= 2.5V

TPC 3. AD7391 Full-Scale Output
Tempco Histogram

SUPPLY VOLTAGE – V

12 7

34 56

THRESHOLD VOLTAGE – V

5.0

4.5

0.0

2.0

1.5

1.0

0.5

4.0

2.5

3.0

3.5

V

LOGIC

FROM

HIGH TO LOW

V

LOGIC

FROM

LOW TO HIGH

CODE = FFF

H

V

REF

= 2V

RS LOGIC VOLTAGE
VARIED

TPC 6. AD7390 Logic Threshold
vs. Supply Voltage

FREQUENCY – Hz

PSRR – dB

60

50

0

10 100 10k

1k

30

20

10

40

VDD = 3V  5%

VDD = 5V  5%

TA = 25C

TPC 9. Power Supply Rejection
vs. Frequency

REV. A

–7–

AD7390/AD7391

V

OUT

– V

I

OUT

– mA

40

30

0

01 5

23 4

20

10

VDD = 5V
V

REF

= 3V

CODE = ØØØ

H

TPC 10. I

OUT

at Zero Scale vs. V

OUT

100s

1V

TIME – 100s/DIV

V

OUT

(1V/DIV)

LD

(5V/DIV)

VDD = 5V
V

REF

= 2.5V

f

CLK

= 50kHz

TPC 13. AD7390 Large Signal
Settling Time

HOURS OF OPERATION AT 150C

NOMINAL CHANGE IN VOLTAGE – mV

1.2

0.0
0 100 600

200 300 400 500

1.0

0.8

0.6

0.4

0.2

SAMPLE SIZE = 50

CODE = FFF

H

CODE = 000

H

TPC 16. AD7390 Long-Term Drift
Accelerated by Burn-In

2s

20mV

VDD = 5V
V

REF

= 2.5V

f

CLK

= 50kHz

CODE: 7F

H

to 80

H

TIME – 2s/DIV

V

OUT

(5mV/DIV)

LD

(5V/DIV)

TPC 11. AD7390 Midscale Transi­tion Performance

FREQUENCY – Hz

GAIN – dB

100 1k 100k10k

0

–5

VDD = 5V
V

REF

= 50mV  2V dc

DATA = FFF

H

5

10

–10

–15

–20

–25

–30

–35

–40

TPC 14. AD7390 Gain vs.
Frequency

5s

5mV

VDD = 5V
V

REF

= 2.5V

f

CLK

= 50kHz

LD = HIGH

TIME – 5s/DIV

V

OUT

(5mV/DIV)

CLK

(5V/DIV)

TPC 12. Digital Feedthrough

REFERENCE VOLTAGE – V

05

1324

INTEGRAL NONLINEARITY – LSB

2.0

1.8

0.0

0.8

0.6

0.4

0.2

1.6

1.0

1.2

1.4

VDD = 5V

CODE = 768

H

TA = 25C

TPC 15. AD7390 INL Error vs.
Reference Voltage

REV. A

AD7390/AD7391

–8–

OPERATION

The AD7390 and AD7391 are a set of pin compatible, 12-bit/
10-bit digital-to-analog converters. These single-supply opera­tion devices consume less than 100 microamps of current while
operating from power supplies in the 2.7 V to 5.5 V range mak­ing them ideal for battery operated applications. They contain a
voltage-switched, 12-bit/10-bit, laser-trimmed digital-to-analog
converter, rail-to-rail output op amps, serial-input register, and
a DAC register. The external reference input has constant input
resistance independent of the digital code setting of the DAC.
In addition, the reference input can be tied to the same supply
voltage as VDD resulting in a maximum output voltage span of
0 to VDD. The SPI compatible, serial-data interface consists of
a serial data input (SDI), clock (CLK), and load (LD) pins.
A CLR pin is available to reset the DAC register to zero-scale.
This function is useful for power-on reset or system failure
recovery to a known state.

D/A CONVERTER SECTION

The voltage switched R-2R DAC generates an output voltage
dependent on the external reference voltage connected to the
V

REF

pin according to the following equation:

VV

D

OUT REF

N

=×

2

(1)

where D is the decimal data word loaded into the DAC register,
and N is the number of bits of DAC resolution. In the case of the
10-bit AD7391 using a 2.5 V reference, Equation 1 simplifies to:

V

D

OUT

=×25

1024

.

(2)

Using Equation 2 the nominal midscale voltage at V

OUT

is

1.25 V for D = 512; full-scale voltage is 2.497 V. The LSB step
size is = 2.5  1/1024 = 0.0024 V.

For the 12-bit AD7390 operating from a 5.0 V reference
Equation 1 becomes:

V

D

OUT

=×50

4096

.

(3)

Using Equation 3 the AD7390 provides a nominal midscale
voltage of 2.5 V for D = 2048, and a full-scale output of 4.998 V.
The LSB step size is = 5.0  1/4096 = 0.0012 V.

AMPLIFIER SECTION

The internal DAC’s output is buffered by a low power con­sumption precision amplifier. The op amp has a 60 µs typical
settling time to 0.1% of full scale. There are slight differences in
settling time for negative slewing signals versus positive. Also,
negative transition settling time to within the last 6 LSBs of zero
volts has an extended settling time. The rail-to-rail output stage
of this amplifier has been designed to provide precision perfor­mance while operating near either power supply. Figure 5
shows an equivalent output schematic of the rail-to-rail ampli­fier with its N-channel pull-down FETs that will pull an output
load directly to GND. The output sourcing current is provided
by a P-channel pull-up device that can source current to GND
terminated loads.

AGND

V

OUT

V

DD

P-CH

N-CH

Figure 5. Equivalent Analog Output Circuit

The rail-to-rail output stage provides ±1 mA of output current.
The N-channel output pull-down MOSFET shown in Figure 5
has a 35 Ω ON resistance, which sets the sink current capability
near ground. In addition to resistive load driving capability, the
amplifier has also been carefully designed and characterized for
up to 100 pF capacitive load driving capability.

REFERENCE INPUT

The reference input terminal has a constant input-resistance
independent of digital code which results in reduced glitches on
the external reference voltage source. The high 2 MΩ input­resistance minimizes power dissipation within the AD7390/
AD7391 D/A converters. The V

REF

input accepts input voltages

ranging from ground to the positive-supply voltage V

DD

. One of
the simplest applications which saves an external reference
voltage source is connection of the V

REF

terminal to the positive

V

DD

supply. This connection results in a rail-to-rail voltage
output span maximizing the programmed range. The reference
input will accept ac signals as long as they are kept within the
supply voltage range, 0 < V

REF IN

< VDD. The reference band­width and integral nonlinearity error performance are plotted in
the typical performance section (see TPCs 14 and 15). The
ratiometric reference feature makes the AD7390/AD7391 an
ideal companion to ratiometric analog-to-digital converters such
as the AD7896.

POWER SUPPLY

The very low power consumption of the AD7390/AD7391 is a
direct result of a circuit design optimizing the use of a CBCMOS
process. By using the low power characteristics of CMOS for the
logic, and the low noise, tight-matching of the complementary
bipolar transistors, excellent analog accuracy is achieved. One
advantage of the rail-to-rail output amplifiers used in the AD7390/
AD7391 is the wide range of usable supply voltage. The part is
fully specified and tested for operation from 2.7 V to 5.5 V.

POWER SUPPLY BYPASSING AND GROUNDING

Precision analog products, such as the AD7390/AD7391, require
a well filtered power source. Since the AD7390/AD7391 operates
from a single 3 V to 5 V supply, it seems convenient to simply tap
into the digital logic power supply. Unfortunately, the logic sup­ply is often a switch-mode design, which generates noise in the
20 kHz to 1 MHz range. In addition, fast logic gates can generate
glitches hundred of millivolts in amplitude due to wiring resis­tance and inductance. The power supply noise generated thereby
means that special care must be taken to assure that the inherent
precision of the DAC is maintained. Good engineering judgment
should be exercised when addressing the power supply ground­ing and bypassing of the AD7390.

REV. A

AD7390/AD7391

–9–

The AD7390 should be powered directly from the system
power supply. This arrangement, shown in Figure 6, employs an
LC filter and separate power and ground connections to isolate
the analog section from the logic switching transients.

FERRITE BEAD:
TWO TURNS, FAIR-RITE
#2677006301

TTL/CMOS

LOGIC

CIRCUITS

5V

POWER SUPPLY

100F
ELECT.

10F–22F
TANTALUM

0.1F
CERAMIC
CAPACITOR

5V

5V
RETURN

Figure 6. Use Separate Traces to Reduce Power
Supply Noise

Whether or not a separate power supply trace is available, how­ever, generous supply bypassing will reduce supply-line induced
errors. Local supply bypassing consisting of a 10 µF tantalum
electrolytic in parallel with a 0.1 µF ceramic capacitor is recom-
mended in all applications (Figure 7).

AD7390

OR

AD7391

0.1F

CLK

V

OUT

REF

V

DD

GND

C

*

10F

6

78

5

1
2
3
4

SDI

CLR

LD

*OPTIONAL EXTERNAL
REFERENCE BYPASS

2.7V TO 5.5V

Figure 7. Recommended Supply Bypassing

INPUT LOGIC LEVELS

All digital inputs are protected with a Zener-type ESD protection
structure (Figure 8) that allows logic input voltages to exceed the
V

DD

supply voltage. This feature can be useful if the user is driving
one or more of the digital inputs with a 5 V CMOS logic input­voltage level while operating the AD7390/AD7391 on a 3 V power
supply. If this mode of interface is used, make sure that the V

OL

of the 5 V CMOS meets the VIL input requirement of the AD7390/
AD7391 operating at 3 V. See TPC 6 for a graph for digital
logic input threshold versus operating V

DD

supply voltage.

LOGIC

IN

V

DD

GND

Figure 8. Equivalent Digital Input ESD Protection

In order to minimize power dissipation from input-logic levels

that

are near the V

IH

and VIL logic input voltage specifications,

a
Schmitt trigger design was used that minimizes the input-buffer
current consumption compared to traditional CMOS input
stages. TPC 5 shows a plot of incremental input voltage versus

supply current showing that negligible current consumption
takes place when logic levels are in their quiescent state. The
normal crossover current still occurs during logic transitions. A
secondary advantage of this Schmitt trigger is the prevention of
false triggers that would occur with slow moving logic transi­tions when a standard CMOS logic interface or opto isolators
are used. The logic inputs SDI, CLK, LD, CLR all contain the
Schmitt trigger circuits.

DIGITAL INTERFACE

The AD7390/AD7391 have a double-buffered serial data input.
The serial-input register is separate from the DAC register,
which allows preloading of a new data value into the serial regis­ter without disturbing the present DAC values. A functional
block diagram of the digital section is shown in Figure 4, while
Table I contains the truth table for the control logic inputs.
Three pins control the serial data input. Data at the Serial Data
Input (SDI) is clocked into the shift register on the rising edge
of CLK. Data is entered in MSB-first format. Twelve clock
pulses are required to load the 12-bit AD7390 DAC value. If
additional bits are clocked into the shift register, for example
when a microcontroller sends two 8-bit bytes, the MSBs are
ignored (Figure 9). The CLK pin is only enabled when Load
(LD) is high. The lower resolution 10-bit AD7391 contains a
10-bit shift register. The AD7391 is also loaded MSB first with
10 bits of data. Again if additional bits are clocked into the shift
register, only the last 10 bits clocked in are used.

The Load pin (LD) controls the flow of data from the shift
register to the DAC register. After a new value is clocked into
the serial-input register, it will be transferred to the DAC register
by the negative transition of the Load pin (LD).

BYTE 1 BYTE 0

MSB LSB

MSB

LSB

B15 B14 B13 B12 B11 B10 B9 B8

B7 B6 B5 B4 B3 B2 B1 B0

X X X X D11 D10 D9 D8

D7 D6 D5 D4 D3 D2 D1 D0

X X X X X X D9 D8

D7 D6 D5 D4 D3 D2 D1 D0

D11–D0: 12-BIT AD7390 DAC VALUE; D9–D0: 10-BIT AD7391 DAC VALUE
X = DON’T CARE
THE MSB OF BYTE 1 IS THE FIRST BIT THAT IS LOADED INTO THE DAC

Figure 9. Typical AD7390-Microprocessor Serial Data
Input Forms

RESET (CLR) PIN

Forcing the CLR pin low will set the DAC register to all zeros
and the DAC output voltage will be zero volts. The reset function
is useful for setting the DAC outputs to zero at power-up or
after a power supply interruption. Test systems and motor
controllers are two of many applications which benefit from
powering up to a known state. The external reset pulse can be
generated by the microprocessor’s power-on RESET signal, by
an output from the microprocessor, or by an external resistor
and capacitor. CLR has a Schmitt trigger input which results in
a clean reset function when using external resistor/capacitor
generated pulses. The CLR input overrides other logic inputs,
specifically LD. However, LD should be set high before CLR
goes high. If CLR is kept low, then the contents of the shift
register will be transferred to the DAC register as soon as CLR
returns high. See the Control-Logic Truth Table I.

REV. A

AD7390/AD7391

–10–

UNIPOLAR OUTPUT OPERATION

This is the basic mode of operation for the AD7390. As shown
in Figure 10, the AD7390 has been designed to drive loads as
low as 5 kΩ in parallel with 100 pF. The code table for this
operation is shown in Table IV.

AD7390

0.1F

CLK

V

OUT

REF

V

DD

GND

R

10F

6

7

5

1

2

3

4

SDI

CLR

LD

2.7V TO 5.5V

R

L

5k

C

L

100pF

C

RS

EXT
REF

0.01F

Figure 10. AD7390 Unipolar Output Operation

Table IV. AD7390 Unipolar Code Table

Hexadecimal Decimal Output
Number Number Voltage (V)
in DAC Register in DAC Register V

REF

= 2.5 V

FFF 4095 2.4994
801 2049 1.2506
800 2048 1.2500
7FF 2047 1.2494
000 0 0

The circuit can be configured with an external reference plus
power supply, or powered from a single dedicated regulator or
reference, depending on the application performance requirements.

BIPOLAR OUTPUT OPERATION

Although the AD7391 has been designed for single-supply opera­tion, the output can be easily configured for bipolar operation.
A typical circuit is shown in Figure 11. This circuit uses a clean
regulated 5 V supply for power, which also provides the circuit’s
reference voltage. Since the AD7391 output span swings from
ground to very near 5 V, it is necessary to choose an external
amplifier with a common-mode input voltage range that extends
to its positive supply rail. The micropower consumption OP196 has
been designed just for this purpose and results in only 50 micro­amps of maximum current consumption. Connection of the equally
valued 470 kΩ resistors results in a differential amplifier mode
of operation with a voltage gain of two, which results in a circuit
output span of ten volts, that is, 25 V to 15 V. As the DAC is
programmed with zero-code 000

H

to midscale 200H to full-scale

3FF

H

, the circuit output voltage VO is set at 25 V, 0 V and 15 V

(minus 1 LSB). The output voltage V

O

is coded in offset binary

according to Equation 4.

V

D

O

=

























×

512

15–

(4)

where D is the decimal code loaded in the AD7391 DAC register.
Note that the LSB step size is 10/1024 = 10 mV. This circuit has
been optimized for micropower consumption including the 470 kΩ

gain setting resistors, which should have low temperature coeffi­cients to maintain accuracy and matching (preferably the same
material, such as metal film). If better stability is required, the power
supply could be substituted with a precision reference voltage such
as the low dropout REF195, which can easily supply the circuit’s
162 µA of current, and still provide additional power for the
load connected to V

O

. The micropower REF195 is guaranteed

to source 10 mA output drive current, but only consumes 50 µA
internally. If higher resolution is required, the AD7390 can be
used with the addition of two more bits of data inserted into the
software coding, which would result in a 2.5 mV LSB step size.
Table V shows examples of nominal output voltages V

O

provided

by the Bipolar Operation circuit application.

C

ISY < 162A

BIPOLAR
OUTPUT
SWING

V

O

+5V

–5V

–5V

V

OUT

AD7391

V

DD

REF

GND

+5V

< 100A

470k 470k

< 50A

OP196

DIGITAL INTERFACE CIRCUITRY OMITTED FOR CLARITY

Figure 11. Bipolar Output Operation

Table V. Bipolar Code Table

Hexadecimal Decimal Analog
Number Number Output
in DAC Register in DAC Register Voltage (V)

3FF 1023 4.9902
201 513 0.0097
200 512 0.0000
1FF 511 –0.0097
000 0 –5.0000

MICROCOMPUTER INTERFACES

The AD7390 serial data input provides an easy interface to a
variety of single-chip microcomputers (µCs). Many µCs have a
built-in serial data capability which can be used for communi­cating with the DAC. In cases where no serial port is provided,
or it is being used for some other purpose (such as an RS-232
communications interface), the AD7390/AD7391 can easily be
addressed in software.

Twelve data bits are required to load a value into the AD7390.
If more than 12 bits are transmitted before the load LD input
goes high, the extra (i.e., the most-significant) bits are ignored.
This feature is valuable because most µCs only transmit data
in 8-bit increments. Thus, the µC sends 16 bits to the DAC
instead of 12 bits. The AD7390 will only respond to the last
12 bits clocked into the SDI input, however, so the serial-data
interface is not affected.

Ten data bits are required to load a value into the AD7391. If
more than 10 bits are transmitted before load LD returns high,
the extra bits are ignored.

REV. A

AD7390/AD7391

–11–

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

8-Lead SOIC

(R-8)

0.0098 (0.25)

0.0075 (0.19)

0.0500 (1.27)

0.0160 (0.41)

8
0

0.0196 (0.50)

0.0099 (0.25)

 45

85

41

0.1968 (5.00)

0.1890 (4.80)

0.2440 (6.20)

0.2284 (5.80)

PIN 1

0.1574 (4.00)

0.1497 (3.80)

0.0500 (1.27)
BSC

0.0688 (1.75)

0.0532 (1.35)

SEATING

PLANE

0.0098 (0.25)

0.0040 (0.10)

0.0192 (0.49)

0.0138 (0.35)

8-Lead Plastic DIP

(N-8)

SEATING
PLANE

0.060 (1.52)

0.015 (0.38)

0.210

(5.33)

MAX

0.022 (0.558)

0.014 (0.356)

0.160 (4.06)

0.115 (2.93)

0.070 (1.77)

0.045 (1.15)

0.130
(3.30)
MIN

8

1

4

5

PIN 1

0.280 (7.11)

0.240 (6.10)

0.100 (2.54)
BSC

0.430 (10.92)

0.348 (8.84)

0.195 (4.95)

0.115 (2.93)

0.015 (0.381)

0.008 (0.204)

0.325 (8.25)

0.300 (7.62)

8-Lead TSSOP

(RU-8)

8

5

41

0.256 (6.50)

0.246 (6.25)

0.177 (4.50)

0.169 (4.30)

PIN 1

0.0256 (0.65)
BSC

0.122 (3.10)

0.114 (2.90)

SEATING

PLANE

0.006 (0.15)

0.002 (0.05)

0.0118 (0.30)

0.0075 (0.19)

0.0433
(1.10)
MAX

0.0079 (0.20)

0.0035 (0.090)

0.028 (0.70)

0.020 (0.50)

8
0

REV. A

–12–

C01120–0–2/02(A)

PRINTED IN U.S.A.

AD7390/AD7391

Revision History

Location Page

Data Sheet changed from REV. 0 to REV. A.

Edits to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Edits to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Edit to Figure 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Edit to TPC 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7