Page 1
+3 Volt Serial-Input
a
Micropower 10-Bit & 12-Bit DACs
FEATURES
Micropower—100 mA
Single-Supply—12.7 to 15.5 V Operation
Compact 1.75 mm Height SO-8 Package
& 1.1 mm Height TSSOP-8
AD7390—12-Bit Resolution
AD7391—10-Bit Resolution
SPI & QSPI Serial Interface Compatible with Schmitt
Trigger Inputs
APPLICATIONS
Automotive 0.5 V to 4.5 V Output Span Voltage
Portable Communications
Digitally Controlled Calibration
GENERAL DESCRIPTION
The AD7390/AD7391 family of 10-bit & 12-bit voltage-output
digital-to-analog converters is designed to operate from a single
13 V supply. Built using a CBCMOS process, these monolithic
DACs offer the user low cost, and ease-of-use in single-supply
13 V systems. Operation is guaranteed over the supply voltage
range of 12.7 V to 15.5 V consuming less than 100 µA making
this device ideal for battery operated applications.
The full-scale voltage output is determined by the external reference input voltage applied. The rail-to-rail REF
to DAC
IN
OUT
allows for a full-scale voltage set equal to the positive supply
or any value in between.
V
DD
AD7390/AD7391
FUNCTIONAL DIAGRAM
AD7390
REF
CLR
LD
EN
CLK
SDI
12-BIT DAC
12
DAC REGISTER
12
SERIAL REGISTER
A doubled-buffered serial-data interface offers high speed,
three-wire, SPI and microcontroller compatible inputs using
data in (SDI), clock (CLK) and load strobe (
tionally, a
CLR input sets the output to zero scale at power on
or upon user demand.
Both parts are offered in the same pinout to allow users to select
the amount of resolution appropriate for their application without circuit card redesign.
The AD7390/AD7391 are specified over the extended industrial
(240°C to 185°C) temperature range. The AD7391AR is
specified for the 240°C to 1125°C automotive temperature
range. The AD7390/AD7391s are available in plastic DIP, and
low profile 1.75 mm height SO-8 surface mount packages. The
AD7391ARU is available for ultracompact applications in a thin
1.1 mm TSSOP-8 package.
V
DD
V
OUT
GND
LD) pins. Addi-
1.00
0.75
0.50
0.25
0.00
DNL – LSB
0.25
0.50
0.75
1.00
0 4096512
AD7390
TA = 55 C, 25 C, 85 C
SUPERIMPOSED
1024 1536 2048 2560 3072 3584
CODE – Decimal
VDD = +3.0V
Figure 1. Differential Nonlinearity Error vs. Code
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
2.0
AD7390
1.5
1.0
0.5
0.0
INL – LSB
20.5
21.0
21.5
22.0
0 4096512 1024 1536 2048 2560 3072 2584
258, 858C
2558
CODE – Decimal
VDD = +3.0V
= +2.5V
V
REF
Figure 2. INL Error vs. Code & Temperature
© Analog Devices, Inc., 1996
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700 Fax: 617/326-8703
Page 2
AD7390/AD7391–SPECIFICATIONS
AD7390 ELECTRICAL CHARACTERISTICS
(@ V
= 2.5 V, 2408C < TA < 1858C, unless otherwise noted)
REF IN
Parameter Symbol Conditions 3 V 6 10% 5 V 6 10% Units
STATIC PERFORMANCE
Resolution
Relative Accuracy
Relative Accuracy
Differential Nonlinearity
Differential Nonlinearity
Zero-Scale Error V
Full-Scale Voltage Error V
Full-Scale Voltage Error V
Full-Scale Tempco
1
2
2
2
2
3
N 12 12 Bits
INL T
INL T
DNL T
= 125°C 61.6 61.6 LSB max
A
= 240°C, 185°C 62.0 62 LSB max
A
= 125°C, Monotonic 60.9 60.9 LSB max
A
DNL Monotonic 61 61 LSB max
ZSE
FSE
FSE
TCV
FS
Data = 000
T
= 125°C, 185°C, Data = FFF
A
T
= 240°C, Data = FFF
A
H
H
4.0 4.0 mV max
68 68 mV max
H
620 620 mV max
16 16 ppm/°C typ
REFERENCE INPUT
V
Range V
REF IN
Input Resistance R
Input Capacitance
3
REF
REF
C
REF
0/V
DD
0/V
DD
V min/max
2.5 2.5 MΩ typ
5 5 pF typ
ANALOG OUTPUT
Output Current (Source) I
Output Current (Sink) I
Capacitive Load
3
OUT
OUT
C
Data = 800
Data = 800
L
No Oscillation 100 100 pF typ
H
H
, ∆V
, ∆V
= 5 LSB 1 1 mA typ
OUT
= 5 LSB 3 3 mA typ
OUT
LOGIC INPUTS
Logic Input Low Voltage V
Logic Input High Voltage V
Input Leakage Current I
Input Capacitance
INTERFACE TIMING
3
3, 5
Clock Width High t
Clock Width Low t
Load Pulse Width t
Data Setup t
Data Hold t
Clear Pulse Width t
Load Setup t
Load Hold t
AC CHARACTERISTICS
6
IL
IH
IL
C
IL
CH
CL
LDW
DS
DH
CLRW
LD1
LD2
Output Slew Rate SR Data = 000H to FFFH to 000
Settling Time t
S
DAC Glitch Q Code 7FF
To 60.1% of Full Scale 70 60 µs typ
to 800H to 7FF
H
H
H
0.5 0.8 V max
VDD20.6 VDD20.6 V min
10 10 µA max
10 10 pF max
50 30 ns min
50 30 ns min
30 20 ns min
10 10 ns min
30 15 ns min
15 15 ns min
30 15 ns min
40 20 ns min
0.05 0.05 V/µs typ
65 65 nVs typ
Digital Feedthrough Q 15 15 nVs typ
Feedthrough V
OUT/VREFVREF
= 1.5 VDC 11 V p-p
,
263 263 dB typ
Data = 000H, f = 100 kHz
4
SUPPLY CHARACTERISTICS
Power Supply Range V
Positive Supply Current I
Positive Supply Current I
Power Dissipation P
DD RANGE
DD
DD
DISS
Power Supply Sensitivity PSS ∆V
NOTES
1
One LSB = V
2
The first two codes (000H, 001H) are excluded from the linearity error measurement.
3
These parameters are guaranteed by design and not subject to production testing.
4
Typicals represent average readings measured at 25°C.
5
All input control signals are specified with
6
The settling time specification does not apply for negative going transitions within the last 3 LSBs of ground.
Specifications subject to change without notice.
/4096 V for the 12-bit AD7390.
REF
t
=
t
= 2 ns (10% to 90% of 13 V) and timed from a voltage level of 1.6 V.
R
F
DNL < 61 LSB 2.7/5.5 2.7/5.5 V min/max
VIL = 0 V, No Load, T
V
= 0 V, No Load 100 100 µA max
IL
V
= 0 V, No Load 300 500 µW max
IL
= 65% 0.003 0.006 %/% max
DD
= 125°C55 55 µA typ
A
REV. 0–2–
Page 3
SPECIFICATIONS
AD7390/AD7391
AD7391 ELECTRICAL CHARACTERISTICS
(@ V
= 2.5 V, 2408C < TA < 1858C, unless otherwise noted)
REF IN
Parameter Symbol Conditions 3 V 6 10% 5 V 6 10% Units
STATIC PERFORMANCE
Resolution
Relative Accuracy
Relative Accuracy
Differential Nonlinearity
Zero-Scale Error V
Full-Scale Voltage Error V
Full-Scale Voltage Error V
Full-Scale Tempco
1
2
2
2
3
N 10 10 Bits
INL T
INL T
= 125°C 61.75 61.75 LSB max
A
= 240°C, 185°C, 1125°C 62.0 62.0 LSB max
A
DNL Monotonic 60.9 60.9 LSB max
ZSE
FSE
FSE
TCV
FS
Data = 000
T
= 125°C, 185°C, 1125°C, 632 632 mV max
A
Data = 3FF
T
= 240°C, Data = 3FF
A
H
H
H
9.0 9.0 mV max
635 635 mV max
16 16 ppm/°C typ
REFERENCE INPUT
Range V
V
REF IN
Input Resistance R
Input Capacitance
3
REF
REF
C
REF
0/V
DD
0/V
DD
V min/max
2.5 2.5 MΩ typ
5 5 pF typ
ANALOG OUTPUT
Output Current (Source) I
Output Current (Sink) I
Capacitive Load
3
OUT
OUT
C
Data = 800
Data = 800
L
No Oscillation 100 100 pF typ
H
H
, ∆V
, ∆V
= 5 LSB 1 1 mA typ
OUT
= 5 LSB 3 3 mA typ
OUT
LOGIC INPUTS
Logic Input Low Voltage V
Logic Input High Voltage V
Input Leakage Current I
Input Capacitance
INTERFACE TIMING
3
3, 5
Clock Width High t
Clock Width Low t
Load Pulse Width t
Data Setup t
Data Hold t
Clear Pulse Width t
Load Setup t
Load Hold t
AC CHARACTERISTICS
6
IL
IH
IL
C
IL
CH
CL
LDW
DS
DH
CLRW
LD1
LD2
Output Slew Rate SR Data = 000H to 3FFH to 000
Settling Time t
S
DAC Glitch Q Code 7FF
To 60.1% of Full Scale 70 60 µs typ
to 800H to 7FF
H
H
H
0.5 0.8 V min
VDD20.6 VDD20.6 V max
10 10 µA max
10 10 pF max
50 30 ns
50 30 ns
30 20 ns
10 10 ns
30 15 ns
15 15 ns
30 15 ns
40 20 ns
0.05 0.05 V/µs typ
65 65 nVs typ
Digital Feedthrough Q 15 15 nVs typ
Feedthrough V
OUT/VREFVREF
= 1.5 VDC 11 V p-p, 263 263 dB typ
Data = 000H, f = 100 kHz
4
SUPPLY CHARACTERISTICS
Power Supply Range V
Positive Supply Current I
Positive Supply Current I
Power Dissipation P
DD RANGE
DD
DD
DISS
Power Supply Sensitivity PSS ∆V
NOTES
1
One LSB = V
2
The first two codes (000H, 001H) are excluded from the linearity error measurement.
3
These parameters are guaranteed by design and not subject to production testing.
4
Typicals represent average readings measured at 25°C.
5
All input control signals are specified with tR = tF = 2 ns (10% to 90% of 13 V) and timed from a voltage level of 1.6 V.
6
The settling time specification does not apply for negative going transitions within the last 3 LSBs of ground.
Specifications subject to change without notice.
/1024 V for the 10-bit AD7391.
REF
DNL < 61 LSB 2.7/5.5 2.7/5.5 V min/max
VIL = 0 V, No Load, T
V
= 0 V, No Load 100 100 µA max
IL
V
= 0 V, No Load 300 500 µW max
IL
= 65% 0.003 0.006 %/% max
DD
= 125°C55 55 µA typ
A
REV. 0 –3–
Page 4
AD7390/AD7391
WARNING!
ESD SENSITIVE DEVICE
ABSOLUTE MAXIMUM RATINGS*
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . 20.3 V, 18 V
to GND . . . . . . . . . . . . . . . . . . . . . . . 0.3 V, V
V
REF
1 0.3 V
DD
Logic Inputs to GND . . . . . . . . . . . . . . . . . . . . .20.3 V, 18 V
to GND . . . . . . . . . . . . . . . . . . . . . 20.3 V, V
V
OUT
Short Circuit to GND . . . . . . . . . . . . . . . . . . . . . . 50 mA
I
OUT
Package Power Dissipation . . . . . . . . . . . . . . (T
Thermal Resistance θ
JA
J MAX
1 0.3 V
DD
2 T
)/θ
A
JA
8-Pin Plastic DIP Package (N-8) . . . . . . . . . . . . . . 103°C/W
8-Lead SOIC Package (SO-8) . . . . . . . . . . . . . . . . 158°C/W
TSSOP-8 Package (RU-8) . . . . . . . . . . . . . . . . . . . 240°C/W
Maximum Junction Temperature (T
) . . . . . . . . . . 150°C
J MAX
Operating Temperature Range . . . . . . . . . . . 240°C to 1 85°C
Storage Temperature Range . . . . . . . . . . . . 265°C to 1150°C
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . . 1300°C
NOTES
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational specification is not implied. Exposure to the above maximum rating
conditions for extended periods may affect device reliability.
ORDERING GUIDE
Package Package
Model Res Temp Description Option
AD7390AN 12 XIND 8-Pin P-DIP N-8
AD7390AR 12 XIND 8-Lead SOIC SO-8
AD7391AN 10 XIND 8-Pin P-DIP N-8
AD7391AR 10 AUTO 8-Lead SOIC SO-8
AD7391ARU 10 XIND TSSOP-8 RU-8
NOTES
XIND = 240°C to 185°C; AUTO = 240°C to 1125°C
The AD7390 contains 558 transistors. The die size measures 70 mil X 68 mil.
CLR
LD
CLK
SDI
RESET
REGISTER
LOAD
CLK
12-BIT AD7390*
SHIFT REGISTER
D
DAC
12
PIN CONFIGURATIONS
SO-8
TSSOP-8
1
TOP
2
VIEW
3
(Not to
Scale)
4
1
8
7
6
5
2
TOP VIEW
(Not to Scale)
3
4
8
7
6
5
P-DIP-8
LD
CLK
SDI
CLR
1
2
3
4
TOP VIEW
(Not to Scale)
V
8
REF
V
7
DD
6
V
OUT
5
GND
PIN DESCRIPTIONS
Pin No. Name Function
1
LD Load Strobe. Transfers shift register
data to DAC register while active low.
See truth table for operation.
2 CLK Clock Input. Positive edge clocks data
into shift register.
3 SDI Serial Data Input. Data loads directly
into the shift register.
4
CLR Resets DAC register to zero condition.
Active low input.
5 GND Analog & Digital Ground.
6V
OUT
DAC Voltage Output. Full-scale output
1 LSB less than reference input voltage
REF.
7V
DD
Positive Power Supply Input. Specified
range of operation 12.7 V to 15.5 V.
8V
REF
DAC Reference Input Pin. Establishes
DAC full-scale voltage.
* NOTE: AD7391 HAS A 10-BIT SHIFT REGISTER
Figure 3. Digital Control Logic
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7390/AD7391 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper
ESD precautions are recommended to avoid performance degradation or loss of functionality.
REV. 0–4–
Page 5
AD7390/AD7391
SDI
CLK
t
LD
SDI
CLK
LD
CLR
FS
V
OUT
ZS
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
AD7390 AD7391
LD1
t
LD1
DAC REGISTER LOAD
t
t
DS
DH
t
CL
t
CH
t
LDW
t
S
0.1% FS
ERROR BAND
t
CLRW
t
LD2
t
S
Figure 4. Timing Diagram
Table I. Control-Logic Truth Table
CLK CLR LD Serial Shift Register Function DAC Register Function
↑ H H Shift-Register-Data Advanced One-Bit Latched
X H L Disables Updated with Current Shift Register Contents
X L X No Effect Loaded with all Zeros
X ↑ H No Effect Latched with all Zeros
X ↑ L Disabled Previous SR Contents Loaded (Avoid usage of
LD is logic low, since SR data could be corrupted
when
CLR
if a clock edge takes place, while CLR returns high.)
NOTES
1
↑ = Positive logic transition.
2
X = Don’t care.
Table II. AD7390 Serial Input Register Data Format, Data is Loaded in the MSB-First Format
MSB LSB
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
AD7390 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Table III. AD7391 Serial Input Register Data Format, Data is Loaded in the MSB-First Format
MSB LSB
B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
AD7391 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
REV. 0 –5–
Page 6
FULL SCALE TEMPCO – ppm/°C
FREQUENCY
0
–33
12
6
24
18
–30 –26 –23 –20 –16 –13–10 –6 –3
30
0
AD7391
SS = 100 units
T
A
= 2408 to 858C
VDD = 2.7V
V
REF
= 2.5V
SUPPLY VOLTAGE – V
12 7
3456
THRESHOLD VOLTAGE – V
5.0
4.5
0.0
2.0
1.5
1.0
0.5
4.0
2.5
3.0
3.5
V
LOGIC
FROM
HIGH TO LOW
V
LOGIC
FROM
LOW TO HIGH
AD7390
CODE = FFF
H
V
REF
= 2V
LOGIC VOLTAGE
VARIED
AD7390/AD7391–Typical Performance Characteristics
25
AD7390
SS = 100 units
T
= 25 C
A
20
VDD = 2.7V
V
= 2.5V
REF
15
10
FREQUENCY
5
0
5.8 6.6 7.3 8.1 8.9 9.7 10.511.2 12.0
5.0
TOTAL UNADJUSTED ERROR – LSB
Figure 5. AD7390 Total Unadjusted
Error Histogram
16
14
12
10
8
6
4
2
OUTPUT VOLTAGE NOISE – µV/√Hz
0
1 10 100K
100 1K 10K
FREQUENCY – Hz
AD7390
VDD = 5V
V
= 2.5V
REF
= 25 C
T
A
Figure 8. Voltage Noise Density vs.
Frequency
100
90
80
70
60
50
40
FREQUENCY
30
20
10
0
–10
–3.3
3.3 10 16 23 30 36 43 50
TOTAL UNADJUSTED ERROR – LSB
AD7391
SS = 300 units
T
= 258C
A
VDD = 2.7V
V
= 2.5V
REF
Figure 6. AD7391 Total Unadjusted
Error Histogram
100
V
FROM
LOGIC
95
3.0V TO 0V
90
85
AD7390
80
75
70
65
SUPPLY CURRENT – µA
60
55
50
0.0 0.5 3.0
1.0 1.5 2.0 2.5
VIN – Volts
V
FROM
LOGIC
0V TO 3.0V
TA = 25 C
V
= 3.0V
DD
Figure 9. Supply Current vs. Logic
Input Voltage
Figure 7. AD7391 Full-Scale Output
Tempco Histogram
Figure 10. Logic Threshold vs. Supply
Voltage
100
AD7390
SAMPLE SIZE = 300 UNITS
90
80
70
60
50
40
SUPPLY CURRENT – µA
30
20
55 35 12515 5 25 65 85 10545
Figure 11. Supply Current vs.
Temperature
VDD = 5.0V, V
VDD = 3.6V, V
VDD = 3.0V, V
TEMPERATURE – C
LOGIC
= 2.4V
LOGIC
LOGIC
= 0V
= 0V
1000
AD7391
V
= 0V TO VDD TO 0V
LOGIC
V
= 2.5V
REF
800
= 25 C
T
A
600
a. VDD = 5.5V, CODE = 155
b. VDD = 5.5V, CODE = 3FF
c. VDD = 2.7V, CODE = 155
400
d. V
= 2.7V, CODE = 355
DD
SUPPLY CURRENT – µA
200
0
1K 10K 10M100K 1M
CLOCK FREQUENCY – Hz
H
b
a
H
H
H
c
d
Figure 12. Supply Current vs. Clock
Frequency
60
50
40
VDD = 3V 5%
30
PSRR – dB
20
10
0
10 100 10K
VDD = 5V 5%
FREQUENCY – Hz
TA = 25 C
1K
Figure 13. Power Supply Rejection vs.
Frequency
REV. 0–6–
Page 7
AD7390/AD7391
5µs
5mV
VDD = 5V
V
REF
= 2.5V
f
CLK
= 50KHz
= HIGH
TIME – 5µs/DIV
V
OUT
(5mV/DIV)
CLK
(5V/DIV)
REFERENCE VOLTAGE – V
05
1324
INTEGRAL NONLINEARITY – LSB
2.0
1.8
0.0
0.8
0.6
0.4
0.2
1.6
1.0
1.2
1.4
AD7390
VDD = +5V
CODE = 768
H
TA = 25 C
40
30
20
– mA
OUT
I
10
0
01 5
Figure 14. I
100µs
V
(1V/DIV)
234
V
at Zero Scale vs. V
OUT
OUT
(5V/DIV)
OUT
VDD = +5V
V
CODE = ØØØ
– V
VDD = 5V
= 2.5V
V
REF
f
= 50KHz
CLK
REF
AD7390
= +3V
H
OUT
2µs
V
OUT
(5mV/DIV)
(5V/DIV)
20mV
TIME – 2µs/DIV
VDD = 5V
= 2.5V
V
REF
f
= 50KHz
CLK
CODE: 7F
AD7390
to 80
H
Figure 15. Midscale Transition
Performance
5
0
5
VDD = +5V
10
V
= +100mV + 2V
15
GAIN – dB
20
REF
DATA = FFF
DC
H
H
Figure 16. Digital Feedthrough
1V
TIME – 100µs/div
Figure 17. Large Signal Settling Time
1.2
1.0
0.8
0.6
0.4
0.2
NOMINAL CHANGE IN VOLTAGE – mV
0.0
0 100 600
HOURS OF OPERATION AT 150°C
AD7390
SAMPLE SIZE = 50
CODE = FFF
CODE = 000
200 300 400 500
H
H
Figure 20. Long-Term Drift
Accelerated by Burn-In
REV. 0 –7–
25
30
10 100 100K
1K 10K
FREQUENCY – Hz
Figure 18. Reference Multiplying
Bandwidth
Figure 19. INL Error vs. Reference
Voltage
Page 8
AD7390/AD7391
OPERATION
The AD7390 and AD7391 are a set of pin compatible, 12-bit/10bit digital-to-analog converters. These single-supply operation
devices consume less than 100 microamps of current while operating from power supplies in the 12.7 V to 15.5 V range
making them ideal for battery operated applications. They contain a voltage-switched, 12-bit/10-bit, laser-trimmed digital-toanalog converter, rail-to-rail output op amps, serial-input
register, and a DAC register. The external reference input has
constant input resistance independent of the digital code setting
of the DAC. In addition, the reference input can be tied to the
same supply voltage as V
age span of 0 to V
DD
consists of a serial data input (SDI), clock (CLK), and load
LD) pins. A CLR pin is available to reset the DAC register to
(
zero-scale. This function is useful for power-on reset or system
failure recovery to a known state.
D/A CONVERTER SECTION
The voltage switched R-2R DAC generates an output voltage
dependent on the external reference voltage connected to the
pin according to the following equation:
V
REF
= V
V
OUT
REF
where D is the decimal data word loaded into the DAC register,
and N is the number of bits of DAC resolution. In the case of
the 10-bit AD7391 using a 2.5 V reference, Equation 1
simplifies to:
= 2.5
V
OUT
Using Equation 2 the nominal midscale voltage at V
1.25 V for D = 512; full-scale voltage is 2.497 volts. The LSB
step size is = 2.5 3 1/1024 = 0.0024 volts.
For the 12-bit AD7390 operating from a 5.0 V reference Equation 1 becomes:
= 5.0
V
OUT
Using Equation 3 the AD7390 provides a nominal midscale
voltage of 2.5 V for D =2048, and a full-scale output of 4.998 V.
The LSB step size is = 5.0 3 1/4096 = 0.0012 volts.
AMPLIFIER SECTION
The internal DAC’s output is buffered by a low power consumption precision amplifier. The op amp has a 60 µs typical
settling time to 0.1% of full scale. There are slight differences in
settling time for negative slewing signals versus positive. Also,
negative transition settling time to within the last 6 LSBs of zero
volts has an extended settling time. The rail-to-rail output stage
of this amplifier has been designed to provide precision performance while operating near either power supply. Figure 21
shows an equivalent output schematic of the rail-to-rail amplifier with its N-channel pull-down FETs that will pull an output
load directly to GND. The output sourcing current is provided
by a P-channel pull-up device that can source current to GND
terminated loads.
resulting in a maximum output volt-
DD
. The SPI compatible, serial-data interface
D
3
3
3
D
1024
D
4096
N
2
Equation 1
Equation 2
is
OUT
Equation 3
V
P-CH
N-CH
DD
V
OUT
AGND
Figure 21. Equivalent Analog Output Circuit
The rail-to-rail output stage provides 61 mA of output current.
The N-channel output pull-down MOSFET shown in Figure 21
has a 35 Ω ON resistance, which sets the sink current capability
near ground. In addition to resistive load driving capability, the
amplifier has also been carefully designed and characterized for
up to 100 pF capacitive load driving capability.
REFERENCE INPUT
The reference input terminal has a constant input-resistance independent of digital code which results in reduced glitches on
the external reference voltage source. The high 2 MΩ inputresistance minimizes power dissipation within the AD7390/
AD7391 D/A converters. The V
ranging from ground to the positive-supply voltage V
input accepts input voltages
REF
. One of
DD
the simplest applications which saves an external reference voltage source is connection of the V
supply. This connection results in a rail-to-rail voltage out-
V
DD
terminal to the positive
REF
put span maximizing the programmed range. The reference input will accept ac signals as long as they are kept within the
supply voltage range, 0 < V
< VDD. The reference
REF IN
bandwidth and integral nonlinearity error performance are plotted in the typical performance section, see Figures 18 and 19.
The ratiometric reference feature makes the AD7390/AD7391
an ideal companion to ratiometric analog-to-digital converters
such as the AD7896.
POWER SUPPLY
The very low power consumption of the AD7390/AD7391 is a direct result of a circuit design optimizing the use of a CBCMOS
process. By using the low power characteristics of CMOS for the
logic, and the low noise, tight-matching of the complementary bipolar transistors, excellent analog accuracy is achieved. One advantage of the rail-to-rail output amplifiers used in the AD7390/
AD7391 is the wide range of usable supply voltage. The part is
fully specified and tested for operation from 12.7 V to 15.5 V.
POWER SUPPLY BYPASSING AND GROUNDING
Precision analog products, such as the AD7390/AD7391, require a well filtered power source. Since the AD7390/AD7391
operates from a single 13 V to 15 V supply, it seems convenient to simply tap into the digital logic power supply. Unfortunately, the logic supply is often a switch-mode design, which
generates noise in the 20 kHz to 1 MHz range. In addition, fast
logic gates can generate glitches hundred of millivolts in amplitude due to wiring resistance and inductance. The power supply
noise generated thereby means that special care must be taken
to assure that the inherent precision of the DAC is maintained.
Good engineering judgment should be exercised when addressing the power supply grounding and bypassing of the AD7390.
REV. 0–8–
Page 9
The AD7390 should be powered directly from the system power
V
DD
LOGIC
IN
GND
supply. This arrangement, shown in Figure 22, employs an LC
filter and separate power and ground connections to isolate the
analog section from the logic switching transients.
FERRITE BEAD:
2 TURNS, FAIR-RITE
#2677006301
0.1µF
CER.
+5V
+5V
RETURN
TTL/CMOS
LOGIC
CIRCUITS
+5V
POWER SUPPLY
100µF
ELECT.
10-22µF
TANT.
Figure 22. Use Separate Traces to Reduce Power Supply Noise
Whether or not a separate power supply trace is available, however, generous supply bypassing will reduce supply-line induced
errors. Local supply bypassing consisting of a 10 µF tantalum
electrolytic in parallel with a 0.1 µF ceramic capacitor is recom-
mended in all applications (Figure 23).
+2.7V to +5.5V
C
*
LD
CLK
SDI
CLR
* OPTIONAL EXTERNAL
REFERENCE BYPASS
REF V
1
2
3
4
8 7
DD
AD7390
or
AD7391
GND
5
0.1 µF
1
10 µF
6
V
OUT
Figure 23. Recommended Supply Bypassing for the
AD7390/AD7391
INPUT LOGIC LEVELS
All digital inputs are protected with a Zener-type ESD protection structure (Figure 24) that allows logic input voltages to exceed the V
supply voltage. This feature can be useful if the
DD
user is driving one or more of the digital inputs with a 5 V
CMOS logic input-voltage level while operating the AD7390/
AD7391 on a 13 V power supply. If this mode of interface is
used, make sure that the V
of the 5 V CMOS meets the V
OL
IL
input requirement of the AD7390/AD7391 operating at 3 V.
See Figure 10 for a graph for digital logic input threshold versus
operating V
supply voltage.
DD
AD7390/AD7391
Figure 24. Equivalent Digital Input ESD Protection
In order to minimize power dissipation from input-logic levels
that are near the V
Schmitt trigger design was used that minimizes the input-buffer
current consumption compared to traditional CMOS input
stages. Figure 9 shows a plot of incremental input voltage versus
supply current showing that negligible current consumption
takes place when logic levels are in their quiescent state. The
normal crossover current still occurs during logic transitions. A
secondary advantage of this Schmitt trigger, is the prevention of
false triggers that would occur with slow moving logic transitions when a standard CMOS logic interface or opto isolators
are used. The logic inputs SDI, CLK,
Schmitt trigger circuits.
DIGITAL INTERFACE
The AD7390/AD7391 have a double-buffered serial data input.
The serial-input register is separate from the DAC register,
which allows preloading of a new data value into the serial register without disturbing the present DAC values. A functional
block diagram of the digital section is shown in Figure 4, while
Table I contains the truth table for the control logic inputs.
Three pins control the serial data input. Data at the Serial Data
Input (SDI) is clocked into the shift register on the rising edge
of CLK. Data is entered in MSB-first format. Twelve clock
pulses are required to load the 12-bit AD7390 DAC value. If
additional bits are clocked into the shift register, for example
when a microcontroller sends two 8-bit bytes, the MSBs are ignored (Figure 25). The CLK pin is only enabled when Load
LD) is high. The lower resolution 10-bit AD7391 contains a
(
10-bit shift register. The AD7391 is also loaded MSB first with
10 bits of data. Again if additional bits are clocked into the shift
register, only the last 10 bits clocked in are used.
The Load pin (
ister to the DAC register. After a new value is clocked into the
serial-input register, it will be transferred to the DAC register by
the negative transition of the Load pin (
and VIL logic input voltage specifications, a
IH
LD, CLR all contain the
LD) controls the flow of data from the shift reg-
LD).
BYTE 0BYTE 1
MSB
B15
B14
B13
B12
B11
B10
B9
X
X
X
X
D11
D!0
D9
X
X
X
X
X
X
D9
D11_D0: 12-BIT AD7390 DAC VALUE; D9_D0 10-BIT AD7391 DAC VALUE
X = DON’T CARE
THE MSB OF BYTE 1 IS THE FIRST BIT THAT IS LOADED INTO THE DAC
Figure 25. Typical AD7390-Microprocessor Serial Data Input Forms
MSBLSB LSB
B8
B7
B6
B5
B4
B3
B2
D8
D7
D6
D5
D4
D3
D2
D8
D7
D6
D5
D4
D3
D2
B1
B0
D1
D0
D1
D0
REV. 0 –9–
Page 10
AD7390/AD7391
RESET (CLR) PIN
Forcing the CLR pin low will set the DAC register to all zeros
and the DAC output voltage will be zero volts. The reset function is useful for setting the DAC outputs to zero at power-up or
after a power supply interruption. Test systems and motor controllers are two of many applications which benefit from powering up to a known state. The external reset pulse can be
generated by the microprocessor’s power-on RESET signal, by
an output from the microprocessor, or by an external resistor
and capacitor.
CLR has a Schmitt trigger input which results in
a clean reset function when using external resistor/capacitor
generated pulses. The
specifically
goes high. If
LD. However, LD should be set high before CLR
CLR is kept low, then the contents of the shift reg-
ister will be transferred to the DAC register as soon as
CLR input overrides other logic inputs,
CLR re-
turns high. See the Control-Logic Truth Table I.
UNIPOLAR OUTPUT OPERATION
This is the basic mode of operation for the AD7390. As shown
in Figure 26, the AD7390 has been designed to drive loads as
low as 5 kΩ in parallel with 100 pF. The code table for this operation is shown in Table IV.
+2.7V to +5.5V
R
0.01µF
EXT
REF
µC
RS
LD 3
CLK
SDI
CLR
REF V
2
1
4
AD7390
GND
5
7
DD
V
OUT
0.1µF
6
RL
≥ 5kΩ
1
10µF
CL
≤ 100pF
sumption OP196 has been designed just for this purpose and results in only 50 microamps of maximum current consumption.
Connection of the equal valued 470 kΩ resistors results in a differential amplifier mode of operation with a voltage gain of two,
which results in a circuit output span of ten volts, that is, 25 V
to 15 V. As the DAC is programmed with zero-code 000
midscale 200
to full-scale 3FFH, the circuit output voltage V
H
to
H
O
is set at 25 V, 0 V and 15 V (minus 1 LSB). The output volt-
is coded in offset binary according to Equation 4.
age V
O
=
V
O
D
3 4
1 2
512
21
3
5
Equation 4
where D is the decimal code loaded in the AD7391 DAC register. Note that the LSB step size is 10/1024 = 10 mV. This circuit has been optimized for micropower consumption including
the 470 kΩ gain setting resistors, which should have low temperature coefficients to maintain accuracy and matching (preferably the same material, such as metal film). If better stability is
required the power supply could be substituted with a precision
reference voltage such as the low dropout REF195, which can
easily supply the circuit’s 162 µA of current, and still provide
additional power for the load connected to V
. The micropower
O
REF195 is guaranteed to source 10 mA output drive current,
but only consumes 50 µA internally. If higher resolution is re-
quired, the AD7390 can be used with the addition of two more
bits of data inserted into the software coding, which would result in a 2.5 mV LSB step size. Table V shows examples of
nominal output voltages V
provided by the Bipolar Operation
O
circuit application.
ISY < 162µA
15V
470kΩ470kΩ
Figure 26. AD7390 Unipolar Output Operation
Table IV. AD7390 Unipolar Code Table
Hexadecimal Decimal Output
Number Number Voltage (V)
in DAC Register in DAC Register V
= 2.5 V
REF
FFF 4095 2.4994
801 2049 1.2506
800 2048 1.2500
7FF 2047 1.2494
000 0 0
The circuit can be configured with an external reference plus
power supply, or powered from a single dedicated regulator or reference depending on the application performance requirements.
BIPOLAR OUTPUT OPERATION
Although the AD7391 has been designed for single-supply operation, the output can be easily configured for bipolar operation. A typical circuit is shown in Figure 27. This circuit uses a
clean regulated 15 V supply for power, which also provides the
circuit’s reference voltage. Since the AD7391 output span
swings from ground to very near 15 V, it is necessary to choose
an external amplifier with a common-mode input voltage range
that extends to its positive supply rail. The micropower con-
OP196
1
< 50µA
25V
15V
V
O
BIPOLAR
OUTPUT
SWING
25V
< 100µA
REF V
C
DD
AD7391
GND
DIGITAL INTERFACE CIRCUITRY OMITTED FOR CLARITY
V
OUT
Figure 27. Bipolar Output Operation
Table V. Bipolar Code Table
Hexadecimal Decimal Analog
Number Number Output
In DAC Register in DAC Register Voltage (V)
3FF 1023 4.9902
201 513 0.0097
200 512 0.0000
1FF 511 -0.0097
000 0 -5.0000
REV. 0–10–
Page 11
MICROCOMPUTER INTERFACES
The AD7390 serial data input provides an easy interface to a variety of single-chip microcomputers (µCs). Many µCs have a
built-in serial data capability which can be used for communicating with the DAC. In cases where no serial port is provided,
or it is being used for some other purpose (such as an RS-232
communications interface), the AD7390/AD7391 can easily be
addressed in software.
Twelve data bits are required to load a value into the AD7390.
If more than 12 bits are transmitted before the load
goes high, the extra (i.e., the most-significant) bits are ignored.
This feature is valuable because most µCs only transmit data in
8-bit increments. Thus, the µC sends 16 bits to the DAC in-
stead of 12 bits. The AD7390 will only respond to the last
12 bits clocked into the SDI input, however, so the serial-data
interface is not affected.
Ten data bits are required to load a value into the AD7391. If
more than 10 bits are transmitted before load
the extra bits are ignored.
LD input
LD returns high,
AD7390/AD7391
REV. 0 –11–
Page 12
AD7390/AD7391
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
0.1574 (4.00)
0.1497 (3.80)
PIN 1
0.0098 (0.25)
0.0040 (0.10)
SEATING
PLANE
8-Lead SOIC (SO-8)
0.1968 (5.00)
0.1890 (4.80)
8
5
0.2440 (6.20)
41
0.2284 (5.80)
0.0688 (1.75)
0.0532 (1.35)
0.0500
0.0192 (0.49)
(1.27)
0.0138 (0.35)
BSC
0.0098 (0.25)
0.0075 (0.19)
0.0196 (0.50)
0.0099 (0.25)
8°
0°
0.0500 (1.27)
0.0160 (0.41)
0.177 (4.50)
x 45°
8-Pin TSSOP (RU-8)
0.122 (3.10)
0.114 (2.90)
8
5
0.169 (4.30)
1
4
0.256 (6.50)
0.246 (6.25)
0.210 (5.33)
MAX
0.160 (4.06)
0.115 (2.93)
0.022 (0.558)
0.014 (0.356)
8-Pin Plastic DIP (N-8)
0.430 (10.92)
0.348 (8.84)
8
14
PIN 1
0.100
(2.54)
BSC
5
0.280 (7.11)
0.240 (6.10)
0.060 (1.52)
0.015 (0.38)
0.070 (1.77)
0.045 (1.15)
0.130
(3.30)
MIN
SEATING
PLANE
0.325 (8.25)
0.300 (7.62)
0.015 (0.381)
0.008 (0.204)
0.195 (4.95)
0.115 (2.93)
C2151–18–7/96
PIN 1
0.006 (0.15)
0.002 (0.05)
SEATING
PLANE
0.0256 (0.65)
BSC
0.0118 (0.30)
0.0075 (0.19)
0.0433
(1.10)
MAX
0.0079 (0.20)
0.0035 (0.090)
8°
0°
0.028 (0.70)
0.020 (0.50)
PRINTED IN U.S.A.
REV. 0–12–
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