Datasheet AD734 Datasheet (ANALOG DEVICES)

10 MHz, Four-Quadrant

X1X

Y

FEATURES

High accuracy

0.1% typical error

High speed

10 MHz full power bandwidth
450 V/μs slew rate
200 ns settling to 0.1% at full power

Low distortion

−80 dBc from any input
Third-order IMD typically −75 dBc at 10 MHz

Low noise

94 dB SNR, 10 Hz to 20 kHz
70 dB SNR, 10 Hz to 10 MHz

Direct division mode

2 MHz BW at gain of 100

APPLICATIONS

High performance replacement for AD534
Multiply, divide, square, square root
Modulators, demodulators
Wideband gain control, rms-to-dc conversion
Voltage-controlled amplifiers, oscillators, and filters
Demodulator with 40 MHz input bandwidth

Multiplier/Divider

AD734

FUNCTIONAL BLOCK DIAGRAM

AD734

X = X1 – X

2

XZ

U

2

Figure 1.

HIGH ACCURAC Y
TRANSLINEAR CO RE

XY ÷ U – Z

+

–

Z = Z1 – Z

A

2

WIF

O

ZIF

W

∞

Z1

Z2

00827-003

XIF

2

DD

DENOMINATOR

YIF

CONTROL

R

U

ER

U0

U1

U2

1

Y2

U

Y = Y1 –Y

GENERAL DESCRIPTION

The AD734 is an accurate high speed, four-quadrant analog
multiplier that is pin compatible with the industry-standard
AD534 and provides the transfer function W = XY/U. The
AD734 provides a low impedance voltage output with a full
power (20 V p-p) bandwidth of 10 MHz. Total static error
(scaling, offsets, and nonlinearities combined) is 0.1% of full
scale. Distortion is typically less than −80 dBc and guaranteed.
The low capacitance X, Y, and Z inputs are fully differential.
In most applications, no external components are required to
define the function.

The internal scaling (denominator) voltage, U, is 10 V, derived
from a buried-Zener voltage reference. A new feature provides
the option of substituting an external denominator voltage,
allowing the use of the AD734 as a two-quadrant divider with a
1000:1 denominator range and a signal bandwidth that remains

10 MHz to a gain of 20 dB, 2 MHz at a gain of 40 dB, and 200 kHz
at a gain of 60 dB, for a gain-bandwidth product of 200 MHz.

The advanced performance of the AD734 is achieved by a
combination of new circuit techniques, the use of a high speed
complementary bipolar process, and a novel approach to laser
trimming based on ac signals rather than the customary dc
methods. The wide bandwidth (>40 MHz) of the AD734’s input
stages and the 200 MHz gain-bandwidth product of the multiplier
core allow the AD734 to be used as a low distortion demodulator
with input frequencies as high as 40 MHz as long as the desired
output frequency is less than 10 MHz.

The AD734AQ and AD734BQ are specified for the industrial
temperature range of −40°C to +85°C and come in a 14-lead
CERDIP and a 14-lead PDIP package. The AD734SQ/883B,
available processed to MIL-STD-883B for the military range of

−55°C to +125°C, is available in a 14-lead CERDIP.

Rev. E

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2011 Analog Devices, Inc. All rights reserved.

AD734

TABLE OF CONTENTS

Features.............................................................................................. 1

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Absolute Maximum Ratings............................................................ 5

Thermal Resistance ...................................................................... 5

ESD Caution.................................................................................. 5

Pin Configuration and Function Descriptions............................. 6

Typical Performance Characteristics ............................................. 7

REVISION HISTORY

2/11—Rev. D to Rev. E

Changes to Figure 4, Figure 5, and Figure 6.................................. 7

Changes to Figure 22 and Figure 23............................................. 12

Changes to Figure 27 and Figure 28............................................. 14

Changes to Figure 36...................................................................... 17

1/11—Rev. C to Rev. D

Updated Format..................................................................Universal

Changes to Figure 1 and General Description Section ............... 1

Deleted Product Highlights Section............................................... 1

Change to Endnote 3........................................................................ 4

Changes to Table 2 and Table 3....................................................... 5

Added Pin Configuration and Function Descriptions Section.. 6

Added Figure 3; Renumbered Sequentially .................................. 6

Added Table 4; Renumbered Sequentially .................................... 6

Changes to Functional Description Section ............................... 10

Changes to Figure 36...................................................................... 17

Updated Outline Dimensions....................................................... 19

Changes to Ordering Guide.......................................................... 19

Functional Description.................................................................. 10

Available Transfer Functions .................................................... 10

Direct Denominator Control.................................................... 11

Operation as a Multiplier.......................................................... 12

Operation as a Divider............................................................... 14

Division by Direct Denominator Control............................... 14

A Precision AGC Loop.............................................................. 15

Wideband RMS-to-DC Converter Using U Interface........... 16

Low Distortion Mixer................................................................ 17

Outline Dimensions....................................................................... 18

Ordering Guide .......................................................................... 19

Rev. E | Page 2 of 20

AD734

()(

)

SPECIFICATIONS

TA = +25°C, +VS = VP = +15 V, −VS = VN = −15 V, RL ≥ 2 kΩ, unless otherwise noted.

Generalized transfer function:

⎧

⎪

AW

=

⎨

O

⎪

⎩

YYXX

−−

2121

UU

−

21

()

⎫

⎪

ZZ

−−

⎬

21

⎪

⎭

Table 1.

A B S

Parameter Conditions Min Typ Max Min Typ Max Min Typ Max Unit

MULTIPLIER PERFORMANCE

Transfer Function W =

Total Static Error1 −10 V ≤ X, Y ≤ 10 V 0.1 0.4 0.1 0.25 0.1 0.4 %

Over T
vs. Temperature T
vs. Either Supply ±VS = 14 V to 16 V 0.01 0.05 0.01 0.05 0.01 0.05 %/V

Peak Nonlinearity −10 V ≤ X ≤ +10 V,

−10 V ≤ Y ≤ +10 V,

THD2 X = 7 V rms, Y =

T
Y = 7 V rms, X =

T
Feedthrough X = 7 V rms, Y =

Y = 7 V rms, X =

Noise (RTO) X = Y = 0 V

Spectral Density 100 Hz to 1 MHz 1.0 1.0 1.0 μV/√Hz

Total Output Noise 10 Hz to 20 kHz −94 −88 −94 −88 −94 −88 dBc
T
DIVIDER PERFORMANCE

(Y = 10 V)
Transfer Function W =

Gain Error Y = 10 V, U = 100 mV

X Input Clipping Level Y ≤ 10 V 1.25 × U 1.25 × U 1.25 × U V
U Input Scaling Error3 0.3 0.15 0.3 %

T

Output to 1% U = 1 V to 10 V step,

INPUT INTERFACES

(X, Y, AND Z)
3 dB Bandwidth 40 40 40 MHz
Operating Range Differential or

X Input Offset Voltage 15 5 15 mV

T

Y Input Offset Voltage 10 5 10 mV
T

Z Input Offset Voltage 20 10 20 mV
T

Z Input PSRR (Either

T

MIN

Supply)

to T

1 0.6 1.25 %

MAX

to T

MIN

Y = +10 V

X = +10 V

+10 V, f ≤ 5 kHz

MIN

+10 V, f ≤ 5 kHz

MIN

nulled, f ≤ 5 kHz

nulled, f ≤ 5 kHz

MIN

to 10 V

MIN

X = 1 V

common mode

MIN

MIN

MIN

f ≤ 1 kHz 54 70 66 70 54 70 dB

MIN

0.004 0.003 0.004 %/°C

MAX

0.05 0.05 0.05 %

0.025 0.025 0.025 %

−58 −66 −58 dBc

to T

−55 −63 −55 dBc

MAX

−60 −80 −60 dBc

to T

−57 −74 −57 dBc

MAX

−85 −60 −85 −70 –85 –60 dBc

−85 −66 −85 −76 −85 −66 dBc

to T

−85 −85 −85 dBc

MAX

1 1 1 %

to T

0.8 0.65 1 %

MAX

100 100 100 ns

±12.5 ±12.5 ±12.5 V

to T

25 15 25 mV

MAX

to T

12 6 12 mV

MAX

to T

50 50 90 mV

MAX

to T

50 56 50 dB

MAX

XY/10

XY/U

W =

XY/10

W =

XY/U

W =

XY/10

W =

XY/U

Rev. E | Page 3 of 20

AD734

A B S

Parameter Conditions Min Typ Max Min Typ Max Min Typ Max Unit

CMRR f = 5 kHz 70 85 70 85 70 85 dB

Input Bias Current

(X, Y, Z Inputs)
T
Input Resistance Differential 50 50 50 kΩ
Input Capacitance Differential 2 2 2 pF

DENOMINATOR INTERFACES

(U0, U1, AND U2)
Operating Range VN to

Denominator Range 1000:1 1000:1 1000:1
Interface Resistor U1 to U2 28 28 28 kΩ

OUTPUT AMPLIFIER (W)

Output Voltage Swing T
Open-Loop Voltage Gain X = Y = 0, input to Z 72 72 72 dB
Dynamic Response From X or Y input,

3 dB Bandwidth W ≤ 7 V rms 8 10 8 10 8 10 MHz
Slew Rate 450 450 450 V/μs

Settling Time +20 V or −20 V

To 1% 125 125 125 ns
To 0.1% 200 200 200 ns

Short-Circuit Current T

POWER SUPPLIES, ±VS

Operating Supply Range ±8 ±16.5 ±8 ±16.5 ±8 ±16.5 V
Quiescent Current T

1

Figures given are percent of full scale (for example, 0.01% = 1 mV).

2

dBc refers to decibels relative to the full-scale input (carrier) level of 7 V rms.

3

See for test circuit. Figure 28

50 300 50 150 50 300 nA

to T

MIN

400 300 500 nA

MAX

MIN

VP − 3

to T

±12 ±12 ±12 V

MAX

VP − 3

VN to

VN to

V

VP − 3

C

≤ 20 pF

LOAD

output step

to T

MIN

MIN

20 50 80 20 50 80 20 50 80 mA

MAX

to T

6 9 12 6 9 12 6 9 12 mA

MAX

Rev. E | Page 4 of 20

AD734

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

Supply Voltage ±18 V
Internal Power Dissipation

for TJ max = 175°C 500 mW
X, Y, and Z Input Voltages VN to VP
Output Short-Circuit Duration Indefinite
Storage Temperature Range

Q-14 −65°C to +150°C

N-14 −65°C to +150°C
Operating Temperature Range

AD734A, AD734B (Industrial) −40°C to +85°C

AD734S (Military) −55°C to +125°C
Lead Temperature Range (Soldering, 60 sec) +300°C
Transistor Count 81
ESD Rating 500 V

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.

Table 3. Thermal Resistance

Package Type θJA Unit

14-Lead PDIP (N-14) 150 °C/W
14-Lead CERDIP (Q-14) 110 °C/W

ESD CAUTION

W

12

DD

13

VP

X1

14

1

2

X2

0.093 (2.3622)

Z1

11

Z2

10

ER

9

8

7

6

VN

0.122

(3.0988)

Y2

Y1

3

U0

U1

54

U2

Figure 2. Chip Dimensions and Bonding Diagram, Dimensions shown in inches and (mm), (Contact factory for latest dimensions)

Rev. E | Page 5 of 20

00827-002

AD734

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

X1

X2

U0

U1

U2

Y1

Y2

1

2

AD734

3

TOP VIEW

(Not to S cale)

4

5

6

7

14

VP

DD

13

W

12

Z1

11

10

Z2

ER

9

VN

8

00827-001

Figure 3. 14-Lead PDIP and 14-Lead CERDIP

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description

1 X1 X Differential Multiplicand Input.
2 X2 X Differential Multiplicand Input.
3 U0 Denominator Current Source Enable Interface.
4 U1 Denominator Interface—see the Functional Description section.
5 U2 Denominator Interface—see the Functional Description section.
6 Y1 Y Differential Multiplicand Input.
7 Y2 Y Differential Multiplicand Input.
8 VN Negative Supply.
9 ER Reference Voltage.
10 Z2 Z Differential Summing Input.
11 Z1 Z Differential Summing Input.
12 W Output.
13 DD Denominator Disable.
14 VP Positive Supply.

Rev. E | Page 6 of 20

AD734

TYPICAL PERFORMANCE CHARACTERISTICS

0.10

0.08

0.06

0.04

0.02

0

–0.02

–0.04

DIFFERENTIAL GAIN (dB)

–0.06

–0.08

–0.10

–2V 0 2V

Figure 4. Differential Gain at 3.58 MHz and R

VS = ±15V
R

= 2kΩ

LOAD

C

= 20pF

LOAD

SIGNAL AMPLI TUDE

LOAD

00827-022

= 2 kΩ

100

80

60

40

CMRR (dB)

20

COMMON-MODE
SIGNAL = 7V RMS

0

1k 10k 100k 1M 10M

FREQUENC Y (Hz)

Y INPUT, X = 10V

X INPUT, Y = 10V

Figure 7. CMRR vs. Frequency

00827-025

0.25

0.20

0.15

0.10

0.05

0

–0.05

–0.10

–0.15

DIFFE RENTIAL PHASE (De grees)

–0.20

–0.25

–2V 0 2V

Figure 5. Differential Phase at 3.58 MHz and R

0.5

0.4

0.3

0.2

0.1

0

–0.1

GAIN FLATNESS

–0.2

–0.3

–0.4

–0.5

100k 1M 10M

Figure 6. Gain Flatness, 300 kHz to 10 MHz, R

VS = ±15V
R

= 2kΩ

LOAD

C

= 20pF

LOAD

SIGNAL AMPLI TUDE

VS = ±15V
X = 1.4V RMS
Y = 10V
R
C

FREQUENCY (Hz)

LOAD
LOAD

LOAD

= 500Ω
= 20pF

= 500 Ω

LOAD

= 2 kΩ

100

80

60

PSRR (dB)

40

20

00827-023

0

1k 10k 100k 1M 10M

VP

FREQUENC Y (Hz)

VN

00827-026

Figure 8. PSRR vs. Frequency

0

INPUT SIGNAL = 7V RMS

–40

–60

–80

FEEDTHRO UGH (dBc)

–100

00827-024

1k 10k 100k 1M 10M

X INPUT, Y NULLED

Y INPUT, X NULLED

FREQUENC Y (Hz)

00827-027

Figure 9. Feedthrough vs. Frequency

Rev. E | Page 7 of 20

AD734

0

–20

–40

THD (dBc)

–60

–80

1k 10k 100k 1M 10M

TEST INPUT = 1V RMS
U = 2V
OTHER INPUT = 2V DC

FREQUENC Y (Hz)

X INPUT

Figure 10. THD vs. Frequency, U = 2 V

0

–20

–40

THD (dBc)

–60

–80

1k 10k 100k 1M 10M

TEST INPUT = 7V RMS
OTHER INPUT = 10V DC

≥2kΩ

R

LOAD

FREQUENC Y (Hz)

X INPUT

Y INPUT

Figure 11. THD vs. Frequency, U = 10 V

0

Y INPUT

00827-028

00827-029

5

VS= ±15V

4

X = 1.4V RMS
Y = 10V

3

2

1

0

–1

AMPLIT UTE (d B)

–2

–3

–4

–5

100k 1M 10M

= 500Ω

R

LOAD

= 20pF, 47pF, 100pF

C

LOAD

FREQUENCY (Hz)

Figure 13. Gain vs. Frequency vs. C

0

–30

–60

–90

VS = ±15V

–120

X = 1.4V RMS
Y = 10V

–150

PHASE SHIFT (Degrees)

R

= 500Ω

LOAD

C

–180

–210

100k 1M 10M

= 20pF, 47pF, 100pF

LOAD

FREQUENCY (Hz)

INCREASING
C

LOAD

Figure 14. Phase vs. Frequency vs. C

INCREASING
C

LOAD

LOAD

LOAD

00827-031

00827-032

–20

–40

THD (dBc)

–60

–80

–100

–10dBm

70.7mV RMS

FREQUENC Y = 1MHz
VP = +15V
VN = –15V
R

= 2kΩ

LOAD

X INPUT. Y = 10V DC

Y INPUT. X = 10V DC

10dBm

707mV RMS

SIGNAL LEVEL

Figure 12. THD vs. Signal Level, f = 1 MHz

00827-030

30dBm

7V RMS

Rev. E | Page 8 of 20

INCREASING
C

LOAD

5V 50n s

Figure 15. Pulse Response vs. C

= 0 pF, 47 pF, 100 pF, 200 pF

C

LOAD

LOAD

00827-033

,

AD734

A

A

A

20

15

10

5

0

–5

OUTPUT SWING (V)

–10

–15

–20

89 181716151413121110

SUPPLY VOLTAGE (±VS)

Figure 16. Output Swing vs. Supply Voltage

0

–10

–20

X1 FREQ =

OUTPUT AMPLI TUDE (dB)

Y
(FOR EXAMPLE,

FOR ALL CURVES)

–30

10 20 10090807060504030

FREQ –1MHz

1

Y

– X1 = 1MHz

1

U = 1V

Y1 FREQUENCY (MHz)

U = 5V

U = 2V

Figure 17. Output Amplitude vs. Input Frequency, When Used as

Demodulator

U = 10V

20

15

10

5

0

–5

TION OF INPUT OFFSET VOLTAGE (mV)

–10

DEVI

00827-034

–15

–55 –35 125105856545255–15

60

40

20

0

–20

–40

TION OF INPUT OFFSET VOLTAGE (mV)

–60

00827-035

DEVI

–55 –35 105 125856545255–15

8

6

4

INPUT OFFSET VOLTAGE
DRIFT WI LL TYPICALLY BE
WITHIN SHADED AREA

TEMPERATURE (°C)

Figure 18. V

INPUT OFFSET VOLTAGE
DRIFT WI LL TYPICALLY BE
WITHIN SHADED AREA

Figure 19. V

INPUT OFFSET VOLTAGE
DRIFT WILL TYPICALLY BE
WITHI N SHADED AREA

Drift, X Input

OS

TEMPERATURE (°C)

Drift, Z Input

OS

00827-036

00827-037

2

0

–2

TION OF INPUT OFF SET VOLTAGE (mV)

–4

DEVI

–6

–55 –35 125105856545255–1 5

TEMPERATURE (°C)

Figure 20. V

Drift, Y Input

OS

00827-038

Rev. E | Page 9 of 20

AD734

()(

FUNCTIONAL DESCRIPTION

The AD734 embodies more than two decades of experience in
the design and manufacture of analog multipliers to provide:

• A new output amplifier design with more than 20 times the

slew rate of the AD534 (450 V/μs vs. 20 V/μs) for a full
power (20 V p-p) bandwidth of 10 MHz.

• Very low distortion, even at full power, through the use of

circuit and trimming techniques that virtually eliminate all
of the spurious nonlinearities found in earlier designs.

• Direct control of the denominator, resulting in higher

multiplier accuracy and a gain-bandwidth product at small
denominator values that is typically 200 times greater than
that of the AD534 in divider modes.

• Very clean transient response, achieved through the use of

a novel input stage design and wideband output amplifier,
which also ensure that distortion remains low even at high
frequencies.

• Superior noise performance by careful choice of device

geometries and operating conditions, which provide a
guaranteed 88 dB of dynamic range in a 20 kHz bandwidth.

Figure 3 shows the lead configuration of the 14-lead PDIP and
CERDIP packages.

Figure 1 is a simplified block diagram of the AD734. Operation
is similar to that of the industry-standard AD534, and in many
applications, these parts are pin compatible. The main functional
difference is the provision for direct control of the denominator
voltage, U, explained fully in the Direct Denominator Control
section. Internal signals are in the form of currents, but the
function of the AD734 can be understood using voltages
throughout, as shown in Figure 1.

The AD734 differential X, Y, and Z inputs are handled by
wideband interfaces that have low offset, low bias current, and
low distortion. The AD734 responds to the difference signals
X = X

− X2, Y = Y1 − Y2, and Z = Z1 − Z2, and rejects common-

1

mode voltages on these inputs. The X, Y, and Z interfaces provide a
nominal full-scale (FS) voltage of ±10 V, but, due to the special
design of the input stages, the linear range of the differential
input can be as large as ±17 V. Also, unlike previous designs, the
response on these inputs is not clipped abruptly above ±15 V,
but drops to a slope of one half.

The bipolar input signals X and Y are multiplied in a translinear
core of novel design to generate the product XY/U. The denomina­tor voltage, U, is internally set to an accurate, temperature-stable
value of 10 V, derived from a buried-Zener reference. An uncali­brated fraction of the denominator voltage U appears between
the voltage reference pin (ER) and the negative supply pin (VN),
for use in certain applications where a temperature-compensated
voltage reference is desirable. The internal denominator, U, can
be disabled, by connecting the denominator disable Pin 13
(DD) to the positive supply pin (VP); the denominator can then

Rev. E | Page 10 of 20

be replaced by a fixed or variable external voltage ranging from
10 mV to more than 10 V.

The high gain output op amp nulls the difference between XY/
U and an additional signal, Z, to generate the final output, W.
The actual transfer function can take on several forms, depending
on the connections used. The AD734 can perform all of the
functions supported by the AD534, and new functions using
the direct-division mode provided by the U interface.

Each input pair (X1 and X2, Y1 and Y2, Z1 and Z2) has a
differential input resistance of 50 kΩ; this is formed by actual
resistors (not a small-signal approximation) and is subject to a
tolerance of ±20%. The common-mode input resistance is
several megohms and the parasitic capacitance is about 2 pF.

The bias currents associated with these inputs are nulled by
laser-trimming, such that when one input of a pair is optionally
ac-coupled and the other is grounded, the residual offset voltage
is typically less than 5 mV, which corresponds to a bias current
of only 100 nA. This low bias current ensures that mismatches
in the sources’ resistances at a pair of inputs does not cause an
offset error. These currents remain low over the full temperature
range and supply voltages.

The common-mode range of the X, Y, and Z inputs does not
fully extend to the supply rails. Nevertheless, it is often possible
to operate the AD734 with one terminal of an input pair con­nected to either the positive or negative supply, unlike previous
multipliers. The common-mode resistance is several megohms.

The full-scale output of ±10 V can be delivered to a load resistance
of 1 kΩ (although the specifications apply to the standard multi­plier load condition of 2 kΩ). The output amplifier is stable,
driving capacitive loads of at least 100 pF, when a slight increase
in bandwidth results from the peaking caused by this capacitance.
The 450 V/μs slew rate of the AD734 output amplifier ensures
that the bandwidth of 10 MHz can be maintained up to the full
output of 20 V p-p. Operation at reduced supply voltages is
possible, down to ±8 V, with reduced signal levels.

AVAILABLE TRANSFER FUNCTIONS

The uncommitted (open-loop) transfer function of the AD734 is

)

−−

⎧

=

AW

⎨

O

⎩

where A
72 dB. When a negative feedback path is provided, the circuit
forces the quantity inside the brackets essentially to zero,
resulting in the equation

This is the most useful generalized transfer function for the
AD734; it expresses a balance between the product XY and the
product UZ. The absence of the output, W, in this equation only
reflects the fact that the input to be connected to the op amp
output is not specified.

is the open-loop gain of the output op amp, typically

O

(X

− X2)(Y1 − Y2) = U (Z1 − Z2) (2)

1

YYXX

2121

U

(

⎫

)

−−

ZZ

(1)

⎬

21

⎭

AD734

(

)

Most of the functions of the AD734 (including division, unlike
the AD534 in this respect) are realized with Z1 connected to W.
Therefore, substituting W in place of Z

in Equation 2 results in

1

an output.

))((

YYXX

−−

2121

(3)

W +

=

U

Z

2

The free input, Z2, can be used to sum another signal to the
output; in the absence of a product signal, W simply follows the
voltage at Z2 with the full 10 MHz bandwidth. When not needed
for summation, Z2 should be connected to the ground
associated with the load circuit. The allowable polarities can be
shown in the following shorthand form:

YX

±±

))((

W ±+

=±

)(

U

+

)(

Z

(4)

In the recommended direct divider mode, the Y input is set to a
fixed voltage (typically 10 V) and U is varied directly; it can have
any value from 10 mV to 10 V. The magnitude of the ratio X/U
cannot exceed 1.25; for example, the peak X input for U = 1 V is
±1.25 V. Above this level, clipping occurs at the positive and
negative extremities of the X input. Alternatively, the AD734
can be operated using the standard (AD534) divider connections
(see Figure 27), when the negative feedback path is established
via the Y2 input. Substituting W for Y

ZZ

−

12

UW +

= (5)

()

Y

1

XX

−

21

in Equation 2,

2

In this case, note that the variable X is now the denominator,
and the previous restriction (X/U ≤ 1.25) on the magnitude of
the X input does not apply. However, X must be positive for the
feedback polarity to be correct. Y

can be used for summing

1

purposes or connected to the load ground if not needed. The
shorthand form in this case is

)(

Z

±

)()( Y

UW ±+

+=±

X

+

)(

)(

(6)

In some cases, feedback can be connected to two of the available
inputs. This is true for the square-rooting connections (see
Figure 28), where W is connected to both X1 and Y2. Set X
W and Y
again providing a summing input, set X

= W in Equation 2, and anticipating the possibility of

2

= S and Y1 = S, so that,

2

=

1

in shorthand form,

)())(()( SZUW ±+++=±

(7)

This is seen more generally to be the geometric-mean function,
because both U and Z can be variable; operation is restricted to
one quadrant. Feedback can also be taken to the U interface.
Full details of the operation in these modes is provided in the
Wideband RMS-to-DC Converter Using U Interface section.

DIRECT DENOMINATOR CONTROL

A valuable new feature of the AD734 is the provision to replace
the internal denominator voltage, U, with any value from 10 mV to
10 V. This can be used

• To simply alter the multiplier scaling, thus improve accu-

racy and achieve reduced noise levels when operating with
small input signals.

• To implement an accurate two-quadrant divider, with a

1000:1 gain range and an asymptotic gain-bandwidth
product of 200 MHz.

• To achieve certain other special functions, such as

AGC or rms.

Figure 21 shows the internal circuitry associated with
denominator control. Note, first, that the denominator is
actually proportional to a current, Iu, having a nominal value of

LINK TO
DISABLE

BE

,

ve a

V

00827-004

. For

356 μA for U = 10 V, whereas the primary reference is a voltage
generated by a buried-Zener circuit and laser-trimmed to ha
very low temperature coefficient. This voltage is nominally 8

Iu

.

NOMINAL LY
356µA for
U = 10V

Qd

Rd
NOM

22.5kΩ

+

AD734

Rr
100kΩ

TC

Qr
NOM
8V

NEGATIVE SUPPLY

VP

14

13

DD

ER

9

VN

8

with a tolerance of ±10%

3

U0

U1

U2

Qu

4

Ru
28kΩ

5

Figure 21. Denominator Control Circuitry

After temperature-correction (block TC), the reference voltage
is applied to Transistor Qd and trimmed Resistor Rd, which
generate the required reference current. Transistor Qu and
Resistor Ru are not involved in setting up the internal denomina­tor, and their associated control pins, U0, U1, and U2, are
normally grounded. The reference voltage is also made
available, via the 100 kΩ resistor, Rr, at Pin 9 (ER).

When the control pin, DD (denominator disable), is connected
to VP, the internal source of Iu is shut off, and the collector
current of Qu must provide the denominator current. The resistor
Ru is laser-trimmed such that the multiplier denominator is
exactly equal to the voltage across it (that is, across Pin U1 and
Pin U2). Note that this trimming only sets up the correct
internal ratio; the absolute value of Ru (nominally 28 kΩ) has a
tolerance of ±20%. Also, the alpha of Qu (typically 0.995), which
may be seen as a source of scaling error, is canceled by the alpha of
other transistors in the complete circuit.

In the simplest scheme (see Figure 22), an externally provided
control voltage, V

, is applied directly to U0 and U2 and the

G

resulting voltage across Ru is therefore reduced by one V
example, when V

= 2 V, the actual value of U is about 1.3 V.

G

Rev. E | Page 11 of 20

AD734

X

This error is not important in some closed-loop applications,
such as automatic gain control (AGC), but clearly is not acceptable
where the denominator value must be well-defined. When it is
required to set up an accurate, fixed value of U, the on-chip
reference can be used. The transistor Qr is provided to cancel
the V

of Qu, and is biased by an external resistor, R2, as shown

BE

in Figure 23. R1 is chosen to set the desired value of U and
consists of a fixed and adjustable resistor.

Iu

AD734

NC

U0

3

Qu

U1

4

Ru

U2

5

28kΩ

+

V

G

–

Figure 22. Low Accuracy Denominator Control

Iu

AD734

U0

3

Qu

U1

4

Ru

U2

5

NC

R1

28kΩ

NOM
8V

Figure 23. Connections for a Fixed Denominator

Rr
100kΩ

Rr
100kΩ

VP

14

DD

13

ER

9

Qr

VN

8

VP

14

DD

13

ER

9

Qr

VN

8

NC

–V

R2

+V

~60µA

S

+V

–V

S

00827-005

S

S

Tabl e 5 shows useful values of the external components for
setting up nonstandard denominator values.

Table 5. Component Values for Setting Up Nonstandard
Denominator Values

Denominator R1 (Fixed) R1 (Variable) R2

5 V 34.8 kΩ 20 kΩ 120 kΩ
3 V 64.9 kΩ 20 kΩ 220 kΩ
2 V 86.6 kΩ 50 kΩ 300 kΩ
1 V 174 kΩ 100 kΩ 620 kΩ

The denominator can also be current controlled, by grounding
Pin 3 (U0) and withdrawing a current of Iu from Pin 4 (U1).
The nominal scaling relationship is U = 28 × Iu, where u is
expressed in volts and Iu is expressed in milliamps. Note,
however, that while the linearity of this relationship is very
good, it is subject to a scale tolerance of ±20%. Note that the
common-mode range on Pin 3 through Pin 5 actually extends
from 4 V to 36 V below VP; therefore, it is not necessary to
restrict the connection of U0 to ground to use some other
voltage.

The output ER can also be buffered, rescaled, and used as a
general-purpose reference voltage. It is generated with respect
to the negative supply line, Pin 8 (VN), but this is acceptable
when driving one of the signal interfaces. An example is shown

Rev. E | Page 12 of 20

00827-006

in Figure 31, where a fixed numerator of 10 V is generated for a
divider application. Y2 is tied to VN, but Y1 is 10 V above this;
therefore, the common-mode voltage at this interface is still 5 V
above VN, which satisfies the internal biasing requirements (see
Tabl e 1).

OPERATION AS A MULTIPLIER

All of the connection schemes used in this section are essentially
identical to those used for the AD534, with which the AD734 is
pin compatible. The only precaution to be noted in this regard
is that in the AD534, Pin 3, Pin 5, Pin 9, and Pin 13 are not
internally connected, and Pin 4 has a slightly different purpose.
In many cases, an AD734 can be directly substituted for an
AD534 with immediate benefits in static accuracy, distortion,
feedthrough, and speed. Where Pin 4 was used in an AD534
application to achieve a reduced denominator voltage, this
function can now be much more precisely implemented with
the AD734 using alternative connections (see the Direct
Denominator Control section).

Operation from supplies down to ±8 V is possible. The supply
current is essentially independent of voltage. As is true of all
high speed circuits, careful power supply decoupling is important
in maintaining stability under all conditions of use. The decoupling
capacitors should always be connected to the load ground,
because the load current circulates in these capacitors at high
frequencies. Note the use of the special symbol (a triangle with
the letter L inside it) to denote the load ground (see Figure 24).

Standard Multiplier Connections

Figure 24 shows the basic connections for multiplication. The X
and Y inputs are shown as optionally having their negative nodes
grounded, but they are fully differential, and in many applications
the grounded inputs can be reversed (to facilitate interfacing
with signals of a particular polarity, while achieving some desired
output polarity) or both can be driven.

The AD734 has an input resistance of 50 kΩ ± 20% at the X, Y,
and Z interfaces, which allows ac coupling to be achieved with
moderately good control of the high-pass (HP) corner frequency;
a capacitor of 0.1 μF provides a HP corner frequency of 32 Hz.
When a tighter control of this frequency is needed, or when the
HP corner is above about 100 kHz, an external resistor should
be added across the pair of input nodes.

+15V

13

NC

NC

0.1µF

L

0.1µF

–15V

12

W

11

Z1

10

Z2

W =

LOAD
GROUND

OPTIONAL

L

SUMMING INPUT
±10V FS

(X1 – X2)(Y1 –Y2)

10V

Z

2

+ Z

2

INPUT

±10V FS

Y INPUT

±10V FS

AD734

X11

VP 14

X22

DD

3

U0

4

U1

5

U2

Y16

ER 9

Y27

VN 8

Figure 24. Basic Multiplier Circuit

00827-007

AD734

V

At least one of the two inputs of any pair must be provided with
a dc path (usually to ground). The careful selection of ground
returns is important in realizing the full accuracy of the AD734.
The Z2 pin is normally connected to the load ground, which can be
remote in some cases. It can also be used as an optional summing
input (see Equation 3 and Equation 4) having a nominal FS
input of ±10 V and the full 10 MHz bandwidth.

In applications where high absolute accuracy is essential, the
scaling error caused by the finite resistance of the signal source(s)
may be troublesome; for example, a 50 Ω source resistance at
just one input introduces a gain error of −0.1%; if both the X
and Y inputs are driven from 50 Ω sources, the scaling error in
the product is −0.2%. If the source resistances are known, this
gain error can be completely compensated by including the
appropriate resistance (50 Ω or 100 Ω, respectively, in the
preceding cases) between the output, W (Pin 12), and the Z1
feedback input (Pin 11). If Rx is the total source resistance
associated with the X1 and X2 inputs, and Ry is the total source
resistance associated with the Y1 and Y2 inputs, and neither Rx
nor Ry exceeds 1 kΩ, a resistance of Rx + Ry in series with
Pin Z1 provides the required gain restoration.

Pin 9 (ER) and Pin 13 (DD) should be left unconnected in this
application. The U inputs (Pin 3, Pin 4, and Pin 5) are shown
connected to ground; they can alternatively be connected to
VN, if desired. In applications where Pin 2 (X2) happens to
be driven with a high amplitude, high frequency signal, the
capacitive coupling to the denominator control circuitry via
an ungrounded Pin 3 can cause high frequency distortion.
However, the AD734 can be operated without modification in

AD534 socket and these three pins left unconnected with the

an
preceding caution noted.

+15

X INPUT

±10V FS

Y INPUT

±10V FS

AD734

X1

1

2

U0

3

U1

4

U2

5

6

Y1

Y2

7

Figure 25. Conversion of Output to a Current

VP

X2

DD

W

Z1

Z2

ER

VN

0.1µF

14

13

12

11

10

9

8

–15V

NC

NC

0.1µF

IW =

R

L

S

L

(X

– X2)(Y1 –Y2)

1

10V

LOAD

L

1

R

S

I

W

±10mA MAX FS

±10V MAXIMUM
LOAD VOLTAGE

+

1

50kΩ

Current Output

It may occasionally be desirable to convert the output voltage to
a current. In correlation applications, for example, multiplication is
followed by integration; if the output is in the form of a current,
a simple grounded capacitor can perform this function. Figure 25
shows how this can be achieved. The op amp forces the voltage
across Z1 and Z2, and thus across the resistor, RS, to be the
product XY/U. Note that the input resistance of the Z interface
is in shunt with RS, which must be calculated accordingly.

0827-008

The smallest FS current is simply ±10 V/50 kΩ, or ±200 μA,
with a tolerance of about 20%. To guarantee a 1% conversion
tolerance without adjustment, R

must be less than 2.5 kΩ. The

S

maximum full-scale output current should be limited to about
±10 mA (thus, R

= 1 kΩ). This concept can be applied to all

S

connection modes, with the appropriate choice of terminals.

Squaring and Frequency-Doubling

Squaring of an input signal, E, is achieved by connecting the X
and Y inputs in parallel; the phasing can be chosen to produce
an output of E

2

/U or −E2/U as desired. The input can have
either polarity, but the basic output is either always positive or
negative; as for multiplication, the Z2 input can be used to add a
further signal to the output.

When the input is a sine wave, a squarer behaves as a frequency
doubler, because

(Esinwt)2 = E2 (1 − cos2wt)/2 (8)

Equation 8 shows a dc term at the output, which varies strongly
with the amplitude of the input, E. This dc term can be avoided
using the connection shown in Figure 26, where an RC network
is used to generate two signals whose product has no dc term.
The output is

⎞

W

E

⎧

4

⎨
⎩

⎛

+=

sin

wt

⎜
⎝

2

E

⎧

⎫

⎞
⎟

⎨

⎬

4

⎠

⎩

⎭

⎛

sin

wt

⎜
⎝

2

⎛

ππ

1

⎫

⎞

−

⎟

4

⎠

⎟

⎜
⎜
⎝

(9)

⎟

V10

⎠

⎬
⎭

for w = 1/CR1, which is just

2

(cos2wt)/(10 V) (10)

W = E

which has no dc component. To restore the output to ±10 V
when E = 10 V, a feedback attenuator with an approximate ratio
of 4 is used between W and Z1; this technique can be used
wherever it is desired to achieve a higher overall gain in the
transfer function.

The values of R3 and R4 include additional compensation for the
effects of the 50 kΩ input resistance of all three interfaces; R2 is
included for a similar reason. These resistor values should not
be altered without careful calculation of the consequences. With
the values shown, the center frequency f

is 100 kHz for C =

0

1 nF. The amplitude of the output is only a weak function of
frequency; the output amplitude is 0.5% too low at f = 0.9f
f = 1.1f

. The cross-connection is simply to produce the cosine

0

and

0

output with the sign shown in Equation 10; however, the sign in
this case is rarely important.

Rev. E | Page 13 of 20

AD734

V

V

V

−

−

R2

1.6kΩ

R1

1.6kΩ

Esinωt E2 cos2ωt/10V

C

1

2

3

4

5

6

7

AD734

X1

X2

U0

U1

U2

Y1

Y2

DD

VP

ER

VN

+15

0.1µF

14

13

W

12

Z1

11

Z2

10

9

8

NC

NC

–15V

0.1µF

L

R3
13kΩ

R4

4.32kΩ

L

L

0827-009

Figure 26. Frequency Doubler

OPERATION AS A DIVIDER

The AD734 supports two methods for performing analog
division. The first is based on the use of a multiplier in a
feedback loop. This is the standard mode recommended for
multipliers having a fixed scaling voltage, such as the AD534,
and is described in this section. The second uses the AD734’s
unique capability for externally varying the scaling (denominator)
voltage directly, and is described in the Division by Direct
Denominator Control section.

Feedback Divider Connections

Figure 27 shows the connections for the standard (AD534)
divider mode. Feedback from the output, W, is now taken to the
Y2 (inverting) input, which, if the X input is positive, establishes a
negative feedback path. Y1 should normally be connected to the
ground associated with the load circuit, but can optionally be
used to sum a further signal to the output. If desired, the
polarity of the Y input connections can be reversed, with W
connected to Y1 and Y2 used as the optional summation input. In
this case, either the polarity of the X input connections must be
reversed or the X input voltage must be negative.

+15

AD734

X INPUT

+0.1V TO

+10V

OPTIONAL

SUMMING

INPUT

±10V FS

Y

1

1

X1

X2

2

U0

3

U1

4

U2

5

Y1

6

7

L

Y2

VP

DD

W

Z1

Z2

ER

VN

Figure 27. Standard (AD534) Divider Connection

The numerator input, which is differential and can have either
polarity, is applied to Pin Z1 and Pin Z2. As with all dividers
based on feedback, the bandwidth is directly proportional to
the denominator, being 10 MHz for X = 10 V and reducing to
100 kHz for X = 100 mV. This reduction in bandwidth, and
the increase in output noise (which is inversely proportional
to the denominator voltage) preclude operation much below a
denominator of 100 mV. Division using direct control of the
denominator (see Figure 29) does not have these shortcomings.

14

13

12

11

10

9

8

NC

NC

–15V

0.1µF

Z INPUT
±10V FS

0.1µF

L

W = 10 +Y1

L

– Z1)

(Z

2

(X

– X2)

1

VP

DD

ER

VN

+15

0.1µF

14

13

W

12

Z1

11

10

Z2

9

8

–15V

NC

NC

D

–

Z INPUT

+

+10mV TO
+10V

0.1µF

L

W = (10V) (Z

L

– Z1) + S

2

00827-011

AD734

X1

1

2

X2

U0

3

OPTIONAL

SUMMING

INPUT

±10V FS

S

L

U1

4

5

U2

6

Y1

Y2

7

Figure 28. Connection for Square Rooting

Connections for Square-Rooting

The AD734 can be used to generate an output proportional to
the square root of an input using the connections shown in
Figure 28. Feedback is now via both the X and Y inputs, and is
always negative because of the reversed polarity between these
two inputs. The Z input must have the polarity shown, but
because it is applied to a differential port, either polarity of
input can be accepted with reversal of Z1 and Z2, if necessary.
The diode, D, which can be any small-signal type (1N4148
being suitable), is included to prevent a latching condition,
which can occur if the input is momentarily of the incorrect
polarity of the input. The output is always negative.

Note that the loading on the output side of the diode is provided
by the 25 kΩ of input resistance at X1 and Y2, and by the user’s
load. In high speed applications, it may be beneficial to include
further loading at the output (to 1 kΩ minimum) to speed up
response time. As in previous applications, a further signal, shown
in Figure 28 as S, can be summed to the output; if this option is
not used, this node should be connected to the load ground.

DIVISION BY DIRECT DENOMINATOR CONTROL

The AD734 can be used as an analog divider by directly varying
the denominator voltage. In addition to providing much higher
accuracy and bandwidth, this mode also provides greater
flexibility, because all inputs remain available. Figure 29 shows
the connections for the general case of a three-input multiplier
divider, providing the function

))((

YYXX

2121

= (11)

W +

00827-010

where the
but the difference U = U

X, Y, and Z signals can all be positive or negative,

)(

UU

−

21

10 mV to 10 V. If a negative denominator voltage must be used,
simply ground the noninverting input of the op amp. As previ­ously noted, the X input must have a magnitude of less than 1.25U.

Z

2

− U2 must be positive and in the range

1

Rev. E | Page 14 of 20

AD734

V

+1V

X INPUT

U INPUT

Y INPUT

AD734

1

X1

X2

2MΩ

2

3

4

5

6

7

U

1

U

2

DD

U0

U1

U2

Y1

Y2

VP

ER

VN

+15V

14

13

0.1µF

W

12

Z1

11

L

10

Z2

NC

9

0.1µF

8

–15V

W =

LOAD
GROUND

L

(X1 – X2)(Y1 –Y2)

– U

U

1

2

Z

2

OPTIONAL
SUMMING
INPUT
±10V FS

+ Z

2

Figure 29. Three-Variable Multiplier/Divider Using Direct Denominator

Control

This connection scheme can also be viewed as a variable-gain
element, whose output, in response to a signal at the X input, is
controllable by both the Y input (for attenuation, using Y less
than U) and the U input (for amplification, using U less than
Y). The ac performance is shown in Figure 30; for these results,
Y was maintained at a constant 10 V. At U = 10 V, the gain is
unity and the circuit bandwidth is a full 10 MHz. At U = 1 V,
the gain is 20 dB and the bandwidth is essentially unaltered. At
U = 100 mV, the gain is 40 dB and the bandwidth is 2 MHz.
Finally, at U = 10 mV, the gain is 60 dB and the bandwidth is
250 kHz, corresponding to a 250 MHz gain-bandwidth product.

70

U = 10mV

60

50

U = 100mV

40

30

U

=

1

U = 10V

V

00827-013

FREQUENCY (Hz)

GAIN (IdB)

20

10

0

10k 100k 1M 10M

Figure 30. Three-Variable Multiplier/Divider Performance

The 2 MΩ resistor is included to improve the accuracy of the
gain for small denominator voltages. At high gains, the X input
offset voltage can cause a significant output offset voltage. To
eliminate this problem, a low-pass feedback path can be used
from W to X2; see Figure 32 for details.

Where a numerator of 10 V is needed, to implement a two­quadrant divider with fixed scaling, the connections shown in
Figure 31 can be used. The reference voltage output appearing
between Pin 9 (ER) and Pin 8 (VN) is amplified and buffered by
the second op amp, to impose 10 V across the Y1/Y2 input.
Note that Y2 is connected to the negative supply in this application.
This is permissible because the common-mode voltage is still
high enough to meet the internal requirements.

The transfer function is

⎛
⎜

= (12)

10 Z

VW +

⎜
⎝

⎞

−

XX

21

⎟

2

⎟

−

UU

21

⎠

The ac performance of this circuit remains as shown in Figure 30.

AD734

1

X1

X INPUT

00827-012

U INPUT

200kΩ

U

1

U

2

100kΩ

SCALE

AJDUST

2MΩ

2

3

4

5

6

7

VP

X2

DD

U0

W

U1

Z1

U2

Z2

Y1

ER

Y2

VN

Figure 31. Two-Quadrant Divider with Fixed 10 V Scaling

+15

14

13

12

11

10

9

8

0.1µF

L

0.1µF

–15V

OP AMP = AD712 DUAL

W =

LOAD
GROUND

L

(X1 – X2)10V

U

– U

1

2

Z

2

OPTIONAL
SUMMING
INPUT
±10V FS

+ Z

2

00827-014

A PRECISION AGC LOOP

The variable denominator of the AD734 and its high gain
bandwidth product make it an excellent choice for precise
automatic gain control (AGC) applications. Figure 32 shows a
suggested method. The input signal, E
amplitude from 10 mV to 10 V at any frequency from 100 Hz to
10 MHz, is applied to the X input and a fixed positive voltage E
to the Y input. Op Amp A2 and Capacitor C2 form an integrator
with a current summing node at its inverting input. (The AD712
dual op amp is a suitable choice for this application.) In the absence
of an input, the current in D2 and R2 causes the integrator output
to ramp negative, clamped by Diode D3, which is included to
reduce the time required for the loop to establish a stable,
calibrated, output level after the circuit has received an input
signal. With no input to the denominator (U0 and U2), the gain
of the AD734 is very high (about 70 dB), and thus even a small
input causes a substantial output.

R3

NC

2

4

7

1MΩ

AD734

X11

X2

U03

U1

U25

Y16

Y2

E

+10V

IN

1N914

E

C

TO

1µF

D3

C1

C2

1µF

D2
1N914

R2

1MΩR11MΩ

A1

A2

Figure 32. Precision AGC Loop

Diode D1 and C1 form a peak detector, which rectifies the output
and causes the integrator to ramp positive. When the current in
R1 balances the current in R2, the integrator output holds the
denominator output at a constant value. This occurs when there

, which can have a peak

IN

+15V

VP 14

0.1µF

L

0.1µF

D1
1N914

C1

1µF

13

DD

W 12

11

Z1

Z2 10

ER 9

8

VN

–15V

OP AMP = AD712 DUAL

C

E

OUT

L

00827-015

Rev. E | Page 15 of 20

AD734

V

is sufficient gain to raise the amplitude of EIN to that required to
establish an output amplitude of E

over the range of 1 V to 10 V.

C

The X input of the AD734, which has finite offset voltage, can be
troublesome at the output at high gains. The output offset is
reduced to that of the X input (1 mV or 2 mV) by the offset
loop comprising R3, C3, and Buffer A1. The low-pass corner
frequency of 0.16 Hz is transformed to a high-pass corner that is
multiplied by the gain (for example, 160 Hz at a gain of 1000).

In applications not requiring operation down to low frequencies,
Amplifier A1 can be eliminated, but the AD734’s input resistance
of 50 kΩ between X1 and X2 reduces the time constant and
increases the input offset. Using a nonpolar 20 mF tantalum
capacitor for C1 results in the same unity-gain high-pass corner; in
this case, the offset gain increases to 20, which is still acceptable.

Figure 33 shows the error in the output for sinusoidal inputs at
100 Hz, 100 kHz, and 1 MHz, with E

set to 10 V. The output

C

error for any frequency between 300 Hz and 300 kHz is similar
to that for 100 kHz. At low signal frequencies and low input
amplitudes, the dynamics of the control loop determine the gain
error and distortion; at high frequencies, the 200 MHz gain­bandwidth product of the AD734 limits the available gain.

The output amplitude tracks E

over the range of 1 V to slightly

C

more than 10 V.

2

1

100kHz

0

ERROR (dB)

–1

100Hz

1MHz

+15

0.1µF

L

R1

3.32kΩ

C1

47µF

10

9

8

–15V

L

L

0.1µF

L

C2
1µF

U2b

1/2

AD708

VO = V

2

IN

L

U2a

L

L

5

7

AD734

X11

X22

U03

U14

U2

Y16

Y2

VP 14

DD 13

W 12

Z1 11

Z2

ER

VN

V

IN

1/2

AD708

Figure 34. A Two-Chip, Wideband RMS-to-DC Converter

In this application, the AD734 and an AD708 dual op amp
serve as a two-chip rms-to-dc converter with a 10 MHz
bandwidth. Figure 35 shows the circuit’s performance for
square-, sine-, and triangle-wave inputs. The circuit accepts
signals as high as 10 V p-p with a crest factor of 1 or 1 V p-p
with a crest factor of 10. The circuit’s response is flat to 10 MHz
with an input of 10 V, flat to almost 5 MHz for an input of 1 V,
and to almost 1 MHz for inputs of 100 mV. For accurate
measurements of input levels below 100 mV, the AD734’s
output offset (Z interface) voltage, which contributes a dc error,
must be trimmed out.

In the circuit shown in Figure 34, the AD734 squares the input
signal, and its output (V

2

) is averaged by a low-pass filter that

IN

consists of R1 and C1 and has a corner frequency of 1 Hz. Because
of the implicit feedback loop, this value is both the output value,
V

, and the denominator in Equation 13. U2a and U2b, an

RMS

AD708 dual dc precision op amp, serve as unity-gain buffers,
supplying both the output voltage and driving the U interface.

100

10

1

00827-017

–2

0.01 0.1 1 10
INPUT AMPLITUDE (V)

Figure 33. AGC Amplifier Output Error vs. Input Voltage

WIDEBAND RMS-TO-DC CONVERTER USING U INTERFACE

The AD734 is well-suited to such applications as implicit rms­to-dc conversion, where the AD734 implements the function

2

[]

avg

V

= (13)

V

RMS

using its direct divide mode. Figure 34 shows the circuit.

IN

V

RMS

00827-016

Rev. E | Page 16 of 20

100m

10m

OUTPUT VOLTAGE (V)

SQUARE WAVE

1m

100µ

SINE WAVE

TRI-WAVE

10k 100k 1M 10M

INPUT FREQUENCY (Hz)

Figure 35. RMS-to-DC Converter Performance

00827-018

AD734

m

V

m

LOW DISTORTION MIXER

The AD734’s low noise and distortion make it especially suitable
for use a s a mixe r, modu l ator, or demodulator. Althou g h the
AD734’s −3 dB bandwidth is typically 10 MHz and is established
by the output amplifier, the bandwidth of its X and Y interfaces
and the multiplier core are typically in excess of 40 MHz. Thus,
provided that the desired output signal is less than 10 MHz, as
is typically the case in demodulation, the AD734 can be used
with both its X and Y input signals as high as 40 MHz. One test
of mixer performance is to linearly combine two closely spaced,
equal-amplitude sinusoidal signals and then mix them with a
third signal to determine the mixer’s two-tone, third-order
intermodulation products.

DD

VP

ER

VN

+15

0.1µF

14

13

W

12

Z1

11

Z2

10

2kΩ

9

0.1µF

8

–15V

HP3585A

WITH 10X PROBE
dBm REF TO 50Ω

HP3326A

COMBINE

A + B

OP177

DATEL

DVC-8500

HP3326A

HIGH VOLTAGE

OPTION

1

2

3

4

5

6

7

AD734

X1

X2

U0

U1

U2

Y1

Y2

Figure 36. AD734 Mixer Test Circuit

Figure 36 shows a test circuit for measuring the AD734’s
performance in this regard. In this test, two signals, at 10.05 MHz
and 9.95 MHz, are summed and applied to the AD734 X
interface. A second 9 MHz signal is applied to the AD734 Y
interface. The voltage at the U interface is set to 2 V to use the
full dynamic range of the AD734; that is, by connecting the W
and Z1 pins together, grounding the Y2 and X2 pins, and setting
U = 2 V, the overall transfer function is

YX

11

W

=

(14)

V

2

00827-019

Figure 37. AD734 Third-Order Intermodulation Performance for f1 =

The possible two-tone intermodulation products are at 2 ×

9.95 MHz − 10.05 MHz ± 9.00 MHz and 2 × 10.05 − 9.95 MHz
± 9.00 MHz; of these, only the third-order products at 0.850 MHz
and 1.150 MHz are within the 10 MHz bandwidth of the AD734;
the desired output signals are at 0.950 MHz and 1.050 MHz.
Note that the difference between the desired outputs and third­order products (see Figure 37) is approximately 78 dB, which
corresponds to a computed third-order intercept point of +46 dBm.

9.95 MHz, f

6 dBm and f

REF – 10.0 dB
10dB/DIV

CENTER 990 000. 0Hz
RBW 1kHz

= 10.05 MHz, and f0 = 9.00 MHz and for Signal Levels of f1 = f2 =

2

= +24 dBm (All Displayed Signal Levels Are Attenuated 20 dB by

0

RANGE – 5.0dBm

VBW 30Hz

the 10X Probe Used to Measure the Mixer’s Output)

REF – 10.0 dB
10dB/DIV

RANGE – 10.0dBm

MARKER 950 000.0Hz

MARKER 950 000.0Hz

– 15.8dBm

SPAN 500 000.0Hz

ST 47.0sec

– 21.8dBm

00827-020

and W can be as high as 20 V p-p when X1 = 2 V p-p and Y1 =
10 V p-p. The 2 V p-p signal level corresponds to 10 dBm into a
50 Ω input termination resistor connected from X1 or Y1 to
ground.

If the two X1 inputs are at Frequency f
frequency at the Y1 input is f

, then the two-tone third-order

0

intermodulation products should appear at Frequency 2f
f

and Frequency 2f2 – f1 ± f0. Figure 37 and Figure 38 show the

0

output spectra of the AD734 with f
and f

= 9.00 MHz for a signal level of f1 = f2 = 6 dBm and f0 =

0

+24 dBm in Figure 37 and f

= f2 = 0 dBm and f0 = +24 dBm in

1

and Frequency f2 and the

1

– f2 ±

1

= 9.95 MHz, f2 = 10.05 MHz,

1

CENTER 990 000. 0Hz
RBW 1kHz

VBW 10Hz

Figure 38. AD734 Third-Order Intermodulation Performance for f

9.95 MHz, f

0 dBm and f

= 10.05 MHz, and f0 = 9.00 MHz and for Signal Levels of f1 = f2 =

2

= +24 dBm (All Displayed Signal Levels Are Attenuated 20 dB by

0

the 10X Probe Used to Measure the Mixer’s Output)

SPAN 500 000.0Hz

ST 156sec

00827-021

=

1

Figure 38. This performance is without external trimming of
the AD734 X and Y input offset voltages.

Rev. E | Page 17 of 20

AD734

OUTLINE DIMENSIONS

0.775 (19.69)

0.750 (19.05)

0.735 (18.67)

0.210 (5.33)

0.150 (3.81)

0.130 (3.30)

0.110 (2.79)

0.022 (0.56)

0.018 (0.46)

0.014 (0.36)

MAX

14

1

0.100 (2.54)
BSC

0.070 (1.78)

0.050 (1.27)

0.045 (1.14)

8

7

0.280 (7. 11)

0.250 (6.35)

0.240 (6.10)

0.015
(0.38)
MIN

SEATING
PLANE

0.005 (0.13)
MIN

0.060 (1.52)
MAX

0.015 (0.38)
GAUGE

PLANE

0.325 (8.26)

0.310 (7.87)

0.300 (7.62)

0.430 (10.92)
MAX

0.195 (4.95)

0.130 (3.30)

0.115 (2.92)

0.014 (0.36)

0.010 (0.25)

0.008 (0.20)

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSI ONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUI VALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE I N DESIGN.
CORNER LEADS M AY BE CONFIGURED AS WHO LE OR HALF LEADS.

COMPLIANT TO JEDEC STANDARDS MS-001

070606-A

Figure 39. 14-Lead Plastic Dual In-Line Package [PDIP]

Narrow Body

(N-14)

Dimensions shown in inches and (millimeters)

0.005 (0.13) MIN

PIN 1

0.785 (19.94) MAX

0.200 (5.08)
MAX

0.200 (5.08)

0.125 (3.18)

0.023 (0.58)

0.014 (0.36)

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

Figure 40. 14-Lead Ceramic Dual In-Line Package [CERDIP]

Dimensions shown in inches and (millimeters)

0.098 (2.49) MAX

1

0.100 (2.54) BSC

0.070 (1.78)

0.030 (0.76)

814

7

0.310 (7.87)

0.220 (5.59)

0.060 (1.52)

0.015 (0.38)

SEATING
PLANE

(Q-14)

0.150
(3.81)
MIN

0.320 (8.13)

0.290 (7.37)

15°

0°

0.015 (0.38)

0.008 (0.20)

Rev. E | Page 18 of 20

AD734

ORDERING GUIDE

Model1 Temperature Range Package Description Package Option

AD734AN −40°C to +85°C 14-Lead Plastic Dual In-Line Package [PDIP] N-14
AD734ANZ −40°C to +85°C 14-Lead Plastic Dual In-Line Package [PDIP] N-14
AD734BN −40°C to +85°C 14-Lead Plastic Dual In-Line Package [PDIP] N-14
AD734BNZ −40°C to +85°C 14-Lead Plastic Dual In-Line Package [PDIP] N-14
AD734AQ −40°C to +85°C 14-Lead Ceramic Dual In-Line Package [CERDIP] Q-14
AD734BQ −40°C to +85°C 14-Lead Ceramic Dual In-Line Package [CERDIP] Q-14
AD734SQ/883B −55°C to +125°C 14-Lead Ceramic Dual In-Line Package [CERDIP] Q-14
AD734SCHIPS −55°C to +125°C Die

1

Z = RoHS Compliant Part.

Rev. E | Page 19 of 20

AD734

NOTES

©2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00827-0-2/11(E)

Rev. E | Page 20 of 20