Datasheet AD7328 Datasheet (ANALOG DEVICES)

Page 1

8-Channel, Software-Selectable True

FEATURES

12-bit plus sign SAR ADC True bipolar input ranges Software-selectable input ranges

±10 V, ±5 V, ±2.5 V, 0 V to +10 V 1 MSPS throughput rate Eight analog input channels with channel sequencer Single-ended, true differential, and pseudo differential

analog input capability High analog input impedance Low power: 21 mW Temperature indicator Full power signal bandwidth: 22 MHz Internal 2.5 V reference High speed serial interface Power-down modes 20-lead TSSOP package

™

process technology

iCMOS

GENERAL DESCRIPTION

The AD73281 is an 8-channel, 12-bit plus sign, successive approximation ADC designed on the iCMOS (industrial CMOS) process. iCMOS is a process combining high voltage silicon with submicron CMOS and complementary bipolar technologies. It enables the development of a wide range of high performance analog ICs capable of 33 V operation in a footprint that no previous generation of high voltage parts could achieve. Unlike analog ICs using conventional CMOS processes, iCMOS components can accept bipolar input signals while providing increased performance, dramatically reduced power consumption, and reduced package size.

Bipolar Input, 12-Bit Plus Sign ADC

AD7328

FUNCTIONAL BLOCK DIAGRAM

AD7328

VIN0

VIN1

VIN2

VIN3

VIN4

VIN5

VIN6

VIN7

I/P

MUX

CHANNEL

SEQUENCER

AGND V

T/H

PRODUCT HIGHLIGHTS

1. The AD7328 can accept true bipolar analog input signals,

±10 V, ±5 V, ±2.5 V, and 0 V to +10 V unipolar signals.

2. The eight analog inputs can be configured as eight single-

ended inputs, four true differential input pairs, four pseudo differential inputs, or seven pseudo differential inputs.

3. 1 MSPS serial interface. SPI®-/QSPI™-/DSP-/MICROWIRE™-

compatible interface.

4. Low power, 30 mW, at a maximum throughput rate of

1 MSPS.

REFIN/OUT

2.5V

VREF

TEMPERAT URE

INDICATOR

Figure 1.

13-BIT

SUCCESSIVE

APPROXIMATION

ADC

CONTROL L OGIC AND REGIS TERS

DGND

DOUT

SCLK

DIN

DRIVE

04852-001

The AD7328 can accept true bipolar analog input signals. The AD7328 has four software-selectable input ranges, ±10 V, ±5 V, ±2.5 V, and 0 V to +10 V. Each analog input channel can be independently programmed to one of the four input ranges. The analog input channels on the AD7328 can be programmed to be single-ended, true differential, or pseudo differential.

The ADC contains a 2.5 V internal reference. The AD7328 also allows for external reference operation. If a 3 V reference is applied to the REFIN/OUT pin, the AD7328 can accept a true bipolar ±12 V analog input. Minimum ±12 V V

and VSS supplies are

required for the ±12 V input range. The ADC has a high speed serial interface that can operate at throughput rates up to 1 MSPS.

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

5. Channel sequencer.

Table 1. Similar Product Selection

Device Number

Throughput Rate

Number of Bits

Number of Channels

AD7329 1000 kSPS 12-bit plus sign 8 AD7327 500 kSPS 12-bit plus sign 8 AD7324 1000 kSPS 12-bit plus sign 4 AD7323 500 kSPS 12-bit plus sign 4 AD7322 1000 kSPS 12-bit plus sign 2 AD7321 500 kSPS 12-bit plus sign 2

Protected by U.S. Patent No. 6,731,232.

Page 2

AD7328

Features .............................................................................................. 1

Control Register ......................................................................... 22

General Description......................................................................... 1

Functional Block Diagram .............................................................. 1

Product Highlights........................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Timing Specifications .................................................................. 6

Absolute Maximum Ratings............................................................ 7

ESD Caution.................................................................................. 7

Pin Configuration and Function Descriptions............................. 8

Typical Performance Characteristics............................................. 9

Te r mi n ol o g y .................................................................................... 13

Theory of Operation ...................................................................... 15

Circuit Information.................................................................... 15

Converter Operation.................................................................. 15

Analog Input Structure.............................................................. 16

Sequence Register....................................................................... 24

Range Registers........................................................................... 24

Sequencer Operation ..................................................................... 25

Reference ..................................................................................... 27

............................................................................................ 27

DRIVE

Temperature Indicator............................................................... 27

Modes of Operation ....................................................................... 28

Normal Mode.............................................................................. 28

Full Shutdown Mode.................................................................. 28

Autoshutdown Mode................................................................. 29

Autostandby Mode ..................................................................... 29

Power vs. Throughput Rate....................................................... 30

Serial Interface................................................................................ 31

Microprocessor Interfacing ........................................................... 32

AD7328 to ADSP-21xx.............................................................. 32

Typical C o n n e ction Di a g r am ................................................... 18

Analog Input ............................................................................... 18

Driver Amplifier Choice............................................................ 20

Registers........................................................................................... 21

Addressing Registers.................................................................. 21

REVISION HISTORY

6/06—Rev. 0 to Rev. A

Changes to Table 1............................................................................ 1

Changes to Specifications................................................................ 3

Added Thermal Hysteresis to Terminology Section.................. 14

Change to Figure 42 ....................................................................... 20

Change to Control Register Section............................................. 23

10/05—Revision 0: Initial Version

AD7328 to ADSP-BF53x........................................................... 32

Application Hints ........................................................................... 33

Layout and Grounding .............................................................. 33

Outline Dimensions ....................................................................... 34

Ordering Guide .......................................................................... 34

Rev. A | Page 2 of 36

Page 3

AD7328

SPECIFICATIONS

Unless otherwise noted, VDD = 12 V to 16.5 V, VSS = −12 V to −16.5 V, VCC = 4.75 V to 5.25 V, V internal/external, f

= 20 MHz, fS = 1 MSPS, TA = T

SCLK

MAX

to T

. With VCC < 4.75 V, all specifications are typical.

MIN

Table 2.

B Version Parameter

DYNAMIC PERFORMANCE f

Signal-to-Noise Ratio (SNR)

Min Typ Max Unit Test Conditions/Comments

= 50 kHz sine wave

76 dB Differential mode

72.5 dB Single-ended/pseudo differential mode Signal-to-Noise + Distortion

(SINAD)

75 dB Differential mode; ±2.5 V and ±5 V ranges

76 dB Differential mode; 0 V to +10 V and ±10 V ranges 72 dB

Single-ended/pseudo differential mode; ±2.5 V and ±5 V ranges

72.5 dB

Single-ended/pseudo differential mode; 0 V to +10 V and ±10 V ranges

Total Harmonic Distortion (THD)2 −80 dB Differential mode; ±2.5 V and ±5 V ranges

−82 dB Differential mode; 0 V to +10 V and ±10 V ranges

−77 dB

Single-ended/pseudo differential mode; ±2.5 V and ±5 V ranges

−80 dB

Single-ended/pseudo differential mode; 0 V to +10 V and ±10 V ranges

Peak Harmonic or Spurious Noise

(SFDR)

−80 dB Differential mode; ±2.5 V and ±5 V ranges

−82 dB Differential mode; 0 V to +10 V and ±10 V ranges

−78 dB

Single-ended/pseudo differential mode; ±2.5 V and ±5 V ranges

−79 dB

Single-ended/pseudo differential mode; 0 V to +10 V and ±10 V ranges

Intermodulation Distortion (IMD)

fa = 50 kHz, fb = 30 kHz Second-Order Terms −88 dB Third-Order Terms

Aperture Delay Aperture Jitter Common-Mode Rejection Ratio

(CMRR)

Channel-to-Channel Isolation Full Power Bandwidth

−90 dB

7 ns

50 ps

−79 dB Up to 100 kHz ripple frequency; see Figure 17

−72 dB fIN on unselected channels up to 100 kHz; see Figure 14

22 MHz At 3 dB

5 MHz At 0.1 dB

DC ACCURACY

All specifications are typical for 0 V to 10 V mode.

Resolution 13 Bits No Missing Codes

12-bit

Bits Differential mode

plus sign

11-bit

Bits Single-ended/pseudo differential mode

plus sign

Integral Nonlinearity

±1.1 LSB Differential mode

±1 LSB Single-ended/pseudo differential mode

−0.7/+1.2 LSB

Single-ended/pseudo differential mode (LSB = FSR/8192)

Differential Nonlinearity

−0.9/+1.5 LSB

Differential mode; guaranteed no missing codes to 13 bits

±0.9 LSB

Single-ended mode; guaranteed no missing codes to 12 bits

−0.7/+1 LSB

Single-ended/psuedo differential mode (LSB = FSR/8192)

= 2.7 V to 5.25 V, V

DRIVE

= 2.5 V to 3.0 V

REF

Rev. A | Page 3 of 36

Page 4

AD7328

B Version Parameter

Offset Error

−7/+10 LSB Differential mode Offset Error Match ±0.5 LSB Differential mode Gain Error ±14 LSB Differential mode Gain Error Match ±0.5 LSB Differential mode Positive Full-Scale Error ±7 LSB Differential mode Positive Full-Scale Error Match ±0.5 LSB Differential mode Bipolar Zero Error ±7.5 LSB Differential mode Bipolar Zero Error Match ±0.5 LSB Differential mode Negative Full-Scale Error ±6 LSB Differential mode

Negative Full-Scale Error Match ±0.5 LSB Differential mode ANALOG INPUT

Input Voltage Ranges Reference = 2.5 V; see Table 6

±5 V VDD = 5 V min, VSS = −5 V min, VCC = 2.7 V to 5.25 V

±2.5 V VDD = 5 V min, VSS = − 5 V min, VCC = 2.7 V to 5.25 V

0 to 10 V VDD = 10 V min, VSS = AGND min, VCC = 2.7 V to 5.25 V

±3.5 V Reference = 2.5 V; range = ±10 V

±6 V Reference = 2.5 V; range = ±5 V

±5 V Reference = 2.5 V; range = ±2.5 V

+3/−5 V Reference = 2.5 V; range = 0 V to +10 V

DC Leakage Current ±200 nA VIN = VDD or V

Input Capacitance

16.5 pF When in track, ±5 V and 0 V to +10 V ranges

21.5 pF When in track, ±2.5 V range 3 pF When in hold, all ranges REFERENCE INPUT/OUTPUT

Input Voltage Range 2.5 3 V

Input DC Leakage Current ±1 μA

Input Capacitance 10 pF

Reference Output Voltage 2.5 V

Long Term Stability 150 ppm For 1000 hours

Output Voltage Hysteresis

Reference Output Voltage Error

Reference Output Voltage

Reference Temperature

6 ppm/°C

Reference Output Impedance 7 Ω

2, 5

2, 6

(Programmed via Range

Pseudo Differential VIN(−)

Input Range

@ 25°C

to T

MIN

MAX

Coefficient

Min Typ Max Unit Test Conditions/Comments

−4/+9 LSB Single-ended/pseudo differential mode

±0.6 LSB Single-ended/pseudo differential mode

±8 LSB Single-ended/pseudo differential mode

±0.5 LSB Single-ended/pseudo differential mode

±4 LSB Single-ended/pseudo differential mode

2, 6

±0.5 LSB Single-ended/pseudo differential mode

±8.5 LSB Single-ended/pseudo differential mode

±0.5 LSB Single-ended/pseudo differential mode

±4 LSB Single-ended/pseudo differential mode

2, 6

±0.5 LSB Single-ended/pseudo differential mode

±10 V V

= 10 V min, VSS = −10 V min, VCC = 2.7 V to 5.25 V

= 16.5 V, VSS = −16.5 V, VCC = 5 V; see Figure 40 and

Figure 41

13.5 pF When in track, ±10 V range

50 ppm ±5 mV

±10 mV

25 ppm/°C

Rev. A | Page 4 of 36

Page 5

AD7328

B Version Parameter

LOGIC INPUTS

Input High Voltage, V Input Low Voltage, V

0.4 V VCC = 2.7 to 3.6 V Input Current, I Input Capacitance, C

LOGIC OUTPUTS

Output High Voltage, V

Output Low Voltage, V Floating-State Leakage Current ±1 μA Floating-State Output

Output Coding Straight natural binary Coding bit set to 1 in control register Twos complement Coding bit set to 0 in control register CONVERSION RATE

Conversion Time 800 ns 16 SCLK cycles with SCLK = 20 MHz

Track-and-Hold Acquisition

Throughput Rate 1 MSPS See the Serial Interface section; VCC = 4.75 V to 5.25 V 770 kSPS VCC < 4.75 V POWER REQUIREMENTS Digital inputs = 0 V or V

Normal Mode (Static) 0.9 mA VDD/VSS = ±16.5 V, VCC/V

Normal Mode (Operational) f

Autostandby Mode (Dynamic) f

Autoshutdown Mode (Static) SCLK on or off

Full Shutdown Mode SCLK on or off

POWER DISSIPATION

Normal Mode 30 mW VDD = 16.5 V, VSS = −16.5 V, VCC = 5.25 V

21 mW VDD = 12 V, VSS = −12 V, VCC = 5 V

Full Shutdown Mode 38.25 μW VDD = 16.5 V, VSS = −16.5 V, VCC = 5.25 V

Temperature range is −40°C to +85°C.

See the Terminology section.

Sample tested during initial release to ensure compliance.

For dc accuracy specifications, the LSB size for differential mode is FSR/8192. For single-ended mode/pseudo differential mode, the LSB size is FSR/4096, unless otherwise noted.

Unipolar 0 V to 10 V range with straight binary output coding.

Bipolar range with twos complement output coding.

Capacitance

2, 3

Time

DRIVE

ICC and I

DRIVE

ICC and I

DRIVE

ICC and I

DRIVE

ICC and I

DRIVE

Min Typ Max Unit Test Conditions/Comments

INH

INL

2.4 V

0.8 V VCC = 4.75 V to 5.25 V

±1 μA V

= 0 V or V

DRIVE

10 pF

DRIVE

V I

−

SOURCE

= 200 μA

0.2

0.4 V I

5 pF

= 200 μA

SINK

305 ns Full-scale step input; see the Terminology section

DRIVE

12 16.5 V See Tabl e 6

−12 −16.5 V See Table 6

2.7 5.25 V See Table 6; typical specifications for VCC < 4.75 V

2.7 5.25 V = 5.25 V

DRIVE

= 1 MSPS

SAMPLE

360 μA VDD = 16.5 V 410 μA VSS = −16.5 V

3.2 mA VCC/V

SAMPLE

= 5.25 V

DRIVE

= 250 kSPS 200 μA VDD = 16.5 V 210 μA VSS = −16.5 V

1.3 mA VCC/V

DRIVE

= 5.25 V

1 μA VDD = 16.5 V 1 μA VSS = −16.5 V 1 μA VCC/V

DRIVE

= 5.25 V

1 μA VDD = 16.5 V 1 μA VSS = −16.5 V 1 μA VCC/V

Rev. A | Page 5 of 36

DRIVE

= 5.25 V

Page 6

AD7328

TIMING SPECIFICATIONS

VDD = 12 V to 16.5 V, VSS = −12 V to −16.5 V, VCC = 2.7 V to 5.25 V, V T

= T

to T

MAX

. Timing specifications apply with a 32 pF load, unless otherwise noted.

MIN

Table 3.

Limit at T

MIN

, T

MAX

Description

Parameter VCC < 4.75 V VCC = 4.75 V to 5.25 V Unit V

SCLK

50 50 kHz min 14 20 MHz max t

CONVER T

QUIET

16 × t

SCLK

16 × t

SCLK

ns max t 75 60 ns min 12 5 ns min

25 20 ns min

45 35 ns min Unipolar input range (0 V to 10 V) t

26 14 ns max 57 43 ns max Data access time after SCLK falling edge

0.4 × t

SCLK

0.4 × t

SCLK

ns min SCLK low pulse width

ns min SCLK high pulse width 13 8 ns min SCLK to data valid hold time 40 22 ns max SCLK falling edge to DOUT high impedance

10 9 ns min SCLK falling edge to DOUT high impedance t

POWER-UP

Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V ) and timed from a voltage level of 1.6 V.

When using the 0 V to 10 V unipolar range, running at 1 MSPS throughput rate with t at 20 ns, the mark space ratio needs to be limited to 50:50.

4 4 ns min DIN set-up time prior to SCLK falling edge 2 2 ns min DIN hold time after SCLK falling edge 750 750 ns max Power up from autostandby

500 500 μs max Power up from full shutdown/autoshutdown mode, internal reference

25 25 μs typ Power up from full shutdown/autoshutdown mode, external reference

= 2.7 V to 5.25 V, V

DRIVE

≤ V

DRIVE

= 1/f

SCLK

= 2.5 V to 3.0 V internal/external,

REF

Minimum time between end of serial read and next falling edge of Minimum

CS pulse width

CS to SCLK set-up time; bipolar input ranges (±10 V, ±5 V, ±2.5 V)

Delay from

CS until DOUT three-state disabled

DRIVE

QUIET

04852-002

SCLK

DOUT

DIN

THREE-

STATE

1 2 3 4 5 13 14 15 16

3 IDENTIFICATION BITS

ADD1

ADD2

WRITE

ADD0 SI GN DB11 DB10 DB2 DB1 DB0

REG

SEL2

MSB

SEL1

CONVERT

LSB

DON’T

CARE

THREE-STATE

Figure 2. Serial Interface Timing Diagram

Rev. A | Page 6 of 36

Page 7

AD7328

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted

Table 4.

Parameter Rating

VDD to AGND, DGND −0.3 V to +16.5 V VSS to AGND, DGND +0.3 V to −16.5 V VDD to V

VCC − 0.3 V to +16.5 V VCC to AGND, DGND −0.3 V to +7 V V

to AGND, DGND −0.3 V to +7 V

DRIVE

AGND to DGND −0.3 V to +0.3 V Analog Input Voltage to AGND

VSS − 0.3 V to VDD + 0.3 V Digital Input Voltage to DGND −0.3 V to +7 V Digital Output Voltage to GND −0.3 V to V

DRIVE

+ 0.3 V REFIN to AGND −0.3 V to VCC + 0.3 V Input Current to Any Pin

Except Supplies

±10 mA

Operating Temperature Range −40°C to +85°C Storage Temperature Range −65°C to +150°C Junction Temperature 150°C TSSOP Package

θJA Thermal Impedance 143°C/W θJC Thermal Impedance 45°C/W

Pb-Free Temperature, Soldering

Reflow 260(0)°C

ESD 2.5 kV

If the analog inputs are driven from alternative VDD and VSS supply circuitry,

Schottky diodes should be placed in series with the AD7328’s VDD and VSS supplies.

Transient currents of up to 100 mA do not cause SCR latch-up.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Rev. A | Page 7 of 36

Page 8

AD7328

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

REFIN/OUT

Table 5. Pin Function Descriptions

Pin No. Mnemonic Description

CS Chip Select. Active low logic input. This input provides the dual function of initiating conversions on

the AD7328 and frames the serial data transfer.

2 DIN

Data In. Data to be written to the on-chip registers is provided on this input and is clocked into the register on the falling edge of SCLK (see the

3, 19 DGND

Digital Ground. Ground reference point for all digital circuitry on the AD7328. The DGND and AGND voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis.

4 AGND

Analog Ground. Ground reference point for all analog circuitry on the AD7328. All analog input signals and any external reference signal should be referred to this AGND voltage. The AGND and DGND voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis.

5 REFIN/OUT

Reference Input/Reference Output. The on-chip reference is available on this pin for use external to the AD7328. The nominal internal reference voltage is 2.5 V, which appears at the pin. A 680 nF capacitor should be placed on the reference pin. Alternatively, the internal reference can be disabled and an external reference applied to this input. On power-up, the external reference mode is the default

condition (see the 6 V 7, 8, 14, 13, 9, 10,

12, 11

0 to VIN7

Negative Power Supply Voltage. This is the negative supply voltage for the analog input section.

Analog Input 0 to Analog Input 7. The analog inputs are multiplexed into the on-chip track-and-hold.

The analog input channel for conversion is selected by programming the Channel Address Bit ADD2

through Bit ADD0 in the control register. The inputs can be configured as eight single-ended inputs,

four true differential input pairs, four pseudo differential inputs, or seven pseudo differential inputs.

The configuration of the analog inputs is selected by programming the mode bits, Bit Mode 1 and

Bit Mode 0, in the control register. The input range on each input channel is controlled by program-

ming the range registers. Input ranges of ±10 V, ±5 V, ±2.5 V, and 0 V to +10 V can be selected on each

analog input channel when a +2.5 V reference voltage is used (see the 15 V 16 V

Positive Power Supply Voltage. This is the positive supply voltage for the analog input section.

Analog Supply Voltage, 2.7 V to 5.25 V. This is the supply voltage for the ADC core on the AD7328.

This supply should be decoupled to AGND. 17 V

DRIVE

Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the interface

operates. This pin should be decoupled to DGND. The voltage at this pin may be different to that at V

but it should not exceed V 18 DOUT

Serial Data Output. The conversion output data is supplied to this pin as a serial data stream. The bits

are clocked out on the falling edge of the SCLK input, and 16 SCLKs are required to access the data. The

data stream consists of three channel identification bits, the sign bit, and 12 bits of conversion data.

The data is provided MSB first (see the 20 SCLK

Serial Clock, Logic Input. A serial clock input provides the SCLK used for accessing the data from the

AD7328. This clock is also used as the clock source for the conversion process.

DIN

DGND

AGND

VIN5

(Not to Scale)

AD7328

TOP VIEW

SCLK

DGND

DOUT

VIN2

Figure 3. TSSOP Pin Configuration

Registers section).

Reference section).

Specifications apply from VCC = 4.75 V to 5.25 V.

by more than 0.3 V.

Serial Interface section).

DRIVE

04852-003

Reference section).

Rev. A | Page 8 of 36

Page 9

AD7328

TYPICAL PERFORMANCE CHARACTERISTICS

SNR (dB)

–20

–40

–60

–80

–100

–120

–140

50 100 150 200 250 300 350 400 450

FREQUENCY (kHz)

4096 POINT FFT V

CC=VDRIVE

DD,VSS

= 25°C

INT/EXT 2.5V REFERENCE ±10V RANGE F

= 50kHz

SNR = 77. 30dB SINAD = 76. 85dB THD = –86. 96dB SFDR = –88.22dB

Figure 4. FFT True Differential Mode

= ±15V

=5V

500

04852-004

1.0 VCC=V

0.8

= 25°C

DD,VSS

0.6

0.4

0.2

–0.2

INL ERROR (LSB)

–0.4

–0.6

–0.8

–1.0

0 8192

512 1536 2560 3584 4608 5632 6656 7680

=5V

DRIVE

= ±15V

1024 2048 3072 4096 512 0 6144 7168

INT/EXT 2.5V REFERENCE ±10V RANGE +INL = + 0.55LSB –INL = –0.68LSB

CODE

Figure 7. Typical INL True Differential Mode

04852-007

SNR (dB)

–20

–40

–60

–80

–100

–120

–140

50 100 150 200 250 300 350 400 450

FREQUENCY (kHz)

4096 POINT FFT V

CC=VDRIVE

DD,VSS

INT/EXT 2.5V REFERENCE ±10V RANGE F

SNR = 74. 67dB SINAD = 74.03dB THD = –82. 68dB SFDR = – 85.40dB

= 25°C

= 50kHz

= ±15V

=5V

Figure 5. FFT Single-Ended Mode

1.0

0.8

0.6

0.4

0.2

–0.2

DNL ERROR (LSB)

–0.4

–0.6

–0.8

–1.0

0 8192

1024 2048 3072 4096 5120 6144 7168

512 1536 2560 3584 4608 5632 6656 7680

VCC=V

DRIVE

=25°C

=±15V

DD,VSS

INT/EXT 2.5V REFERENCE ±10V RANGE +DNL = +0.72LSB –DNL = –0.22LSB

CODE

=5V

Figure 6. Typical DNL True Differential Mode

500

1.0

0.8

0.6

0.4

0.2

–0.2

DNL ERROR (LSB)

–0.4

VCC=V

–0.6

= 25°C

–0.8

DD,VSS

04852-005

INT/EXT 2.5V REFERENCE

–1.0

0 8192

512 1536 2560 358 4 4608 5632 6656 7680

=5V

DRIVE

= ±15V

1024 2048 3072 4096 5120 6144 7168

±10V RANGE +DNL = +0.79LSB –DNL = –0.38LSB

CODE

04852-043

Figure 8. Typical DNL Single-Ended Mode

1.0

0.8

0.6

0.4

0.2

–0.2

INL ERROR (LSB)

–0.4

–0.6

–0.8

04852-006

–1.0

0 8192

1024 2048 3072 4096 5120 6144 7168

512 1536 2560 358 4 4608 5632 6656 7680

VCC=V

DRIVE

= 25°C

= ±15V

DD,VSS

INT/EXT 2.5V REFERENCE ±10V RANGE +INL = + 0.87LSB –INL = –0.49LSB

CODE

=5V

04852-044

Figure 9. Typical INL Single-Ended Mode

Rev. A | Page 9 of 36

Page 10

AD7328

–

VCC=5V V

–55

–60

–65

–70

–75

THD (dB)

–80

–85

–90

–95

–100

Figure 10. THD vs. Analog Input Frequency for Single-Ended (SE) and True

–55

–60

–65

–70

–75

THD (dB)

–80

–85

–90

–95

–100

10 1000

= ±12V

DD/VSS

= 25°C

=1MSPS

0V TO +10V SE

±10V DIF F

ANALOG INPUT F REQUENCY (kHz)

Differential Mode (Diff) at 5 V V

VCC=3V

= ±12V

DD/VSS

= 25°C

=1MSPS

0V TO + 10V SE

±10V DIFF

ANALOG INPUT FREQUENCY (kHz)

100

±10V SE

0V TO +10V DIF F

±5V SE

±5V DIFF

±2.5V DIFF

±2.5V SE

1000

±10V SE

±5V SE

±2.5V SE

±5V DIFF

±2.5V DIFF

04852-008

Rev. A | Page 10 of 36

Page 11

AD7328

–

NUMBER OF OCCURRENCES

023

–3

–2–10123

1201

7600

CODE

VCC=5V V

DD/VSS

RANGE = ±10V 10k SAMPLE S T

1165

Figure 16. Histogram of Codes, Single-Ended Mode

–55

–60

–65

VCC=5V

–70

–75

CMRR (dB)

–80

–85

–90

–95

–100

=3V

DIFFERENTIAL MODE

= 50kHz

DD/VSS

= 1MSPS

=25°C

200 400 600 800 1000 1200

RIPPLE F REQUENCY (kHz)

Figure 17. CMRR vs. Common-Mode Ripple Frequency

=25°C

11 0

= ±12V

04852-014

04852-055

2.0

1.5

1.0

0.5

–0.5

INL ERROR (LSB)

–1.0

–1.5

–2.0

5 7 9 11 13 15 17 19

INL = 1MSPS

±V

INL = 500kSPS

SUPPLY VOLTAGE (V)

DD/VSS

INL = 750kSPS

INL = 1MSPS

INL = 750kSPS

±5V RANGE V

CC=VDRIVE

INTERNAL RE FERENCE SINGLE-E NDED MODE

=5V

04852-050

Figure 19. INL Error vs. Supply Voltage at 500 kSPS, 750 kSPS, and 1 MSPS

100mV p-p SINE WAVE ON EACH SUPPLY

–55

NO DECOUPL ING SINGLE-E NDED MODE f

=1MSPS

–60

–65

–70

–75

PSRR (dB)

–80

–85

–90

–95

–100

200 400 600 800 1000

0 1200

SUPPLY RIPPLE F REQUENCY (kHz)

VCC=5V

VCC=3V

VDD= 12V

VSS= –12V

04852-054

Figure 20. PSRR vs. Supply Ripple Frequency Without Supply Decoupling

2.0

1.5

1.0

0.5

±V

DD/VSS

DNL = 1MSPS

DNL = 750kSPS

SUPPLY VOLTAGE (V)

–0.5

DNL ERROR (LSB)

–1.0

±5V RANGE V

CC=VDRIVE

–1.5

INTERNAL REF ERENCE SINGLE-ENDED MODE

–2.0

5 7 9 11 13 15 17 19

=5V

DNL = 750kSPS

DNL = 500kSPS

DNL = 1MSPS

DNL = 500kS PS

04852-049

–55

–60

–65

–70

–75

THD (dB)

–80

–85

–90

–95

10 1000

ANALOG INPUT F REQUENCY (kHz)

100

04852-015

Figure 18. DNL Error vs. Supply Voltage at 500 kSPS, 750 kSPS, and 1 MSPS

Rev. A | Page 11 of 36

Page 12

AD7328

–

VCC=V V

DD/VSS

–55

= 25°C

INTERNAL RE FERENCE

–60

RANGE = ±10V AND ±2.5V

–65

–70

–75

THD (dB)

–80

–85

–90

–95

10 1000

Figure 22. THD vs. Analog Input Frequency for Various Source Impedances,

=5V

DRIVE

= ±12V

=2000Ω, ±10V RANG E

= 1000Ω, ±10V RANGE

INPUT FREQ UENCY (kHz)

Single-Ended Mode

=100Ω,

±10V RANGE

=50Ω,

±10V RANGE

=2000Ω,

±2.5V RANGE

=1000Ω,

±2.5V RANGE

=100Ω,

±2.5V RANGE

RIN=50Ω, ±2.5V RANGE

100

04852-016

Rev. A | Page 12 of 36

Page 13

AD7328

TERMINOLOGY

Differential Nonlinearity

This is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC.

Integral Nonlinearity

This is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function. The endpoints of the transfer function are zero scale (a point 1 LSB below the first code transition) and full scale (a point 1 LSB above the last code transition).

Negative Full-Scale Error

This applies when using twos complement output coding and any of the bipolar analog input ranges. This is the deviation of the first code transition (10 … 000) to (10 … 001) from the ideal (that is, −4 × V

+ 1 LSB, −2 × V

REF

+ 1 LSB, −V

REF

+ 1 LSB)

REF

after adjusting for the bipolar zero code error.

Negative Full-Scale Error Match

This is the difference in negative full-scale error between any two input channels.

Offset Code Error

This applies to straight binary output coding. It is the deviation of the first code transition (00 ... 000) to (00 ... 001) from the ideal, that is, AGND + 1 LSB.

Offset Error Match

This is the difference in offset error between any two input channels.

Gain Error

This applies to straight binary output coding. It is the deviation of the last code transition (111 ... 110) to (111 ... 111) from the ideal (that is, 4 × V

− 1 LSB, 2 × V

REF

− 1 LSB, V

REF

− 1 LSB)

REF

after adjusting for the offset error.

Gain Error Match

This is the difference in gain error between any two input channels.

Bipolar Zero Code Error

This applies when using twos complement output coding and a bipolar analog input. It is the deviation of the midscale transition (all 1s to all 0s) from the ideal input voltage, that is, AGND − 1 LSB.

Bipolar Zero Code Error Match

This refers to the difference in bipolar zero code error between any two input channels.

Positive Full-Scale Error

This applies when using twos complement output coding and any of the bipolar analog input ranges. It is the deviation of the last code transition (011 … 110) to (011 … 111) from the ideal (4 × V

− 1 LSB, 2 × V

REF

− 1 LSB, V

REF

− 1 LSB) after adjusting

REF

for the bipolar zero code error.

Positive Full-Scale Error Match

This is the difference in positive full-scale error between any two input channels.

Track-and-Hold Acquisition Time

The track-and-hold amplifier returns into track mode after the

SCLK rising edge. Track-and-hold acquisition time is the time required for the output of the track-and-hold amplifier to reach its final value, within ±½ LSB, after the end of a conversion. For the ±2.5 V range, the specified acquisition time is the time required for the track-and-hold amplifier to settle to within ±1 LSB.

Signal to (Noise + Distortion) Ratio

This is the measured ratio of signal to (noise + distortion) at the output of the A/D converter. The signal is the rms amplitude of the fundamental. Noise is the sum of all nonfundamental signals up to half the sampling frequency (f

/2), excluding dc.

The ratio is dependent on the number of quantization levels in the digitization process. The more levels, the smaller the quantization noise. Theoretically, the signal to (noise + distortion) ratio for an ideal N-bit converter with a sine wave input is given by

Signal to (Noise + Distortion) = (6.02 N + 1.76) dB

For a 13-bit converter, this is 80.02 dB.

Total Harmonic Distortion

Total harmonic distortion (THD) is the ratio of the rms sum of harmonics to the fundamental. For the AD7328, it is defined as

THD

where V V

, V5, and V6 are the rms amplitudes of the second through the

is the rms amplitude of the fundamental, and V2, V3,

log20)dB(

++++

VVVVV

sixth harmonics.

Peak Harmonic or Spurious Noise

Peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the ADC output spectrum (up to f

/2, excluding dc) to the rms value of the

fundamental. Normally, the value of this specification is determined by the largest harmonic in the spectrum, but for ADCs where the harmonics are buried in the noise floor, the largest harmonic could be a noise peak.

Rev. A | Page 13 of 36

Page 14

AD7328

Channel-to-Channel Isolation

Channel-to-channel isolation is a measure of the level of crosstalk between any two channels. It is measured by applying a full-scale, 100 kHz sine wave signal to all unselected input channels and determining the degree to which the signal attenuates in the selected channel with a 50 kHz signal. case across all eight channels for the AD7328. The analog input range is programmed to be the same on all channels.

Intermodulation Distortion

With inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities creates distortion products at sum and difference frequencies of mfa ± nfb, where m, n = 0, 1, 2, 3, and so on. Intermodulation distortion terms are those for which neither m nor n are equal to 0. For example, the second-order terms include (fa + fb) and (fa − fb), whereas the third-order terms include (2fa + fb), (2fa − fb), (fa + 2fb), and (fa − 2fb).

The AD7328 is tested using the CCIF standard where two input frequencies near the top end of the input bandwidth are used. In this case, the second-order terms are usually distanced in frequency from the original sine waves, whereas the third-order terms are usually at a frequency close to the input frequencies. As a result, the second- and third-order terms are specified separately. The calculation of the intermodulation distortion is per the THD specification, where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals expressed in decibels.

Figure 14 shows the worst-

Thermal Hysteresis

Thermal hysteresis is defined as the absolute maximum change of reference output voltage after the device is cycled through temperature from either

T_HYS+ = +25°C to T

to +25°C

MAX

T_HYS− = +25°C to T

to +25°C

MIN

It is expressed in ppm using the following equation:

HYS

ppmV

)( ×

−°

REF

HYSTVCV

)_()25(

REFREF

)25(

where:

(25°C) is V

REF

(T_HYS) is the maximum change of V

REF

at 25°C.

REF

at T_HYS+ or

REF

T_HYS−.

CMRR (Common-Mode Rejection Ratio)

CMRR is defined as the ratio of the power in the ADC output at full-scale frequency, f, to the power of a 100 mV sine wave applied to the common-mode voltage of the VIN+ and VIN− frequency, f

, as

CMRR (dB) = 10 log (Pf/Pf

)

where Pf is the power at frequency f in the ADC output, and Pf is the power at frequency f

in the ADC output (see Figure 17).

PSR (Power Supply Rejection)

Variations in power supply affect the full-scale transition but not the linearity of the converter. Power supply rejection is the maximum change in the full-scale transition point due to a change in power supply voltage from the nominal value (see the Typical Performance Characteristics section).

Rev. A | Page 14 of 36

Page 15

AD7328

THEORY OF OPERATION

CIRCUIT INFORMATION

The AD7328 is a fast, 8-channel, 12-bit plus sign, bipolar input, serial A/D converter. The AD7328 can accept bipolar input ranges that include ±10 V, ±5 V, and ±2.5 V;/MCI234.36 756 alsI234oe6t +110 un(i)15(p)-8((la)8()-3( in)-4(n)22(p)11(u)6( r(a)8(g(e)7v. Adifr)-4(fc)5(er)10e(n)22t (a)8(n35(a)-4logr in)22(p)11(u)6(t )]TJ0.0129 Tc -0.0042 Tw 0 -1.285 TD[r(a)10(n)10gt)7( c(a)10(n4-6I234bet p)13rc)5(gr(a)10mmr)10edn4-6oc)5(n4-6er)-05(a4(ct)7hn4-6(a)10(n4-alogr in)3( p)13ut)7t ctan-n n4-8-c6(h(i)6(p rp)11e6)-gI234.33[(s)7thrs.( Th)10ee AD7328has a hsig spserd sI234e6.33[(al in)3(th)8(6)-rrfracst hratr ct-295(a)-13(n)-9(6oc)-1(ps)3rrratr(r)2atr trhrrcocur ()-30(atr)-4((r)20[(s))21 ur tror 1rSrPr

Rev. A | Page 15 of 36

Page 16

AD7328

CAPACITIVE

DAC

COMPARATOR

SW2

CONTROL

LOGIC

AGND

SW1

Figure 24. ADC Conversion Phase (Single-Ended)

The ideal transfer characteristic for the AD7328 when twos complement coding is selected is shown in

Figure 27. The ideal transfer characteristic for the AD7328 when straight binary coding is selected is shown in

04852-018

011. ..111

011...110

Figure 28.

Figure 25 shows the differential configuration during the acquisition phase. For the conversion phase, SW3 opens and SW1 and SW2 move to Position B (see impedances of the source driving the V

Figure 26). The output

+ and VIN− pins must

match; otherwise, the two inputs have different settling times, resulting in errors.

CAPACITIVE

DAC

SW1 SW2

–

REF

COMPARATOR

SW3

CONTROL

LOGIC

CAPACITIVE

DAC

04852-019

Figure 25. ADC Differential Configuration During Acquisition Phase

CAPACITIVE

DAC

SW1 SW2

–

REF

COMPARATOR

SW3

CONTROL

LOGIC

CAPACITIVE

DAC

04852-020

Figure 26. ADC Differential Configuration During Conversion Phase

Output Coding

The AD7328 default output coding is set to twos complement. The output coding is controlled by the coding bit in the control register. To change the output coding to straight binary coding, the coding bit in the control register must be set. When operating in sequence mode, the output coding for each channel in the sequence is the value written to the coding bit during the last write to the control register.

Transfer Functions

The designed code transitions occur at successive integer LSB values (that is, 1 LSB, 2 LSB, and so on). The LSB size is dependent on the analog input range selected.

Table 7. LSB Sizes for Each Analog Input Range

Input Range Full-Scale Range/8192 Codes LSB Size

±10 V 20 V 2.441 mV ±5 V 10 V 1.22 mV ±2.5 V 5 V 0.61 mV 0 V to +10 V 10 V 1.22 mV

000...001

000...000

111.. .111

ADC CODE

100...010

100...001

100...000

–FSR/2 + 1L SB

AGND + 1LS B

AGND – 1LSB

ANALOG INPUT

+FSR/2 – 1LS B BIPOLAR RANG ES +FSR – 1LSB UNIPOLAR RANGE

04852-021

Figure 27. Twos Complement Transfer Characteristic (Bipolar Ranges)

111.. .111

111.. .110

111.. .00 0

011. ..111

ADC CODE

000...010

000...001

000...000

–FSR/2 + 1LSB

AGND + 1LS B

+FSR/2 – 1LS B BIPOLAR RANG ES +FSR – 1LSB UNIPOLAR RANGE

ANALOG INPUT

04852-022

Figure 28. Straight Binary Transfer Characteristic (Bipolar Ranges)

ANALOG INPUT STRUCTURE

The analog inputs of the AD7328 can be configured as singleended, true differential, or pseudo differential via the control register mode bits (see bipolar input signals. On power-up, the analog inputs operate as eight single-ended analog input channels. If true differential or pseudo differential is required, a write to the control register is necessary after power-up to change this configuration.

Figure 29 shows the equivalent analog input circuit of the AD7328 in single-ended mode. analog input structure in differential mode. The two diodes provide ESD protection for the analog inputs.

Figure 29. Equivalent Analog Input Circuit (Single-Ended)

Table 1 0). The AD7328 can accept true

Figure 30 shows the equivalent

04852-023

Rev. A | Page 16 of 36

Page 17

AD7328

–

04852-024

Figure 30. Equivalent Analog Input Circuit (Differential)

The AD7328 enters track moda on the 14 When th328 is rETit a thrughput rate of 1 MSPS with a 20 MHz SCLK signal, the ADC has approxT2(ima)22(t)2(e)8(l)7(y )]TJETEMC /P <</MCID 50 >>BDC BT/T1_3 1 Tf0.0006 Tc 0.0002 Tw 9.48 0 0 9.48 350.9998 663.9602 Tm(1.5 SCLK + )Tj/T1_5 1 Tf0 Tc 0 Tw 4.804 0 Td(t)TjETEMC /Span <</MCID 51 >>BDC BT/T1_5 1 Tf5.52 0 0 5.52 399.48 663.48 Tm(8)TjETEMC /P <</MCID 52 >>BDC BT/T1_3 1 Tf0.0018 Tc -0.001 Tw 9.48 0 0 9.48 402.12 663.9601 Tm( + )Tj/T1_5 1 Tf0 Tc 0 Tw 1.038 0 Td(t)TjETEMC /Span <</MCID 53 >>BDC BT/T1_5 1 Tf-0.0014 Tc 5.52 0 0 5.52 414.9 663.48 Tm(QUIET)TjETEMC /P <</MCID 54 >>BDC BT/T1_3 1 Tf-0.0001 Tc 0.0009 Tw 9.48 0 0 9.48 333 643.86 Tm[(t)7(o)-3( acq)11(u)iha analog input signal. The ADC goes back into hold mode on the

fallindge.

As the V

suT11(pT11(pT2(l)5(y)-4( )6(v)7(o)-3(l)12(t)-12(a)8(g)-17a is r)9(e)-6(d)8(u)i)ced, tha on-resistance of

DD/VSS

the inpT22(u)17(t)12( m)26(u)4(l)23(t)-1(i)26(pT1)7lexer incT1eases. Therefore, based on the equation for t

, it is necessary to increase the acquT2(isi)13(t)-6(ion t)-6(i)-5(m)87a pT1ovided

ACQ

t the AD7328 and hene the ovarall throughput rate. Figure 31 shows that if the throughput rate is reduced when

SCLK rising edge.

operating with minimuT8(m )6(V)]TJETEMC /Span <</MCID 66 >>BDC BT/T1_3 1 Tf-0.0067 Tc 0 Tw 5.52 0 0 5.52 437.94 549.42 Tm(DD)TjETEMC /P <</MCID 67 >>BDC BT/T1_3 1 Tf-0.0018 Tc 0.0026 Tw 9.48 0 0 9.48 446.04 549.9 Tm[( a)7(nd V)]TJETEMC /Span <</MCID 68 >>BDC BT/T1_3 1 Tf0.0043 Tc 0 Tw 5.52 0 0 5.52 471.24 549.42 Tm(SS)TjETEMC /P <</MCID 69 >>BDC BT/T1_3 1 Tf-0.0039 Tc 0.0048 Tw 9.48 0 0 9.48 476.52 549.9 Tm[( suT8(p)7(p)17l)-4(i)-2(e)-3(s)-1 the specified

Care should be taken to ensure that the analog input does not exceed the V

and VSS supply rails by more than 300 mV.

Exceeding this value causes the diodes to become forward biased and to start conducting into either the V or V

supply rail. These diodes can conduct up to 10 mA

without causing irreversible damage to the part.

Figure 29 and Figure 30, Capacitor C1 is typically 4 pF and

In can primarily be attributed to pin capacitance. Resistor R1 is a lumped component made up of the on-resistance of the input multiplexer and the track-and-hold switch. Capacitor C2 is the sampling capacitor; its capacitance varies depending on the analog input range selected (see the

Track-and-Hold Section

The track-and-hold on the analog input of the AD7328 allows the ADC to accurately convert an input sine wave of full-scale amplitude to 13-bit accuracy. The input bandwidth of the trackand-hold is greater than the Nyquist rate of the ADC. The AD7328 can handle frequencies up to 22 MHz.

The track-and-hold enters its tracking mode on the 14th SCLK

rising edge after the

falling edge. The time required to acquire an input signal depends on how quickly the sampling capacitor is charged. With zero source impedance, 305 ns is sufficient to l e6ETithe signal to the 13-bit level. The ac( e6ETi)1sition time for lV, ±5 V, and 0 V to +10 V ranges to settle to within ±½ LSB is typically 200 ns.

THD perornce is maintained.

supply rail

Specifications section).

–5

–6

–7

THD (dB)

–8

–9

Fie 31 vs. ±V

1MSPS

7PS

7 9 11 13 15 1

±VDD/VSSSUPIES (V)

Supply Voltage at 500 kSPS, 750 kSPS, and 1 MSPS

DD/VSS

VCC=V INTERL REF ERENCE T

±5V RE SE MODE

=5V

DRIVE

=2°C

= 1

50PS

Unlike other bipolar ADCs, the AD7328 does nt have a resistive analog input structure. On the AD7328, the bipolar analog signal is sampled dirctly onto the sampling capacitor This gives the AD7328 high anaput impedance. The analog input impdance can be calculatd from the following formua:

Z = 1/(f

× CS)

04852-051

is the sampling frequency, and CS is the sampling

where f

capacitor value.

The 3( e6ET2(is)-7(i)14(t)-6(io)9(n )-6(t)-6(i)-5(m)8(e r)9(e)-6(q)10(uT2(ir)9(e)-13(d)2( is)-7( ca)-5(lc)-8(u)-8(l)-8(a)20(t)6(e)-13(d)2( using t)-6(h)8(e fol)-8(l)-1(o)15(w)-6(in)8(g )]TJ-0.0031 Tc 0 Tw 0 -1.278 TD[(fo)7(r)-12(m)18(u)-10(l)-3(a: )]TJETEMC /P <</MCID 36 >>BDC BT/T1_5 1 Tf0 Tc 9.48 0 0 9.48 72.0001 174.8385 Tm(t)TjETEMC /Span <</MCID 37 >>BDC BT/T1_5 1 Tf-0.0028 Tc 5.52 0 0 5.52 74.94 174.36 Tm(ACQ)TjETEMC /P <</MCID 38 >>BDC BT/T1_3 1 Tf0.0017 Tc -0.0009 Tw 9.48 0 0 9.48 85.98 174.8401 Tm( = 10 × (()Tj/T1_5 1 Tf0 Tc 0 Tw 3.728 0 Td(R)TjETEMC /Span <</MCID 39 >>BDC BT/T1_5 1 Tf-0.0022 Tc 5.52 0 0 5.52 126.96 174.36 Tm(SOURCE)TjETEMC /P <</MCID 40 >>BDC BT/T1_3 1 Tf0.0018 Tc -0.001 Tw 9.48 0 0 9.48 147.18 174.8401 Tm( + )Tj/T1_5 1 Tf0 Tc 0 Tw 1.038 0 Td(R)Tj/T1_3 1 Tf0.0021 Tc 0.601 0 Td() )Tj/T1_5 1 Tf0 Tc 0.576 0 Td(C)Tj/T1_3 1 Tf0.0021 Tc 0.633 0 Td() )TjETEMC /P <</MCID 41 >>BDC BT/T1_3 1 Tf-0.0009 Tc 9.48 0 0 9.48 54.0001 154.6799 Tm[(w)-6(h)2(er)9(e )]TJ/T1_5 1 Tf0 Tc 2.658 0 Td(C)Tj/T1_3 1 Tf0.0101 Tc -0.0093 Tw 0.633 0 Td[( i)12(s)10( th)19(e)11( sa)19(m)32(p)15(l)10(i)12(n)13(g)10( c)9(a)31(pa)12(ci)25(ta)19(n)19(c)3(e)17(,)10( a)12(n)19(d)13( )]TJ/T1_5 1 Tf0 Tc 0 Tw (R)Tj/T1_3 1 Tf-0.0018 Tc 0.0026 Tw 13.88 0 Td[( is t)-13(h)7(e r)8(e)-1(sist)-7(an)7(c)-9(e)-1( )]TJ-0.0012 Tc 0.002 Tw -17.171 -1.272 Td[(s)-8(e)-7(en )-6(b)20(y)-4( t)-13(h)87a t)-6(r)-4(ack-and-)-6(h)8(o)3(ld am)14(plif)-15(ier lo)-10(ok)-5(in)8(g a)14(t t)-6(h)1(e i)-5(n)21(p)10(uT11(t)-6(.)-1( )]TJETEMC /P <</MCID 42 >>BDC BT/T1_3 1 Tf0.0013 Tc -0.0005 Tw 9.48 0 0 9.48 54.0001 122.4593 Tm[(F)18(oT11(r th)1)7a AD7328)-6(, th)1)7a value oT11(f R )-6(in)1ludes thnT2(-r)12(esis)8(ta)10(n)10(ce oT11(f t)-10(h)1)7a input multiplexer and is typically 300 Ω. R

depends on the analog input rang chosen (se the

Spcifications s ction). When operating at 1 MS S, the analog input impedance is typically 75 k for the ±10 V range. As the sampling frequency is reduced, the analog input impedance further increases. As the analog input impedance increases, the current required to drive the analog input therefore decreases.

should inT11(c)-15(l)-8(u)-21(d)-17(e)-19( )]TJ-0.0003 Tc 0.0011 Tw -18.449 -1.272 Td[(a)8(n)28(y ext)-5(r)-3(a s)-7(o)10(ur)1e impedanchput.

SOURCE

Rev. A | Page 17 of 36

Page 18

AD7328

TYPICAL CONNECTION DIAGRAM

Figure 32 shows a typical connection diagram for the AD7328. In this configuration, the AGND pin is connected to the analog ground plane of the system, and the DGND pin is connected to the digital ground plane of the system. The analog inputs on the AD7328 can be configured to operate in single-ended, true differential, or pseudo differential mode. The AD7328 can operate with either an internal or external reference. In

Figure 32, the AD7328 is configured to operate with the internal 2.5 V reference. A 680 nF decoupling capacitor is required when operating with the internal reference.

pin can be connected to either a 3 V or 5 V supply voltage.

The V

and VSS are the dual supplies for the high voltage analog

input structures. The voltage on these pins must be equal to or greater than the highest analog input range selected on the analog input channels (see

Tabl e 6 for more information). The V

DRIVE

pin is connected to the supply voltage of the microprocessor. The voltage applied to the V serial interface. V

+15

ANALOG INPUT S ±10V, ±5V, ±2. 5V 0V TO + 10V

680nF

–15V

DRIVE

10µF0.1µF

VIN0 VIN1 VIN2 VIN3 VIN4 VIN5 VIN6 VIN7

REFIN/OUT

10µF0.1µF

Figure 32. Typical Connection Diagram

input controls the voltage of the

DRIVE

can be set to 3 V or 5 V.

10µF 0. 1µF

DRIVE

10µF 0.1µF

AD7328

DOUT

SCLK

DIN

DGND

AGND

MINIMUM VDDAND VSSSUPPLY VOLTAGES DEPEND ON THE HIG HEST ANALOG INPUT RANGE SELECT ED.

INTERFACE

+3V SUPPLY

SERIAL

+2.7VTO +5. 25

µC/µP

ANALOG INPUT

Single-Ended Inputs

The AD7328 has a total of eight analog inputs when operating in single-ended mode. Each analog input can be independently programmed to one of the four analog input ranges. In applications where the signal source is high impedance, it is recommended to buffer the signal before applying it to the ADC analog inputs. Figure 33 shows the configuration of the AD7328 in singleended mode.

AGND

AD7328

V–

ADDITIONAL PINS OMIT TED FOR CL ARITY.

04852-026

Figure 33. Single-Ended Mode Typical Connection Diagram

True Differential Mode

The AD7328 can have four true differential analog input pairs. Differential signals have some benefits over single-ended signals, including better noise immunity based on the device’s common-mode rejection and improvements in distortion performance.

Figure 34 defines the configuration of the true

differential analog inputs of the AD7328.

AD7328

–

ADDITIONAL PI NS OMITT ED FOR CLARITY.

04852-027

Figure 34. True Differential Inputs

The amplitude of the differential signal is the difference between the signals applied to the V each differential pair (V

+ − VIN−). VIN+ and VIN− should

+ and VIN− pins in

be simultaneously driven by two signals of equal amplitude, dependent on the input range selected, that are 180° out of phase. Assuming the ±4 × V the differential signal is −20 V to +20 V p-p (2 × 4 × V

mode, the amplitude of

REF

regardless of the common mode.

04852-025

The common mode is the average of the two signals

+ + VIN−)/2

and is therefore the voltage on which the two input signals are centered.

This voltage is set up externally, and its range varies with reference voltage. As the reference voltage increases, the common-mode range decreases. When driving the differential inputs with an amplifier, the actual common-mode range is determined by the amplifier’s output swing. If the differential inputs are not driven from an amplifier, the common-mode range is determined by the supply voltage on the V

supply pin and the VSS supply pin.

When a conversion takes place, the common mode is rejected, resulting in a noise-free signal of amplitude −2 × (4 × V +2 × (4 × V

Rev. A | Page 18 of 36

), corresponding to Digital Codes −4096 to +4095.

REF

) to

Page 19

AD7328

RANGE (V)

–1

COM

–2

–3

–4

VCC=3V

–5

REF

–6

RANGE

=3V

±5V RANGE

±10V

±16.5V VDD/V

Figure 35. Common-Mode Range for V

RANGE

=3V

±5V RANGE

±10V

±16.5V VDD/V

RANGE (V)

COM

–2

VCC=5V V

REF

–4

Figure 36. Common-Mode Range for V

RANGE (V)

–2

COM

–4

±10V

RANGE

±5V RANGE

±2.5V

RANGE

±2.5V

RANGE

±2.5V

RANGE

±5V RANGE

±10V

RANGE

±12V VDD/V

= 3 V and REFIN/OUT = 3 V

±5V RANGE

±10V

RANGE

±12V VDD/V

= 5 V and REFIN/OUT = 3 V

±5V RANGE

±10V

RANGE

±2.5V

RANGE

VCC=5V

=2.5V

REF

±10V

RANGE

±5V RANGE

±16.5V VDD/V

±2.5V

RANGE

04852-045

RANGE (V)

–2

COM

–4

–6

–8

Figure 38. Common-Mode Range for V

±5V RANGE

±10V

RANGE

±2.5V

RANGE

±12V VDD/V

= 5 V and REFIN/OUT = 2.5 V

04852-048

Pseudo Differential Inputs

The AD7328 can have four pseudo differential pairs or seven

±2.5V

RANGE

pseudo differential inputs referenced to a common V V

+ inputs are coupled to the signal source and must have an

− pin. The

amplitude within the selected range for that channel as programmed in the range register. A dc input is applied to the V

− pin.

The voltage applied to this input provides an offset for the V

+ input from ground or a pseudo ground. Pseudo differential

inputs separate the analog input signal ground from the ADC ground, allowing cancellation of dc common-mode voltages. Figure 39 shows the configuration of the AD7328 in pseudo

04852-046

differential mode.

When a conversion takes place, the pseudo ground corresponds to Code −4096, and the maximum amplitude corresponds to Code +4095.

±2.5V

RANGE

AD7328

VIN–

–6

VCC=3V

=2.5V

REF

–8

±16.5V VDD/V

Figure 37. Common-Mode Range for V

±12V VDD/V

= 3 V and REFIN/OUT = 2.5 V

04852-047

Figure 40 and Figure 41 show the typical voltage range on the

− pin for various analog input ranges when configured in

V–

ADDITIONAL PI NS OMITTED FOR CLARITY.

Figure 39. Pseudo Differential Inputs

04852-028

the pseudo differential mode.

For example, when the AD7328 is configured to operate in pseudo differential mode and the ±5 V range is selected with ±16.5 V V V

− pin can vary from −6.5 V to +6.5 V.

Rev. A | Page 19 of 36

supplies and 5 V VCC, the voltage on the

DD/VSS

Page 20

AD7328

–

–2–4–

–2

–4

–6

VCC=5V V

REF

–8

VCC=3V V

REF

±5V RANGE

±10V

RANGE

±12V VDD/V

±10V

RANGE

=2.5V

±5V RANGE

RANGE

±16.5V VDD/V

±2.5V

0V TO +10V

RANGE

Figure 40. Pseudo Input Range with V

±5V RANGE

±10V

0V TO + 10V

RANGE

±12V VDD/V

±10V

RANGE

=2.5V

RANGE

±16.5V V

±2.5V

DD/VSS

±2.5V

RANGE

0V TO +10V

RANGE

= 5 V

±2.5V

RANGE

0V TO +10V

RANGE

The driver amplifier must be able to settle for a full-scale step to a 13-bit level, 0.0122%, in less than the specified acquisition time of the AD7328. An op amp such as the AD8021 meets this requirement when operating in single-ended mode. The

AD8021

needs an external compensating NPO type of capacitor. The

AD8022 can also be used in high frequency applications where

a dual version is required. For lower frequency applications, op amps such as the

AD797, AD845, and AD8610 can be used with

the AD7328 in single-ended mode configuration.

Differential operation requires that V

+ and VIN− be simulta-

neously driven with two signals of equal amplitude that are 180°

04852-039

out of phase. The common mode must be set up externally to the AD7328. The common-mode range is determined by the REFIN/OUT voltage, the V

supply voltage, and the particular

amplifier used to drive the analog inputs. Differential mode with either an ac input or a dc input provides the best THD performance over a wide frequency range. Because not all applications have a signal preconditioned for differential operation, there is often a need to perform a single-ended-to-differential conversion. This single-ended-to-differential conversion can be performed using an op amp pair. Typical connection diagrams for an op amp pair are shown in

Figure 42 and Figure 43. In Figure 42, the common-mode signal is applied to the noninverting input of the second amplifier.

1.5kΩ

04852-040

2kΩ

1.5kΩ

10kΩ

1.5kΩ

–

04852-029

Rev. A | Page 20 of 36

Page 21

AD7328

REGISTERS

The AD7328 has four programmable registers: the control register, sequence register, Range Register 1, and Range Register 2. These registers are write-only registers.

ADDRESSING REGISTERS

A serial transfer on the AD7328 consists of 16 SCLK cycles. The three MSBs on the DIN line during the 16 SCLK transfer are decoded to determine which register is addressed. The three MSBs consist of the write bit, Register Select 1 bit, and Register Select 2 bit. The register select bits are used to determine which of the four on-board registers is selected. The write bit determines if the data on the DIN line following the register select bits loads into the addressed register. If the write bit is 1, the bits load into the register addressed by the register select bits. If the write bit is 0, the data on the DIN line does not load into any register.

Table 8. Decoding Register Select Bits and Write Bit

Write Register Select 1 Register Select 2 Description

0 0 0 Data on the DIN line during this serial transfer is ignored. 1 0 0

1 0 1

1 1 0

1 1 1

This combination selects the control register. The subsequent 12 bits are loaded into the control register.

This combination selects Range Register 1. The subsequent 8 bits are loaded into Range Register 1.

This combination selects Range Register 2. The subsequent 8 bits are loaded into Range Register 2.

This combination selects the sequence register. The subsequent 8 bits are loaded into the sequence register.

Rev. A | Page 21 of 36

Page 22

AD7328

CONTROL REGISTER

The control register is used to select the analog input channel, analog input configuration, reference, coding, and power mode. The control register is a write-only, 12-bit register. Data loaded on the DIN line corresponds to the AD7328 configuration for the next conversion. If the sequence register is being used, data should be loaded into the control register after the range registers and the sequence register have been initialized. The bit functions of the control register are shown in

MSB LSB 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Write Register

Select 1

ADD2 ADD1 ADD0 Mode 1 Mode 0 PM1 PM0 Coding Ref Seq1 Seq2 Weak/

Table 9. Control Register Details

Bit Mnemonic Description

12, 11, 10

9, 8 Mode 1, Mode 0

7, 6 PM1, PM0 The power management bits are used to select different power mode options on the AD7328 (see Table 11). 5 Coding

4 Ref

3, 2 Seq1/Seq2 The Sequence 1 and Sequence 2 bits are used to control the operation of the sequencer (see Tab le 12). 1

ADD2, ADD1, ADD0

Three-State This bit selects the state of the DOUT line at the end of the current serial transfer. If the bit is set to 1, the

Weak/

These three channel address bits are used to select the analog input channel for the next conversion if the sequencer is not being used. If the sequencer is being used, the three channel address bits are used to select the final channel in a consecutive sequence.

These two mode bits are used to select the configuration of the eight analog input pins, V pins are used in conjunction with the channel address bits. On the AD7328, the analog inputs can be configured as eight single-ended inputs, four fully differential input pairs, four pseudo differential inputs, or seven pseudo differential inputs (see

This bit is used to select the type of output coding the AD7328 uses for the next conversion result. If the coding = 0, the output coding is twos complement. If the coding = 1, the output coding is straight binary. When operating in sequence mode, the output coding for each channel is the value written to the coding bit during the last write to the control register.

The reference bit is used to enable or disable the internal reference. If Ref = 0, the external reference is enabled and used for the next conversion, and the internal reference is disabled. If Ref = 1, the internal reference is used for the next conversion. When operating in sequence mode, the reference used for each channel is the value written to the Ref bit during the last write to the control register.

DOUT line is weakly driven to Channel Address Bit ADD2 of the following conversion. If this bit is set to 0, DOUT returns to three-state at the end of the serial transfer (see the Serial Interface section).

The eight analog input channels can be configured as seven pseudo differential analog inputs, four pseudo differential inputs, four true differential input pairs, or eight single-ended analog inputs.

Table 10. Analog Input Configuration Selection

Mode 1 = 1, Mode 0 = 1 Mode 1 = 1, Mode 0 = 0 Mode 1 = 0, Mode 0 = 1 Mode 1 = 0, Mode 0 = 0 Channel Address Bits 7 Pseudo Differential I/Ps 4 Fully Differential I/Ps 4 Pseudo Differential I/Ps 8 Single-Ended I/Ps ADD2 ADD1 ADD0 VIN+ VIN− VIN+ VIN− VIN+ VIN− VIN+ VIN−

0 0 0 VIN0 VIN7 VIN0 VIN1 VIN0 VIN1 VIN0 AGND 0 0 1 VIN1 VIN7 VIN0 VIN1 VIN0 VIN1 VIN1 AGND 0 1 0 VIN2 VIN7 VIN2 VIN3 VIN2 VIN3 VIN2 AGND 0 1 1 VIN3 VIN7 VIN2 VIN3 VIN2 VIN3 VIN3 AGND 1 0 0 VIN4 VIN7 VIN4 VIN5 VIN4 VIN5 VIN4 AGND 1 0 1 VIN5 VIN7 VIN4 VIN5 VIN4 VIN5 VIN5 AGND 1 1 0 VIN6 VIN7 VIN6 VIN7 VIN6 VIN7 VIN6 AGND 1 1 1 Temperature indicator VIN6 VIN7 VIN6 VIN7 VIN7 AGND

Tabl e 9 (the power-up status of all bits is 0).

Table 10).

Three-State

0 to VIN7. These

Rev. A | Page 22 of 36

Page 23

AD7328

Table 11. Power Mode Selection

PM1 PM0 Description

1 1

1 0

0 1

0 0 Normal Mode. All internal circuitry is powered up at all times.

Table 12. Sequencer Selection

Seq1 Seq2 Description

0 0

0 1

1 0

1 1

Full Shutdown Mode. In this mode, all internal circuitry on the AD7328 is powered down. Information in the control register is retained when the AD7328 is in full shutdown mode.

Autoshutdown Mode. The AD7328 enters autoshutdown on the 15 All internal circuitry is powered down in autoshutdown.

Autostandby Mode. In this mode, all internal circuitry is powered down, excluding the internal reference. The AD7328 enters autostandby mode on the 15

The channel sequencer is not used. The analog channel, selected by programming the ADD2 to ADD0 bits in the control register, selects the next channel for conversion.

Uses the sequence of channels that were previously programmed in the sequence register for conversion. The AD7328 starts converting on the lowest channel in the sequence. The channels are converted in ascending order. If uninterrupted, the AD7328 keeps converting the sequence. The range for each channel defaults to the range previously written into the corresponding range register.

This configuration is used in conjunction with the channel address bits in the control register. This allows continuous conversions on a consecutive sequence of channels, from Channel 0 through a final channel selected by the channel address bits in the control register. The range for each channel defaults to the range previously written into the corresponding range register.

The channel sequencer is not used. The analog channel, selected by programming the ADD2 bit to ADD0 bit in the control register, selects the next channel for conversion.

SCLK rising edge after the control register is updated.

SCLK rising edge when the control register is updated.

Rev. A | Page 23 of 36

Page 24

AD7328

SEQUENCE REGISTER

The sequence register on the AD7328 is an 8-bit, write-only register. Each of the eight analog input channels has one corresponding bit in the sequence register. To select a channel for inclusion in the sequence, set the corresponding channel bit to 1 in the sequence register.

MSB LSB 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

Write Register Select 1 Register Select 2 VIN0 VIN1 VIN2 VIN3 VIN4 VIN5 VIN6 VIN7 0 0 0 0 0

RANGE REGISTERS

The range registers are used to select one analog input range per analog input channel. Range Register 1 is used to set the ranges for Channel 0 to Channel 3. It is an 8-bit, write-only register with two dedicated range bits for each of the analog input channels from Channel 0 to Channel 3. There are four analog input ranges, ±10 V, ±5 V, ±2.5 V, and 0 V to +10 V. A write to Range Register 1 is selected by setting the write bit to 1 and the range select bits to 0 and 1. After the initial write to Range Register 1 occurs, each time an analog input is selected, the AD7328 automatically configures the analog input to the appropriate range, as indicated by Range Register 1. The ±10 V input range is selected by default on each analog input channel (see

MSB LSB 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

Write Register Select 1 Register Select 2 VIN0A VIN0B VIN1A VIN1B VIN2A VIN2B VIN3A VIN3B 0 0 0 0 0

Range Register 2 is used to set the ranges for Channel 4 to Channel 7. It is an 8-bit, write-only register with two dedicated range bits for each of the analog input channels from Channel 4 to Channel 7. There are four analog input ranges, ±10 V, ±5 V, ±2.5 V, and 0 V to +10 V. After the initial write to Range Register 2 occurs, each time an analog input is selected, the AD7328 automatically configures the analog input to the appropriate range, as indicated by Range Register 2. The ±10 V input range is selected by default on each analog input channel (see

Tabl e 13 ).

MSB LSB 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

Write Register Select 1 Register Select 2 VIN4A VIN4B VIN5A VIN5B VIN6A VIN6B VIN7A VIN7B 0 0 0 0 0

Table 13. Range Selection

VINxA VINxB Description

0 0 This combination selects the ±10 V input range on VINx. 0 1 This combination selects the ±5 V input range on VINx. 1 0 This combination selects the ±2.5 V input range on VINx. 1 1 This combination selects the 0 V to +10 V input range on VINx.

Tabl e 13 ).

Rev. A | Page 24 of 36

Page 25

AD7328

SEQUENCER OPERATION

POWER ON.

DIN: WRITE TO RANGE REGISTE R 1 TO SELECT THE RANGE

FOR EACH ANALOG INPUT CHANNEL .

DOUT: CONVERSION RESULT FROM CHANNEL 0, ± 10V

DIN: WRITE TO RANGE REGISTE R 2 TO SELECT THE RANGE

DIN: WRITE TO SEQUENCE REGISTER TO SELECT THE

RANGE, SING LE-ENDED MODE .

FOR EACH ANALOG INPUT CHANNEL .

DOUT: CONVERSION RESULT FRO M CHANNEL 0,

SINGLE-ENDED MODE, RANGE SELECTED IN

ANALOG INPUT CHANNELS TO BE INCLUDED IN

DOUT: CONVERSION RESULT FRO M CHANNEL 0,

SINGLE-ENDED MODE, RANGE SELECTED IN

RANGE REGIST ER 1.

THE SEQUENCE.

RANGE REGIST ER 1.

DIN: WRITE TO CONTROL REGISTE R TO START THE

DOUT: CONVERSION RESULT FRO M CHANNEL 0,

SINGLE-ENDED MODE, RANGE SELECTED IN

DIN: TIE DIN LOW/W RITE BIT = 0 TO CONTINUE TO CONVERT

DIN: WRITE TO CONTROL

SEQUENCE, Seq1 = 0, Seq2 = 0.

DOUT: CONVERSION RESULT

FROM CHANNEL IN SE QUENCE.

THROUGH THE SEQ UENCE OF CHANNELS.

DOUT: CONVERSION RESULT FROM FIRST CHANNEL IN

STOPPING

A SEQUENCE.

SELECTING A NEW SEQUENCE.

DIN: WRITE TO SEQUENCE REGISTER TO SELECT THE

DOUT: CONVERSION RESULT FROM CHANNEL X IN

Figure 44. Programmable Sequence Flowchart

The AD7328 can be configured to automatically cycle through a number of selected channels using the on-chip sequence register with the Seq1 bit and the Seq2 bit in the control register.

Figure 44 shows how to program the AD7328 register to operate in sequence mode.

After power-up, all of the four on-chip registers contain default values. Each analog input has a default input range of ±10 V. If different analog input ranges are required, a write to the range registers is necessary. This is shown in the first two serial transfers of

Figure 44.

SEQUENCE, Seq1 = 0, Seq2 = 1.

RANGE REGIST ER 1.

THE SEQUENCE.

CONTINUOUSLY CONVERT

ON THE SELECTED SEQUENCE

OF CHANNELS.

NEW SEQUENCE.

THE FIRST SEQUENCE.

DINTIEDLOW/WRITEBIT=0.

These two initial serial transfers are only necessary if input ranges other than the default ranges are required. After the analog input ranges are configured, a write to the sequence register is necessary to select the channels to be included in the sequence. Once the channels for the sequence have been selected, the sequence can be initiated by writing to the control register and setting Seq1 to 0 and Seq2 to 1. The AD7328 continues to convert the selected sequence without interruption provided that the sequence register remains unchanged and Seq1 = 0 and Seq2 = 1 in the control register.

04852-031

Rev. A | Page 25 of 36

Page 26

AD7328

If a write to one of the range registers is required during a sequence, it is necessary to first stop the sequence by writing to the control register and setting Seq1 to 0 and Seq2 to 0. Next, the write to the range register should be completed to change the required range. The previously selected sequence should then be initiated again by writing to the control register and setting Seq1 to 0 and Seq2 to 1. The ADC converts the first channel in the sequence.

The AD7328 can be configured to convert a sequence of consecutive channels (see converting on Channel 0 and ends with a final channel as selected by Bit ADD2 to Bit ADD0 in the control register. In this configuration, there is no need for a write to the sequence register. To operate the AD7328 in this mode, set Seq1 to 1 and Seq2 to 0 in the control register, and then select the final channel in the sequence by programming Bit ADD2 to Bit ADD0 in the control register.

Figure 45). This sequence begins by

POWER ON.

Once the control register is configured to operate the AD7328 in this mode, the DIN line can be held low or the write bit can be set to 0. To return to traditional multichannel operation, a write to the control register to set Seq1 to 0 and Seq2 to 0 is necessary.

When Seq1 and Seq2 are both set to 0 or to 1, the AD7328 is configured to operate in traditional multichannel mode, where a write to Channel Address Bit ADD2 to Bit ADD0 in the control register selects the next channel for conversion.

DIN: W RITE TO RANG E REG ISTER 1 TO SELECT THE RANGE

DIN: W RITE TO RANG E REG ISTER 2 TO SELECT THE RANGE

DIN: WRITE TO CONTROL REGIST ER TO SELECT THE FINAL

CHANNEL IN THE CONSECUTIVE SEQUENCE, SET Seq1 = 1

AND Seq2 = 0. S ELECT OUTPUT CODING F OR SEQ UENCE.

DIN: WRITE BI T = 0 OR DIN LI NE HELD LOW T O CONTINUE

FOR ANALOG I NPUT CHANNELS.

DOUT: CONVERSI ON RESULT FROM CHANNEL 0, ± 10V

THROUGH SEQUENCE O F CONSECUTI VE CHANNELS.

RANGE, SINGLE-ENDED MODE.

FOR ANALOG I NPUT CHANNELS.

DOUT: CONVERSION RESULT FROM CHANNEL 0,

RANGE SELECTED I N RANGE REGIST ER 1,

SINGLE-ENDED MODE.

DOUT: CONVERSION RESULT FROM CHANNEL 0,

RANGE SELECTED I N RANGE REGIST ER 1,

SINGLE-ENDED MODE.

TO CONVERT T HROUGH THE SEQ UENCE OF

CONSECUTIVE CHANNELS.

DOUT: CONVERSION RESULT FROM CHANNEL 0,

RANGE SELECTED I N RANGE REGIST ER 1.

DOUT: CONVERSION RESULT FROM CHANNEL 1,

RANGE SELECTED I N RANGE REGIST ER 1.

DINTIEDLOW/WRITEBIT=0.

CONTIN UOUSLY CONVERT

STOPPING

A SEQUENCE.

DIN: WRITE TO CONTROL

SEQUENCE, Seq1 = 0, Seq2 = 0.

DOUT: CONVERSION RESULT

FROM CHANNEL IN SEQ UENCE.

ON CONSECUTIVE SEQUENCE

OF CHANNELS.

4852-032

Figure 45. Flowchart for Consecutive Sequence of Channels

Rev. A | Page 26 of 36

Page 27

AD7328

REFERENCE

The AD7328 can operate with either the internal 2.5 V on-chip reference or an externally applied reference. The internal reference is selected by setting the Ref bit in the control register to 1. On power-up, the Ref bit is 0, which selects the external reference for the AD7328 conversion. Suitable reference sources for the AD7328 include

ADR391.

The internal reference circuitry consists of a 2.5 V band gap reference and a reference buffer. When operating the AD7328 in internal reference mode, the 2.5 V internal reference is available at the REFIN/OUT pin, which should be decoupled to AGND using a 680 nF capacitor. It is recommended that the internal reference be buffered before applying it elsewhere in the system. The internal reference is capable of sourcing up to 90 A.

On power-up, if the internal reference operation is required for the ADC conversion, a write to the control register is necessary to set the Ref bit to 1. During the control register write, the conversion result from the first initial conversion is invalid. The reference buffer requires 500 µs to power up and charge the 680 nF decoupling capacitor during the power-up time.

The AD7328 is specified for a 2.5 V to 3 V reference range. When a 3 V reference is selected, the ranges are ±12 V, ±6 V, ±3 V, and 0 V to +12 V. For these ranges, the V equal to or greater than the maximum analog input range selected.

DRIVE

The AD7328 has a V the serial interface operates. V interface to both 3 V and 5 V processors. For example, if the AD7328 is operated with a V powered from a 3 V supply. This allows the AD7328 to accept large bipolar input signals with low voltage digital processing.

AD780, AD1582, ADR431, REF193, and

and VSS supply must be

feature to control the voltage at which

DRIVE

allows the ADC to easily

DRIVE

of 5 V, the V

pin can be

DRIVE

ADD1, and ADD0 to 1. V small dc voltage within the specified pseudo input range for the selected analog input range. When a conversion is initiated in this configuration, the output code represents the temperature (see

Figure 46 and Figure 47). When using the temperature indicator on the AD7328, the part should be operated at low throughput rates, such as approximately 50 kSPS for the ±10 V range and 30 kSPS for the ±2.5 V range. The throughput rate is reduced for the temperature indicator mode because the AD7328 requires more acquisition time for this mode.

4420

4410

4400

4390

4380

4370

ADC OUTP UT CODE

4360

4350

4340

–40 100

–200 20406080

Figure 46. Temperature vs. ADC Output Code for ±10 V Range

5450

5400

5350

5300

5250

ADC OUTP UT CODE

5200

7 must be tied to AGND or to a

±10V RANGE, INT REF

TEMPERATURE (°C)

VCC=V V

DD/VSS

50kSPS

VCC=V V

DD/VSS

±2.5V RANGE INT REFERENCE 30kSPS

DRIVE

= ±12V

DRIVE

= ±12V

=5V

04852-033

TEMPERATURE INDICATOR

The AD7328 has an on-chip temperature indicator. The temperature indicator can be used to provide local temperature measurements on the AD7328. To access the temperature indicator, the ADC should be configured in pseudo differential mode, Mode 1 = Mode 0 = 1, which sets Channel Bits ADD2,

Rev. A | Page 27 of 36

5150

5100

–40

–20 0 20 40 60

TEMPERATURE (°C)

Figure 47. Temperature vs. ADC Output Code for ±2.5 V Range

04852-034

Page 28

AD7328

MODES OF OPERATION

The AD7328 has several modes of operation that are designed to provide flexible power management options. These options can be chosen to optimize the power dissipation/throughput rate ratio for different application requirements. The mode of operation of the AD7328 is controlled by the power management bits, Bit PM1 and Bit PM0, in the control register as shown in Tabl e 11 . The default mode is normal mode, where all internal circuitry is fully powered up.

NORMAL MODE

(PM1 = PM0 = 0)

This mode is intended for the fastest throughput rate performance with the AD7328 being fully powered up at all times. Figure 48 shows the general operation of the AD7328 in normal mode.

The conversion is initiated on the falling edge of and-hold enters hold mode, as described in the section. The data on the DIN line during the 16 SCLK transfer is loaded into one of the on-chip registers if the write bit is set. The register is selected by programming the register select bits (see

Tabl e 8).

116

SCLK

DOUT

DIN

3 CHANNEL I. D. BIT S, SIG N BIT + CO NVERSIO N RESULT

DATA INTO CONTROL/S EQUENCE/ RANGE1/RAN GE2

Figure 48. Normal Mode

, and the track-

Serial Interface

The AD7328 remains fully powered up at the end of the conversion if both PM1 and PM0 contain 0 in the control register.

To complete the conversion and access the conversion result 16 serial clock cycles are required. At the end of the conversion, CS

can idle either high or low until the next conversion.

Once the data transfer is complete, another conversion can be initiated after the quiet time, t

, has elapsed.

QUIET

FULL SHUTDOWN MODE

(PM1 = PM0 = 1)

In this mode, all internal circuitry on the AD7328 is powered down. The part retains information in the registers during full shutdown. The AD7328 remains in full shutdown mode until the power management bits, Bit PM1 and Bit PM0, in the control register are changed.

A write to the control register with PM1 = PM0 = 1 places the part into full shutdown mode. The AD7328 enters full shutdown mode on the 15 is updated.

If a write to the control register occurs while the part is in full shutdown mode with the power management bits, Bit PM1 and Bit PM0, set to 0 (normal mode), the part begins to power up on the 15

SCLK rising edge once the control register is updated. Figure 49 shows how the AD7328 is configured to exit full shutdown mode. To ensure the AD7328 is fully powered up, t should elapse before the next

04852-035

SCLK rising edge once the control register

POWER-UP

falling edge.

PART IS IN FULL SHUTDOWN

SCLK

SDATA

DIN

CONTROL REGISTER IS LOADED ON THE FIRST 15 CLOCKS,

PART BEGINS TO POWER UP ON THE 15TH SCLK RISING EDG E AS PM1 = PM0 = 0

1161

INVALID DATA CHANNEL IDENTIF IER BITS + CONVERSION RESULT

DATA INTO CONTROL REGISTER DATA INTO CONTROL REGISTER

PM1 = 0, PM0 = 0

Figure 49. Exiting Full Shutdown Mode

POWER-U P

Rev. A | Page 28 of 36

THE PART IS F ULLY POWERED UP ONCE

TO KEEP THE PART IN NORMAL MODE, LOAD PM1 = P M0 = 0

POWER-UP

HAS ELAPSED

IN CONTROL REGISTER

04852-041

Page 29

AD7328

AUTOSHUTDOWN MODE AUTOSTANDBY MODE

(PM1 = 1, PM0 = 0) (PM1 = 0, PM0 =1)

Once the autoshutdown mode is selected, the AD7328 automatically enters shutdown on the 15

SCLK rising edge. In autoshutdown mode, all internal circuitry is powered down. The AD7328 retains information in the registers during autoshutdown. The track-and-hold is in hold mode during autoshutdown. On the rising

edge, the track-and-hold, which was in hold during shutdown, returns to track as the AD7328 begins to power up. The time to power-up from auto shutdown is 500 µs.

When the control register is programmed to transition to

autoshutdown mode, it does so on the 15

SCLK rising edge.

Figure 50 shows the part entering the autoshutdown mode.

Once in autoshutdown mode, the

signal must remain low to

keep the part in autoshutdown mode. The AD7328 automatically

begins to power up on the

rising edge. The t

required before a valid conversion, initiated by bringing the

POWER-UP

signal low, can take place. Once this valid conversion is complete, the AD7328 powers down again on the 15

rising edge. The

signal must remain low again to keep the

SCLK

part in autoshutdown mode.

In autostandby mode, portions of the AD7328 are powered down, but the on-chip reference remains powered up. The reference bit in the control register should be 1 to ensure that the on-chip reference is enabled. This mode is similar to autoshutdown but allows the AD7328 to power up much faster, which allows faster throughput rates.

As is the case with autoshutdown mode, the AD7328 enters

standby on the 15 updated (see

SCLK rising edge once the control register is

Figure 50). The part retains information in the registers during standby. The AD7328 remains in standby until it receives a CS CS

rising edge. On the rising edge, the track-and-hold,

rising edge. The ADC begins to power up on the

which was in hold mode while the part was in standby, returns to track.

The power-up time from standby is 700 ns. The user should

ensure that 700 ns have elapsed before bringing

low to attempt a valid conversion. Once this valid conversion is complete, the AD7328 again returns to standby on the 15 SCLK rising edge. The

signal must remain low to keep the

part in standby mode.

Figure 50 shows the part entering autoshutdown mode. The sequence of events is the same when entering autostandby mode. In

Figure 50, the power management bits are configured for autoshutdown. For autostandby mode, the power management bits, PM1 and PM0, should be set to 0 and 1, respectively.

SCLK

SDATA

DIN

PART ENTERS SHUTDO WN MODE ON THE 15TH RISING SCLK EDGE

11615 1 1615

CONTROL REGI STER IS L OADED ON THE FIRST 15 CLOCKS,

AS PM1 = 1, PM0 = 0

VAL ID DATA VAL ID DATA

DATA INTO CONTROL REGISTER DATA INTO CONTROL REGISTER

PM1 = 1, PM0 = 0

TBEGINSTOPOWE

UP ON CS RISING EDGE

Figure 50. Entering Autoshutdown/Autostandby Mode

POWER-UP

THE P

TISFULLYPOWEREDUP

ONCE

POWER- UP

HAS ELAPSED

04852-042

Rev. A | Page 29 of 36

Page 30

AD7328

POWER VS. THROUGHPUT RATE

The power consumption of the AD7328 varies with throughput rate. The static power consumed by the AD7328 is very low, and significant power savings can be achieved as the throughput rate is reduced. throughput rate for the AD7328 at a V tively. Both plots clearly show that the average power consumed by the AD7328 is greatly reduced as the sample frequency is reduced. This is true whether a fixed SCLK value is used or if it is scaled with the sampling frequency. show the power consumption when operating in normal mode for a fixed 20 MHz SCLK and a variable SCLK that scales with the sampling frequency.

Figure 51 and Figure 52 shows the power vs.

of 3 V and 5 V, respect-

Figure 51 and Figure 52

AVERAGE POWER (mW)

0 1000

100 200 300 400 500 600 700 800 900

THROUGHPUT RATE (kHz)

VARIABLE SCLK

20MHz SCLK

VCC=5V

= ±12V

DD/VSS

=25°C

INTERNAL REF ERENCE

Figure 52. Power vs. Throughput Rate with 5 V V

04852-053

AVERAGE POWER (mW)

0 1100

100 200 300 400 500 600 700 800 900 1000

Figure 51. Power vs. Throughput Rate with 3 V V

20MHz SCLK

THROUGHPUT RATE (kSPS)

VARIABLE SCLK

VCC=3V V

DD/VSS

= 25°C

INTERNAL REF ERENCE

= ±12V

04852-052

Rev. A | Page 30 of 36

Page 31

AD7328

SERIAL INTERFACE

Figure 53 shows the timing diagram for the serial interface of the AD7328. The serial clock applied to the SCLK pin provides the conversion clock and controls the transfer of information to and from the AD7328 during a conversion.

The

signal initiates the data transfer and the conversion

process. The falling edge of

puts the track-and-hold into hold mode and takes the bus out of three-state. The analog input signal is then sampled. Once the conversion is initiated, it requires 16 SCLK cycles to complete.

The track-and-hold goes back into track mode on the 14 rising edge. On the 16 to three-state. If the rising edge of

SCLK falling edge, the DOUT line returns

occurs before 16 SCLK cycles

SCLK

have elapsed, the conversion is terminated and the DOUT line

returns to three-state. Depending on where the

signal is brought

high, the addressed register may be updated.

Data is clocked into the AD7328 on the SCLK falling edge. The three MSBs on the DIN line are decoded to select which register is addressed. The control register is a 12-bit register. If the control register is addressed by the three MSBs, the data on the DIN line is loaded into the control on the 15

SCLK rising edge. If the sequence register or either of the range registers is addressed, the data on the DIN line is loaded into the addressed register on the

SCLK falling edge.

Conversion data is clocked out of the AD7328 on each SCLK falling edge. Data on the DOUT line consists of three channel identifier bits, a sign bit, and a 12-bit conversion result. The channel identifier bits are used to indicate which channel corresponds to the conversion result.

If the Weak/

Three-State

than returning to true three-state upon the 16

bit is set in the control register, rather

SCLK falling edge, the DOUT line is pulled weakly to the logic level corresponding to ADD3 of the next serial transfer. This is done to ensure that the MSB of the next serial transfer is set up in time for the first SCLK falling edge after the

Three-State

Weak/

bit is set to 0 and the DOUT line returns to

falling edge. If the

true three-state between conversions, then depending on the particular processor interfacing to the AD7328, the ADD3 bit may be valid in time for the processor to clock it in successfully. If the Weak/

Three-State

bit is set to 1, then although the DOUT line has been driven to ADD3 since the previous conversion, it is nevertheless so weakly driven that another device could take control of the bus. This will not lead to a bus contention issue because, for example, a 10 k pull-up or pull-down resistor is sufficient to overdrive the logic level of ADD3. When the Weak/ Three-State

the

bit is set to 1, the ADD3 is typically valid 9 ns after

falling edge, compared with 14 ns when the DOUT line

returns to three-state at the end of the conversion.

QUIET

04852-036

SCLK

DOUT

DIN

THREE-

STATE

12345 13141516

3 IDENTIFICATION BITS

ADD1

ADD2

WRITE

ADD0 SI GN DB11 DB10 DB2 DB1 DB0

REG

SEL1

MSB

SEL2

Figure 53. Serial Interface Timing Diagram (Control Register Write)

CONVERT

DON’T

LSB

CARE

THREE-STATE

Rev. A | Page 31 of 36

Page 32

AD7328

MICROPROCESSOR INTERFACING

The serial interface on the AD7328 allows the part to be directly connected to a range of different microprocessors. This section explains how to interface the AD7328 with some common microcontroller and DSP serial interface protocols.

AD7328 TO ADSP-21xx

The ADSP-21xx family of DSPs interface directly to the AD7328 without requiring glue logic. The V the same supply voltage as that of the ADSP-21xx. This allows the ADC to operate at a higher supply voltage than its serial interface. The SPORT0 on the ADSP-21xx should be configured as shown in

Tabl e 14 .

Table 14. SPORT0 Control Register Setup

Setting Description

TFSW = RFSW = 1 Alternative framing INVRFS = INVTFS = 1 Active low frame signal DTYPE = 00 Right justify data SLEN = 1111 16-bit data-word ISCLK = 1 Internal serial clock TFSR = RFSR = 1 Frame every word IRFS = 0 ITFS = 1

The connection diagram is shown in Figure 54. The ADSP-21xx has TFS0 and RFS0 tied together. TFS0 is set as an output, and RFS0 is set as an input. The DSP operates in alternative framing mode, and the SPORT0 control register is set up as described in Tabl e 14 . The frame synchronization signal generated on TFS is

tied to

and, as with all signal processing applications, requires equidistant sampling. However, as in this example, the timer interrupt is used to control the sampling rate of the ADC, and under certain conditions equidistant sampling cannot be achieved.

pin of the AD7328 takes

DRIVE

The frequency of the serial clock is set in the SCLKDIV register. When the instruction to transmit with TFS is given (AX0 = TX0), the state of the serial clock is checked. The DSP waits until the SCLK has gone high, low, and high again before starting the transmission. If the timer and SCLK are chosen so that the instruction to transmit occurs on or near the rising edge of SCLK, data can be transmitted immediately or at the next clock edge.

For example, the

ADSP-2111 has a master clock frequency of

16 MHz. If the SCLKDIV register is loaded with the value 3, an SCLK of 2 MHz is obtained, and eight master clock periods elapse for every one SCLK period. If the timer registers are loaded with the value 803, 100.5 SCLKs occur between interrupts and, subsequently, between transmit instructions. This situation leads to nonequidistant sampling because the transmit instruction occurs on an SCLK edge. If the number of SCLKs between interrupts is an integer of N, equidistant sampling is implemented by the DSP.

AD7328 TO ADSP-BF53x

The ADSP-BF53x family of DSPs interfaces directly to the AD7328 without requiring glue logic, as shown in The SPORT0 Receive Configuration 1 register should be set up as outlined in

AD7328

DRIVE

Table 1 5.

SCLK

DIN

DOUT

ADSP-BF53x

RSCLK0

RFS0

DT0

DR0

Figure 55.

AD7328

SCLK

DIN

ADDITIONAL PINS OMIT TED FOR CL ARITY.

DOUT

DRIVE

Figure 54. Interfacing the AD7328 to the ADSP-21xx

SCLK0

TFS0

RFS0

DT0

DR0

ADSP-21xx

04852-037

The timer registers are loaded with a value that provides an interrupt at the required sampling interval. When an interrupt is received, a value is transmitted with TFS/DT (ADC control word). The TFS is used to control the RFS and, hence, the reading of data.

Rev. A | Page 32 of 36

ADDITIONAL PINS OMIT TED FOR CL ARITY.

Figure 55. Interfacing the AD7328 to the ADSP-BF53x

Table 15. SPORT0 Receive Configuration 1 Register

Setting Description

RCKFE = 1 Sample data with falling edge of RSCLK LRFS = 1 Active low frame signal RFSR = 1 Frame every word IRFS = 1 Internal RFS used RLSBIT = 0 Receive MSB first RDTYPE = 00 Zero fill IRCLK = 1 Internal receive clock RSPEN = 1 Receive enable SLEN = 1111 16-bit data-word TFSR = RFSR = 1

04852-038

Page 33

AD7328

APPLICATION HINTS

LAYOUT AND GROUNDING

The printed circuit board that houses the AD7328 should be designed so that the analog and digital sections are confined to certain areas of the board. This design facilitates the use of ground planes that can be easily separated.

To provide optimum shielding for ground planes, a minimum etch technique is generally best. All AGND pins on the AD7328 should be connected to the AGND plane. Digital and analog ground pins should be joined in only one place. If the AD7328 is in a system where multiple devices require an AGND and DGND connection, the connection should still be made at only one point. A star point should be established as close as possible to the ground pins on the AD7328.

Good connections should be made to the power and ground planes. This can be done with a single via or multiple vias for each supply and ground pin.

Avoid running digital lines under the AD7328 device because this couples noise onto the die. However, the analog ground plane should be allowed to run under the AD7328 to avoid noise coupling. The power supply lines to the AD7328 device should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line.

To avoid radiating noise to other sections of the board, components, such as clocks, with fast switching signals should be shielded with digital ground and never run near the analog inputs. Avoid crossover of digital and analog signals. To reduce the effects of feedthrough within the board, traces should be run at right angles to each other. A microstrip technique is the best method, but its use may not be possible with a double-sided board. In this technique, the component side of the board is dedicated to ground planes, and signals are placed on the other side.

Good decoupling is also important. All analog supplies should be decoupled with 10 µF tantalum capacitors in parallel with

0.1 µF capacitors to AGND. To achieve the best results from these decoupling components, they must be placed as close as possible to the device, ideally right up against the device. The

0.1 µF capacitors should have a low effective series resistance (ESR) and low effective series inductance (ESI), such as is typical of common ceramic and surface mount types of capacitors. These low ESR, low ESI capacitors provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching.

Rev. A | Page 33 of 36

Page 34

AD7328

OUTLINE DIMENSIONS

6.60

6.50

6.40

PIN 1

0.15

0.05

COPLANARIT

0.10

0.65

BSC

0.30

0.19

COMPLIANT TO JEDEC STANDARDS MO-153-AC

1.20 MAX

SEATING PLANE

4.50

4.40

4.30

6.40 BSC

0.20

0.09 8°

0°

0.75

0.60

0.45

Figure 56. 20-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-20)

Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Range Package Description Package Option

AD7328BRUZ –40°C to +85°C 20-Lead TSSOP RU-20 AD7328BRUZ-REEL –40°C to +85°C 20-Lead TSSOP RU-20 AD7328BRUZ-REEL7 –40°C to +85°C 20-Lead TSSOP RU-20 EVAL-AD7328CB Evaluation Board EVAL-CONTROL BRD2 Controller Board

Z = Pb-free part.

This can be used as a stand-alone evaluation board or in conjunction with the EVAL-CONTROL board for evaluation/demonstration purposes.

This board is a complete unit allowing a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators. To order a complete

evaluation kit, the particular ADC evaluation board (for example, EVAL-AD7328CB), the EVAL-CONTROL BRD2, and a 12 V transformer must be ordered. See the relevant evaluation board technical note for more information.

Rev. A | Page 34 of 36

Page 35

AD7328

NOTES

Rev. A | Page 35 of 36

Page 36

AD7328

NOTES

Rev. A | Page 36 of 36

Datasheet AD7328 Datasheet (ANALOG DEVICES)

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

PRODUCT HIGHLIGHTS

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

TIMING SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS

TERMINOLOGY

THEORY OF OPERATION

CIRCUIT INFORMATION

Output Coding

Transfer Functions

ANALOG INPUT STRUCTURE

Track-and-Hold Section

TYPICAL CONNECTION DIAGRAM

ANALOG INPUT

Single-Ended Inputs

True Differential Mode

Pseudo Differential Inputs

REGISTERS

ADDRESSING REGISTERS

CONTROL REGISTER

SEQUENCE REGISTER

RANGE REGISTERS

SEQUENCER OPERATION

REFERENCE

TEMPERATURE INDICATOR

MODES OF OPERATION

NORMAL MODE

FULL SHUTDOWN MODE

AUTOSHUTDOWN MODE AUTOSTANDBY MODE

POWER VS. THROUGHPUT RATE

SERIAL INTERFACE

MICROPROCESSOR INTERFACING

AD7328 TO ADSP-21xx

AD7328 TO ADSP-BF53x

APPLICATION HINTS

LAYOUT AND GROUNDING

OUTLINE DIMENSIONS

ORDERING GUIDE