Datasheet AD7327 Datasheet (Analog Devices)

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Page 1

500 kSPS, 8-Channel, Software Selectable

True bipolar Input, 12-Bit Plus Sign ADC

Preliminary Technical Data

FEATURES

• 12-Bit plus Sign SAR ADC

• True Bipolar Input Ranges

• Software Selectable Input Ranges

± 10V, ± 5V, ± 2.5V, 0 to 10V

• 500 ksps Throughput Rate

• Eight Analog Input Channels with Channel Sequencer

• Single Ended, True Differential and Pseudo Differential

Analog Input Capability

• High Analog Input Impedance

• Low Power: 12 mW

• Full Power Signal Bandwidth: 7 MHz

• Internal 2.5 V Reference

• High Speed Serial Interface

• Power Down Modes

• 20-Lead TSSOP package

• iCMOS

• For four and two channel equivalent devices see

GENERAL DESCRIPTION

The AD7327 is an 8-Channel, 12-Bit plus Sign Successive Approximation ADC. The ADC has a high speed serial interface that can operate at throughput rates up to 500 ksps.

The AD7327 can accept true bipolar Analog Input signals. The AD7327 has four software selectable inputs Ranges, ±10V, ±5V, ±2.5V and 0 to 10V. Each analog input channel can be independently programmed to one of the four input ranges.

Process Technology

AD7323 and AD7321 respectively.

AD7327*

FUNCTIONAL BLOCK DIAGRAM

APPROXIMATION

ADC

CONTROL

LOGIC &

REGISTERS

DOUT

SCLK

DIN

DRIVE

Vin0

Vin1

Vin2

Vin3

Vin4

Vin5

Vin6

Vin7

I/P

MUX

CHANNEL

SEQUENCER

AGND

T/H

Figure 1.

2.5V

VREF

REFIN/OUT

13-BIT SUCCESSIVE

DGND

PRODUCT HIGHLIGHTS

1. The AD7327 can accept True Bipolar Analog Input signals, ±10V, ±5V, ±2.5V and 0 to 10V unipolar signals.

2. The Eight Analog Inputs can be configured as 8 Single-Ended inputs, 4 True Differential, 4 Pseudo Differential or 7 Pseudo Differential Inputs.

3. High Speed Serial Interface. SPI/QSPI/DSP/MICROWIRE Compatible. Throughput Rates up to 500 ksps can be achieved.

The Analog input channels on the AD7327 can be programmed

4. Low Power, 26 mW at maximum throughput rate of 500 ksps.

to be Single-Ended, true Differential or Pseudo Differential.

5. Channel Sequencer. The ADC contains a 2.5V Internal reference. The AD7327 also allows for external Reference operation. If a 3V reference is applied the REF ±12V Analog Input. V

pin the AD7327 can accept a true Bipolar

IN/OUT

and VSS supplies of ±12V are required

for the ±12V Input Range.

Table 1. Related Products

Device Number

Throughput Rate - ksps

Number of bits Number of

AD7328 1000 12 bit + Sign 8 AD7324 1000 12 bit + Sign 4 AD7323 500 12 bit + Sign 4 AD7322 1000 12 bit + Sign 2 AD7321 500 12 bit + Sign 2

Channels

* Protected by U.S. Patent No. 6,731,232

iCMOS

Process Technology For analog systems designers within industrial/instrumentation equipment OEMs who need high performance ICs at higher-voltage levels, iCMOS is a technology platform that enables the development of analog ICs capable of 30V and operating at +/- 15V supplies while allowing dramatic reductions in power consumption and package size, and increased AC and DC performance.

Rev. PrA

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies.

www.analog.com

Page 2

Preliminary Technical Data

TABLE OF CONTENTS

AD7327

AD7327—SPECIFICATIONS ............................ 3

ABSOLUTE MAXIMUM RATINGS................. 6

PIN FUNCTIONAL DESCRIPTIONS........................... 7

TERMINOLOGY................................................ 8

THEORY OF OPERATION ......................................... 9

AD7327 REGISTERS........................................ 13

REVISION HISTORY

Revision PrA: Preliminary Version

SEQUENCER OPERATION............................. 17

MODES OF OPERATION ................................ 21

SERIAL INTERFACE.......................................22

OUTLINE DIMENSIONS................................. 23

Rev. PrA | Page 2 of 23

Page 3

Preliminary Technical Data

AD7327—SPECIFICATIONS

Table 2. Unless otherwise noted, V

2.5V Internal/External, f

SCLK

= 10 MHz, fS = 500 ksps TA = T

= + 12V to +16.5V, VSS = -12V to –16.5V, VCC = 2.7V to 5.25V, V

to T

MAX

MIN

= 2.7V to 5.25V, V

DRIVE

Parameter Specification Units Test Conditions/Comments DYNAMIC PERFORMANCE

Signal to Noise Ratio (SNR)

76 dB min Differential Mode

= 50 kHz Sine Wave

72 dB min Single-Ended/Pesudo Differential Mode Signal to Noise + Distortion (SINAD)2 75 dB min Differential Mode

71.5 dB min Single-Ended/Pseudo Differential Mode Total Harmonic Distortion (THD) Peak Harmonic or Spurious Noise (SFDR) 2

Intermodulation Distortion (IMD)

-80 dB max

-80

dB max

= 40.1 kHz, Fb = 41.5 kHz

Second Order Terms -88 dB typ

Third Order Terms Aperature Delay Aperature Jitter

-88 dB typ 10 ns max

50 ps typ Common Mode Rejection (CMRR) TBD dB typ Channel-to-Channel Isolation Full Power Bandwidth

DC ACCURACY

-80 dB typ F

1.5

MHz typ MHz typ

= 400 kHz

@ 3 dB @ 0.1 dB

Resolution 12 + Sign Bits Integral Nonlinearity Differential Nonlinearity

±1.5 LSB max

± 0.95 LSB max Guaranteed No missing Codes to 13-Bits Offset Error2 ±8 LSB max Unipolar Range with Straight Binary output coding Offset Error Match ±0.5 LSB max Gain Error2 ±6 LSB max Gain Error Match ±0.6 LSB max Positive Full-Scale Error

±3 LSB max Bipolar Range with Twos Complement Output Coding Positive Full Scale Error Match ±0.6 LSB max Bipolar Zero Error2 ±8 LSB max Bipolar Zero Error Match ±0.5 LSB max Negative Full Scale Error2 ±4 LSB max Negative Full Scale Error Match ±0.5 LSB max

ANALOG INPUT

Input Voltage Ranges (Programmed via Range Register)

See Table 6

±10

±5

±2.5

0 to 10

V V V V

VDD = +10V min , VSS = -10V min, VCC = 2.7V to 5.25V V

= +5V min, VSS = -5V min, VCC = 2.7V to 5.25V

= +5V min, VSS = - 5V min, VCC = 2.7V to 5.25V

= +10V min, VSS = AGND min, VCC = 2.7V to 5.25V

DC Leakage Current ±10 nA max Input Capacitance 12 pF typ When in Track, ±10V Range 15 pF typ When in Track, ±5V, 0 to 10V Range 20 pF typ When in Track, ±2.5V Range 3 pF typ When in Hold

REFERENCE INPUT/OUTPUT

Input Voltage Range +2.5 to +3V V min to max Input DC Leakage Current ±1 µA max Input Capactiance 20 pF typ Reference Output Voltage 2.49/2.51 Vmin/max Reference Temperature Coefficient 25 ppm/°C max 10 ppm/°C typ Reference Output Impedance 25

Ω typ

AD7327

REF

Rev. PrA | Page 3 of 23

Page 4

AD7327

Preliminary Technical Data

Parameter Specification Units Test Conditions/Comments LOGIC INPUTS

Input High Voltage, V Input Low Voltage, V

2.4 V min

INH

0.8 V max V

INL

0.4 V max V

= 4.75 to 5.25 V

= 2.7 to 3.6 V

Input Current, IIN ± 1 µA max VIN = 0V or VCC

Input Capacitance, C

LOGIC OUTPUTS

Output High Voltage, VOH V Output Low Voltage, VOL 0.4 V max I

10 pF max

- 0.2V V min I

DRIVE

SOURCE

= 200 µA

SINK

= 200 µA

Floating State Leakage Current ±1 µA max Floating State Output Capacitance

Output Coding

10 pF max Straight

Coding bit set to 1 in Control Register Natural Binary

Two’s

Coding bit set to 0 in Control Register Complement

CONVERSION RATE

Conversion Time 1.6 µs max 16 SCLK Cycles with SCLK = 10 MHz Track-and-Hold Acquisition Time 250 ns min Sine Wave Input 250 ns min Full Scale Step input Throughput Rate 500 kSPS max See Serial Interface section

POWER REQUIREMENTS

12V/+16.5V V min/max See Table 6

-12V/16.5V V min/max See Table 6

Digital Inputs = 0V or VCC

VCC 2.7V / 5.25V V min/max See Table 6 V

2.7V/5.25V V min/max

DRIVE

Normal Mode IDD 300 µA max VDD = +16.5V ISS 370 µA max VSS = -16.5V ICC 2 mA max VCC = 5.25V Auto-Standby Mode F

SAMPLE

= TBD IDD TBD µA max ISS TBD µA max ICC 1.6 mA typ Auto-Standby Mode F

SAMPLE

= TBD IDD TBD µA max ISS TBD µA max ICC 1 mA typ Full Shutdown Mode IDD 0.9 µA max ISS 0.9 µA max ICC 0.9 µA max SCLK On or Off

POWER DISSIPATION

Normal Mode 26 mW max V 12 mW typ V Full Shutdown Mode 35 µW max V

= +16.5V, VSS = -16.5V, V

= +5V, VSS = -5V, V

= +16.5V, VSS = -16.5V, V

= 5V,

= 5.25V,

NOTES

Temperature ranges as follows: -40°C to +85°C

See Terminology

Guaranteed by initial Characterization

Functional from VDD = +4.75V and VSS = -4.75

Specifications subject to change without notice.

Rev. PrA | Page 4 of 23

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Preliminary Technical Data

TIMING SPECIFICATIONS

Table 3. Unless otherwise noted,

2.5V Internal/External, T

Parameter Limit at T

SCLK

20 kHz min 10 MHz max t

CONVERT

50 ns min

QUIET

16×t

10 ns min

20 ns max

TBD ns max Data Access Time after SCLK Falling Edge. t5 0.4t t6 0.4t t

10 ns min SCLK to Data Valid Hold Time

25 ns max SCLK Falling Edge to D 10 ns min SCLK Falling Edge to D t

powerup

TBD ns min DIN set-up time prior to SCLK falling edge

5 ns min DIN hold time after SCLK falling edge

1 µs max Power up from Auto Standby

TBD µs max Power up from Full Shutdown/Auto Shutdown Mode

MIN

ns max T

SCLK

ns min SCLK High Pulsewidth

SCLK

VDD = +12V to + 16.5V, VSS = -12 to –16.5V, V

= T

to T

MIN

Unit Description

SCLK

= 1/f

SCLK

Minimum Time between End of Serial Read and Next Falling Edge of

Minimum CS pulse width CS

to SCLK Setup Time

Delay from CS until D

ns min SCLK Low Pulsewidth

, T

MAX

=2.7V to 5.25, V

Three-State Disabled

OUT

High Impedance

OUT

High Impedance

OUT

=2.7V to 5.25, V

DRIVE

AD7327

REF

+5

SCLK

DOUT

DIN

3-STATE

3 IDENTIFICATION BITS

ADD2

WRITE

ADD1

Reg Sel1

ADD0

convert

DB11

DB10

SIGN

MSBReg Sel2

Figure 2. Serial Interface timing Diagram

DB2

DB1

LSB

DB0

DONTC

3-STATE

QUIET

Rev. PrA | Page 5 of 23

Page 6

Preliminary Technical Data

ABSOLUTE MAXIMUM RATINGS

Table 4. T

VDD to AGND, DGND -0.3 V to +16.5 V VSS to AGND, DGND +0.3 V to –16.5 V VCC to AGND, DGND -0.3V to +7V V

DRIVE

AGND to DGND -0.3 V to +0.3 V Analog Input Voltage to AGND

Digital Input Voltage to DGND -0.3 V to +7 V Digital Output Voltage to GND -0.3 V to V REFIN to AGND -0.3 V to VCC +0.3V Input Current to Any Pin Except Supplies Operating Temperature Range -40°C to +85°C Storage Temperature Range -65°C to +150°C Junction Temperature +150°C TSSOP Package θJA Thermal Impedance 143 °C/W θJC Thermal Impedance 45 °C/W Pb/SN Temperature, Soldering

Reflow (10 s to 30 s) 240(+0/-5)°C

Pb-free Temperature, Soldering

Reflow 260(+0)°C

ESD TBD

Transient currents of up to 100 mA will not cause SCR latch-up.

= 25°C, unless otherwise noted

to VCC -0.3 V to VCC + 0.3V

-0.5V to +VDD +

DRIVE

±10mA

0.5V

+0.3V

AD7327

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Rev. PrA | Page 6 of 23

Page 7

Preliminary Technical Data

AD7327

PIN FUNCTIONAL DESCRIPTIONS

Figure 3. AD7327 Pin Configuration TSSOP

Table 5. AD7327 Pin Function Descriptions

Pin Mnemonic Pin Number Description

SCLK 20

OUT

DIN 2

DRIVE

DGND 3, 19

AGND 4

REF

IN/

VCC 16

VDD 15 Positive power supply voltage. This is the positive supply voltage for the Analog Input section. VSS 6 Negative power supply voltage. This is the negavtive supply voltage for the Analog Input section. Vin0-Vin7

OUT

7,8,9,10,11,12, 13,14

Serial Clock. Logic Input. A serial clock input provides the SCLK used for accessing the data from the AD7327. This clock is also used as the clock source for the conversion process.

Serial Data Output. The conversion output data is supplied to this pin as a serial data stream. The bits are clocked out on the falling edge of the SCLK input and 16 SCLKs are required to access the data. The data stream consists of three channel identification bits, followed by the sign bit followed by the 12 bits of conversion data. The data is provided MSB first.

See the Serial interface section. Chip Select. Active low logic input. This input provides the dual function of initiating conversions on

the AD7327 and frames the serial data transfer. Data In. Data to be written to the on-chip registers is provided on this input and is clocked into the

register on the falling edge of SCLK. See AD7327 REGISTERSsection. Logic power supply input. The voltage supplied at this pin determines at what voltage the interface

will operate. This pin should be decoupled to DGND. The voltage at this pin may be different to that

but should never exceed VCC by more than 0.3V.

at V

Digital Ground. Ground reference point for all digital circuitry on the AD7327. The DGND and AGND voltages ideally should be at the same potential and must not be more than 0.3 V apart even on a transient basis.

Analog Ground. Ground reference point for all analog circuitry on the AD7327. All analog input signals and any external reference signal should be referred to this AGND voltage. The AGND and DGND voltages ideally should be at the same potential and must not be more than 0.3 V apart, even on a transient basis.

Reference Input/ Reference Output pin. The on-chip reference is available on this pin for use external to the AD7327. Alternativley, the internal reference can be disabled and an external reference applied to this input. On power up this is the default condition. The nominal internal reference voltage is 2.5 V, which appears at the pin. A 470 nF capacitor should be placed on the Reference pin. (See REFERENCE Section)

Analog Supply Voltage, 2.7 V to 5.25 V. This is the supply voltage for the ADC core on the AD7327. This supply should be decoupled to AGND.

Analog input 0 through Analog Input 7. The analog inputs are multiplexed into the on-chip trackand-hold. The analog input channel for conversion is selected by programming the channel address bits, ADD2 through ADD0, in the control register. The inputs can be configured as 8 SingleEnded Inputs, 4 True Differential Input pairs, 4 Pseudo differential inputs or 7 pseudo differential inputs. The configuration of the Analog inputs is selected by programming the Mode bits, Mode1 and Mode0, in the Control Register. The input range on each input channel is controlled by programming the range registers. Inputs ranges of ±10V, ±5V, ±2.5V and 0 to 10V can be selected on each analog input channel. See Register section.

Rev. PrA | Page 7 of 23

Page 8

Preliminary Technical Data

TERMINOLOGY

Differential Nonlinearity This is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC.

Integral Nonlinearity This is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function. The endpoints of the transfer function are zero scale, a point 1 LSB below the first code transition, and full scale, a point 1 LSB above the last code transition.

Offset Code Error This applies to Straight Binary output coding. It is the deviation of the first code transition (00 . . . 000) to (00 . . . 001) from the ideal, i.e., AGND + 1 LSB.

Offset Error Match This is the difference in Offset Error between any two input channels.

Gain Error This applies to Straight Binary output coding. It is the deviation of the last code transition (111 . . . 110) to (111 . . . 111) from the ideal (i.e., 4 x V

– 1 LSB, 2 x V

REF

the offset error has been adjusted out.

Gain Error Match This is the difference in Gain Error between any two input channels.

Bipolar Zero Code Error This applies when using twos complement output coding and a bipolar Analog Input. It is the deviation of the midscale transition (all 1s to all 0s) from the ideal V

- 1 LSB.

Bipolar Zero Code Error Match This refers to the difference in Bipolar Zero Code Error between any two input channels.

Positive Full Sc ale Error This applies when using twos complement output coding and any of the bipolar Analog Input ranges. It is the deviation of the last code transition (011…110) to (011…111) from the ideal ( +4 x V

- 1 LSB, + 2 x V

REF

bipolar Zero Code Error has been adjusted out.

Positive Full Sc ale Error Match

This is the difference in Positive Full Scale error between any two input channels.

Negative Full Scale Error This applies when using twos complement output coding and any of the bipolar Analog Input ranges. This is the deviation of the first code transition (10…000) to (10…001) from the ideal

REF

– 1 LSB, + V

REF

–1 LSB, V

REF

–1 LSB) after

REF

voltage, i.e., AGND

– 1 LSB) after the

AD7327

(i.e., - 4 x V

+ 1 LSB, - 2 x V

REF

the Bipolar Zero Code Error has been adjusted out.

Negative Full Scale Error Match

This is the difference in Negative Full Scale error between any two input channels.

Track-and-Hold Acquisition Time The track-and-hold amplifier returns into track mode after the fifteenth SCLK falling edge. Track-and-hold acquisition time is the time required for the output of the track-and-hold amplifier to reach its final value, within ±1/2 LSB, after the end of conversion.

Signal to (Noise + Distortion) Ratio

This is the measured ratio of signal to (noise + distortion) at the output of the A/D converter. The signal is the rms amplitude of the fundamental. Noise is the sum of all non-fundamental signals up to half the sampling frequency (f The ratio is dependent on the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. The theoretical signal to (noise + distortion) ratio for an ideal N-bit converter with a sine wave input is given by:

Signal to (Noise + Distortion) = (6.02N + 1.76) dB

Thus for a 13-bit converter, this is 80.02 dB.

Total Harmonic Distortion

Total harmonic distortion (THD) is the ratio of the rms sum of harmonics to the fundamental. For the AD7327 it is defined as:

dBTHD

where V V

is the rms amplitude of the fundamental and V2, V3,

, V5 and V6 are the rms amplitudes of the second through the

log20)(

sixth harmonics.

Peak Harmonic or Spurious Noise Peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the ADC output spectrum (up to fS/2 and excluding dc) to the rms value of the fundamental. Normally, the value of this specification is determined by the largest harmonic in the spectrum, but for ADCs where the harmonics are buried in the noise floor, it will be a noise peak.

Channel-to-Channel Isolation Channel-to-channel isolation is a measure of the level of crosstalk between any two channels. It is measured by applying a full-scale, 400 kHz sine wave signal to all unselected input channels and determining how much that signal is attenuated in the selected channel with a 50 kHz signal. The figure given is the worst-case across all eight channels for the AD7327.

REF

+ 1 LSB, - V

+ 1 LSB) after

REF

/2), excluding dc.

VVVVV

++++

Rev. PrA | Page 8 of 23

Page 9

Preliminary Technical Data AD7327

Intermodulation Distortion

With inputs consisting of sine waves at two frequencies, fa and fb, any active device with non-linearities will create distortion products at sum and difference frequencies of mfa ± nfb where m, n = 0, 1, 2, 3, etc. Intermodulation distortion terms are those for which neither m nor n are equal to zero. For example, the second order terms include (fa + fb) and (fa – fb), while the third order terms include (2fa + fb), (2fa – fb), (fa + 2fb) and (fa – 2fb).

The AD7327 is tested using the CCIF standard where two input frequencies near the top end of the input bandwidth are used. In this case, the second order terms are usually distanced in frequency from the original sine waves while the third order terms are usually at a frequency close to the input frequencies. As a result, the second and third order terms are specified separately. The calculation of the intermodulation distortion is as per the THD specification where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals expressed in dBs.

Table 6. Reference and Supply Requirements for each Analog Input Range

Selected Analog Input Range (V)

±10

± 5

±2.5

0 to 10

Reference Voltage (V)

2.5 ±10 3/5 ±10

3.0 ±12 3/5 ±12

2.5 ±5 3/5 ±5

3.0 ±6 3/5 ±6

2.5 ±2.5 3/5 ±5

3.0 ±3 3/5 ±5

2.5 0 to 10 3/5 +10/AGND

3.0 0 to 12 3/5 +12/AGND

Full Scale Input Range(V)

AV (V)

Minimum VDD/V

(V)

In order to meet the specified performance specifications when the AD7327 is configured with the minimum V

and VSS

supplies for a chosen Analog input range, the throughput rate should be decreased from the maximum throughput range. See typical performance curves.

PSR (Power Supply Rejection) Variations in power supply will affect the full-scale transition but not the converter’s linearity. Power supply rejection is the maximum change in full-scale transition point due to a change in power supply voltage from the nominal value. See Typical Performance Curves.

THEORY OF OPERATION

CIRCUIT INFORMATION

The AD7327 is a fast, 8-Channel, 12-bit plus sign, bipolar Input, serial A/D converter. The AD7327 can accept bipolar input ranges that include ±10V, ±5V, ±2.5V, it can also accept 0 to 10V unipolar input range. A different Analog input range can be programmed on each analog input channel via the on-chip registers. The AD7327 has a high speed serial interface that can operate at throughput rates up to 500 ksps.

The AD7327 requires V

and V

voltage Analog input structures. These supplies must be equal to or greater than the Analog input range. See Table 6 for the requirements on these supplies for each Analog Input Range. The AD7327 requires a low voltage 2.7V to 5.25 V V power the ADC core.

dual supplies for the high

supply to

The Analog Inputs can be configured as either 8 Single-Ended inputs, 4 True Differential Inputs, 4 Pseudo Differential Inputs or 7 Pseudo Differential Inputs. Selection can be made by programming the Mode bits, Mode0 and Mode1, in the Control Register.

The serial clock input accesses data from the part but also provides the clock source for each successive approximation ADC. The AD7327 has an on-chip 2.5 V reference. However the AD7327 can also work with an external Reference. On power up the external reference operation is the default option. If the internal Reference is the preferred option the user must write to the reference bit in the control register to select the internal Reference operation.

The AD7327 also features power-down options to allow power saving between conversions. The power-down modes are selected by programming the on-chip Control Register, as described in the

modes of operation section.

Rev. PrA | Page 9 of 23

Page 10

AD7327 Preliminary Technical Data

CONVERTER OPERATION The AD7327 is a successive approximation analog-to-digital

converter, based around two capacitive DACs. Figure 4 and Figure 5 show simplified schematics of the ADCs in Single Ended Mode during the acquisition and conversion phase, respectively. Figure 6 and Figure 7 show simplified schematics of the ADCs in Differential Mode during acquisition and conversion phase, respectively. The ADC is comprised of control logic, a SAR, and a capacitive DAC. In Figure 4 (the acquisition phase), SW2 is closed and SW1 is in position A, the comparator is held in a balanced condition, and the sampling capacitor array acquires the signal on the input.

CAPACITIVE

DAC

CONTROL

LOGIC

Vin0

AGND

SW1

COMPARATOR

SW2

Figure 4. ADC Acquisition Phase(Single Ended)

When the ADC starts a conversion (Figure 5), SW2 will open and SW1 will move to position B, causing the comparator to become unbalanced. The control logic and the charge redistribution DAC is used to add and subtract fixed amounts of charge from the capacitive DAC to bring the comparator back into a balanced condition. When the comparator is rebalanced, the conversion is complete. The Control Logic generates the ADC output code

CAPACITIVE

DAC

CONTROL

LOGIC

Vin0

AGND

SW1

COMPARATOR

SW2

Figure 5. ADC Conversion Phase(Single Ended)

Figure 6 shows the differential configuration during the Acquisition phase. For the Conversion Phase, SW3 will open, SW1 and SW2 will move to position B, Figure 7. The output impedances of the source driving the Vin+ and Vin- pins must be matched; otherwise the two inputs will have different settling times, resulting in errors.

COMPARATOR

SW3

Vin+

Vin-

SW1

SW2

REF

Figure 7. ADC Differential Configuration during Conversion Phase

Output Coding The AD7327 default output coding is set to two’s complement. The output coding is controlled by the Coding bit in the Control Register. To change the output coding to Straight Binary Coding the Coding bit in the Control Register must be set. When operating in Sequence mode the output coding for each channel in the sequence will be the value written to the coding bit during the last write to the Control Register.

Transfer Functi o n s The designed code transitions occur at successive integer LSB values (i.e., 1 LSB, 2 LSB, and so on). The LSB size is dependant on the Analog input Range selected.

Table 7. LSB sizes for each Analog Input Range

Input Range Full Scale Range/8192 LSB Size

±10V 20V/8192 2.441 mV

±5V 10V/8192 1.22 mV

±2.5V 5V/8192 0.61 mV

0 to 10V 10V/8192 1.22 mV

The ideal transfer characteristic for the AD7327 when Twos Complement coding is selected is shown in Figure 8, and the ideal transfer characteristic for the AD7327 when Straight Binary coding is selected is shown in Figure 9.

CAPACITIVE

DAC

CONTROL

LOGIC

CAPACITIVE

DAC

CAPACITIVE

DAC

CONTROL

LOGIC

CAPACITIVE

DAC

Vin+

Vin-

SW1

SW2

REF

COMPARATOR

SW3

Figure 6. ADC Differential Configuration during Acquisition Phase

Rev. PrA | Page 10 of 23

Figure 8 Twos Complement Transfer Characteristic (Bipolar Ranges)

Page 11

Preliminary Technical Data AD7327

The Capacitor C1, in figure 10 and 11 is typically 4 pF and can primarily be attributed to pin capacitance. The resistor R1, is a lumped component made up of the on-resistance of the input multiplexer and the track-and-hold switch. The Capacitor C2, is the sampling capacitor, its capacitance will vary depending on the Analog input range selected. (See AD7327—Specifications section)

Track-and-Hold Section

The Track-and-Hold on the Analog Input of the AD7327 allows

Figure 9. Straight Binary Transfer Characteristic (Bipolar Ranges)

ANALOG INPUT

The analog inputs of the AD7327 may be configured as SingleEnded, True differential or Pseudo Differential via the Control Register Mode Bits as shown in Table 3 of the Register Section. The AD7327 can accept True bipolar input signals. On power up the Analog inputs will operate as 8 Single-Ended Analog Input Channels. If True Differential or Pseudo Differential is required, a write to the Control register is necessary to change this configuration after power up.

the ADC to accurately convert an input sine wave of full scale amplitude to 13-Bit accuracy. The input bandwidth of the Track-and-Hold is greater than the Nyquist rate of the ADC , the AD7327 can handle frequencies up to 7 MHz.

The Track-and-Hold enters its tracking mode on the 14

SCLK

rising edge after the CS falling edge. The time required to acquire an input signal will depend on how quickly the sampling capacitor is charged. With zero source impedance 250 ns will be sufficient to acquire the signal to the 13-bit level.

The acquisition time required is calculated using the following formula:

Figure 10 shows the equivalent Analog input circuit of the AD7327 in Single-Ended Mode. Figure 11 shows the equivalent Analog input structure in Differential mode. The Two Diodes provide ESD protection for the Analog Inputs.

Vin0

Figure 10. Equivalent Analog Input Circuit-(Single Ended)

Vin+

Vin-

Figure 11. Equivalent Analog Input Circuit-(Differential)

C2R1

Care should be taken to ensure the Analog Input never exceeds the V

and VSS supply rails by more than 300 mV. This will

cause the diodes to become forward biased and start conducting into either the V

or VSS rails. These diodes can

conduct up to 10 mA without causing irreversible damage to the part.

= 10 x ((R

ACQ

SOURCE

+ R) C)

where C is the Sampling Capacitance and R is the resistance seen by the track-and-hold amplifier looking back on the input. For the AD7327, the value of R will include the on-resistance of the input multiplexer. The value of R is typically 300 Ω. R

SOURCE

should include any extra source impedance on the Analog input.

The AD7327 enters track on the fifteenth SCLK falling edge. When running the AD7327 at a throughput rate of 500 ksps with a 10 MHz SCLK signal the ADC will have approximately 1 SCLK period plus t

plus the quiet time, T

, in order to

QUIET

acquire the analog input signal. The ADC goes back into hold

on the

falling edge.

TYPICAL CONNECTION DIAGRAM

Figure 12 shows a typical connection diagram for the AD7327. In this configuration the AGND pin is connected to the Analog ground plane of the system. The DGND pin is connected to the Digital ground plane of the system. The Analog Inputs on the AD7327 can be configured to operate in Single Ended, True Differential or Pseudo Differential Mode. The AD7327 can operate with either the internal or an external reference. In Figure 12, the AD7327 is configured to operate with the internal

2.5V reference. A 470 nF decoupling capacitor is required when operating with the internal reference.

The V voltage. The V voltage analog input structures. The voltage on these pins must be equal to or greater than the highest analog input range

pin can be connected to either a 3V or a 5V supply

and VSS are the dual supplies for the high

Rev. PrA | Page 11 of 23

Page 12

AD7327 Preliminary Technical Data

selected on the analog input channels, see Table 6 for more information. The V of the microprocessor. The voltage applied to the V controls the voltage of the serial interface.

pin is connected to the supply voltage

DRIVE

input

DRIVE

Figure 12. Typical Connection Diagram

Rev. PrA | Page 12 of 23

Page 13

Preliminary Technical Data

AD7327

AD7327 REGISTERS

The AD7327 has four-programmable registers, the Control Register, Sequence Register, Range Register1 and Range Register2. These registers are write only registers.

Addressing these Registers

A serial transfer on the AD7327 consists of 16 SCLK cycles. The three MSBs on the DIN line during this 16 SCLK transfer are decoded to determine which register is addressed. The three MSBs consists of the Write bit, Register Select 1 bit and Register Select 2 bit. The Register Select bits are used to determine which of the four on-board registers is selected. The Write bit will determine if the Data on the DIN line following the Register select bits will be loaded into the addressed register or not. If the Write bit is 1 the bits will be loaded into the register addressed by the Register Select bits. If the Write Bit is a 0 the data on the DIN will not be loaded into any register.

Table 8. Decoding Register Select bits and Write bit.

Write Register Select1 Register Select2 Comment

0 0 0 Data on the DIN line during this serial transfer will be ignored 1 0 0

1 0 1

1 1 0

1 1 1

CONTROL REGISTER

This combination selects the Control Register. The subsequent 12 bits will be loaded into the Control Register.

This combination selects the Range Register 1 . The subsequent 8 bits will be loaded into the Range Register1.

This combination selects the Range Register 2. The subsequent 8 bits will be loaded into the Range Register 2.

This combination selects the Sequence Register. The subsequent 8 bits will be loaded into the Sequence Register.

The Control Register is used to select the Analog Input Channel for conversion, Analog Input configuration, Reference, Coding, Power mode etc. The Control Register is a write only 12-bit register. Data loaded on the DIN line corresponds to the AD7327 configuration for the next conversion. Data should be loaded into the Control Register after the Range Registers and the Sequence Register has been initialized, that is if the Sequence register is being used. The bit functions of the Control Register are outlined in Table 9.

Control Register (The Power-up status of all bits is 0)

MSB LSB

Write

Select 1

ADD2 ADD1 ADD0 Mode1 Mode0 PM1 PM0 Coding Ref Seq1 Seq2

Weak/

Tri-State

Rev. PrA | Page 13 of 23

Page 14

AD7327 Preliminary Technical Data

Table 9. Control Register

Bit Mnemonic Comment

12,11,10

9, 8

7,6 PM1, PM0

5 Coding

4 Ref

3,2 Seq1/Seq2 The Sequence 1 and Sequence 2 bits are used to control the operation of the Sequencer. See

ADD2, ADD1, ADD0

Mode1, Mode0

Tri-State

Weak/

These three Channel Address bits are used to select the analog input channel for the next conversion if the Sequencer is not being used. If the Sequencer is being used, these three Channel Address bits are used to select the final channel in a consecutive sequence.

These two mode bits are used to select the configuation on the eight Analog Input Pins. They are used in conjunction with the channel Address bits. On the AD7327 the analog inputs can be configured as either 8 Single Ended Inputs, 4 Fully Differential Inputs, 4 Pseudo Differential inputs or 7 Pseudo Differential Inputs. See Table 10.

Power Management Bits. These two bits are used to select different power mode options on the AD7327. See Table 11.

This bit is used to select the type of output coding the AD7327 will use for the next conversion result. If the Coding = 0 then the output coding will be 2s Complement. If Coding = 1, then the output coding will be Straight Binary. When operating in Sequence mode the output coding for each channel will be the value written to the coding bit during the last write to the Control Register.

Reference bit. This bit is used to enable or disable the internal reference. If this Ref = 0 then the External Reference will be enabled and used for the next conversion and the internal reference will be disabled. If Ref = 1 then the Internal Reference will be used for the next conversion. When operating in Sequence mode the Reference used for each channel will be the value written to the Ref bit during the last write to the Control Register.

Table 12. This bit selects the state of the DOUT line at the end of the current serial transfer. If it is set to 1, the DOUT line

will be weakly driven to the channel address bit ADD2 of the ensuing conversion. If this bit is set to 0, then DOUT will return to three-state at the end of the serial transfer. See the Serial interface section for more details.

The 8 Analog Input channels can be configured as either, 7 Pseudo Differential Analog Inputs, 4 Pseudo Differential Inputs, 4 True Differential Inputs or 8 Single Ended Analog Inputs.

Table 10. Analog Input Configuration Selection

Channel Address Bits Mode1 =1, Mode0 = 1 Mode1 = 1, Mode0 =0 Mode1 = 0, Mode0 =1 Mode1 =0, Mode0 =0

7 Pseudo Differential I/ps 4 Fully Differential i/ps 4 Pseudo Differential i/ps Eight-Single Ended i/ps

ADD2 ADD1 ADD0 Vin+ Vin- Vin+ Vin- Vin+ Vin- Vin+ Vin-

0 0 0 Vin0 Vin7 Vin0 Vin1 Vin0 Vin1 Vin0 AGND 0 0 1 Vin1 Vin7 Vin0 Vin1 Vin0 Vin1 Vin1 AGND 0 1 0 Vin2 Vin7 Vin2 Vin3 Vin2 Vin3 Vin2 AGND 0 1 1 Vin3 Vin7 Vin2 Vin3 Vin2 Vin3 Vin3 AGND 1 0 0 Vin4 Vin7 Vin4 Vin5 Vin4 Vin5 Vin4 AGND 1 0 1 Vin5 Vin7 Vin4 Vin5 Vin4 Vin5 Vin5 AGND 1 1 0 Vin6 Vin7 Vin6 Vin7 Vin6 Vin7 Vin6 AGND 1 1 1 Not Allowed Vin6 Vin7 Vin6 Vin7 Vin7 AGND

Rev. PrA | Page 14 of 23

Page 15

Preliminary Technical Data AD7327

Table 11. Power Mode Selection

PM1 PM0 Description

Full Shutdown Mode, In this mode all internal circuitry on the

1 1

1 0

0 1

0 0 Normal Mode, All internal Circuitry is powered up at all times.

Table 12. Sequencer Selection

AD7327 is powered down. Information in the Control register is retained when the AD7327 is in Full Shutdown Mode.

Auto Shutdown Mode, The AD7327 will enter Full Shut down at the end of each conversion when the control register is updated. All internal circuitry is powered down in Full Shutdown.

Auto Standby Mode, In this mode all internal circuitry is powered down excluding the internal Reference. The AD7327 will enter Auto Standby Mode at the end of the Conversion after the control register is updated.

Seq1 Seq2 Sequence type

0 0

0 1

1 0

1 1

The Channel Sequencer is not used. The Analog Channel selected by programming the ADD2 to ADD0 bits in the Control Register selects the next channel for conversion.

This selects the Sequence of Channels as previously programmed in the Sequence register for conversion. The AD7327 will start converting on the lowest channel in the sequence. It converts the channels in ascending order. If uninterrupted the AD7327 will keep converting the sequence. The range for each channel will default to the Ranges previously written into the Range Registers.

This Configuration is used in conjunction with the Channel Address Bits in the Control Register. It allows continuous conversions on a consecutive sequence of channels, from channel 0, up to and including, a final channel selected by the Channel Address Bits in the control register. The range for each channel will default to the Ranges previously written into the Range Registers.

The Channel Sequencer is not used. The Analog Channel selected by programming the ADD2 to ADD0 bits in the Control Register selects the next channel for conversion.

THE SEQUENCE REGISTER

The Sequence Register on the AD7327 is an 8-Bit Write only register. Each of the eight Analog input channels has one corresponding bit in the Sequence Register. To select a channel for inclusion in the sequence set the corresponding channel bit to 1 in the Sequence Register.

Sequence Register

MSB LSB

Write Register Select 1 Register Select 2 Vin0 Vin1 Vin2 Vin3 Vin4 Vin5 Vin6 Vin7

0 0 0 0 0

Rev. PrA | Page 15 of 23

Page 16

AD7327 Preliminary Technical Data

THE RANGE REGISTERS

The Range register to used to select one Analog input Range per Analog input channel. Range Register 1 is used to set the Ranges for Channels 0 to 3. It is an 8-Bit write only Register, with two dedicated Range bits for each of the Analog Input Channels from Channel 0 to Channel3 . There are four Analog input Ranges to choose from, ±10V, ±5V, ±2.5V, 0 to 10V. A write to the Range Register1 is selected by setting the Write bit to 1 and the Range Select bits to 0, 1. Once the initial write to the Range Register1 occurs the AD7327 automatically configure the Analog inputs from Channel 0 to Channel 3 to the appropriate range, as indicated by the Range register1, each time any one of these analog input channels is selected. The ±10V input Range is selected by default on each analog input channel. See Table 13.

Range Register 1

MSB LSB Write Reg Select 1 Reg Select2 Vin0A Vin0B Vin1A Vin1B Vin2A Vin2B Vin3A Vin3B 0 0 0 0 0

Range Register 2 is used to set the Ranges for Channels 4 to 7. It is an 8-Bit write only Register, with two dedicated Range bits for each of the Analog Input Channels from Channel 4 to Channel7 . There are four Analog input Ranges to choose from, ±10V, ±5V, ±2.5V, 0 to 10V. A write to the Range Register2 is selected by setting the Write bit to 1 and the Range Select bits to 1, 0. Once the initial write to the Range Register2 occurs the AD7327 automatically configure the Analog inputs from Channel 4 to Channel 7 to the appropriate range, as indicated by the Range register2, each time any of these analog input channels is selected. The ±10V input Range is selected by default on each analog input channel. See Table 13.

Range Register 2

MSB LSB Write Reg Select1 Reg Select 2 Vin4A Vin4B Vin5A Vin5B Vin6A Vin6B Vin7A Vin7B 0 0 0 0 0

Table 13. Range Selection

VinXA VinXB Description

0 0

0 1

1 0

1 1

This combination selects the ± 10V Input Range on Analog Input X.

This combination selects the ±5V Input Range on Analog Input X.

This combination selects the ± 2.5V Input Range on Analog Input X.

This combination selects the 0 to 10V Input Range on Analog Input X.

Rev. PrA | Page 16 of 23

Page 17

Preliminary Technical Data

SEQUENCER OPERATION

POWER ON

AD7327

DIN:- WRITE TO CONTROL REGISTER TO

STOP THE SEQUENCE, SEQ1 = 0, SEQ2

= 0.

DOUT:- CONVERSION RESULT FROM

CHANNEL IN SEQUENCE

DIN:- WRITE TO RANGE REGISTER 1 TO SELECT THE RANGE FOR EACH ANALOG

INPUT CHANNEL

DOUT:- CONVERSION RESULT FROM CHANNEL O, ± 10V RANGE, SINGLE-ENDED MODE.

DIN:- WRITE TO RANGE REGISTER 2 TO SELECT THE RANGE FOR EACH ANALOG

INPUT CHANNEL

DOUT:- CONVERSION RESULT FROM CHANNEL O, SINGLE-ENDED MODE, RANGE

SELECTED IN RANGE REGISTER 1

DIN:- WRITE TO SEQUENCE REGISTER TO SELECT THE ANALOG INPUT CHANNELS

TO BE INCLUDED IN THE SEQUENCE

DOUT:- CONVERSION RESULT FROM CHANNEL O, SINGLE-ENDED MODE, RANGE

SELECTED IN RANGE REGISTER 1

DIN:- WRITE TO CONTROL REGISTER TO START THE SEQUENCE, SEQ1 = 0, SEQ2 = 1.

DOUT:- CONVERSION RESULT FROM CHANNEL O, SINGLE-ENDED MODE, RANGE

SELECTED IN RANGE REGISTER 1

DIN:- TIE DIN LOW/WRIT E BIT = 0 TO CONTINUE TO CONVERT THROUGH THE

SEQUENCE OF CHANNELS

DOUT:- CONVERSION RESULT FROM FIRST CHANNEL IN THE SEQUENCE

CONTINUOUSLY CON-

STOPPING A

SEQUENCE

SELECTING A NEW SEQUENCE

VERT ON THE SELECT-

ED SEQUENCE OF

CHANNELS

DIN TIED LOW/WRITE BIT = 0

DIN:- WRITE TO SEQUENCE REGISTER TO SELECT THE NEW SEQUENCE

DOUT:- CONVERSION RESULT FROM CHANNEL X IN THE FIRST SEQUENCE

Figure 13. Programmable sequence Flow Chart

The AD7327 can be configured to automatically cycle through a number of selected channels using the on-chip sequence register and the SEQ1 and SEQ2 bits in the control register. Figure 13 shows how to program the AD7327 register in order to operate in sequence mode.

After power up all of the four on-chip registers will contain default values. Each analog input will have a default input range of ± 10V. If different Analog input ranges are required then a write to the range registers is required, this is shown in the first two serial transfers in Figure 13. These two initial serial

Rev. PrA | Page 17 of 23

transfers are only necessary if Input ranges other than the default Ranges are required. After the Analog Input ranges are configured a write to the Sequence register is necessary to select the channels to be included in the sequence. Once the channels for the sequence have been selected, the sequence can be initiated by writing to the control register and setting the SEQ1 =0, SEQ2 = 1. The AD7327 will continue to convert through the selected sequence uninterrupted provided the Sequence Register remains unchanged and SEQ1 = 0 and SEQ2 = 1 in the Control Register.

If during a sequence a change to one of the range registers is

Page 18

AD7327 Preliminary Technical Data

required, it is first necessary to stop the sequence by writing to the Control Register and setting SEQ1 = 0 and SEQ2 = 0. Next the write to the range register can be completed to change the required range. Then the previously selected sequence can be initiated again by writing to the Control Register and setting SEQ1 = 0 and SEQ2 = 1, the ADC will then convert on the first channel in the sequence.

The AD7327 can be configured to convert a sequence of consecutive channels, See Figure 14. This sequence will begin by converting on channel 0 and end with a final channel as selected by bits ADD2 to ADD0 in the Control Register. In this configuration there is no need for a write to the Sequence register. To operate the AD7327 in this mode set SEQ1 = 1 and SEQ2 = 0 and select the final channel in the sequence by

programming bits ADD2 to ADD0 in the Control Register. Once the control register is configured to operate the AD7327 in this mode the DIN line can be held low or the WRITE bit can be set to 0 in order to keep the AD7327 operating in this mode. To return to traditional multichannel operation a write to the Control Register is necessary, setting SEQ1 = 0 and SEQ2 =0.

When the SEQ1 and SEQ2 are both set to 0 or when both are set to 1 the AD7327 is configured to operate in traditional multichannel mode where a write to the channel Address bits, ADD2 to ADD0, in the Control Register selects the next channel for conversion.

Rev. PrA | Page 18 of 23

Page 19

Preliminary Technical Data

DIN:- WRITE TO RANGE REGISTER 1 TO SELECT THE RANGE FOR ANALOG INPUT

CHANNELS

DOUT:- CONVERSION RESULT FROM CHANNEL O, ± 10V RANGE, SINGLE-ENDED

MODE.

DIN:- WRITE TO RANGE REGISTER 2 TO SELECT THE RANGE FOR ANALOG INPUT

CHANNELS

DOUT:- CONVERSION RESULT FROM CHANNEL O, RANGE SELECTED IN RANGE

DIN:- WRITE TO CONTROL REGISTER TO SELECT THE FINAL CHANNEL IN THE

CONSECUTIVE SEQUENCE, SET SEQ1 = 1 AND SEQ2 = 0. SELECT OUTPUT CODING

FOR SEQUENCE.

DOUT;- CONVERSION RESULT FROM CHANNEL 0, RANGE SELECTED IN RANGE

REG 1, SINGLE-ENDED MODE

DIN:- WRITE BIT = 0 OR DIN LINE HELD LOW TO CONTINUE THROUGH SEQUENCE

OF CONSECUTIVE CHANNELS

DOUT;- CONVERSION RESULT FROM CHANNEL 0, RANGE SELECTED IN RANGE

REG 1, SINGLE-ENDED MODE

DIN:- WRITE BIT = 0 OR DIN LINE HELD LOW TO CONTINUE THROUGH SEQUENCE

OF CONSECUTIVE CHANNELS

DOUT;- CONVERSION RESULT FROM CHANNEL 1, RANGE SELECTED IN RANGE

REG 1, SINGLE-ENDED MODE

POWER ON

STOPPING A

SEQUENCE

CONTINUOUSLY CON-

VERT ON CONSECU-

TIVE SEQUENCE OF

CHANNELS

AD7327

DIN TIED LOW/WRITE BIT = 0

Rev. PrA | Page 19 of 23

DIN:- WRITE TO CONTROL REGISTER TO

STOP THE SEQUENCE, SEQ1 = 0, SEQ2

= 0.

DOUT:- CONVERSION RESULT FROM

CHANNEL IN SEQUENCE

Figure 14 Flow Chart for Consecutive Sequence of Channels

Page 20

Preliminary Technical Data

REFERENCE

The AD7327 can operate with either the internal 2.5V on-chip reference or an externally applied reference. The internal reference is selected by setting the REF bit in the Control Register to 1. On power up the REF bit will be 0, selecting the external Reference for the AD7327 conversion. For external reference operation the REF to AGND with a 470 nF capacitor.

The internal Reference circuitry consists of a 2.5V band gap reference and a reference buffer. When operating the AD7327 in internal Reference mode the 2.5V internal reference is available at the REF internal reference the REFIN/REFOUT pin should be decoupled to AGND using a 470 nF cap. It is recommended that the Internal Reference be buffered before applying it else where in the system.

The AD7327 is specified for a 2.5V to 3V reference range. When a 3V reference is selected the ranges will be, ±12V, ±6V, ±3V and 0 to 12V. For these ranges the V equal to or greater than the max Analog Input Range selected.

/REF

pin. When using the AD7327 with the

OUT

/REF

pin should be decoupled

OUT

and VSS supply must be

AD7327

On power up if the internal reference operation is required for the ADC conversion a write to the control register is necessary to set the REF bit to 1. During the Control Register write the conversion result from the first initial conversion will be invalid. The reference buffer will require TBD µs to power up and charge the 470 nF decoupling cap, during the power up time the conversion result from the ADC will be invalid.

Rev. PrA | Page 20 of 23

Page 21

Preliminary Technical Data AD7327

MODES OF OPERATION

The AD7327 has a number of different modes of operation. These modes are designed to provide flexible power management options. These options can be chosen to optimize the power dissipation/throughput rate ratio for the differing application requirements. The mode of operation of the AD7327 is controlled by the Power Management bits, PM1 and PM0, in the Control register as detailed in Table 11.The default mode is Normal Mode, where all internal circuitry is fully powered up.

Normal Mode (PM1 = PM0 = 0)

This mode is intended for the fastest throughput rate performance, the AD7327 is fully powered up at all times. Figure 15 shows the general diagram of operation of the AD7327 in Normal Mode.

If a write to the control register occurs while the part is in Full Shut down mode, with the power management bits, PM1 and PM0 set to 0, Normal mode, the part will begin to power up on

rising edge.

the

To ensure the AD7327 is fully powered up, t

elapse before the next

falling edge.

POWER UP

, shoul d

Auto Shutdown Mode (PM1 = 1, PM0 = 0)

Once the Auto Shutdown mode is selected the AD7327 will automatically enter shutdown at the end of each conversion. The AD7327 retains information in the registers during Shutdown. The track-and-hold is in hold during shutdown. On

the falling

edge, the track-and-hold that was in hold during

shutdown will return to track.

The power-up from Auto Shutdown is TBD µs

The Conversion is initiated on the falling edge of

and the

track and hold will enter hold mode as described in the Serial Interface Section. The Data on the DIN line during the 16 SCLK transfer will be loaded into one of the on-chip registers, provided the Write bit is set. The register is selected by programming the Register select bits, see Table 8 in the Register section.

Figure 15. Normal Mode

The AD7327 will remain fully powered up at the end of the conversion provided both PM1 and PM0 contain 0 in the control Register.

Sixteen serial clock cycles are required to complete the conversion and access the conversion result. At the end of the

conversion

may idle high until the next conversion or may

idle low until sometime prior to the next conversion.

Once the data transfer is complete, another conversion can be initiated after the quiet time, t

, has elapsed.

QUIET

Full Shutdown Mode (PM1 = PM0 = 1)

In this mode the power consumption of the AD7327 is greatly reduced with the part entering shutdown at the end of each conversion. When the control registers is programmed to move into Auto Shutdown mode, it does so at the end of the conversion.

Auto Standby Mode (PM1 = 0, PM0 =1)

In Auto Standby mode portions of the AD7327 are powered down but the on-chip reference remains powered up. The reference bit in the Control register should be 0 to ensure the on-chip reference is enabled. This mode is similar to Auto Shutdown but allows the AD7327 to power up much faster, allowing faster throughput rates to be achieved.

The AD7327 will enter standby at the end of the conversion. The part retains information in the Registers during Standby.

The AD7327 will remain in standby until it receives a edge. The ADC will begin to power up on the On this

falling edge the track-and-hold that was in hold

falling

falling edge.

mode while the part was in Standby will return to track. Wakeup time from Standby is 1 µs. The user should ensure that 1 µs has elapsed before attempting a valid conversion. When running the AD7327 with the maximum 10 Mhz SCLK, one dummy conversion of 16 x SCLKs is sufficient to power up the ADC. This dummy conversion effectively halves the throughput rate of the AD7327, with every second conversion result being a valid result. Once Auto Standby mode is selected, the ADC can

move in and out of the low power state by controlling the signal.

In this mode all internal circuitry on the AD7327 is powered down. The part retains information in the Registers during Full Shut down. The AD7327 remains in Full shutdown mode until the power managements bits in the Control Register, PM1 and PM0, are changed.

Rev. PrA | Page 21 of 23

Page 22

Preliminary Technical Data

SERIAL INTERFACE

Figure 16 shows the timing diagram for the serial interface of the AD7327. The serial clock applied to the SCLK pin provides the conversion clock and also controls the transfer of information to and from the AD7327 during a conversion.

The CS signal initiates the data transfer and the conversion process. The falling edge of CS puts the track-and-hold into hold mode, take the bus out of three-state and the analog input signal is sampled at this point. Once the conversion is initiated it will require 16 SCLK cycles to complete.

The track-and-hold will go back into track on the 14th SCLK rising edge. On the sixteenth SCLK falling edge, the DOUT line will return to three-state. If the rising edge of CS occurs before 16 SCLK cycles have elapsed, the conversion will be terminated, the DOUT line will return to three-state, and depending on

AD7327

where the CS signal is brought high the addressed register may or may not be updated. Data is clocked into the AD7327 on the SCLK falling edge. The three MSBs on the DIN line are decoded to select which register is being addressed. The Control Register is a twelve bit register, if the control register is addressed by the three MSB, the data on the DIN line will be loaded into the Control on the 15 or either of the Range registers is addressed the data on the DIN line will be loaded into the addressed register on the 11 falling edge.

Conversion data is clocked out of the AD7327 on each SCLK falling edge. Data on the DOUT line will consist of three channel identifier bits, a Sign bit and a 12-bit conversion result. The channel identifier bits are used to indicate which channel the conversion result corresponds to.

SCLK falling edge. If the Sequence register

SCLK

+5

SCLK

DOUT

DIN

3-STATE

3 IDENTIFICATION BITS

ADD2

WRITE

ADD1

Reg Sel1

ADD0

SIGN

MSBReg Sel2

DB11

convert

DB10

Figure 16. Serial Interface timing Diagram (Control register write)

DB2

DB1

LSB

DB0

DONTC

3-STATE

QUIET

Rev. PrA | Page 22 of 23

Page 23

Preliminary Technical Data

PR05401-0-2/05(PrA)

OUTLINE DIMENSIONS

20-Lead Thin Shrink Small Outline (TSSOP)

(RU-20)

AD7327

Ordering Guide

AD7327 Products Temperature Package Package Description Package Outline

AD7327BRUZ –40°C to +85°C TSSOP RU-20 EVAL-AD7327CB EVAL-CONTROL BRD2

NOTES 1 This can be used as a stand-alone evaluation board or in conjunction with the EVAL-CONTROL Board for evaluation/demonstration purposes. 2 This board is a complete unit allowing a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators. To order a complete

evaluation kit, the particular ADC evaluation board, e.g., EVAL-AD7327CB, the EVAL-CONTROL BRD2, and a 12V transformer must be ordered. See relevant Evaluation Board Technical note for more information.

Evaluation Board Controller Board

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Rev. PrA | Page 23 of 23

Datasheet AD7327 Datasheet (Analog Devices)

Specifications and Main Features

Frequently Asked Questions

User Manual