Datasheet AD7298 Datasheet (ANALOG DEVICES)

8-Channel, 1 MSPS, 12-Bit SAR ADC

V

V

FEATURES

12-bit SAR ADC

8 single-ended inputs
Channel sequencer functionality
Fast throughput of 1 MSPS

Analog input range: 0 V to 2.5 V
12-bit temperature-to-digital converter
Temperature sensor accuracy of ±1°C
Temperature range: −40°C to +125°C
Specified for V
Logic voltage V
Power-down current: <10 μA
Internal 2.5 V reference
Internal power-on reset
High speed serial interface SPI
20-lead LFCSP

GENERAL DESCRIPTION

The AD7298 is a 12-bit, high speed, low power, 8-channel,
successive approximation ADC with an internal temperature
sensor. The part operates from a single 3.3 V power supply and
features throughput rates up to 1 MSPS. The device contains a
low noise, wide bandwidth track-and-hold amplifier that can
handle input frequencies in excess of 30 MHz.

The AD7298 offers a programmable sequencer, which enables
the selection of a preprogrammable sequence of channels for
conversion. The device has an on-chip, 2.5 V reference that can
be disabled to allow the use of an external reference.

The AD7298 includes a high accuracy band gap temperature
sensor, which is monitored and digitized by the 12-bit ADC to
give a resolution of 0.25°C. The device offers a 4-wire serial
interface compatible with SPI and DSP interface standards.

The AD7298 uses advanced design techniques to achieve very
low power dissipation at high throughput rates. The part also
offers flexible power/throughput rate management options.
The part is offered in a 20-lead LFCSP package.

: 2.8 V to 3.6 V

DD

: 1.65 V to 3.6 V

DRIVE

with Temperature Sensor

AD7298

FUNCTIONAL BLOCK DIAGRAM

DD

REF

BUFREF

V

IN0

V

INPUT

IN7

MUX

PD/RST

T/H

AD7298

TEMP

SENSOR

APPROXIMATION

Figure 1.

SUCCESSIVE

SEQUENCER

CONTROL

PRODUCT HIGHLIGHTS

1. Ideally Suited to Monitoring System Variables in a Variety

of Systems. This includes telecommunications, and process
and industrial control.

2. High Throughput Rate of 1 MSPS with Low Power

Consumption.

3. Eight Single-Ended Inputs with a Channel Sequencer.

A consecutive sequence of channels can be selected on
which the ADC cycles and converts.

4. Integrated Temperature Sensor with 0.25°C Resolution.

12-BIT

ADC

LOGIC

T

SENSE

GND

_BUSY

SCLK
DOUT
DIN

CS

V

DRIVE

08754-001

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2010–2011 Analog Devices, Inc. All rights reserved.

AD7298

TABLE OF CONTENTS

Features.............................................................................................. 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Timing Specifications .................................................................. 5

Absolute Maximum Ratings............................................................ 6

ESD Caution.................................................................................. 6

Thermal Resistance ...................................................................... 6

Pin Configuration and Function Description .............................. 7

Typical Performance Characteristics ............................................. 9

Terminology .................................................................................... 12

Circuit Information........................................................................ 13

Converter Operation.................................................................. 13

Analog Input............................................................................... 13

Temperature Sensor Operation ................................................14

Temperature Sensor Averaging ................................................ 14

V

............................................................................................ 15

DRIVE

The Internal or External Reference.......................................... 15

Control Register.............................................................................. 16

Modes of Operation ....................................................................... 17

Traditional Multichannel Mode of Operation........................ 17

Repeat Operation ....................................................................... 18

Power-Down Modes .................................................................. 19

Powering Up the AD7298 ......................................................... 20

Reset ............................................................................................. 20

Serial Interface ................................................................................ 21

Temperature Sensor Read ......................................................... 22

Layout and Configuration............................................................. 23

Power Supply Bypassing and Grounding................................ 23

Temperature Monitoring........................................................... 23

Outline Dimensions....................................................................... 24

Ordering Guide .......................................................................... 24

REVISION HISTORY

6/11—Rev. A to Rev. B

Changes to Internal Temperature Sensor, Accuracy Parameter

in Table 1............................................................................................ 3

1/11—Rev. 0 to Rev. A

Removed Input Impedance Parameter.......................................... 3

Added Input Capacitance Parameter of 8 pF................................ 3

Changes to Figure 11...................................................................... 10

Changed C1 Value to 8 pF in Analog Input Section.................. 13

Changes to Figure 23...................................................................... 14

Changes to Ordering Guide.......................................................... 24

9/10—Revision 0: Initial Version

Rev. B | Page 2 of 24

AD7298

SPECIFICATIONS

VDD = 2.8 V to 3.6 V; V
otherwise noted.

Table 1.

Parameter Min Typ Max Unit Test Conditions/Comments

DYNAMIC PERFORMANCE fIN = 50 kHz sine wave

Signal-to-Noise Ratio (SNR)

Signal-to-Noise (and Distortion) Ratio (SINAD)1 70 71 dB

Total Harmonic Distortion (THD)

Spurious-Free Dynamic Range (SFDR)

Intermodulation Distortion (IMD)

Second-Order Terms −84 dB
Third-Order Terms −93 dB

Channel-to-Channel Isolation −100 dB fIN = 50 kHz, f

SAMPLE AND HOLD

Aperture Delay3 12 ns

Aperture Jitter3 40 ps

Full Power Bandwidth 30 MHz @ 3 dB

10 MHz @ 0.1 dB
DC ACCURACY

Resolution 12 Bits

Integral Nonlinearity (INL)1 ±0.5 ±1 LSB

Differential Nonlinearity (DNL)1 ±0.5 ±0.99 LSB Guaranteed no missed codes to 12 bits

Offset Error1 ±2 ±4.5 LSB

Offset Error Matching1 ±2.5 ±4.5 LSB

Offset Temperature Drift 4 ppm/°C

Gain Error1 ±1 ±4 LSB

Gain Error Matching1 ±1 ±2.5 LSB

Gain Temperature Drift 0.5 ppm/°C

ANALOG INPUT

Input Voltage Ranges 0 V

DC Leakage Current ±0.01 ±1 µA

Input Capacitance 32 pF When in track

8 pF When in hold mode

REFERENCE INPUT/OUTPUT

Reference Output Voltage4 2.4925 2.5 2.5075 V ±0.3% maximum @ 25°C

Long-Term Stability 150 ppm For 1000 hours

Output Voltage Hysteresis 50 ppm

Reference Input Voltage Range5 1 2.5 V

DC Leakage Current ±0.01 ±1 µA External reference applied to Pin V

V

Output Impedance 1 Ω

REF

V

Temperature Coefficient 12 35 ppm/°C

REF

V

Noise 60 µV rms Bandwidth = 10 MHz

REF

= 1.65 V to 3.6 V; f

DRIVE

1, 2

70 72 dB

1

SAMPLE

= 1 MSPS, f

= 20 MHz, V

SCLK

= 2.5 V internal; TA = −40°C to +125°C, unless

REF

−82 −77 dB

−84 −77.5 dB
f

REF

V

= 40.1 kHz, fB = 41.5 kHz

A

NOISE

= 60 kHz

REF

Rev. B | Page 3 of 24

AD7298

Parameter Min Typ Max Unit Test Conditions/Comments

LOGIC INPUTS

Input High Voltage, V
Input Low Voltage, V
Input Current, I
Input Capacitance, C

INH

INL

IN

3

3 pF

IN

LOGIC OUTPUTS

Output High Voltage, V

OH

V
Output Low Voltage, V

OL

Floating State Leakage Current ±0.01 ±1 µA
Floating State Output Capacitance3 8 pF

INTERNAL TEMPERATURE SENSOR

Operating Range −40 +125
Accuracy ±1 ±2 °C TA = −40°C to +85°C
±1 ±3 °C TA = +85°C to +125°C
Resolution 0.25 °C LSB size

CONVERSION RATE

Conversion Time 1 t2 + 16 × t
100 s T
Track-and-Hold Acquisition Time3 100 ns Full-scale step input
Throughput Rate 1 MSPS

10 KSPS For the T

POWER REQUIREMENTS Digital inputs = 0 V or V

V

DD

V

DRIVE

6

I

V

TOTAL

Normal Mode (Operational) 5.8 6.3 mA
Normal Mode (Static) 4.1 4.6 mA
Partial Power-Down Mode 2.7 3.3 mA
Full Power-Down Mode 1 1.6 A TA = −40°C to +25°C
10 A TA = −40°C to +125°C

Power Dissipation

7

Normal Mode (Operational) 17.4 18.9 mW VDD = 3 V, V

22.7 mW
Normal Mode (Static) 14.8 16.6 mW
Partial Power-Down Mode 9.8 11.9 mW
Full Power-Down Mode 3.6 5.8 W TA = −40°C to +25°C
36 W TA = −40°C to +125°C

1

See the Terminology section.

2

All specifications expressed in decibels are referred to full-scale input, FSR, and tested with an input signal at 0.5 dB below full scale, unless otherwise specified.

3

Sample tested during initial release to ensure compliance.

4

Refers to Pin V

5

A correction factor may be required on the temperature sensor results when using an external V

6

I

is the total current flowing in VDD and V

TOTAL

7

Power dissipation is specified with VDD = V

specified for 25

REF

o

C.

.

DRIVE

= 3.6 V, unless otherwise noted.

DRIVE

0.7 × V
+0.3 × V

V

DRIVE

V

DRIVE

±0.01 ±1 µA VIN = 0 V or V

V

− 0.3 V V

DRIVE

− 0.2 V V

DRIVE

DRIVE

DRIVE

< 1.8
≥ 1.8

0.4 V

s For V

SCLK

to V

IN0

temperature sensor channel

SENSE

= 20 MHz, for analog voltage

f

SCLK

conversions, one cycle latency

SENSE

2.8 3 3.6 V

1.65 3 3.6 V
= 3.6 V, V

DD

DRIVE

(see the Temperature Sensor Averaging section).

REF

DRIVE

, with one cycle latency

IN7

channel, one cycle latency

DRIVE

= 3.6 V

DRIVE

= 3 V

Rev. B | Page 4 of 24

AD7298

TIMING SPECIFICATIONS

VDD = 2.8 V to 3.6 V; V
initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
of 1.6 V.

Table 2.

Parameter Limit at T

t

CONVER T

820 ns typ Each ADC channel V
100 µs max Temperature sensor channel

1

f

SCLK

20 MHz max Frequency of external serial clock
t

QUIET

t2 10 ns min

1

t

3

1

t

4

35 ns max V
28 ns max V
t5 0.4 × t
t6 0.4 × t

1

t

14 ns min SCLK to DOUT valid hold time

7

1

t

8

t9 5 ns min DIN setup time prior to SCLK falling edge
t10 4 ns min DIN hold time after SCLK falling edge
t11 100 ns min

1

t

12

t

POWER-UP_PARTIAL

t

POWER-UP

1

Measured with a load capacitance on DOUT of 15 pF.

DRIVE

t2 + (16 × t

50 kHz min Frequency of external serial clock

6 ns min

15 ns max Delay from CS (falling edge) until DOUT three-state disabled
Data access time after SCLK falling edge

SCLK

SCLK

16/34 ns min/max SCLK falling edge to DOUT high impedance

30 ns max
1 s max Power-up time from partial power-down
6 ms max Internal reference power-up time from full power-down

= 1.65 V to 3.6 V; V

, T

MIN

MAX

) µs max Conversion time

SCLK

Unit Test Conditions/Comments

= 2.5 V internal; TA = −40°C to + 125°C, unless otherwise noted. Sample tested during

REF

IN0

Minimum quiet time required between the end of serial read and the start
of the next voltage conversion in repeat and nonrepeat mode.

to SCLK setup time

CS

= 1.65 V to 3 V

DRIVE

= 3 V to 3.6 V

DRIVE

ns min SCLK low pulse width
ns min SCLK high pulse width

BUSY falling edge to CS falling edge

T

SENSE_

Delay from CS

rising edge to DOUT high impedance

to V

IN7

, f

SCLK

= 20 MHz

) and timed from a voltage level

DRIVE

Rev. B | Page 5 of 24

AD7298

ABSOLUTE MAXIMUM RATINGS

Table 3.

Parameter Rating

VDD to GND, GND1
V

to GND, GND1

DRIVE

Analog Input Voltage to GND1
Digital Input Voltage to GND
Digital Output Voltage to GND
V

to GND1 −0.3 V to +3 V

REF

−0.3 V to +5 V

−0.3 V to + 5 V

−0.3 V to 3 V

−0.3 V to V

−0.3 V to V

DRIVE

DRIVE

+ 0.3 V

+ 0.3 V

GND1 to GND −0.3 V to +0.3 V
Input Current to Any Pin Except Supplies ±10 mA
Operating Temperature Range −40°C to +125°C
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
Pb-Free Temperature, Soldering

Reflow 260(+0)°C

ESD 3.5 kV

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

THERMAL RESISTANCE

Table 4. Thermal Resistance

Package Type θJA θ

20-Lead LFCSP 52 6.5 °C/W

Unit

JC

Rev. B | Page 6 of 24

AD7298

T

PIN CONFIGURATION AND FUNCTION DESCRIPTION

IN1

IN2

IN0

V

V

19

20

1

V

IN3

2

V

IN4

3

V

IN5

4

V

IN6

5

V

IN7

NOTES

1. THE EXPOSED METAL PADDLE ON THE BOTTOM
OF THE LFCSP PACKAGE SHOULD BE SOLDERED
TO PCB GRO UND FOR PROPER F UNCTIONALI TY
AND HEAT DISSIP ATION.

AD7298

TOP VIEW

(Not to Scale)

6

7

REF

V

GND1

Figure 2. Pin Configuration

Table 5. Pin Function Descriptions

Pin No. Mnemonic Description

1 to 5,
18 to 20

6 GND1

V

, V

,

IN3

IN4

V

, V

IN5

IN6

, V

V

IN7

IN0

V

, V

IN1

IN2

Analog Inputs. The AD7298 has eight single-ended analog inputs that are multiplexed into the on-chip track­and-hold. Each input channel can accept analog inputs from 0 V to 2.5 V. Any unused input channels should be

,
,

connected to GND1 to avoid noise pickup.

Ground. Ground reference point for the internal reference circuitry on the AD7298. The external reference signals
and all analog input signals should be referred to this GND1 voltage. The GND1 pin should be connected to the
GND plane of a system. All ground pins should ideally be at the same potential and must not be more than 0.3 V
apart, even on a transient basis. The V
capacitor.

7 V

REF

Internal Reference/External Reference Supply. The nominal internal reference voltage of 2.5 V appears at this pin.
Provided the output is buffered, the on-chip reference can be taken from this pin and applied externally to the
rest of a system. Decoupling capacitors should be connected to this pin to decouple the reference buffer. For
best performance, it is recommended to use a 10 F decoupling capacitor on this pin to GND1. The internal
reference can be disabled and an external reference supplied to this pin, if required. The input voltage range for
the external reference is 2.0 V to 2.5 V.

8 D

CAP

Decoupling Capacitor Pin. Decoupling capacitors (1 F recommended) are connected to this pin to decouple the
internal LDO.

9 GND

Ground. Ground reference point for all analog and digital circuitry on the AD7298. The GND pin should be
connected to the ground plane of the system. All ground pins should ideally be at the same potential and must
not be more than 0.3 V apart, even on a transient basis. Both D
GND pin.

10 V

DD

Supply Voltage, 2.8 V to 3.6 V. This supply should be decoupled to GND with 10 µF and 100 nF decoupling
capacitors.

11

Chip Select, Active Low Logic Input. This pin is edge triggered on the falling edge of this input, the track-and-

CS

hold goes into hold mode, and a conversion is initiated. This input also frames the serial data transfer. When CS
low, the output bus is enabled, and the conversion result becomes available on the DOUT output.

12 T

SENSE

_BUSY

Busy Output. This pin transitions high when a temperature sensor conversion starts and remains high until the
conversion completes.

13 DIN

Data In, Logic input. Data to be written to the AD7298 control register is provided on this input and is clocked
into the register on the falling edge of SCLK.

14 DOUT

Serial Data Output. The conversion result from the AD7298 is provided on this output as a serial data stream. The
bits are clocked out on the falling edge of the SCLK input. The data stream from the AD7298 consists of four
address bits indicating which channel the conversion result corresponds to, followed by the 12 bits of conversion
data (MSB first). The output coding is straight binary for the voltage channels and twos complement for the
temperature sensor result.

15 SCLK Serial Clock, Logic Input. A serial clock input provides the SCLK for accessing the data from the AD7298.

DRIVE

V

PD/RS

V

16

18

17

15

SCLK

14

DOUT

13

DIN

T

_BUSY

12

SENSE

11

CS

9

8

10

DD

CAP

V

GND

D

08754-003

pin should be decoupled to this ground pin via a 10 F decoupling

REF

and VDD pins should be decoupled to this

CAP

is

Rev. B | Page 7 of 24

AD7298

Pin No. Mnemonic Description

16 V

17

DRIVE

/RST Power-Down Pin. This pin places the part into full power-down mode and enables power conservation when operation

PD

EPAD EPAD

Logic Power Supply Input. The voltage supplied at this pin determines at the voltage at which the interface
operates. This pin should be decoupled to GND. The voltage range on this pin is 1.65 V to 3.6 V and may be less
than the voltage at V

is not required. This pin can be used to reset the device by toggling the pin low for a minimum of 1 ns and a maximum
of 100 ns. If the maximum time is exceeded, the part enters power-down mode. When placing the AD7298 in full
power-down mode, the analog inputs must return to 0 V.

The exposed metal paddle on the bottom of the LFCSP package should be soldered to PCB ground for proper
functionality and heat dissipation.

, but should never exceed it by more than 0.3 V.

DD

Rev. B | Page 8 of 24

AD7298

TYPICAL PERFORMANCE CHARACTERISTICS

AMPLITUDE (dB)

–100

–20

–40

–60

–80

0

VDD = V

DRIVE

f

= 1.17647MHz

SAMPLE

f

= 50kHz

IN

f

= 20MHz

SCLK

SNR = 72.621
THD = –82.562

= 3V

0.6

0.4

0.2

TA = 25°C
V

= 3V

DRIVE

V

= 3V

0

DD

INL (LSB)

0.2

0.4

INL MAX

INL MIN

–120

0 50 100 150 200 250 300

FREQUENCY (kHz)

Figure 3.Typical FFT

1.0

TA = 25°C
V

= 3V

DRIVE

0.8

V

= 2.5V

REF

V

= 3 V

DD

0.6

0.4

0.2

0

INL (LSB)

–0.2

–0.4

–0.6

–0.8

–1.0

0

512

1024

256

768

1280

1536

Figure 4.Typical ADC INL

1.0
TA = 25°C
V

= 3V

DRIVE

0.8
V

= 2.5V

REF

V

= 3 V

DD

0.6

0.4

0.2

0

DNL (LSB)

–0.2

–0.4

–0.6

–0.8

–1.0

0

512

1024

256

768

1280

1536

1792

1792

2048

CODE

2048

CODE

350 400 450 500

2560

2304

2816

2560

2304

2816

3072

3072

3328

3328

3584

3584

3840

3840

4096

4096

0.6

1.00 1.25 1.50 1.75 2. 00 2.25 2.50 2.75

08754-035

0.6

0.4

0.2

T

= 25°C

A

V

DRIVE

0

V

INL (LSB)

08754-017

EFFECTI VE NUMBER OF BI TS

08754-016

DD

–0.2

–0.4

–0.6

1.00 1.25 1.50 1.75 2. 00 2.25 2.50 2.75

12

11

10

9

8

7

6

5

4

3

2

00.51.01.52.02.5

REFERENCE VO LTAGE (V)

Figure 6. INL vs. V

= 3V

= 3V

REFERENCE VOLTAGE (V)

Figure 7. DNL vs. V

V

REF

DNL MAX

DNL MIN

(V)

08754-018

REF

REF

VDD = 3V
V

= 3V

DRIVE

08754-020

Figure 5. Typical ADC DNL

Rev. B | Page 9 of 24

Figure 8. Effective Number of Bits vs. V

REF

AD7298

R

A

–

A

3.0
VDD = V

2.5

2.0

(V)

1.5

REF

V

1.0

0.5

DRIVE

= 3V

TION (dB)

ISOL

110

105

100

95

90

85

80

75

0

0 0. 5 1.0 1.5 2.0 2.5 3.0 3. 5 4. 0 4. 5

CURRENT LOAD (mA)

Figure 9. V

55

50

45

40

35

TURE READING (° C)

30

TEMPE

25

20

0 20406080100

vs. Reference Output Current Drive

REF

TIME (Seconds)

08754-021

Figure 10. Response to Thermal Shock from Room Temperature

into 50°C Stirred Oil

90

VDD=3V
V

=3V

DRIVE

–92

–94

–96

–98

–100

PSRR (dB)

–102

–104

–106

–108

–110

1k 10k 100k 1M 10M 100M

RIPPLE FREQUENCY (Hz)

Figure 11. PSRR vs. Supply Ripple Frequency Without Supply Decoupling

70

0 50 100 150 200 250 300 350 400 450 500 550

f

(kHz)

Figure 12. Channel-to-Channel Isolation, f

76

74

RIN=47Ω

72

70

68

SINAD (dB)

66

64

62

60

08754-028

RIN=0Ω

10 100 500

NOISE

R

=47Ω

IN

RIN= 100Ω

INPUT FREQUENCY (kHz)

= 50 kHz

IN

R

=33Ω

IN

RIN= 200Ω

08754-029

08754-024

Figure 13. SINAD vs. Analog Input Frequency for Various Source Impedances

75

70

65

60

55

50

45

40

SINAD (dB)

35

30

25

20

15

0 0.5 1.0 1.5 2.0 2.5

V

(V)

08754-027

REF

VDD = 3V
V

DRIVE

= 3V

8754-022

Figure 14. SINAD vs. Reference Voltage

Rev. B | Page 10 of 24

AD7298

A

–

(

2.0

1.5

1.0

0.5

0

TURE ERROR (°C)

–0.5

TEMPER

–1.0

–1.5

–40 –25 –10 0 10 20 25 30 35 45 60 85 105 125

TEMPERATURE (°C)

Figure 15. Temperature Accuracy at 3 V

08754-034

19

VDD = V

18

17

16

15

14

POWER (mW)

13

12

11

10

0 100 200 300 400 500 600 700 800 900 1000

DRIVE

= 3V

THROUGHPUT ( kSPS)

Figure 18. Power vs. Throughput in Normal Mode with V

DD

= 3 V

08754-025

60

–65

–70

–75

THD (dB)

R

= 43Ω

–80

–85

–90

SOURCE

10 100 500

SIGNAL FREQ UENCY (kHz)

R

SOURCE

R

= 100Ω

R

SOURCE

SOURCE

R

= 200Ω

= 0Ω

SOURCE

R

= 47Ω

SOURCE

= 33Ω

08754-036

Figure 16. THD vs. Analog Input Frequency for Various Source Impedances

6

VDD = V

5

4

3

= 3V

DRIVE

VDD CURRENT

4.0

–40°C
0°C

3.5

+25°C

3.0

µA)

2.5

2.0

1.5

TOTAL CURRENT

1.0

0.5

0

2.8 2.9 3. 0 3.1 3.2 3.3 3.4 3.5 3. 6

+85°C
+105°C
+125°C

VDD (V)

Figure 19. Full Shutdown Current vs. Supply Voltage for Various

Temperatures

V

DRIVE

= 3V

8754-031

CURRENT (mA)

2

1

0

0 200 400 600 800 1000 1200

V

CURRENT

DRIVE

THROUGHPUT (kSPS)

08754-026

Figure 17. Average Supply Current vs. Throughput Rate

Rev. B | Page 11 of 24

AD7298

TERMINOLOGY

Signal-to-Noise and Distortion Ratio (SINAD)

The measured ratio of signal-to-noise and distortion at the
output of the ADC. The signal is the rms amplitude of the
fundamental. Noise is the sum of all nonfundamental signals
up to half the sampling frequency (f
ratio is dependent on the number of quantization levels in the
digitization process; the more levels, the smaller the quantization
noise. The theoretical signal-to-noise and distortion ratio for
an ideal N-bit converter with a sine wave input is given by

Signal-to-(Noise + Distortion) = (6.02 N + 1.76) dB

Thus, the SINAD is 74 dB for an ideal 12-bit converter.

Total Harmonic Distortion (THD)

The ratio of the rms sum of harmonics to the fundamental. For
the AD7298, it is defined as

2

2

THD

where V
V

is the rms amplitude of the fundamental, and V2, V3,

1

, V5, and V6 are the rms amplitudes of the second through

4

log20)dB(

=

sixth harmonics.

Peak Harmonic or Spurious Noise

The ratio of the rms value of the next largest component in the
ADC output spectrum (up to f
value of the fundamental. Typically, the value of this specification
is determined by the largest harmonic in the spectrum, but for
ADCs where the harmonics are buried in the noise floor, it is a
noise peak.

Integral Nonlinearity

The maximum deviation from a straight line passing through
the endpoints of the ADC transfer function. The endpoints are
zero scale, a point 1 LSB below the first code transition, and full
scale, a point 1 LSB above the last code transition.

/2), excluding dc. The

S

2

2

2

2

4

3

V

1

/2 and excluding dc) to the rms

S

VVVVV

++++

6

5

Differential Nonlinearity

The difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.

Offset Error

The deviation of the first code transition (00…000) to
(00…001) from the ideal—that is, GND1 + 1 LSB.

Offset Error Match

The difference in offset error between any two channels.

Gain Error

The deviation of the last code transition (111…110) to
(111…111) from the ideal (that is, REF

− 1 LSB) after the

IN

offset error has been adjusted out.

Gain Error Matching

The difference in gain error between any two channels.

Track-and-Hold Acquisition Time

The track-and-hold amplifier returns to track mode at the end
of conversion. Track-and-hold acquisition time is the time
required for the output of the track-and-hold amplifier to reach
its final value, within ±1 LSB, after the end of conversion.

Power Supply Rejection Ratio (PSRR)

PSRR is defined as the ratio of the power in the ADC output at
full-scale frequency, f, to the power of a 100 mV p-p sine wave
applied to the ADC V

supply of frequency, fS. The frequency

DD

of the input varies from 5 kHz to 25 MHz.

PSRR (dB) = 10 log(Pf/Pf

)

S

where:

Pf is the power at frequency, f, in the ADC output.
Pf

is the power at frequency, fS, in the ADC output.

S

Rev. B | Page 12 of 24

AD7298

CIRCUIT INFORMATION

The AD7298 is a high speed, 8-channel, 12-bit ADC with an
internal temperature sensor. The part can be operated from
a 2.8 V to 3.6 V supply and is capable of throughput rates of
1 MSPS per analog input channel.

The AD7298 provides the user with an on-chip, track-and-hold
ADC and a serial interface housed in a 20-lead LFCSP. The
AD7298 has eight single-ended input channels with channel
repeat functionality, which allows the user to select a channel
sequence through which the ADC can cycle with each conse­cutive

falling edge. The serial clock input accesses data from

CS

the part, controls the transfer of data written to the ADC, and
provides the clock source for the successive approximation
ADC. The analog input range for the AD7928 is 0 V to V

REF

.
The AD7298 operates with one cycle latency, which means that
the conversion result is available in the serial transfer following
the cycle in which the conversion is performed.

The AD7298 includes a high accuracy band gap temperature
sensor, which is monitored and digitized by the 12-bit ADC
to give a resolution of 0.25°C. The AD7298 provides flexible
power management options to allow the user to achieve the best
power performance for a given throughput rate. These options
are selected by programming the partial power-down bit, PPD,
in the control register and using the

PD

/

RST

pin.

CONVERTER OPERATION

The AD7298 is a 12-bit successive approximation ADC based
around a capacitive DAC. Figure 20 and Figure 21 show simplified
schematics of the ADC. The ADC is comprised of control logic,
SAR, and a capacitive DAC that are used to add and subtract
fixed amounts of charge from the sampling capacitor to bring
the comparator back into a balanced condition. Figure 20 shows
the ADC during its acquisition phase. SW2 is closed and SW1 is
in Position A. The comparator is held in a balanced condition
and the sampling capacitor acquires the signal on the selected
V

channel.

IN

CAPACITIVE

DAC

A

V

IN

SW1

B

SW2

GND1

Figure 20. ADC Acquisition Phase

COMPARATOR

When the ADC starts a conversion (see Figure 21), SW2
opens and SW1 moves to Position B, causing the comparator
to become unbalanced. The control logic and the capacitive
DAC are used to add and subtract fixed amounts of charge to
bring the comparator back into a balanced condition. When the
comparator is rebalanced, the conversion is complete. The
control logic generates the ADC output code. Figure 23 shows
the ADC’s transfer functions.

CONTROL

LOGIC

08754-004

A

V

IN

SW1

B

SW2

GND1

Figure 21. ADC Conversion Phase

COMPARATOR

ANALOG INPUT

Figure 22 shows an equivalent circuit of the analog input struc­ture of the AD7298. The two diodes, D1 and D2, provide ESD
protection for the analog inputs. Care must be taken to ensure
that the analog input signal never exceeds the internally
generated LDO voltage of 2.5 V (D
This causes the diodes to become forward-biased and start
conducting current into the substrate. The maximum current
these diodes can conduct without causing irreversible damage
to the part is 10 mA. Capacitor C1, in Figure 22, is typically
about 8 pF and can primarily be attributed to pin capacitance.
The Resistor R1 is a lumped component made up of the on
resistance of a switch (track-and-hold switch) and also includes
the on resistance of the input multiplexer. The total resistance is
typically about 155 . The capacitor, C2, is the ADC sampling
capacitor and has a capacitance of 34 pF typically.

D

(2.5V)

CAP

D1

V

IN

D2

C1
pF

Figure 22. Equivalent Analog Input Circuit

CONVERSION PHASE: SWITCH OPEN
TRACK PHASE: SW ITCH CLOS ED

For ac applications, removing high frequency components from
the analog input signal is recommended by using an RC low­pass filter on the relevant analog input pin. In applications
where harmonic distortion and signal-to-noise ratios are
critical, the analog input should be driven from a low impedance
source. Large source impedances significantly affect the ac
performance of the ADC. This may necessitate the use of an
input buffer amplifier. The choice of the op amp is a function
of the particular application performance criteria.

ADC Transfer Function

The output coding of the AD7298 is straight binary for the
analog input channel conversion results and twos complement,
for the temperature conversion result. The designed code
transitions occur at successive LSB values (that is, 1 LSB, 2 LSBs,
and so forth). The LSB size is V
ideal transfer characteristic for the AD7298 for straight binary
coding is shown in Figure 23.

CAP

R1

/4096 for the AD7298. The

REF

CAPACITIVE

DAC

CONTROL

LOGIC

08754-005

) by more than 300 mV.

C2
pF

08754-006

Rev. B | Page 13 of 24

AD7298

V

111...111

111...110

111...000

011...111

ADC CODE

000...010

000...001

000...000
0V

NOTES

IS 2.5V.

1. V

REF

Figure 23. Straight Binary Transfer Characteristic

TEMPERATURE SENSOR OPERATION

The AD7298 contains one local temperature sensor. The
on-chip, band gap temperature sensor measures the temp­erature of the AD7298 die.

The temperature sensor module on the AD7298 is based on
the three-current principle (see Figure 24), where three currents
are passed through a diode and the forward voltage drop is
measured, allowing the temperature to be calculated free of
errors caused by series resistance.

I4 × I

INTERNAL

SENSE

TRANSISTO R

Figure 24. Top-Level Structure of Internal Temperature Sensor

8 × I I

1LSB = V

ANALOG INP UT

DD

BIAS

BIAS
DIODE

+V

REF

REF

/4096

–1LSB1LSB

08754-007

V

OUT+

TO ADC

V

OUT–

The temperature conversion consists of two phases, the integra­tion followed by the conversion. The integration is initiated on
the

falling edge. It takes a period of approximately 100 s to

CS

complete the integration and conversion of the temperature
result. When the integration is completed, the conversion is
initiated automatically. Once the temperature integration is
initiated, the T

BUSY signal goes high to indicate that a

SENSE_

temperature conversion is in progress and remains high until
the conversion is completed.

Theoretically, the temperature measuring circuit can measure
temperatures from –512°C to +511°C with a resolution of

0.25°C. However, temperatures outside T

(the specified

A

temperature range for the AD7298) are outside the guaranteed
operating temperature range of the device. The temperature
sensor is selected by setting the T

bit in the control register.

SENSE

TEMPERATURE SENSOR AVERAGING

The AD7298 incorporates a temperature sensor averaging
feature to enhance the accuracy of the temperature measure­ments. To enable the temperature sensor averaging feature, both
the T
control register. In this mode the temperature is internally
averaged to reduce the effect of noise on the temperature result.
The temperature is measured each time a T
performed and a moving average method is used to determine
the result in the T
given by the following equation:

SENSE

The T
T

SENSE

The first T
temperature sensor and averaging mode has been selected in
the control register (Bit D1 and Bit D5) is the actual first T
conversion result. If the control register is written to and the
content of the T
reset and the next T

08754-008

temperature conversion result. If the status of the T
is not changed on successive writes to the control register, the
averaging function is reinitialized and continues calculating the
cumulative average.

The user has the option of disabling the averaging by setting
Bit T
on power-up with the averaging function disabled. The total
time to measure a temperature channel is typically 100 s.

AVG bit a nd t he T

SENSE

Result Register. The average result is

SENSE

7

()()

8

result read when averaging is enabled is the

SENSE

bit must be enabled in the

SENSE

conversion is

SENSE

__

1

+=

8

ResultCurrentResultAveragePreviousAVGT

_

AVG result, a moving average temperature measurement.

conversion result given by the AD7298 after the

SENSE

SENSE

AVG bit changed, the averaging function is

SENSE

average conversion result is the current

SENSE

AVG bit

SENSE

AVG to 0 in the control register. The AD7298 defaults

SENSE

Rev. B | Page 14 of 24

AD7298

Temperature Value Format

One LSB of the ADC corresponds to 0.25°C. The temperature
reading from the ADC is stored in a 12-bit twos complement
format to accommodate both positive and negative temperature
measurements. The temperature data format is provided in
Tabl e 6 .

Table 6. Temperature Data Format

Temperature (°C) Digital Output

−40 1111 0110 0000

−25 1111 1001 1100

−10 1111 1101 1000

−0.25 1111 1111 1111
0 0000 0000 0000
+0.25 0000 0000 0001
[phone]
[phone]
[phone]
[phone]
[phone]
[phone]
[phone]

The temperature conversion formulas are as follows:

Positive Temperature = ADC Code/4

Negative Temperature = (4096 − ADC Code)/4

The previous formulas are for a V

of 2.5 V only.

REF

If an external reference is used, the temperature sensor requires
an external reference of between 2 V and 2.5 V for correct
operation. When an external reference of less than 2.5 V is
applied, the temperature results are calculated using the
following formula, where V

is the value of the external

EXT_REF

reference voltage.

ADCCode

VeTemperatur

⎛
⎜

_

REFEXT

10

⎝

⎞

+=

−

⎟
⎠

15.2733.109

V

DRIVE

The AD7298 also provides the V
voltage at which the serial interface operates. V

DRIVE

feature. V

controls the

DRIVE

allows the

DRIVE

ADC to easily interface to both 1.8 V and 3 V processors. For
example, if the AD7298 is operated with a V
V

pin can be powered from a 1.8 V supply.

DRIVE

of 3.3 V, the

DD

This enables the AD7298 to operate with a larger dynamic
range with a V

1.8 V processors. Take care to ensure V
V

by more than 0.3 V (see the Absolute Maximum Ratings

DD

of 3.3 V while still being able to interface to

DD

does not exceed

DRIVE

section).

THE INTERNAL OR EXTERNAL REFERENCE

The AD7298 can operate with either the internal 2.5 V on-chip
reference or an externally applied reference. The EXT_REF bit
in the control register is used to determine whether the internal
reference is used. If the EXT_REF bit is selected in the control
register, an external reference can be supplied through the
V

pin. On power-up, the internal reference is enabled.

REF

Suitable external reference sources for the AD7298 include

AD780, AD1582, ADR431, REF193, and ADR391.

The internal reference circuitry consists of a 2.5 V band gap
reference and a reference buffer. When the AD7298 operates in
internal reference mode, the 2.5 V internal reference is available
at the V
capacitor. It is recommended that the internal reference be buffered
before applying it elsewhere in the system.

The internal reference is capable of sourcing up to 2 mA of
current when the converter is static. The reference buffer
requires 5.5 ms to power up and charge the 10 F decoupling
capacitor during the power-up time.

pin, which should be decoupled to GND1 using a 10 F

REF

Rev. B | Page 15 of 24

AD7298

CONTROL REGISTER

The control register of the AD7298 is a 16-bit, write-only register. Data is loaded from the DIN pin of the AD7298 on the falling edge of
SCLK. The data is transferred on the DIN line at the same time that the conversion result is read from the part. The data transferred on
the DIN line corresponds to the AD7298 configuration for the next conversion. This requires 16 serial clocks for every data transfer. Only
the information provided on the first 16 falling clock edges (after the falling edge of

first bit in the data stream. The bit functions are outlined in and . On power-up, the default content of the control register

Tabl e 7 Ta b le 8

is all zeros.

Table 7. Control Register Bit Functions

MSB LSB

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

WRITE REPEAT CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 T

Table 8. Control Register Bit Function Description

Bit Mnemonic Description

D15 WRITE

The value written to this bit determines whether the subsequent 15 bits are loaded to the control register. If this
bit is a 1, the following 15 bits are written to the control register; if it is a 0, then the remaining 15 bits are not

loaded to the control register and it remains unchanged.
D14 REPEAT This bit enables the repeated conversion of the selected sequence of channels.
D13 to

D6

CH0 to CH7

These eight channel selection bits are loaded at the end of the current conversion and select which analog input

channel is to be converted in the next serial transfer, or they may select the sequence of channels for conversion in

the subsequent serial transfers. Each CHX bit corresponds to an analog input channel. A channel or sequence of

channels is selected for conversion by writing a 1 to the appropriate CHX bit/bits. Channel address bits

D4 T

SENSE

corresponding to the conversion result are output on DOUT prior to the 12 bits of data. The next channel to be

converted is selected by the mux on the 14

Writing a 1 to this bit enables the temperature conversion. When the temperature sensor is selected for

conversion, the T

_BUSY pin goes high after the next CS falling edge to indicate that the conversion is in

SENSE

th

SCLK falling edge.

progress; the previous conversion result can be read while the temperature conversion is in progress. Once

T

_BUSY goes low, CS can be brought low 100 ns later to read the T

SENSE

4 to 3 DONTC Don’t care.
D2 EXT_REF

Writing a Logic 1 to this bit, enables the use of an external reference. The input voltage range for the external

reference is 1 V to 2.5 V. The external reference should not exceed 2.5 V or the device performance is affected.
D1 T

SENSE

AVG

Writing a 1 to this bit enables the temperature sensor averaging function. When averaging is enabled, the AD7298

internally computes a running average of the conversion results to determine the final T

Temperature Sensor Averaging section for more details). This mode reduces the influence of noise on the final

T

result. Selecting this feature does not automatically select the T

SENSE

set to start a temperature sensor conversion.
D0 PPD

This partial power-down mode is selected by writing a 1 to this bit in the control register. In this mode, some of

the internal analog circuitry is powered down. The AD7298 retains the information in the control register while in

partial power-down mode. The part remains in this mode until a 0 is written to this bit.

) is loaded to the control register. MSB denotes the

CS

DONTC DONTC EXT_REF T

SENSE

conversion result.

SENSE

for conversion. The T

SENSE

SENSE

SENSE

result (see the

bit must also be

SENSE

AVG PPD

Table 9. Channel Address Bits

ADD3 ADD2 ADD1 ADD0 Analog Input Channel

0 0 0 0 V
0 0 0 1 V
0 0 1 0 V
0 0 1 1 V
0 1 0 0 V
0 1 0 1 V
0 1 1 0 V
0 1 1 1 V
1 0 0 0 T
1 0 0 1 T

IN0

IN1

IN2

IN3

IN4

IN5

IN6

IN7

SENSE

with averaging enabled

SENSE

Rev. B | Page 16 of 24

AD7298

MODES OF OPERATION

The AD7298 offers different modes of operation that are
designed to provide additional flexibility for the user. These
options can be chosen by programming the content of the
control register to select the desired mode.

TRADITIONAL MULTICHANNEL MODE OF OPERATION

The AD7298 can operate as a traditional multichannel
ADC, where each serial transfer selects the next channel for
conversion. One must write to the control register to configure
and select the desired input channel prior to initiating any
conversions. In the traditional mode of operation, the

is used to frame the first write to the converter on the DIN
In this mode of operation, the REPEAT bit in the control
register is set to a low logic level, 0, thus the REPEAT function
is not in use. The data, which appears on the DOUT pin during
the initial write to the control register, is invalid. The first

falling edge initiates a write to the control register to configure
the device; a conversion is then initiated for the selected analog
input channel (V

) on the subsequent (2nd) CS falling edge; the

IN0

CS

SCLK

DOUT

1 12 16 1 16 1 16 1 16

INVALID DAT AINVALID DATA

DIN

DATA WRITTEN TO CONTROL

REGISTER CHANNEL 1 SELECTED

DATA WRITT EN TO CO NTROL

REGISTE R CHANNEL 4 SELECTE D

Figure 25. Configuring a Conversion and Read with the AD7298. One channel selected for conversion.

CS

112161 161 16

SCLK

DOUT

DIN

DATA WRITTEN TO CONTROL

REGISTER CH 1 AND 2 SELECTED

CS

signal

pin.

CS

NO WRITE TO THE

CONTROL REGISTER

third

reading. The AD7298 operates with one cycle latency, thus the
conversion result corresponding to each conversion is available
one serial read cycle after the cycle in which the conversion was
initiated.

As the device operates with one cycle latency, the control
register configuration sets up the configuration for the next
conversion, which is initiated on the next

the first bit of the corresponding result is not clocked out until
the subsequent falling

If more than one channel is selected in the control register, the
AD7298 converts all selected channels sequentially in ascending
order on successive

channels in the control register are converted, the AD7298
ceases converting until the user rewrites to the control register
to select the next channel for conversion. This operation is
shown in . DOUT returns all 1s if the sequence of
conversions is completed or if no channel is selected.

INVALID DA TAINVALID DAT A

falling edge will have the result (V

CS

edge, as shown in . Figure 25

CS

falling edges. Once all the selected

CS

Figure 26

CONVERSION RESULT

FOR CHANNEL 1

NO WRITE TO THE

CONTROL REGISTER

CONVERSION RESULT

FOR CHANNEL 1

DATA WRITT EN TO CO NTROL

REGISTE R CHANNEL 5 SELECTE D

) available for

IN2

falling edge, but

CS

CONVERSION RESULT

FOR CHANNEL 4

NO WRITE TO THE

CONTROL REGISTER

08754-009

CS

116116

SCLK

DOUT

DIN

CONVERSION RESULT

FOR CHANNEL 2

NO WRITE TO THE

CONTROL REGISTE R

CONVERSION RESULT

FOR CHANNEL 5

NO WRITE TO THE

CONTROL REGISTER

08754-010

Figure 26. Configuring a Conversion and Read with the AD7298. Numerous channels selected for conversion.

Rev. B | Page 17 of 24

AD7298

CS

112161 161 16

SCLK

DOUT

DIN

DATA WRITTEN TO CONTROL

REGISTE R CH 0, CH 1, AND CH 2

SELECTED: REPEAT = 1

CS

116116116

SCLK

DOUT

DIN

CONVERSION RESULT

FOR CHANNEL 1

NO WRITE TO THE

CONTROL REGISTE R

Figure 27. Configuring a Conversion and Read in Repeat Mode

REPEAT OPERATION

The REPEAT bit in the control register allows the user to select
a sequence of channels on which the AD7298 continuously
converts. When the REPEAT bit is set in the control register,
the AD7298 continuously cycles through the selected channels
in ascending order, beginning with the lowest channel and
converting all channels selected in the control register. On
completion of the sequence, the AD7298 returns to the first
selected channel in the control register and recommences the
sequence.

The conversion sequence of the selected channels in the repeat
mode of operation continues until such time as the control
register of the AD7298 is reprogrammed. If the T
selected in the control register, then the temperature conversion
will be available for conversion after the last analog input
channel in the sequence has been converted. It is not necessary
to write to the control register once a repeat operation is
initiated unless a change in the AD7298 configuration is
required. The WRITE bit must be set to zero or the DIN line
tied low to ensure that the control register is not accidentally
overwritten, or the automatic conversion sequence interrupted.

A write to the control register during the repeat mode of
operation resets the cycle even if the selected channels are
unchanged. Thus, the next conversion by the AD7298 after
a write operation will be the first selected channel in the
sequence.

SENSE

bit is

NO WRITE TO THE

CONTROL REGISTER

CONVERSION RESULT

FOR CHANNEL 2

NO WRITE TO THE

CONTROL REGISTER

INVALID DA TAINVAL ID DATA

CONVERSIO N RESULT

FOR CHANNEL 0

NO WRITE TO THE

CONTROL REGISTE R

CONVERSIO N RESULT

FOR CHANNEL 0

NO WRITE TO THE

CONTROL REGISTE R

08754-011

To select a sequence of channels, the associated channel bit
must be set to a logic high state (1) for each analog input whose
conversion is required. For example, if the REPEAT bit = 1,
then CH0, CH1, and CH2 = 1. The V
converted on the first

the control register, the V
subsequent

falling edge, and the V

CS

available for reading. The third

falling edge following the write to

CS

channel is converted on the

IN1

CS

write operation initiates a conversion on V

analog input is

IN0

conversion result is

IN0

falling edge following the

and has the V

IN2

IN1

result available for reading. The AD7298 operates with one
cycle latency, thus the conversion result corresponding to each
conversion is available one serial read cycle after the cycle in
which the conversion is initiated.

This mode of operation simplifies the operation of the device by
allowing consecutive channels to be converted without having
to reprogram the control register or write to the part on each
serial transfer. Figure 27 illustrates how to set up the AD7298
to continuously convert on a particular sequence of channels.
To exit the repeat mode of operation and revert back to the
traditional mode of operation of a multichannel ADC, ensure
that the REPEAT bit = 0 on the next serial write.

Rev. B | Page 18 of 24

AD7298

t

QUIET

CS

SCLK

DOUT

DIN

11

4 CHANNEL ADDRESS BITS

+ CONVERSIO N RESULT

DATA WRITTEN T O CONTRO L

REGISTER IF REQUIRED

Figure 28. Normal Mode Operation

pin if CS is toggled low. If the averaging

has elapsed, a full 16-SCLK write

QUIET

6

08754-012

CS

POWER-DOWN MODES

The AD7298 has a number of power conservation modes
of operation that are designed to provide flexible power
management options. These options can be chosen to optimize
the power dissipation/throughput rate ratio for different
application requirements. The power-down modes of operation
of the AD7298 are controlled by the power-down (PPD)

PD

bit in the control register and the
When power supplies are first applied to the AD7298, care
should be taken to ensure that the part is placed in the required
mode of operation

Normal Mode

Normal mode is intended for the fastest throughput rate
performance because the user does not have to be concerned
about any power-up times because the AD7298 remains fully
powered on at all times. Figure 28 shows the general diagram
of operation of the AD7298 in this mode. The conversion is
initiated on the falling edge of

hold mode. On the 14

CS

th

SCLK falling edge, the track-and-hold
returns to track mode and starts acquiring the analog input, as
described in the section. The data presented to

Serial Interface
the AD7298 on the DIN line during the first 16 clock cycles of
the data transfer are loaded into the control register (provided
the WRITE bit is 1). The part remains fully powered up in
normal mode at the end of the conversion as long as the PPD
bit is set to 0 in the write transfer during that conversion.

To ensure continued operation in normal mode, the PPD bit
should be loaded with 0 on every data write operation. Sixteen
serial clock cycles are required to complete the conversion and
access the conversion result. For specified performance, the
throughput rate should not exceed 1 MSPS. Once a conversion
is complete and the

quiet time, t

QUIET

has returned high, a minimum of the

CS

, must elapse before bringing CS low again

to initiate another conversion and access the previous conver­sion result.

PART IS IN
PARTIAL
POWER DOWN

CS

112161 161 16

SCLK

DOUT

RST

/

pin on the device.

and the track-and-hold enters

PART BEGI NS TO
POWER UP O N CS
RISING EDGE.

t

QUIET

Partial Power-Down Mode

In this mode, part of the internal circuitry on the AD7298 is
powered down. The AD7298 enters partial power-down on

rising edge once the current serial write operation

the

CS

containing 16 SCLK clock cycles is completed. To enter partial
power-down, the PPD bit in the control register should be set
to 1 on the last required read transfer from the AD7298.
Once in partial power-down mode, the AD7298 transmits
all 1s on the DOUT

feature for the temperature sensor is enabled in the control
register, the averaging is reset once the device enters partial
power-down mode.

The AD7298 remains in partial power-down until the power­down bit, PPD, in the control register is changed to a logic level
zero (0). The AD7298 begins powering up on the rising edge
of

following the write to the control register disabling the

CS

power-down bit. Once t
to the control register must be completed to update its content
with the desired channel configuration for the subsequent
conversion. A valid conversion is then initiated on the next

falling edge.

Because the AD7298 has one cycle latency, the first conversion
result after exiting partial power-down mode is available in the
fourth serial transfer, as shown in Figure 29. The first cycle
updates the PPD bit, the second cycle updates the configuration
and Channel ID bits, the third completes the conversion, and
the fourth accesses the DOUT valid result. The use of this
mode enables a reduction in the overall power consumption of
the device.

THE PART IS FULLY
POWERED UP ONCE THE
WRITE TO THE CONTROL
REGISTER IS COMPLETED.

INVALID DAT A INVALID D ATA

DIN

WRITE TO CONTROL

REGISTER, PPD = 0.

CONTROL REGISTE R CONFIG URED

TO POW ER UP DEVICE.

WRITE TO THE CONTROL

REGISTER, SELECT CH1 , PPD = 0

SELECT ANALO G INPUT C HANNELS
FOR CONVERSIO N. THE NEXT CYCLE
WILL CONVERT THE FIRST CHANNEL

PROGRAMMED IN THIS WRITE OPERATION.

Figure 29. Partial Power-Down Mode of Operation

NO WRITE TO

CONTROL REGISTE R

AD7298 CONVERTING CHANNEL 1

NEXT CYCLE HAS CHANNEL 1

RESULT AVAILA BLE FOR READI NG.

08754-013

Rev. B | Page 19 of 24

AD7298

Full Power-Down Mode

In this mode, all internal circuitry on the AD7298 is powered
down and no information is retained in the control register or any
other internal register. If the averaging feature for the tempera­ture sensor is enabled in the control register (T
averaging is reset once the device enters power-down mode.

The AD7298 is placed into full power-down mode by bringing

PD

the logic level on the

RST

/

pin low for greater than 100 ns.

When placing the AD7298 in full power-down mode, the ADC

PD

inputs must return to 0 V. The

RST

/

pin is asynchronous to
the clock, thus it can be triggered at any time. The part can be
powered up for normal operation by bringing the
logic level back to a high logic state.

The full power-down feature can be used to reduce the average
power consumed by the AD7298 when operating at lower
throughput rates. The user should ensure that t
elapsed prior to programming the control register and initiating
a valid conversion.

POWERING UP THE AD7298

The AD7298 contains a power-on reset circuit, which sets
the control register to its default setting of all zeros, thus the
internal reference is enabled and the device is configured for the
normal mode of operation. On power-up, the internal reference
is by default enabled, which takes up 6 ms (maximum) to
power-up.

AVG ), t he

SENSE

PD

POWER_UP

RST

/

pin

has

If an external reference is being used, the user does not need to
wait for the internal reference to power-up fully. The AD7298
digital interface is fully functional after 500 µs from initial
power-up. Therefore, the user can write to the control register
after 500 µs to switch to external reference mode. The AD7298
is then immediately ready to convert once the external reference
is available on the V

REF

pin.

When supplies are first applied to the AD7298, the user must
wait the specified 500 µs before programming the control
register to select the desired channels for conversion.

RESET

The AD7298 includes a reset feature that can be used to reset
the device and the contents of all internal registers, including
the control register, to their default state.

PD

PD

RST

/

RST

/

pin should be

PD

/

pin be held at a

RST

pin

To activate the reset operation, the
brought low for no longer than 100 ns. It is asynchronous with
the clock, thus it can be triggered at any time. If the
is held low for greater than 100 ns, the part enters full power­down mode. It is imperative that the
stable logic level at all times to ensure normal operation.

Rev. B | Page 20 of 24

AD7298

SERIAL INTERFACE

The

going low provides the first address bit to be read in by

Figure 30 shows the detailed timing diagram for the serial
interface to the AD7298. The serial clock provides the conver­sion clock and controls the transfer of information to and from
the AD7298 during each conversion.

The

signal initiates the data transfer and conversion process.

CS

The falling edge of

puts the track-and-hold into hold mode

CS
at which point the analog input is sampled and the bus is taken
out of three-state. The conversion is also initiated at this point
and requires 16 SCLK cycles to complete. The track-and-hold
goes back into track on the 14

Figure 30

rising edge of

If the rising edge of

at Point B. On the 16

, the DOUT line goes back into three-state.

CS

CS

th

SCLK falling edge as shown in

th

SCLK falling edge or on the

occurs before 16 SCLKs have elapsed,

the conversion is terminated, the DOUT line goes back into tri­state, and the control register is not updated; otherwise, DOUT
returns to three-state on the 16

th

SCLK falling edge. Sixteen serial
clock cycles are required to perform the conversion process and
to access data from the AD7298.

For the AD7298, four-channel address bits (ADD3 to ADD0)
that identify which channel the conversion result corresponds
to precede the 12 bits of data (see Tabl e 9).

CS

t

2

SCLK

DOUT

DIN

THREE-

STATE

12345 1314B15 16

t

3

ADD3

ADD2

WRITE REPEAT CH0 CH1 CH2 CH3 EXT_REF PPD

ADD1 ADD0 DB11 DB10 DB2 DB1 DB0

t

9

t

10

t

4

Figure 30. Serial Interface Timing Diagram

t

6

CS

the microcontroller or DSP. The remaining data is then clocked
out by subsequent SCLK falling edges, beginning with a second
address bit. Thus, the first falling clock edge on the serial clock
has the first address bit provided for reading and also clocks out
the second address bit. The three remaining address bits and
12 data bits are clocked out by subsequent SCLK falling edges.
The final bit in the data transfer is valid for reading on the

th

16

falling edge having been clocked out on the previous (15th)

falling edge.

In applications with a slower SCLK, it may be possible to read
in data on each SCLK rising edge depending on the SCLK
frequency. The first rising edge of SCLK after the

edge would have the first address bit provided, and the 15

CS

falling

th

rising SCLK edge would have last data bit provided.

Writing information to the control register takes place on the
first 16 falling edges of SCLK in a data transfer, assuming the MSB
(that is, the WRITE bit) has been set to 1. The 16-bit word read
from the AD7298 always contains four channel address bits that
the conversion result corresponds to, followed by the 12-bit
conversion result.

t

QUIET

t

ACQUISI TION

t

SENSE

AVG

5

t

8

THREE-

STATE

08754-014

t

7

T

Rev. B | Page 21 of 24

AD7298

TEMPERATURE SENSOR READ

The temperature sensor conversion involves two phases, the
integration phase and the conversion phase as detailed in the
Temperature Sensor Operation section. The integration phase
is initiated on the falling edge of
conversion is automatically initiated internally by the AD7298.
When a temperature conversion integration is initiated, the
T

_BUSY signal goes high to indicate that a temperature

SENSE

conversion is in progress and remains high until the conversion
is completed.

The total time to measure and convert a temperature channel
with the AD7298 is 100 s max. Once the T
goes low to indicate that the temperature conversion is
completed, 100 ns must elapse prior to the next falling edge

CS

of

. If a minimum of 100 ns is not adhered to between the
falling edge of T
CS

, the next conversion will be corrupted but the temperature

_BUSY and the subsequent falling edge of

SENSE

result that is framed by the
restriction is in place to ensure that sufficient acquisition time
is allowed for the next conversion.

Once the T
CS

falling edge to frame the read of the previous conversion and

_BUSY signal goes high, the user may provide a

SENSE

program the control register if required (see ). Figure 31

Once the previous conversion result has been read, any
subsequent

CS

falling edges which occur while the T

signal is high are internally ignored by the AD7298. If addi-

CS

tional

falling edges are provided while T

the AD7298 provides an invalid digital output of all 1s.

CS

112161 16 1 16

SCLK

DOUT

DIN

DATA WRITTEN TO CONTROL

REGISTER CH T

CS

and once completed the

_BUSY signal

SENSE

CS

will not be affected. This

_BUSY is high,

SENSE

SELECTED

SENSE

_BUSY

SENSE

THE TEMPERAT URE

INTEGRATION BEGINS

PREVIOUS CONVERSI ON

RESULT

CONFIG URE CONTROL REGIST ER

FOR NEXT CONVERSIO N

Alternatively, if

CS

remains high while T

_BUSY is high,

SENSE

then the DOUT bus remains in three-state.

If the user writes to the control register during the first 16 SCLK
cycles following T

_BUSY going high, the configuration of

SENSE

the device for the next conversion, which is initiated on the
subsequent

CS

falling edge after T

_BUSY goes low, is

SENSE

altered. If the user configures the part for partial power-down in
a write to the control register during the first 16 SCLK cycles
following T

_BUSY going high, the temperature sensor

SENSE

conversion is aborted and the part enters partial power-down
on the 16

th

SCLK falling edge.

Thus, it is recommended not to write to the control register if

CS

the

signal will be toggling while T

_BUSY is high. Care

SENSE

should be taken to ensure that the WRITE bit is set to zero
during the temperature conversion phase when

CS

is toggling.

If an SCLK frequency of more than 10 kHz is used, the
temperature conversion requires more than one standard
read cycle to complete. In this case, the user can monitor the
T

_BUSY signal to determine when the conversion is

SENSE

completed and the result is available for reading.

ENSURES ADEQUATE ACQUISITION

TIME FO R NEXT ADC CONVERS ION

t

11

TEMPERATURE SENSOR RESULT

T

SENSE

_BUSY

THE TEMPERATURE

CONVERSION I S COMPLETED

Figure 31. Serial Interface Timing Diagram for the Temperature Sensor Conversion

Rev. B | Page 22 of 24

08754-015

AD7298

LAYOUT AND CONFIGURATION

POWER SUPPLY BYPASSING AND GROUNDING

For optimum performance, carefully consider the power supply
and ground return layout on any PCB where the AD7298 is
used. The PCB containing the AD7298 should have separate
analog and digital sections, each having its own area of the
board. The AD7298 should be located in the analog section
on any PCB.

Decouple the power supply to the AD7298 to ground with
10 µF and 0.1 µF capacitors. Place the capacitors as physically
close as possible to the device, with the 0.1 µF capacitor ideally
right up against the device. It is important that the 0.1 µF
capacitor have low effective series resistance (ESR) and low
effective series inductance (ESL); common ceramic types of
capacitors are suitable. The 0.1 µF capacitor provides a low
impedance path to ground for high frequencies caused by
transient currents due to internal logic switching. The 10 µF
capacitors are the tantalum bead type.

The power supply line should have as large a trace as possible
to provide a low impedance path and reduce glitch effects on
the supply line. Shield clocks and other components with fast
switching digital signals from other parts of the board by a
digital ground. Avoid crossover of digital and analog signals,
if possible. When traces cross on opposite sides of the board,
ensure that they run at right angles to each other to reduce
feedthrough effects on the board.

The best board layout technique is the microstrip technique
where the component side of the board is dedicated to the
ground plane only and the signal traces are placed on the solder
side; however, this is not always possible with a 2-layer board.

TEMPERATURE MONITORING

The AD7298 is ideal for monitoring the thermal environment.
The die accurately reflects the exact thermal conditions that
affect nearby integrated circuits. The AD7298 measures and
converts the temperature at the surface of its own semicon­ductor chip.

When it is used to measure the temperature of a nearby heat
source, the thermal impedance between the heat source and the
AD7298 must be considered. When the thermal impedance is
determined, the temperature of the heat source can be inferred
from the AD7298 output.

As much as 60% of the heat transferred from the heat source to
the thermal sensor on the AD7298 die is discharged via the
copper tracks and the bond pads. Of the pads on the AD7298,
the GND pad transfers most of the heat. Therefore, to measure
the temperature of a heat source, it is recommended that the
thermal resistance between the AD7298 GND pad and the
GND of the heat source be reduced as much as possible.

Rev. B | Page 23 of 24

AD7298

C

OUTLINE DIMENSIONS

PIN 1

INDI

ATO R

0.80

0.75

0.70

SEATING

PLANE

4.10

4.00 SQ

3.90

0.50

BSC

0.50

0.40

0.30

0.05 MAX

0.02 NOM

0.20 REF

0.30

0.25

0.18

16

15

11

10

BOTTOM VIEWTOP VIEW

COPLANARITY

0.08

N

1

P

I

D

C

I

A

N

I

20

1

EXPOSED

PAD

6

FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONF IGURATIO N AND
FUNCTION DES CRIPTIONS
SECTION O F THIS DAT A SHEET.

2.75

2.60 SQ

2.35

5

0.25 MIN

R

O

T

COMPLIANTTOJEDEC STANDARDS MO -220-WGG D.

020509-B

Figure 32. 20-Lead Lead Frame Chip Scale Package [LFCSP_WQ]

4 mm × 4 mm Body, Very, Very Thin Quad

(CP-20-8)

Dimensions shown in millimeters

ORDERING GUIDE

Model1 Temperature Range Package Description Package Option

AD7298BCPZ −40°C to +125°C 20-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-20-8
AD7298BCPZ-RL7 −40°C to +125°C 20-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-20-8
EVAL-AD7298SDZ Evaluation Board

1

Z = RoHS Compliant Part.

©2010–2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D08754-0-6/11(B)

Rev. B | Page 24 of 24