Datasheet AD7277, AD7278 Datasheet (ANALOG DEVICES)

3 MSPS, 12-/10-/8-Bit

V

V

www.BDTIC.com/ADI

FEATURES

Throughput rate: 3 MSPS
Specified for V
Power consumption

12.6 mW at 3 MSPS with 3 V supplies

Wide input bandwidth

70 dB SNR at 1 MHz input frequency
Flexible power/serial clock speed management
No pipeline delays
High speed serial interface

SPI®-/QSPI™-/MICROWIRE™-/DSP-compatible
Temperature range: −40°C to +125°C
Power-down mode: 0.1 μA typical
6-lead TSOT package
8-lead MSOP package
AD7476 and AD7476A pin-compatible

GENERAL DESCRIPTION

The AD7276/AD7277/AD7278 are 12-/10-/8-bit, high speed,
low power, successive approximation analog-to-digital
converters (ADCs), respectively. The parts operate from a single

2.35 V to 3.6 V power supply and feature throughput rates of up
to 3 MSPS. The parts contain a low noise, wide bandwidth
track-and-hold amplifier that can handle input frequencies in
excess of 55 MHz.

The conversion process and data acquisition are controlled

g

usin

with microprocessors or DSPs. The input signal is sampled on
the falling edge of

point. There are no pipeline delays associated with the part.

The AD7276/AD7277/AD7278 use advanced design techniques

o achieve very low power dissipation at high throughput rates.

t

The reference for the part is taken internally from V
allows the widest dynamic input range to the ADC; therefore,
the analog input range for the part is 0 to V
rate is determined by the SCLK.

and the serial clock, allowing the devices to interface

CS

of 2.35 V to 3.6 V

DD

, and the conversion is also initiated at this

CS

. The conversion

DD

DD

. This

ADCs in 6-Lead TSOT

AD7276/AD7277/AD7278

FUNCTIONAL BLOCK DIAGRAM

DD

12-/10-/8-BIT

IN

T/H

AD7276/
AD7277/
AD7278

Table 1.

Part Number Resolution Package

AD7276 12 8-Lead MSOP 6-Lead TSOT
AD7277 10 8-Lead MSOP 6-Lead TSOT
AD7278 8 8-Lead MSOP 6-Lead TSOT
AD72741 12 8-Lead MSOP 8-Lead TSOT
AD72731 10 8-Lead MSOP 8-Lead TSOT

1

Part contains external reference pin.

PRODUCT HIGHLIGHTS

1. 3 MSPS ADCs in a 6-lead TSOT package.

2. AD7476/AD74

AD7478A pin-compatible.

3. H

igh throughput with low power consumption.

4. Flexi

ble power/serial clock speed management. This
allows maximum power efficiency at low throughput
rates.

SUCCESSIVE

APPROXIMATION

ADC

SCLK

CONTROL

LOGIC

GND

Figure 1.

SDATA

CS

04903-001

77/AD7478 and AD7476A/AD7477A/

5. Refer

6. N

ence derived from the power supply.

o pipeline delay. The parts feature a standard
successive approximation ADC with accurate control
of the sampling instant via a

conversion control.

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2005 Analog Devices, Inc. All rights reserved.

input and once-off

CS

AD7276/AD7277/AD7278

www.BDTIC.com/ADI

TABLE OF CONTENTS

Features.............................................................................................. 1

Theory of Operation ...................................................................... 16

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Product Highlights ........................................................................... 1

Specifications..................................................................................... 3

AD7276 Specifications................................................................. 3

AD7277 Specifications................................................................. 5

AD7278 Specifications................................................................. 7

Timing Specifications—AD7276/AD7277/AD7278 ...............8

Timing Examples........................................................................ 10

Absolute Maximum Ratings.......................................................... 11

ESD Caution................................................................................ 11

Pin Configurations and Function Descriptions ......................... 12

Typical Performance Characteristics ........................................... 13

Terminology .................................................................................... 15

Circuit Information.................................................................... 16

Converter Operation.................................................................. 16

ADC Transfer Function............................................................. 16

Typical Connection Diagram ................................................... 16

Modes of Operation................................................................... 18

Power vs. Throughput Rate....................................................... 21

Serial Interface ................................................................................ 22

AD7278 in a 10 SCLK Cycle Serial Interface.......................... 24

Microprocessor Interfacing....................................................... 24

Application Hints ........................................................................... 25

Grounding and Layout.............................................................. 25

Evaluating Performance.............................................................. 25

Outline Dimensions....................................................................... 26

Ordering Guide .......................................................................... 26

REVISION HISTORY

10/05—Rev. 0 to Rev. A

Updated Format..................................................................Universal

Changes to Table 2............................................................................ 3

Changes to Table 5............................................................................ 8

Changes to the Partial Power-Down Mode Section .................. 18

Changes to the Power vs. Throughput Rate Section.................. 21

Updated Outline Dimensions....................................................... 26

Changes to Ordering Guide.......................................................... 26

7/05—Revision 0: Initial Version

Rev. A | Page 2 of 28

AD7276/AD7277/AD7278

www.BDTIC.com/ADI

SPECIFICATIONS

AD7276 SPECIFICATIONS

VDD = 2.35 V to 3.6 V, B Grade: f
otherwise noted.

Table 2.

Parameter B, Y Grade

DYNAMIC PERFORMANCE fIN = 1 MHz sine wave, B Grade
f

Signal-to-Noise + Distortion (SINAD)
Signal-to-Noise Ratio (SNR) 69 dB min
70 dB typ
Total Harmonic Distortion (THD)4 −73 dB max

−78 dB typ
Peak Harmonic or Spurious Noise (SFDR)4 −80 dB typ
Intermodulation Distortion (IMD)4

Second-Order Terms −82 dB typ fa = 1 MHz, fb = 0.97 MHz

Third-Order Terms −82 dB typ fa = 1 MHz, fb = 0.97 MHz
Aperture Delay 5 ns typ
Aperture Jitter 18 ps typ
Full Power Bandwidth 55 MHz typ @ 3 dB
8 MHz typ @ 0.1 dB

DC ACCURACY

Resolution 12 Bits
Integral Nonlinearity
Differential Nonlinearity
Offset Error
Gain Error

4

4

4

4

Total Unadjusted Error4 (TUE) ±3.5 LSB max

ANALOG INPUT

Input Voltage Ranges 0 to VDD V
DC Leakage Current ±1 μA max −40°C to +85°C
±5.5 μA max 85°C to 125°C
Input Capacitance 42 pF typ When in track
10 pF typ When in hold

LOGIC INPUTS

Input High Voltage, V

1.7 V min 2.35 V ≤ VDD ≤ 2.7 V

INH

2 V min 2.7 V < VDD ≤ 3.6 V
Input Low Voltage, V

0.7 V max 2.35 V ≤ VDD ≤ 2.7 V

INL

0.8 V max 2.7 V < VDD ≤ 3.6 V
Input Current, IIN ±1 μA max Typically 10 nA, VIN = 0 V or VDD
Input Capacitance, C

5

IN

LOGIC OUTPUTS

Output High Voltage, VOH V
Output Low Voltage, VOL 0.2 V max I
Floating-State Leakage Current ±2.5 μA max
Floating-State Output Capacitance
Output Coding Straight (natural) binary

= 48 MHz, f

SCLK

4

5

= 3 MSPS, Y Grade:1 f

SAMPLE

2, 3

Unit Test Conditions/Comments

= 16 MHz, f

SCLK

= 1 MSPS, TA = T

SAMPLE

= 100 KHz sine wave, Y Grade

IN

68 dB min

±1 LSB max
+1/−0.99 LSB max Guaranteed no missed codes to 12 bits
±3 LSB max
±3.5 LSB max

2 pF typ

– 0.2 V min I

DD

= 200 μA, VDD = 2.35 V to 3.6 V

SOURCE

= 200 μA

SINK

4.5 pF typ

MIN

to T

MAX

, unless

Rev. A | Page 3 of 28

AD7276/AD7277/AD7278

www.BDTIC.com/ADI

Parameter B, Y Grade

2, 3

Unit Test Conditions/Comments

CONVERSION RATE

Conversion Time 291 ns max 14 SCLK cycles with SCLK at 48 MHz, B Grade
875 ns max 14 SCLK cycles with SCLK at 16 MHz, Y Grade
Track-and-Hold Acquisition Time

4

60 ns min

Throughput Rate 3 MSPS max See the Serial Interface section

POWER REQUIREMENTS

VDD 2.35/3.6 V min/max
IDD Digital I/Ps 0 V or VDD

Normal Mode (Static) 1 mA typ VDD = 3.6 V, SCLK on or off
Normal Mode (Operational) 5.5 mA max VDD = 2.35 V to 3.6 V, f

2.5 mA max VDD = 2.35 V to 3.6 V, f

4.2 mA typ VDD = 3 V, f

1.6 mA typ VDD = 3 V, f

= 3 MSPS, B Grade

SAMPLE

= 1 MSPS, Y Grade

SAMPLE

= 3 MSPS, B Grade

SAMPLE

= 1 MSPS, Y Grade

SAMPLE

Partial Power-Down Mode (Static) 34 μA typ
Full Power-Down Mode (Static) 2 μA max −40°C to +85°C, typically 0.1 μA
10 μA max 85°C to 125°C

Power Dissipation

Normal Mode (Operational) 19.8 mW max VDD = 3.6 V, f
9 mW max VDD = 3.6 V, f

12.6 mW typ VDD = 3 V, f

4.8 mW typ VDD = 3 V, f

6

SAMPLE

SAMPLE

= 3 MSPS, B Grade

SAMPLE

= 1 MSPS, Y Grade

SAMPLE

= 3 MSPS, B Grade
= 1 MSPS, Y Grade

Partial Power-Down 102 μW typ VDD = 3 V
Full Power-Down 7.2 μW max VDD = 3.6 V, −40°C to +85°C

1

Y Grade specifications are guaranteed by characterization.

2

Temperature range from −40°C to +125°C.

3

Typical specifications are tested with VDD = 3 V and at 25°C.

4

See the Terminology section.

5

Guaranteed by characterization.

6

See the Power vs. Throughput Rate section.

Rev. A | Page 4 of 28

AD7276/AD7277/AD7278

www.BDTIC.com/ADI

AD7277 SPECIFICATIONS

VDD = 2.35 V to 3.6 V, f

Table 3.

Parameter B Grade

DYNAMIC PERFORMANCE fIN = 1 MHz sine wave

Signal-to-Noise + Distortion (SINAD)
Total Harmonic Distortion (THD)3 −71 dB max

−76 dB typ
Peak Harmonic or Spurious Noise (SFDR)3 −80 dB typ
Intermodulation Distortion (IMD)3

Second-Order Terms −82 dB typ fa = 1 MHz, fb = 0.97 MHz

Third-Order Terms −82 dB typ fa = 1 MHz, fb = 0.97 MHz
Aperture Delay 5 ns typ
Aperture Jitter 18 ps typ
Full Power Bandwidth 74 MHz typ @ 3 dB
10 MHz typ @ 0.1 dB

DC ACCURACY

Resolution 10 Bits
Integral Nonlinearity
Differential Nonlinearity
Offset Error
Gain Error

3

3

Total Unadjusted Error (TUE)3 ±2.5 LSB max

ANALOG INPUT

Input Voltage Ranges 0 to VDD V
DC Leakage Current ±1 μA max −40°C to +85°C
±5.5 μA max 85°C to 125°C
Input Capacitance 42 pF typ When in track
10 pF typ When in hold

LOGIC INPUTS

Input High Voltage, V
2 V min 2.7 V < VDD ≤ 3.6 V
Input Low Voltage, V

0.8 V max 2.7 V < VDD ≤ 3.6 V
Input Current, IIN ±1 μA max Typically 10 nA, VIN = 0 V or VDD
Input Capacitance, C

LOGIC OUTPUTS

Output High Voltage, VOH V
Output Low Voltage, VOL 0.2 V max I
Floating-State Leakage Current ±2.5 μA max
Floating-State Output Capacitance
Output Coding Straight (natural) binary

CONVERSION RATE

Conversion Time 250 ns max 12 SCLK cycles with SCLK at 48 MHz
Track-and-Hold Acquisition Time
Throughput Rate 3.45 MSPS max SCLK at 48 MHz

= 48 MHz, f

SCLK

3

3

= 3 MSPS, TA = T

SAMPLE

3

MIN

to T

1, 2

, unless otherwise noted.

MAX

Unit Test Conditions/Comments

60.5 dB min

±0.5 LSB max
±0.5 LSB max Guaranteed no missed codes to 10 bits
±1 LSB max
±1.5 LSB max

1.7 V min 2.35 V ≤ VDD ≤ 2.7 V

INH

0.7 V max 2.35 V ≤ VDD ≤ 2.7 V

INL

4

IN

4

3

2 pF typ

− 0.2 V min I

DD

= 200 μA, VDD = 2.35 V to 3.6 V

SOURCE

= 200 μA

SINK

4.5 pF typ

60 ns min

Rev. A | Page 5 of 28

AD7276/AD7277/AD7278

www.BDTIC.com/ADI

Parameter B Grade

POWER REQUIREMENTS

VDD 2.35/3.6 V min/max
IDD Digital I/Ps 0 V or VDD

Normal Mode (Static) 0.6 mA typ VDD = 3.6 V, SCLK on or off
Normal Mode (Operational) 5.5 mA max VDD = 2.35 V to 3.6 V, f

3.5 mA typ VDD = 3 V
Partial Power-Down Mode (Static) 34 μA typ
Full Power-Down Mode (Static) 2 μA max −40°C to +85°C, typically 0.1 μA
10 μA max 85°C to 125°C

Power Dissipation

Normal Mode (Operational) 19.8 mW max VDD = 3.6 V, f

10.5 mW typ VDD = 3 V
Partial Power-Down 102 μW typ VDD = 3 V
Full Power-Down 7.2 μW max VDD = 3.6 V, −40°C to +85°C

1

Temperature range from −40°C to +125°C.

2

Typical specifications are tested with VDD = 3 V and at 25°C.

3

See the Terminology section.

4

Guaranteed by characterization.

5

See the Power vs. Throughput Rate section.

5

1, 2

Unit Test Conditions/Comments

SAMPLE

= 3 MSPS

SAMPLE

= 3 MSPS

Rev. A | Page 6 of 28

AD7276/AD7277/AD7278

www.BDTIC.com/ADI

AD7278 SPECIFICATIONS

VDD = 2.35 V to 3.6 V, f

Table 4.

Parameter B Grade

DYNAMIC PERFORMANCE fIN = 1 MHz sine wave

Signal-to-Noise + Distortion (SINAD)
Total Harmonic Distortion (THD)3 −67 dB max

−73 dB typ
Peak Harmonic or Spurious Noise (SFDR)3 −69 dB typ
Intermodulation Distortion (IMD)3

Second-Order Terms −76 dB typ fa = 1 MHz, fb = 0.97 MHz

Third-Order Terms −76 dB typ fa = 1 MHz, fb = 0.97 MHz
Aperture Delay 5 ns typ
Aperture Jitter 18 ps typ
Full Power Bandwidth 74 MHz typ @ 3 dB
Full Power Bandwidth 10 MHz typ @ 0.1 dB

DC ACCURACY

Resolution 8 Bits
Integral Nonlinearity
Differential Nonlinearity
Offset Error
Gain Error

3

3

Total Unadjusted Error (TUE)3 ±1.5 LSB max

ANALOG INPUT

Input Voltage Ranges 0 to VDD V
DC Leakage Current ±1 μA max −40°C to +85°C
±5.5 μA max 85°C to 125°C
Input Capacitance 42 pF typ When in track
10 pF typ When in hold

LOGIC INPUTS

Input High Voltage, V
2 V min 2.7 V < VDD ≤ 3.6 V
Input Low Voltage, V

0.8 V max 2.7 V < VDD ≤ 3.6 V
Input Current, IIN ±1 μA max
Input Capacitance, C

LOGIC OUTPUTS

Output High Voltage, VOH V
Output Low Voltage, VOL 0.2 V max I
Floating-State Leakage Current ±2.5 μA max
Floating-State Output Capacitance
Output Coding Straight (natural) binary

CONVERSION RATE

Conversion Time 208 ns max 10 SCLK cycles with SCLK at 48 MHz
Track-and-Hold Acquisition Time
Throughput Rate 4 MSPS max SCLK at 48 MHz

= 48 MHz, f

SCLK

3

3

= 3 MSPS, TA = T

SAMPLE

3

MIN

to T

1, 2

, unless otherwise noted.

MAX

Unit Test Conditions/Comments

49 dB min

±0.2 LSB max
±0.3 LSB max Guaranteed no missed codes to 8 bits
±0.5 LSB max
±1 LSB max

1.7 V min 2.35 V ≤ VDD ≤ 2.7 V

INH

0.7 V max 2.35 V ≤ VDD ≤ 2.7 V

INL

4

IN

4

3

2 pF typ

– 0.2 V min I

DD

= 200 μA, VDD = 2.35 V to 3.6 V

SOURCE

= 200 μA

SINK

4.5 pF typ

60 ns min

Rev. A | Page 7 of 28

AD7276/AD7277/AD7278

www.BDTIC.com/ADI

Parameter B Grade

1, 2

Unit Test Conditions/Comments

POWER REQUIREMENTS

VDD 2.35/3.6 V min/max
IDD Digital I/Ps = 0 V or VDD

Normal Mode (Static) 0.5 mA typ VDD = 3.6 V, SCLK on or off
Normal Mode (Operational) 5.5 mA max VDD = 2.35 V to 3.6 V, f

SAMPLE

= 3 MSPS

3.5 mA typ VDD = 3 V
Partial Power-Down Mode (Static) 34 μA typ
Full Power-Down Mode (Static) 2 μA max −40°C to +85°C, typically 0.1 μA
10 μA max +85°C to +125°C
Power Dissipation

Normal Mode (Operational) 19.8 mW max VDD = 3.6 V, f

5

SAMPLE

= 3 MSPS

10.5 mW typ VDD = 3 V
Partial Power-Down 102 μW typ VDD = 3 V
Full Power-Down 7.2 μW max VDD = 3.6 V, −40°C to +85°C

1

Temperature range from −40°C to +125°C.

2

Typical specifications are tested with VDD = 3 V and at 25°C.

3

See the Terminology section.

4

Guaranteed by characterization.

5

See the Power vs. Throughput Rate section.

TIMING SPECIFICATIONS—AD7276/AD7277/AD7278

VDD = 2.35 V to 3.6 V, TA = T

MIN

to T

, unless otherwise noted.

MAX

Table 5.

Parameter2Limit at T

3

f

SCLK

500 kHz min

MIN

, T

Unit Description

MAX

48 MHz max B grade
16 MHz max Y grade
t

14 × t

CONVER T

12 × t
10 × t
t

4 ns min

QUIET

AD7276

SCLK

AD7277

SCLK

AD7278

SCLK

t1 3 ns min
t2 6 ns min

5

t

3

5

t

4

t5 0.4 t
t6 0.4 t

5

t

7

4 ns max
15 ns max Data access time after SCLK falling edge

ns min SCLK low pulse width

SCLK

ns min SCLK high pulse width

SCLK

5 ns min SCLK to data valid hold time
t8 14 ns max SCLK falling edge to SDATA three-state
5 ns min SCLK falling edge to SDATA three-state
t

9

T

POWER-UP

1

Sample tested during initial release to ensure compliance. All timing specifications given are with a 10 pF load capacitance. With a load capacitance greater than this

value, a digital buffer or latch must be used.

2

Guaranteed by characterization. All input signals are specified with tr = tf = 2 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.

3

Mark/space ratio for the SCLK input is 40/60 to 60/40.

4

Minimum f

5

The time required for the output to cross the VIH or VIL voltage.

6

See the Power-Up Times section.

4.2 ns max

6

1 μs max Power-up time from full power-down

at which specifications are guaranteed.

SCLK

1

4

Minimum quiet time required between the bus relinquish and the

t of the next conversion

star
Minimum CS

to SCLK setup time

CS
Delay from CS

rising edge to SDATA three-state

CS

pulse width

until SDATA three-state disabled

Rev. A | Page 8 of 28

AD7276/AD7277/AD7278

www.BDTIC.com/ADI

t

SCLK

SDATA

SCLK

SDATA

4

Figure 2. Access Time After SCLK Falling Edge

t

7

V

IH

V

IL

Figure 3. Hold Time After SCLK Falling Edge

SCLK

V

IH

V

IL

04903-002

SDATA

Figure 4. SCLK Falling Edge SDATA Three-State

04903-003

t

8

1.4V

04903-004

Rev. A | Page 9 of 28

AD7276/AD7277/AD7278

S

K

www.BDTIC.com/ADI

TIMING EXAMPLES

For the AD7276, if CS is brought high during the 14th SCLK rising

edge after the two leading zeros and 12 bits of the conversion
have been provided, the part can achieve the fastest throughput
rate, 3 MSPS. If

edge after the two leading zeros and 12 bits of the conversion
and two trailing zeros have been provided, a throughput rate of

2.97 MSPS is achievable. This is illustrated in the following two
timing examples.

Timing Example 1

In Figure 6, using a 14 SCLK cycle, f
throughput is 3 MSPS. This produces a cycle time of t

12.5(1/f
t

= 67 ns.

ACQ

SCLK

is brought high during the 16th SCLK rising

CS

= 48 MHz and the

SCLK

) + t

= 333 ns, where t2 = 6 ns minimum and

ACQ

CS

t

CONVERT

234

DB11 DB10 DB9 DB1 DB0

SCLK

DATA

SDATA

CS

SCL

STATE

CS

SCLK

THREE-

STATE 2 LE ADING

t

2

1 2 345 13141516

t

3

ZEROZ DB11 DB10 DB9 DB1 DB0 ZERO ZERO

2 LEADING

ZEROS

t

2

1513

t

3

ZZERO

ZEROS

t

2

12345 1312 14 15 16

+

2

t

6

t

4

Figure 5. AD7276 Serial Interface Timing Diagram

t

CONVERT

t

t

4

Figure 6. AD7276 Serial Interface Timing 14 SCLK Cycle

t

CONVERT

SCLK

)

12.5(1/f

Figure 7. AD7276 Serial Interface Timing 16 SCLK Cycle

t

7

1/THROUGHPUT

6

t

7

1/THROUGHPUT

This satisfies the requirement of 60 ns for t
shows that t
t

= 14 ns max. This allows a value of 43 ns for t

8

comprises 0.5(1/f

ACQ

SCLK

) + t8 + t

the minimum requirement of 4 ns.

Timing Example 2

The example in Figure 7 uses a 16 SCLK cycle, f
and the throughput is 2.97 MSPS. This produces a cycle time of
t

+ 12.5(1/f

2

t

= 70 ns. Figure 7 shows that t

ACQ

t

, where t8 = 14 ns max. This satisfies the minimum

QUIET

requirement of 4 ns for t

B

t

5

t

1/THROUGHPUT

B

SCLK

2 TRAILI NG

ZEROS

B

5

t

t

8

) + t

= 336 ns, where t2 = 6 ns minimum and

ACQ

comprises 2.5(1/f

ACQ

QUIET.

t

1

8

14

t

9

t

ACQUISITION

t

QUIET

THREE-STATETHREE-

t

1

t

QUIET

THREE-STATE

t

QUIET

t

1

. Figure 6 also

ACQ

, where

QUIET

, satisfying

QUIET

= 48 MHz,

SCLK

04903-005

04903-034

04903-006

SCLK

) + t8 +

Rev. A | Page 10 of 28

AD7276/AD7277/AD7278

www.BDTIC.com/ADI

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 6.

Parameters Ratings

VDD to GND −0.3 V to +6 V
Analog Input Voltage to GND −0.3 V to VDD + 0.3 V
Digital Input Voltage to GND −0.3 V to +6 V
Digital Output Voltage to GND −0.3 V to VDD + 0.3 V
Input Current to Any Pin Except Supplies1±10 mA
Operating Temperature Range

Commercial (B grade) −40°C to +125°C

Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
6-Lead TSOT Package

θJA Thermal Impedance 230°C/W

θJC Thermal Impedance 92°C/W
8-Lead MSOP Package

θJA Thermal Impedance 205.9°C/W

θJC Thermal Impedance 43.74°C/W
Lead Temperature Soldering

Reflow (10 sec to 30 sec) 255°C
Lead Temperature Soldering

Reflow (10 sec to 30 sec) 260°C
ESD 1.5 kV

1

Transient currents of up to 100 mA cause SCR latch-up.

Stresses above those listed under Absolute Maximum Ratings
ma
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

y cause permanent damage to the device. This is a stress

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. A | Page 11 of 28

AD7276/AD7277/AD7278

www.BDTIC.com/ADI

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

V

GND

V

DD

IN

1

AD7276/
AD7277/

2

AD7278

TOP VIEW

(Not to Scale)

3

6

5

4

CS

SDATA

SCLK

04903-007

Figure 8. 6-Lead TSOT Pin Configuration

1

V

DD

AD7276/

2

SDATA

AD7277/

AD7278

CS

3

TOP VIEW

NC

4

(Not to Scale)

NC = NO CO NNECT

Figure 9. 8-Lead MSOP Pin Configuration

8

7

6

5

V

IN

GND

SCLK

NC

Table 7. Pin Function Descriptions

6-Lead
TSOT
Pin No.

8-Lead
MSOP
Pin No.

Mnemonic

Description

1 1 VDD Power Supply Input. The VDD range for the AD7276/AD7277/AD7278 is 2.35 V to 3.6 V.
2 7 GND

Analog Ground. Ground reference point for all circuitry on the AD7276/AD7277/AD7278. All analog
input signal

s should be referred to this GND voltage.
3 8 VIN Analog Input. Single-ended analog input channel. The input range is 0 V to VDD.
4 6 SCLK

Serial Clock. Logic input. SCLK provides the serial clock f

or accessing data from the part. This clock

input is also used as the clock source for the conversion process of the AD7276/AD7277/AD7278.

5 2 SDATA

Data Out. Logic output. The conversion result fr

om the AD7276/AD7277/AD7278 is provided on this
output as a serial data stream. The bits are clocked out on the falling edge of the SCLK input. The data
stream from the AD7276 consists of two leading zeros followed by 12 bits of conversion data and two
trailing zeros, provided MSB first. The data stream from the AD7277 consists of two leading zeros
followed by 10 bits of conversion data and four trailing zeros, provided MSB first. The data stream from
the AD7278 consists of two leading zeros followed by 8 bits of conversion data and six trailing zeros,
provided MSB first.

6 3

CS

Chip Select. Active low logic input. This input provides the dual function of initiating conversion on
the AD7276/AD7277/AD7278 and framing the serial data transfer.

4, 5 NC No Connect.

04903-008

Rev. A | Page 12 of 28

AD7276/AD7277/AD7278

–

–

www.BDTIC.com/ADI

TYPICAL PERFORMANCE CHARACTERISTICS

TA = 25°C.

16,384 POI NT FF T
F

–20

–40

–60

SNR (dB)

–80

–100

–120

0 100 200 300 400 500 600 700 800 900 1000 11001200 1300 1400

FREQUENCY (kHz)

=3MSPS

SAMPLE

F

=1MHz

IN

SINAD = 71. 2dB
THD = –80. 9dB
SFDR = –82.4dB
V

=3V

DD

04903-009

1500

Figure 10. AD7276 Dynamic Performance at 3 MSPS, Input Tone = 1 MHz

73.0

72.5

72.0

71.5
VDD=3V

71.0

SNR (dB)

70.5

70.0

69.5

69.0

100

INPUT FREQUENCY (kHz)

VDD=3.6V

VDD= 2.35V

Figure 13. AD7276 SNR vs. Analog Input Frequency at 3 MSPS

arious Supply Voltages, SCLK Frequency = 48 MHz

for V

04903-013

15001000

10

–20

–30

–40

–50

–60

SNR (dB)

–70

–80

–90

–100

–110

0 100 200 300 400 500 600 700 800 900 1000 11001200 1300 1400

FREQUENCY (kHz)

16,384 POINT F FT
F

= 3MSPS

SAMPLE

F

=1MHz

IN

SINAD = 61.6dB
THD = –80 .2dB
SFDR = –83.4dB
V

=3V

DD

04903-010

1500

Figure 11. AD7277 Dynamic Performance at 3 MSPS, Input Tone = 1 MHz

72.5

72.0

71.5

71.0

70.5

70.0

SINAD (dB)

69.5

69.0

68.5

68.0

67.5
100

VDD= 2.35V

INPUT FREQUENCY (kHz)

VDD=3.6V

VDD=3V

04903-012

15001000

Figure 12. AD7276 SINAD vs. Analog Input Frequency at 3 MSPS

for V

arious Supply Voltages, SCLK Frequency = 48 MHz

30,000

25,000

20,000

15,000

10,000

NUMBER OF OCCURRENCES

5,000

0

2046

30,000

CODES

CODE

Figure 14. Histogram of Codes for 30,000 Samples

72

–74

–76

–78

–80

–82

THD (dB)

–84

–86

–88

–90

100

INPUT FRE QUENCY (kHz)

VDD= 2.35V

VDD=3V

Figure 15. THD vs. Analog Input Frequency at 3 MSPS

arious Supply Voltages, SCLK Frequency = 48 MHz

for V

2050204920482047

04903-016

VDD=3.6V

04903-017

15001000

Rev. A | Page 13 of 28

AD7276/AD7277/AD7278

–

www.BDTIC.com/ADI

50

–55

–60

–65

–70

THD (dB)

–75

–80

–85

–90

100

RIN= 100Ω

RIN=10Ω

RIN=0Ω

04903-015

15001000

INPUT FRE QUENCY (kHz)

Figure 16. THD vs. Analog Input Frequency at 3 MSPS for Various Source

Impedances, SCLK Frequency = 48 MHz, Supply Voltage = 3 V

1.0

0.8

0.6

0.4

0.2

0

–0.2

DNL ERROR (LSB)

–0.4

–0.6

–0.8

–1.0

0

CODE

VDD=3V

04903-014

4000350030002500200015001000500

Figure 18. AD7276 DNL Performance

INL ERROR (LSB)

–0.2

–0.4

–0.6

–0.8

–1.0

1.0

0.8

0.6

0.4

0.2

0

0

CODE

VDD=3V

04903-011

4000350030002500200015001000500

Figure 17. AD7276 INL Performance

Rev. A | Page 14 of 28

AD7276/AD7277/AD7278

www.BDTIC.com/ADI

TERMINOLOGY

Integral Nonlinearity

The maximum deviation from a straight line passing through
the endpoints of the ADC transfer function. For the AD7276/
AD7277/AD7278, the endpoints of the transfer function are
zero scale at 0.5 LSB below the first code transition, and full
scale at 0.5 LSB above the last code transition.

Differential Nonlinearity

ference between the measured and the ideal 1 LSB

The dif
change between any two adjacent codes in the ADC.

Offset Error

The devia
(00 . . . 001) from the ideal, that is, AGND + 0.5 LSB.

Gain Error

The devia
(111 . . . 111) from the ideal after adjusting for the offset error,
that is, V

Tot a l U n ad ju s te d E rr o r

A co
offset errors.

Track-and-Hold Acquisition Time

The t
track-and-hold amplifier to reach its final value within ±0.5 LSB.
See the Serial Interface section for more details.

Signal-to-Noise + Distortion Ratio (SINAD)

The me
of the ADC. The signal is the rms amplitude of the fundamental,
and noise is the rms sum of all nonfundamental signals up to half
the sampling frequency (fs/2), including harmonics but excluding
dc. The ratio is dependent on the number of quantization levels
in the digitization process: the more levels, the smaller the quanti­zation noise. For an ideal N-bit converter, the SINAD is defined as

According to this equation, the SINAD is 74 dB for a 12-bit
co
error sources in the ADC, including integral and differential
nonlinearities and internal ac noise sources, cause the measured
SINAD to be less than its theoretical value.

tion of the first code transition (00 . . . 000) to

tion of the last code transition (111 . . . 110) to

− 1.5 LSB.

REF

mprehensive specification that includes gain, linearity, and

ime required after the conversion for the output of the

asured ratio of signal to noise plus distortion at the output

dB76.102.6 += NSINAD

nverter and 62 dB for a 10-bit converter. However, various

Total Harmonic Distortion (THD)

The ratio of the rms sum of harmonics to the fundamental. It is
defined as:

2

2

2

2

2

()

THD

where:

V

is the rms amplitude of the fundamental.

1

V

, V3, V4, V5, and V6 are the rms amplitudes of the second

2

through sixth harmonics.

Peak Harmonic or Spurious Noise

The ratio of the rms value of the next largest component in the
ADC output spectrum (up to f
of the fundamental. Normally, the value of this specification is
determined by the largest harmonic in the spectrum; however, for
ADCs with harmonics buried in the noise floor, it is determined
by a noise peak.

Intermodulation Distortion

With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities creates distortion
products at sum and difference frequencies of mfa ± nfb, where
m and n = 0, 1, 2, 3, …. Intermodulation distortion terms are
those for which neither m nor n are equal to zero. For example,
the second-order terms include (fa + fb) and (fa − fb), and the
third-order terms include (2fa + fb), (2fa − fb), (fa + 2fb), and
(fa − 2fb).

The AD7276/AD7277/AD7278 are tested using the CCIF

tandard in which two input frequencies are used (see fa and fb

s
in the specifications). In this case, the second-order terms are
usually distanced in frequency from the original sine waves, and
the third-order terms are usually at a frequency close to the input
frequencies. As a result, the second- and third-order terms are
specified separately. The calculation of the intermodulation
distortion is as per the THD specification, where it is the ratio
of the rms sum of the individual distortion products to the rms
amplitude of the sum of the fundamentals expressed in decibels.

Aperture Delay

The measured interval between the leading edge of the sampling
clock and the point at which the ADC takes the sample.

Aperture Jitter

The sample-to-sample variation when the sample is taken.

=

2

log20dB

/2, excluding dc) to the rms value

S

4

3

V

1

VVVVV

++++

5

6

Rev. A | Page 15 of 28

AD7276/AD7277/AD7278

www.BDTIC.com/ADI

THEORY OF OPERATION

CIRCUIT INFORMATION

The AD7276/AD7277/AD7278 are fast, micropower, 12-/10-/
8-bit, single-supply ADCs, respectively. The parts can be operated
from a 2.35 V to 3.6 V supply. When operated from a supply
voltage within this range, the AD7276/AD7277/AD7278 are
capable of throughput rates of 3 MSPS when provided with a
48 MHz clock.

The AD7276/AD7277/AD7278 provide the user with an on­chi

p track-and-hold ADC and a serial interface housed in a tiny
6-lead TSOT or an 8-lead MSOP package, which offers the user
considerable space-saving advantages over alternative solutions.
The serial clock input accesses data from the part and provides
the clock source for the successive approximation ADC. The
analog input range is 0 V to V
required for the ADC, and there is no reference on-chip. The
reference for the AD7276/AD7277/AD7278 is derived from the
power supply, resulting in the widest dynamic input range.

. An external reference is not

DD

SAMPLING

CAPACITOR

A

V

IN

SW1

ACQUISITION

B

PHASE

V

AGND

Figure 20. ADC Conversion Phase

SW2

/2

DD

COMPARATOR

ADC TRANSFER FUNCTION

The output coding of the AD7276/AD7277/AD7278 is straight
binary. The designed code transitions occur midway between
successive integer LSB values, such as 0.5 LSB and 1.5 LSB. The
LSB size is V
and V

DD

for the AD7276/AD7277/AD7278 is shown in

/4,096 for the AD7276, VDD/1,024 for the AD7277,

DD

/256 for the AD7278. The ideal transfer characteristic

CHARGE

REDISTRIBUT ION

DAC

CONTROL

LOGIC

Figure 21.

04903-020

The AD7276/AD7277/AD7278 also feature a power-down

ion to save power between conversions. The power-down

opt
feature is implemented across the standard serial interface as
described in the

Modes of Operation section.

CONVERTER OPERATION

The AD7276/AD7277/AD7278 are successive approximation
ADCs that are based on a charge redistribution DAC. Figure 19
and Figure 20 show simplified schematics of the ADC. Figure 19

ws the ADC during its acquisition phase, where SW2 is closed,

sho
SW1 is in Position A, the comparator is held in a balanced con­dition, and the sampling capacitor acquires the signal on V

CHARGE

REDISTRIBUT ION

DAC

SAMPLING

CAPACITOR

A

V

IN

SW1

ACQUISITION

B

PHASE

V

AGND

Figure 19. ADC Acquisition Phase

SW2

/2

DD

COMPARATOR

CONTROL

LOGIC

When the ADC starts a conversion, SW2 opens and SW1 moves
to Position B, causing the comparator to become unbalanced
(see Figure 20). The control logic and the charge redistribution

ACs are used to add and subtract fixed amounts of charge

D
from the sampling capacitor to bring the comparator back into
a balanced condition. When the comparator is rebalanced, the
conversion is complete. The control logic generates the ADC
output code.

.

IN

04903-019

111.. .111

111. ..110

111...000

011...111

ADC CODE

000...010

000...001

000...000

0V

Figure 21. AD7276/AD7277/AD7278 Transfer Characteristics

1LSB = V
1LSB = V
1LSB = V

ANALOG INPUT

/4096 (AD7278)

REF

/1024 (AD7277)

REF

/256 (AD7276)

REF

+V

DD

–1.5LSB0.5LSB

04903-021

TYPICAL CONNECTION DIAGRAM

Figure 22 shows a typical connection diagram for the AD7276/
AD7277/AD7278. V

should be decoupled. This provides an analog input range

V

DD

of 0 V to V

. The conversion result is output in a 16-bit word

DD

with two leading zeros followed by the 12-bit, 10-bit, or 8-bit
result. The 12-bit result from the AD7276 is followed by two
trailing zeros; the 10-bit and 8-bit results from the AD7277 and
AD7278 are followed by four and six trailing zeros, respectively.

Alternatively, because the supply current required by the AD7276/
AD7277/AD7

278 is so low, a precision reference can be used as the
supply source for the AD7276/AD7277/AD7278. A REF19x voltage
reference (REF193 for 3 V) can be used to supply the required
voltage to the ADC (see Figure 22). This configuration is especially

eful if the power supply is noisy or the system’s supply voltage is a

us
value other than 3 V (for example, 5 V or 15 V). The REF19x
outputs a steady voltage to the AD7276/AD7277/AD7278. If the
low dropout REF193 is used, it must supply a current of typically
1 mA to the AD7276/AD7277/AD7278. When the ADC is
converting at a rate of 3 MSPS, the REF193 must supply a maxi­mum of 5 mA to the AD7276/AD7277/AD7278.

is taken internally from VDD; therefore,

REF

Rev. A | Page 16 of 28

AD7276/AD7277/AD7278

0

V

V

www.BDTIC.com/ADI

The load regulation of the REF193 is typically 10 ppm/mA
(REF193, V
for the 5 mA drawn from it. When V

= 5 V), which results in an error of 50 ppm (150 µV)

S

= 3 V from the REF193, it

DD

corresponds to an error of 0.204 LSB, 0.051 LSB, and 0.0128 LSB
for the AD7276, AD7277, and AD7278, respectively. For applica­tions where power consumption is of concern, use the power-down
mode of the ADC and the sleep mode of the REF19x reference to
improve power performance. See the

3

TANT

AD7276/
AD7277/

AD7278

1µF

0.1µF

680nF

V

DD

VTOV

INPUT

Figure 22. REF193 as Power Supply to AD7276/AD7277/AD7278

V

DD

IN

GND

Modes of Operation section.

REF193

0.1µF10µF

SCLK

SDATA

CS

SERIAL

INTERFACE

DSP/

µC/µP

5V
SUPPLY

04903-022

Tabl e 8 provides typical performance data with various
references used as a V

source with the same setup conditions.

DD

Table 8. AD7276 Performance (Various Voltage References IC)

Reference Tied to VDD SNR Performance, 1 MHz Input

AD780 @ 3 V 71.3 dB
AD780 @ 2.5 V 70.1 dB
REF193 70.9 dB

Analog Input

Figure 23 shows an equivalent circuit of the analog input structure
of the AD7276/AD7277/AD7278. The two diodes, D1 and D2,
provide ESD protection for the analog inputs. Care must be taken
to ensure that the analog input signal never exceeds the supply
rails by more than 300 mV. Signals exceeding this value cause
these diodes to become forward biased and to start conducting
current into the substrate. These diodes can conduct a maximum
current of 10 mA without causing irreversible damage to the
part. Capacitor C1 in
p

rimarily be attributed to pin capacitance. Resistor R1 is a

Figure 23 is typically about 4 pF and can

lumped component made up of the on resistance of a switch.
This resistor is typically about 75 Ω. Capacitor C2 is the ADC
sampling capacitor and has a capacitance of 4 pF typically when
in hold mode and 32 pF typically when in track mode. For ac
applications, removing high frequency components from the
analog input signal is recommended by using a band-pass filter
on the relevant analog input pin. In applications where the
harmonic distortion and signal-to-noise ratio are critical, the
analog input should be driven from a low impedance source.

Large source impedances significantly affect the ac performance

f these ADCs and can necessitate the use of an input buffer

o
amplifier. The AD8021 op amp is compatible with these devices;
however, the choice of the op amp is a function of the particular
application.

DD

D1

V

IN

C1

4pF

Figure 23. Equivalent Analog Input Circuit

D2

CONVERSION PHASE—SWITCH OPEN
TRACK PHASE—SW ITCH CLOSED

R1

C2

04903-023

When no amplifier is used to drive the analog input, the source
impedance should be limited to a low value. The maximum source
impedance depends on the amount of THD that can be tolerated.
The THD increases as the source impedance increases and per­formance degrades. Figure 16 shows a graph of the THD vs. the

nalog input frequency for different source impedances when

a
using a supply voltage of 3 V and sampling at a rate of 3 MSPS.

Digital Inputs

The digital inputs applied to the AD7276/AD7277/AD7278 are
not limited by the maximum ratings that limit the analog inputs.
Instead, the digital inputs applied to the AD7276/AD7277/
AD7278 can be 6 V and are not restricted by the V

+ 0.3 V

DD

limit of the analog inputs. For example, if the AD7276/AD7277/
AD7278 are operated with a V

of 3 V, then 5 V logic levels can

DD

be used on the digital inputs. However, it is important to note
that the data output on SDATA still has 3 V logic levels when

= 3 V. Another advantage of SCLK and CS not being

V

DD

restricted by the V

+ 0.3 V limit is that power supply sequencing

DD

issues are avoided. For example, unlike with the analog inputs,
with the digital inputs, if

or SCLK is applied before VDD,

CS

there is no risk of latch-up.

Rev. A | Page 17 of 28

AD7276/AD7277/AD7278

A

/

www.BDTIC.com/ADI

MODES OF OPERATION

The mode of operation of the AD7276/AD7277/AD7278 is
selected by controlling the logic state of the

conversion. There are three possible modes of operation: normal
mode, partial power-down mode, and full power-down mode.
The point at which

is pulled high after the conversion has

CS

been initiated determines which power-down mode, if any, the
device enters. Similarly, if the device is already in power-down
mode,

can control whether the device returns to normal

CS

operation or remains in power-down mode. These modes of
operation are designed to provide flexible power management
options, which can be chosen to optimize the power dissipation/
throughput rate ratio for different application requirements.

Normal Mode

This mode is intended for fastest throughput rate performance
because the device remains fully powered at all times, eliminating
worry about power-up times. Figure 24 shows the general diagram

f AD7276/AD7277/AD7278 operation in this mode.

o

signal during a

CS

can idle high until the next conversion or low until CS returns

CS

high before the next conversion (effectively idling

CS

low).

Once a data transfer is complete (SDATA has returned to three­s

tate), another conversion can be initiated after the quiet time,

, has elapsed by bringing CS low again.

t

QUIET

Partial Power-Down Mode

This mode is intended for use in applications where slower
throughput rates are required. An example of this is when either
the ADC is powered down between each conversion or a series
of conversions is performed at a high throughput rate and then
the ADC is powered down for a relatively long duration between
these bursts of several conversions. When the AD7276/AD7277/
AD7278 are in partial power-down mode, all analog circuitry is
powered down except the bias-generation circuit.

To enter partial power-down mode, interrupt the conversion

cess by bringing

pro

high between the second and 10th falling

CS

edges of SCLK, as shown in Figure 25.

The conversion is initiated on the falling edge of

as described

CS

in the Serial Interface section. To ensure that the part remains
full

y powered up at all times,
10 SCLK falling edges elapse after the falling edge of
brought high after the 10

must remain low until at least

CS

. If CS is

th

SCLK falling edge but before the 16th

CS

SCLK falling edge, the part remains powered up, but the con­version is terminated and SDATA goes back into three-state.

For the AD7276, a minimum of 14 serial clock cycles are required
to

complete the conversion and access the complete conversion
result. For the AD7277 and AD7278, a minimum of 12 and
10 serial clock cycles are required to complete the conversion
and to access the complete conversion result, respectively.

CS

110121416

SCLK

SDATA VAL ID DATA

Figure 24. Normal Mode Operation

Once

is brought high in this window of SCLKs, the part

CS

enters partial power-down mode, the conversion that was
initiated by the falling edge of

goes back into three-state. If

is terminated, and SDATA

CS

is brought high before the

CS

second SCLK falling edge, the part remains in normal mode and
does not power down. This prevents accidental power-down due
to glitches on the

CS

line.

D7276

AD7677/AD7278

04903-024

CS

12 10 16

SCLK

SDATA

Figure 25. Entering Partial Power-Down Mode

Rev. A | Page 18 of 28

THREE-STATE

04903-025

AD7276/AD7277/AD7278

www.BDTIC.com/ADI

To exit this mode of operation and power up the AD7276/
AD7277/AD7278, users should perform a dummy conversion.
On the falling edge of
continues to power up as long as
falling edge of the 10
once 16 SCLKs elapse; valid data results from the next conversion,
as shown in
edge of SCLK, the AD7276/AD7277/AD7278 go into full power­down mode. Therefore, although the device can begin to power
up on the falling edge of

CS

of

If the AD7276/AD7277/AD7278 are already in partial power­do

wn mode and

of SCLK, the device enters full power-down mode. For more
information on the power-up times associated with partial
power-down mode in various configurations, see the Power-Up

mes

Ti

Figure 26. If

as long as this occurs before the 10th SCLK falling edge.

CS

section.

, the device begins to power up and

CS

is held low until after the

th

SCLK. The device is fully powered up

CS

CS

is brought high before the 10th falling edge

CS

is brought high before the 10th falling

, it powers down on the rising edge

Full Power-Down Mode

This mode is intended for use in applications where throughput
rates slower than those in the partial power-down mode are
required, because power-up from a full power-down takes
substantially longer than that from a partial power-down. This
mode is suited to applications where a series of conversions
performed at a relatively high throughput rate are followed by a
long period of inactivity and thus power down.

When the AD7276/AD7277/AD7278 are in full power-down

de, all analog circuitry is powered down. To enter full power-

mo
down mode, put the device into partial power-down mode by
bringing

SCLK. In the next conversion cycle, interrupt the conversion
process in the same way as shown in Figure 27 by bringing

high before the 10

in this window of SCLKs, the part powers down completely.
Note that it is not necessary to complete the 16 SCLKs once

brought high to enter either of the power-down modes. Glitch
protection is not available when entering full power-down mode.

To exit full power-down mode and power up AD7276/
AD7277/AD72
similar to when powering up from partial power-down mode.
On the falling edge of

continues to power up as long as
falling edge of the 10

elapse before a conversion can be initiated, as shown in Figure

28. See the Power-Up Times section for the power-up times
sociated with the AD7276/AD7277/AD7278.

as

high between the second and 10th falling edges of

CS

th

SCLK falling edge. Once CS is brought high

78, users should perform a dummy conversion,

, the device begins to power up and

CS

is held low until after the

th

SCLK. The required power-up time must

CS

CS

CS

is

Power-Up Times

The AD7276/AD7277/AD7278 have two power-down modes,
partial power-down and full power-down, which are described
in detail in the Modes of Operation section. This section deals

th the power-up time required when coming out of either of

wi
these modes.

To power up from partial power-down mode, one cycle is
re

quired. Therefore, with an SCLK frequency of up to 48 MHz,
one dummy cycle is sufficient to allow the device to power up
from partial power-down mode. Once the dummy cycle is
complete, the ADC is fully powered up and the input signal is
acquired properly. The quiet time, t
from the point where the bus goes back into three-state after the
dummy conversion to the next falling edge of

To power up from full power-down, approximately 1 s should
b

e allowed from the falling edge of

.

t

POWER UP

Note that during power-up from partial power-down mode, the
t

rack-and-hold, which is in hold mode while the part is powered
down, returns to track mode after the first SCLK edge that the
part receives after the falling edge of
in Figure 26.

When power supplies are first applied to the AD7276/AD7277/
AD7278, t
modes or in normal mode. Because of this, it is best to allow a
dummy cycle to elapse to ensure that the part is fully powered
up before attempting a valid conversion. Likewise, if the part is
to be kept in partial power-down mode immediately after the
supplies are applied, then two dummy cycles must be initiated.
The first dummy cycle must hold
SCLK falling edge; in the second cycle,
between the second and 10

Alternatively, if the part is to be placed into full power-down
m

ode when the supplies are applied, three dummy cycles must

be initiated. The first dummy cycle must hold

the 10
place the part into full power-down mode (see Figure 27). See

e

th

he ADC can power up in either of the power-down

th

SCLK falling edges (see Figure 25).

th

SCLK falling edge; the second and third dummy cycles

Modes of Operation section.

, must still be allowed

QUIET

.

CS

, shown in Figure 28 as

CS

. This is shown as Point A

CS

low until after the 10th

CS

must be brought high

CS

low until after

CS

Rev. A | Page 19 of 28

AD7276/AD7277/AD7278

AR

S

S

S

www.BDTIC.com/ADI

TISFULLY

THE PART BEGINS

TO PO WER UP

CS

THE P
POWERED UP, SEE T HE POWE R­UP TIMES SECTION

SCLK

DATA

CS

SCLK

DATA

CS

SCLK

1

10 16 1 16

A

INVALID DATA VALID DATA

04903-026

Figure 26. Exiting Partial Power-Down Mode

THE PARTENTERS

PARTIAL POWER-DOWN

12 10 16 1 1610

INVALID DATA VALID DATA

THREE-STATE THREE-STATE

THE PARTBEGINS

TO PO WER UP

THE PARTENTERS

FULL POWER-DOWN

04903-027

Figure 27. Entering Full Power-Down Mode

THE PART BEGINS

TO PO WER UP

110161 1

t

POWER UP

THE PARTIS

FULLY POWERED UP

6

DATA

INVALID DATA VALID DATA

04903-028

Figure 28. Exiting Full Power-Down Mode

Rev. A | Page 20 of 28

AD7276/AD7277/AD7278

www.BDTIC.com/ADI

POWER VS. THROUGHPUT RATE

Figure 29 shows the power consumption of the device in
normal mode, in which the part is never powered down. By
using the power-down mode of the AD7276/AD7277/AD7278
when not performing a conversion, the average power consump­tion of the ADC decreases as the throughput rate decreases.
Figure 30 shows that as the throughput rate is reduced, the

vice remains in its power-down state longer and the average

de
power consumption over time drops accordingly. For example,
if the AD7276/AD7277/AD7278 are operated in continuous
sampling mode with a throughput rate of 200 kSPS and an SCLK
of 48 MHz (V
down mode between conversions, then the power consumption
is calculated as follows. The power dissipation during normal
operation is 12.6 mW (V
dummy cycle, that is, 333 ns, and the remaining conversion
time is 290 ns, then the AD7276/AD7277/AD7278 can be said
to dissipate 12.6 mW for 623 ns during each conversion cycle. If
the throughput rate is 200 kSPS, then the cycle time is 5 µs and
the average power dissipated during each cycle is 623/5,000 ×

12.6 mW = 1.56 mW.
ra

te when using the partial power-down mode between conver­sions at 3 V. The power-down mode is intended for use with
throughput rates of less than 600 kSPS, because at higher
sampling rates, there is no power saving achieved by using the
power-down mode.

= 3 V) and the devices are placed into power-

DD

= 3 V). If the power-up time is one

DD

Figure 29 shows the power vs. throughput

7.4

7.2

7.0

6.8

6.6

6.4

6.2

6.0

5.8

5.6

5.4

5.2

5.0

4.8

POWER (mW)

4.6

4.4

4.2

4.0

3.8

3.6

3.4

3.2

3.0
0

200 400 600 800 1000 1200 1400 1600 1800

THROUGHPUT (kSPS)

50MHz SCLK

Figure 29. Power vs. Throughput Normal Mode

8.0

7.5

7.0

6.5

6.0

5.5

5.0

4.5

4.0

3.5

POWER (mW)

3.0

2.5

2.0

1.5

1.0

0.5

0

0

200 400 600 800

THROUGHPUT (kSPS)

Figure 30. Power vs. Throughput Partial Powe

VARIABLE

SCLK

VDD=3V

r-Down Mode

04903-029

2000

04903-035

1000

Rev. A | Page 21 of 28

AD7276/AD7277/AD7278

www.BDTIC.com/ADI

SERIAL INTERFACE

Figure 31 through Figure 34 show the detailed timing diagrams
for serial interfacing to the AD7276, AD7277, and AD7278. The
serial clock provides the conversion clock and controls the transfer
of information from the AD7276/AD7277/AD7278 during
conversion.

The

signal initiates the data transfer and conversion process.

CS

The falling edge of

puts the track-and-hold into hold mode

CS
and takes the bus out of three-state. The analog input is sampled
and the conversion is initiated at this point.

For the AD7276, the conversion requires completing 14 SCLK

ycles. Once 13 SCLK falling edges have elapsed, the track-and-

c
hold goes back into track mode on the next SCLK rising edge,
as shown in Figure 31 at Point B. If the rising edge of

occurs

CS
before 14 SCLKs have elapsed, the conversion is terminated and
the SDATA line goes back into three-state. If 16 SCLKs are
considered in the cycle, the last two bits are zeros and SDATA

th

returns to three-state on the 16

SCLK falling edge, as shown in

Figure 32.

For the AD7277, the conversion requires completing 12 SCLK
c

ycles. Once 11 SCLK falling edges elapse, the track-and-hold
goes back into track mode on the next SCLK rising edge, as
shown in

Figure 33 at Point B. If the rising edge of

CS

occurs

before 12 SCLKs elapse, the conversion is terminated and the
SDATA line goes back into three-state. If 16 SCLKs are considered
in the cycle, the AD7277 clocks out four trailing zeros for the
last four bits and SDATA returns to three-state on the 16
falling edge, as shown in

Figure 33.

th

SCLK

For the AD7278, the conversion requires completing 10 SCLK
c

ycles. Once 9 SCLK falling edges elapse, the track-and-hold
goes back into track mode on the next rising edge. If the rising
edge of

occurs before 10 SCLKs elapse, the part enters power-

CS

down mode.

CS

SCLK

SDATA

THREE-

STATE

t

2

1513

t

3

ZZERO

2 LEADING

ZEROS

234

DB11 DB10 DB9 DB1 DB0

Figure 31. AD7276 Serial Interface Timing Diagram 14 SCLK Cycle

t

CONVERT

t

6

t

4

If 16 SCLKs are considered in the cycle, then the AD7278 clocks
o

ut six trailing zeros for the last six bits and SDATA returns to

three-state on the 16

th

SCLK falling edge, as shown in Figure 34.

If the user considers a 14 SCLK cycle serial interface for the
AD7276/AD72

th

the 14

SCLK falling edge. Then the last two trailing zeros are

77/AD7278, then

must be brought high after

CS

ignored, and SDATA goes back into three-state. In this case, the
3 MSPS throughput can be achieved by using a 48 MHz clock
frequency.

going low clocks out the first leading zero to be read by the

CS
microcontroller or DSP. The remaining data is then clocked out
by subsequent SCLK falling edges, beginning with the second
leading zero. Therefore, the first falling clock edge on the serial
clock provides the first leading zero and clocks out the second
leading zero. The final bit in the data transfer is valid on the 16
falling edge, because it is clocked out on the previous (15

falling edge.

In applications with a slower SCLK, it is possible to read data on

h SCLK rising edge. In such cases, the first falling edge of SCLK

eac
clocks out the second leading zero and can be read on the first
rising edge. However, the first leading zero clocked out when

goes low is missed if read within the first falling edge. The

CS

th

15

falling edge of SCLK clocks out the last bit and can be read

th

on the 15

If

CS

rising SCLK edge.

goes low just after one SCLK falling edge elapses, then CS

clocks out the first leading zero and can be read on the SCLK
rising edge. The next SCLK falling edge clocks out the second
leading zero and can be read on the following rising edge.

t

1

B

14

t

7

t

5

1/THROUGHPUT

t

9

t

QUIET

THREE-STATE

04903-099

th

th

)

Rev. A | Page 22 of 28

AD7276/AD7277/AD7278

S

S

S

www.BDTIC.com/ADI

t

1

CS

t

CONVERT

SCLK

DATA

CS

SCLK

DATA

THREE­STATE

THREE­STATE

t

2

1 2 3 4 5 13 15 1614

t

3

DB11 DB10 DB9 DB1 DB0 ZERO ZEROZEROZ

2 LEADING
ZEROS

Figure 32. AD7276 Serial Interface Timing Diagram 16 SCLK Cycle

t

2

1 2 3 4 10 11 12 14 161513

t

2 LEADING
ZEROS

t

3

4

DB9 DB8 DB0DB1 ZERO ZERO ZERO ZEROZEROZ

t

6

t

4

1/THROUGHPUT

B

t

t

7

5

2 TRAILI NG
ZEROS

t

CONVERT

t

5

B

1/THROUGHPUT

t

6

t

7

4 TRAILI NG ZERO S

Figure 33. AD7277 Serial Interface Timing Diagram

t

8

THREE-STATE

t

THREE-STATE

t

QUIET

8

t

QUIET

04903-030

t

1

4903-031

CS

SCLK

DATA

CS

SCLK

SDATA

THREE­STATE

THREE­STATE

t

t

2

1 2 3 4 8910 14 161511

t

3

2 LEADING
ZEROS

t

4

DB7 DB6 DB0DB1 ZERO ZERO ZEROZEROZ

CONVERT

t

5

t

6

B

1/THROUGHPUT

Figure 34. AD7278 Serial Interface Timing Diagram

t

CONVERT

t

2

1 2 3 4 9 105

DB7 DB6 DB5 DB1 DB0ZEROZ

2 LEADING ZEROS

8.5 (1/f

t

6

)

SCLK

1/THROUGHPUT

Figure 35. AD7278 in a 10 SCLK Cycle Serial Interface

t

7

6 TRAILI NG ZERO S

B

THREE-STATE

t

1

t

8

t

QUIET

THREE-STATE

04903-032

t

1

t

8

t

QUIET

t

ACQ

04903-033

Rev. A | Page 23 of 28

AD7276/AD7277/AD7278

www.BDTIC.com/ADI

AD7278 IN A 10 SCLK CYCLE SERIAL INTERFACE

For the AD7278, if CS is brought high during the 10th rising

edge after the two leading zeros and eight bits of the conversion
are provided, then the part can achieve a 4 MSPS throughput
rate. For the AD7278, the track-and-hold goes back into track
mode on the ninth rising edge. In this case, a f
and throughput of 4 MSPS result in a cycle time of t

) + t

8.5(1/f

SCLK

= 250 ns, where t2 = 6 ns minimum and t

ACQ

67 ns. This satisfies the requirement of 60 ns for t
shows that t

comprises 0.5(1/f

ACQ

ns max. This allows a value of 43 ns for t

SCLK

) + t8 + t

QUIET

= 48 MHz

SCLK

+

2

. Figure 35

ACQ

, where t8 = 14

QUIET

, satisfying the

ACQ

=

minimum requirement of 4 ns.

MICROPROCESSOR INTERFACING

AD7276/AD7277/AD7278-to-ADSP-BF53x

The ADSP-BF53x family of DSPs interfaces directly to the
AD7276/AD7277/AD7278 without requiring glue logic. The
SPORT0 Receive Configuration 1 Register should be set up as
outlined in

Tabl e 9 .

Table 9. The SPORT0 Receive Configuration 1 Register
(SPORT0_RCR1)

Setting Description

RCKFE = 1 Sample data with falling edge of RSCLK
LRFS = 1 Active low frame signal
RFSR = 1 Frame every word
IRFS = 1 Internal RFS used
RLSBIT = 0 Receive MSB first
RDTYPE = 00 Zero fill
IRCLK = 1 Internal receive clock
RSPEN = 1 Receive enabled
SLEN = 1111

16-bit data-word (or can be set to 1101 for
14-bit da

ta-word)

TFSR = RFSR = 1

To implement the power-down modes, SLEN should be set to
1001 to issue an 8-bit SCLK burst.

AD7276/
AD7277/

AD7278*

SCLK RCLK0

DOUT

CS

DIN

*ADDITIONAL PINS OMIT TED FOR CL ARITY

Figure 36. Interfacing with ADSP-BF53x

ADSP-BF53x*

SPORT0

DR0PRI

RFS0

DT0

4903-098

Rev. A | Page 24 of 28

AD7276/AD7277/AD7278

www.BDTIC.com/ADI

APPLICATION HINTS

GROUNDING AND LAYOUT

The printed circuit board that houses the AD7276/AD7277/
AD7278 should be designed so that the analog and digital
sections are separated and confined to certain areas of the
board. This design facilitates using ground planes that can easily
be separated.

To provide optimum shielding for ground planes, a minimum
et

ch technique is generally best. All AGND pins of the AD7276/
AD7277/AD7278 should be sunk into the AGND plane. Digital
and analog ground planes should be joined in one place only. If
the AD7276/AD7277/AD7278 are in a system where multiple
devices require an AGND-to-DGND connection, the connection
should still be made at only one point, a star ground point
established as close as possible to the ground pin on the
AD7276/AD7277/AD7278.

Avoid running digital lines under the device because this

uples noise onto the die. However, the analog ground plane

co
should be allowed to run under the AD7276/AD7277/AD7278
to avoid noise coupling. The power supply lines to the AD7276/
AD7277/AD7278 should use as large a trace as possible to provide
low impedance paths and reduce the effects of glitches on the
power supply line.

To avoid radiating noise to other sections of the board,
co

mponents with fast-switching signals, such as clocks, should
be shielded with digital ground, and they should never be run
near the analog inputs. Avoid crossover of digital and analog
signals. To reduce the effects of feedthrough within the board,
traces on opposite sides of the board should run at right angles
to each other. A microstrip technique is by far the best method,
but it is not always possible to use this approach with a double­sided board. In this technique, the component side of the board
is dedicated to ground planes, and signals are placed on the
solder side.

Good decoupling is also important. All analog supplies should

decoupled with 10 µF ceramic capacitors in parallel with

be

0.1 µF capacitors to GND. To achieve the best results from these
decoupling components, they must be placed as close as possible
to the device, ideally right up against the device. The 0.1 µF
capacitors should have low effective series resistance (ESR) and
low effective series inductance (ESI), such as is typical of common
ceramic or surface-mount types of capacitors. Capacitors with
low ESR and low ESI provide a low impedance path to ground
at high frequencies, which allow them to handle transient
currents due to internal logic switching.

EVALUATING PERFORMANCE

The recommended layout for the AD7276/AD7277/AD7278 is
outlined in the evaluation board documentation. The evaluation
board package includes a fully assembled and tested evaluation
board, documentation, and software for controlling the board
from the PC via the evaluation board controller. To
demonstrate/evaluate the ac and dc performance of the
AD7276/AD7277, the evaluation board controller can be used
in conjunction with the AD7276/AD7277 evaluation board, as
well as with many other Analog Devices evaluation boards
ending in the CB designator,

The software allows the user to perform ac (fast Fourier

nsform) and dc (histogram of codes) tests on the AD7276/

tra
AD7277. The software and documentation are on a CD shipped
with the evaluation board.

Rev. A | Page 25 of 28

AD7276/AD7277/AD7278

R

www.BDTIC.com/ADI

OUTLINE DIMENSIONS

2.90 BSC

1.90
BSC

0.50

0.30

45

2.80 BSC

2

0.95 BSC

0.95

*

1.00 MAX

SEATING
PLANE

0.20

0.08
8°

0.60

4°

0.45

0°

0.30

0.85

0.75

0.15

0.00

COPLANARITY

1.60 BSC

PIN 1

INDICATO

*

0.90

0.87

0.84

0.10 MAX

6

13

*

COMPLIANT TO JEDEC STANDARDS MO-193-AA WITH

THE EXCEPTION OF PACKAGE HEIGHT AND THICKNESS.

Figure 37. 6-Lead Thin Small Outline Transistor Package [TSOT ]

(UJ-6)

Di

mensions shown in millimeters

ORDERING GUIDE

Model

AD7276BRM −40°C to +125°C ±1 max 8-Lead Mini Small Outline Package (MSOP) RM-8 C1W
AD7276BRMZ −40°C to +125°C ±1 max 8-Lead Mini Small Outline Package (MSOP) RM-8 C30

2

AD7276BRMZ-REEL −40°C to +125°C ±1 max 8-Lead Mini Small Outline Package (MSOP) RM-8 C30
AD7276BUJ-500RL7 −40°C to +125°C ±1 max 6-Lead Thin Small Outline Transistor Package (TSOT) UJ-6 C1W
AD7276BUJZ-500RL7 −40°C to +125°C ±1 max 6-Lead Thin Small Outline Transistor Package (TSOT) UJ-6
AD7276BUJZ-REEL7 −40°C to +125°C ±1 max 6-Lead Thin Small Outline Transistor Package (TSOT) UJ-6 C30
AD7276YUJZ-500RL72, −40°C to +125°C ±1 max 6-Lead Thin Small Outline Transistor Package (TSOT) UJ-6 C4W
AD7276YUJZ-REEL2, −40°C to +125°C ±1 max 6-Lead Thin Small Outline Transistor Package (TSOT) UJ-6 C4W
AD7277BRMZ −40°C to +125°C ±0.5 max 8-Lead Mini Small Outline Package (MSOP) RM-8 C31

2

AD7277BRMZ-REEL −40°C to +125°C ±0.5 max 8-Lead Mini Small Outline Package (MSOP) RM-8 C31
AD7277BUJZ-500RL7 −40°C to +125°C ±0.5 max 6-Lead Thin Small Outline Transistor Package (TSOT) UJ-6 C31
AD7277BUJZ-REEL7 −40°C to +125°C ±0.5 max 6-Lead Thin Small Outline Transistor Package (TSOT) UJ-6 C31
AD7278BRMZ −40°C to +125°C ±0.3 max 8-Lead Mini Small Outline Package (MSOP) RM-8 C32

2

AD7278BRMZ-REEL −40°C to +125°C ±0.3 max 8-Lead Mini Small Outline Package (MSOP) RM-8 C32
AD7278BUJZ-500RL7 −40°C to +125°C ±0.3 max 6-Lead Thin Small Outline Transistor Package (TSOT) UJ-6 C32
AD7278BUJZ-REEL7 −40°C to +125°C ±0.3 max 6-Lead Thin Small Outline Transistor Package (TSOT) UJ-6 C32
EVAL-AD7276CB Evaluation Board
EVAL-AD7277CB Evaluation Board

4

4

EVAL-CONTROL BRD2 Control Board

1

Linearity error refers to integral nonlinearity.

2

Z = Pb-free part.

3

Y Grade part, F

4

This can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL board for evaluation/demonstration purposes.

5

This board is a complete unit allowing a PC to control and communicate with all Analog Devices evaluation boards that end in a CB designator. To order a complete

SAMPLE

= 1 MSPS.

evaluation kit, the particular ADC evaluation board (such as, EVAL-AD7276/AD7277CB), the EVAL-CONTROL BRD2, and a 12 V transformer must be ordered. See the
relevant evaluation board technical note for more information.

2

2

2

3

3

2

2

2

2

2

2

5

Temperature
Range

Linearity
Error

1

(LSB)

Package Description

3.20

3.00

2.80

8

5

4

SEATING
PLANE

5.15

4.90

4.65

1.10 MAX

0.23

0.08

8°
0°

3.20

3.00

1

2.80

PIN 1

0.65 BSC

0.38

0.22

0.10

COMPLIANT TO JEDEC STANDARDS MO-187-AA

Figure 38. 8-Lead Mini Small Outline Package [MSOP]

(RM-8)

mensions shown in millimeters

Di

Package
Option

0.80

0.60

0.40

Branding

C30

Rev. A | Page 26 of 28

AD7276/AD7277/AD7278

www.BDTIC.com/ADI

NOTES

Rev. A | Page 27 of 28

AD7276/AD7277/AD7278

www.BDTIC.com/ADI

NOTES

© 2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04903-0-10/05(A)

Rev. A | Page 28 of 28