Datasheet AD7266 Datasheet (ANALOG DEVICES)

Differential/Single-Ended Input, Dual

FEATURES

Dual 12-bit, 3-channel ADC
Throughput rate: 2 MSPS
Specified for V
Power consumption

9 mW at 1.5 MSPS with 3 V supplies
27 mW at 2 MSPS with 5 V supplies

Pin-configurable analog inputs

12-channel single-ended inputs
6-channel fully differential inputs

6-channel pseudo differential inputs
70 dB SNR at 50 kHz input frequency
Accurate on-chip reference: 2.5 V

±0.2% maximum @ 25°C, 20 ppm/°C maximum
Dual conversion with read 437.5 ns, 32 MHz SCLK
High speed serial interface

SPI®-/QSPI™-/MICROWIRE™-/DSP-compatible

−40°C to +125°C operation
Shutdown mode: 1 μA maximum
32-lead LFCSP and 32-lead TQFP
1 MSPS version,

GENERAL DESCRIPTION

The AD72661 is a dual, 12-bit, high speed, low power, successive
approximation ADC that operates from a single 2.7 V to 5.25 V
power supply and features throughput rates up to 2 MSPS. The
device contains two ADCs, each preceded by a 3-channel
multiplexer, and a low noise, wide bandwidth track-and-hold
amplifier that can handle input frequencies in excess of 30 MHz.

The conversion process and data acquisition use standard
control inputs allowing easy interfacing to microprocessors or
DSPs. The input signal is sampled on the falling edge of
conversion is also initiated at this point. The conversion time is
determined by the SCLK frequency. There are no pipelined
delays associated with the part.

The AD7266 uses advanced design techniques to achieve very
low power dissipation at high throughput rates. With 5 V
supplies and a 2 MSPS throughput rate, the part consumes

6.2 mA maximum. The part also offers flexible power/
throughput rate management when operating in normal mode
as the quiescent current consumption is so low.

The analog input range for the part can be selected to be a 0 V
to V

(or 2 × V

REF

complement output coding. The AD7266 has an on-chip 2.5 V
reference that can be overdriven when an external reference is
preferred. This external reference range is 100 mV to V

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

of 2.7 V to 5.25 V

DD

AD7265

) range, with either straight binary or twos

REF

DD

CS

;

.

2 MSPS, 12-Bit, 3-Channel SAR ADC

AD7266

FUNCTIONAL BLOCK DIAGRAM

REF SELECT D

BUF

REF

V

A1

V

A2

V

A3

MUX

V

A4

V

A5

V

A6

V

B1

V

B2

V

B3

MUX

V

B4

V

B5

V

B6

AGND AGND AGND D

T/H

T/H

BUF

The AD7266 is available in a 32-lead LFCSP and a
32-lead TQFP.

PRODUCT HIGHLIGHTS

1. Two Complete ADC Functions Allow Simultaneous

Sampling and Conversion of Two Channels.
Each ADC has three fully/pseudo differential pairs, or six
single-ended channels, as programmed. The conversion
result of both channels is simultaneously available on
separate data lines, or in succession on one data line if only
one serial port is available.

2. High Throughput with Low Power Consumption.

The AD7266 offers a 1.5 MSPS throughput rate with 11.4 mW
maximum power dissipation when operating at 3 V.

3. The AD7266 offers both a standard 0 V to V

and a 2 × V

4. No Pipeline Delay.

The part features two standard successive approximation
ADCs with accurate control of the sampling instant via a
CS

input and once off conversion control.

1

Protected by U.S. Patent No. 6,681,332

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2005–2011 Analog Devices, Inc. All rights reserved.

input range.

REF

A AV

CAP

DD

AD7266

12-BIT

SUCCESSIVE

APPROXIMATION

ADC

CONTROL

LOGIC

12-BIT

SUCCESSIVE

APPROXIMATION

ADC

B DGND DGND

CAP

Figure 1.

DV

DD

OUTPUT

DRIVERS

OUTPUT

DRIVERS

D

A

OUT

SCLK

CS
RANGE
SGL/DIFF
A0
A1
A2

V

DRIVE

D

B

OUT

input range

REF

04603-001

AD7266

TABLE OF CONTENTS

Features.............................................................................................. 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Timing Specifications .................................................................. 5

Absolute Maximum Ratings............................................................ 6

ESD Caution.................................................................................. 6

Pin Configuration and Function Descriptions............................. 7

Typical Performance Characteristics ............................................. 9

Terminology .................................................................................... 11

Theory of Operation ...................................................................... 13

Circuit Information.................................................................... 13

Converter Operation.................................................................. 13

Analog Input Structure.............................................................. 13

Analog Inputs.............................................................................. 14

Analog Input Selection .............................................................. 17

Output Coding............................................................................ 17

Transfer Functions...................................................................... 18

Digital Inputs ..............................................................................18

V

............................................................................................ 18

DRIVE

Modes of Operation ....................................................................... 19

Normal Mode.............................................................................. 19

Partial Power-Down Mode ....................................................... 19

Full Power-Down Mode............................................................ 20

Power-Up Times......................................................................... 21

Power vs. Throughput Rate....................................................... 21

Serial Interface ................................................................................ 22

Microprocessor Interfacing........................................................... 23

AD7266 to ADSP218x............................................................... 23

AD7266 to ADSP-BF53x........................................................... 24

AD7266 to TMS320C541.......................................................... 24

AD7266 to DSP563xx................................................................ 25

Application Hints ........................................................................... 26

Grounding and Layout.............................................................. 26

PCB Design Guidelines for LFCSP.......................................... 26

Evaluating the AD7266 Performance...................................... 26

Outline Dimensions....................................................................... 27

Ordering Guide .......................................................................... 27

REVISION HISTORY

5/11—Rev. A to Rev. B

Changes to Mnemonic Order for Pin 13 to Pin 18, Pin 23 to Pin

25, and Pin 28, Pin 30 in Table 4 .................................................... 7

Added EPAD Note............................................................................ 7

Updated Outline Dimensions....................................................... 27

Changes to Ordering Guide.......................................................... 27

11/06—Rev. 0 to Rev. A

Changes to Format ............................................................. Universal

Changes to Reference Input/Output Section ................................ 4

Changes to Table 4............................................................................ 7

Changes to Terminology Section.................................................. 11

Changes to Figure 24 and Differential Mode Section................ 15

Changes to Figure 29...................................................................... 16

Changes to Figure 39...................................................................... 21

Changes to AD7265 to ADSP-BF53x Section............................. 24

Updated Outline Dimensions....................................................... 27

Changes to Ordering Guide.......................................................... 27

4/05—Revision 0: Initial Version

Rev. B | Page 2 of 28

AD7266

SPECIFICATIONS

TA = T
f

SCLK

unless otherwise noted

Table 1.

Parameter Specification Unit Test Conditions/Comments

DYNAMIC PERFORMANCE

SAMPLE AND HOLD

3.5/3 MHz typ @ 0.1 dB, VDD = 5 V/VDD = 3 V
DC ACCURACY

±1.5 LSB max

ANALOG INPUT5

to T

MIN

= 32 MHz, fS = 2 MSPS, V

Signal-to-Noise Ratio (SNR)
69 dB min

, VDD = 2.7 V to 3.6 V, f

MAX

DRIVE

1

.

2

= 24 MHz, fS = 1.5 MSPS, V

SCLK

= 2.7 V to 3.6 V; VDD = 4.75 V to 5.25 V,

DRIVE

= 2.7 V to 5.25 V; specifications apply using internal reference or external reference = 2.5 V ± 1%,

71 dB min fIN = 50 kHz sine wave; differential mode

= 50 kHz sine wave; single-ended and

f

IN

pseudo differential modes
Signal-to-Noise + Distortion Ratio (SINAD)
68 dB min

2

70 dB min fIN = 50 kHz sine wave; differential mode

= 50 kHz sine wave; single-ended and

f

IN

pseudo differential modes
Total Harmonic Distortion (THD)
–73 dB max

2

–77 dB max fIN = 50 kHz sine wave; differential mode

= 50 kHz sine wave; single-ended and

f

IN

pseudo differential modes
Spurious-Free Dynamic Range (SFDR)
Intermodulation Distortion (IMD)

2

2

–75 dB max fIN = 50 kHz sine wave

fa = 30 kHz, fb = 50 kHz
Second-Order Terms –88 dB typ
Third-Order Terms

Channel-to-Channel Isolation

–88 dB typ

–88 dB typ

Aperture Delay3 11 ns max
Aperture Jitter3 50 ps typ
Aperture Delay Matching3 200 ps max
Full Power Bandwidth 33/26 MHz typ @ 3 dB, VDD = 5 V/VDD = 3 V

Resolution 12 Bits
Integral Nonlinearity

2

±1 LSB max ±0.5 LSB typ; differential mode

±0.5 LSB typ; single-ended and pseudo
differential modes

Differential Nonlinearity

2, 4

±0.99 LSB max Differential mode

−0.99/+1.5 LSB max Single-ended and pseudo differential modes
Straight Binary Output Coding

Offset Error ±7 LSB max ±2 LSB typ
Offset Error Match ±2 LSB typ
Gain Error ±2.5 LSB max
Gain Error Match ±0.5 LSB typ

Twos Complement Output Coding

Positive Gain Error ±2 LSB max
Positive Gain Error Match ±0.5 LSB typ
Zero Code Error ±5 LSB max
Zero Code Error Match ±1 LSB typ
Negative Gain Error ±2 LSB max
Negative Gain Error Match ±0.5 LSB typ

Single-Ended Input Range 0 V to V
0 V to 2 × V
Pseudo Differential Input Range: V

IN+

− V

6

0 to V

IN−

2 × V

Fully Differential Input Range: V

IN+

V

and V

and V

IN+

VCM ± V

IN−

VCM ± V

IN−

V RANGE pin low

REF

RANGE pin high

REF

V RANGE pin low

REF

V RANGE pin high

REF

/2 V VCM = common-mode voltage7 = V

REF

V VCM = V

REF

REF

REF

/2

Rev. B | Page 3 of 28

AD7266

Parameter Specification Unit Test Conditions/Comments

DC Leakage Current ±1 μA max

Input Capacitance 45 pF typ When in track
10 pF typ When in hold
REFERENCE INPUT/OUTPUT

Reference Output Voltage

Long-Term Stability 150 ppm typ For 1000 hours

Output Voltage Hysteresis2 50 ppm typ

Reference Input Voltage Range 0.1/VDD V min/V max See Typical Performance Characteristics section

DC Leakage Current ±2 μA max External reference applied to Pin D

Input Capacitance 25 pF typ

D

A, D

CAP

B Output Impedance

CAP

Reference Temperature Coefficient 20 ppm/°C max

10 ppm/°C typ

V

Noise 20 μV rms typ

REF

LOGIC INPUTS

Input High Voltage, V

Input Low Voltage, V

Input Current, IIN ±15 nA typ VIN = 0 V or V

Input Capacitance, C
LOGIC OUTPUTS

Output High Voltage, VOH V

Output Low Voltage, VOL 0.4 V max

Floating State Leakage Current ±1 μA max

Floating State Output Capacitance

Output Coding
Twos complement

CONVERSION RATE

Conversion Time 14 SCLK cycles 437.5 ns with SCLK = 32 MHz

Track-and-Hold Acquisition Time

110 ns max Full-scale step input; VDD = 3 V

Throughput Rate 2 MSPS max
POWER REQUIREMENTS

V

DD

V

2.7/5.25 V min/V max

DRIVE

I

DD

Normal Mode (Static) 2.3 mA max VDD = 5.25 V
Operational, fS = 2 MSPS 6.4 mA max VDD = 5.25 V; 5.7 mA typ

fS = 1.5 MSPS 4 mA max VDD = 3.6 V; 3.4 mA typ
Partial Power-Down Mode 500 μA max Static
Full Power-Down Mode (VDD) 1 μA max TA = −40°C to +85°C

2.8 μA max TA > 85°C to 125°C

Power Dissipation

Normal Mode (Operational) 33.6 mW max VDD = 5.25 V
Partial Power-Down (Static) 2.625 mW max VDD = 5.25 V
Full Power-Down (Static) 5.25 μW max VDD = 5.25 V, TA = −40°C to +85°C

1

Temperature range is −40°C to +125°C.

2

See Terminology section.

3

Sample tested during initial release to ensure compliance.

4

Guaranteed no missed codes to 12 bits.

5

V

or V

must remain within GND/VDD.

IN−

IN+

6

V

= 0 V for specified performance. For full input range on V

IN−

7

For full common-mode range, see Figure 24 and Figure 25.

8

Relates to Pin D

A or Pin D

CAP

8

2.8 V min

INH

0.4 V max

INL

3

IN

3

3

2.5 V min/V max ±0.2% max @ 25°C

10 Ω typ

DRIVE

5 pF typ

− 0.2 V min

DRIVE

7 pF typ

Straight (natural) binary

SGL/DIFF
SGL/DIFF

= 1 with 0 V to V

= 0; SGL/DIFF = 1 with 0 V to 2 × V

90 ns max Full-scale step input; VDD = 5 V

2.7/5.25 V min/V max

Digital I/Ps = 0 V or V

B.

CAP

pin, see Figure 28 and Figure 29.

IN−

A/Pin D

CAP

CAP

B

range selected

REF

range

REF

DRIVE

Rev. B | Page 4 of 28

AD7266

TIMING SPECIFICATIONS

AVDD = DVDD = 2.7 V to 5.25 V, V

Table 2.

Parameter Limit at T

2

f

SCLK

t

CONVER T

t

30 ns min

QUIET

t

2

t

3

3

t

4

1 MHz min TA = −40°C to +85°C
4 MHz min TA > 85°C to 125°C
32 MHz max
14 × t

437.5 ns max f

583.3 ns max f

15/20 ns min
20/30 ns min
15 ns max
36 ns max Data access time after SCLK falling edge, VDD = 3 V

27 ns max Data access time after SCLK falling edge, VDD = 5 V
t5 0.45 t
t6 0.45 t
t

7

t

8

10 ns min SCLK to data valid hold time, VDD = 3 V

5 ns min SCLK to data valid hold time, VDD = 5 V

15 ns max

, T

MIN

ns max t

SCLK

SCLK

ns min SCLK high pulse width

SCLK

t9 30 ns min
t

10

1

Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.

All timing specifications given are with a 25 pF load capacitance. With a load capacitance greater than this value, a digital buffer or latch must be used. See Serial
Interface section and Figure 41 and Figure 42.

2

Minimum SCLK for specified performance; with slower SCLK frequencies, performance specifications apply typically.

3

The time required for the output to cross 0.4 V or 2.4 V.

5 ns min SCLK falling edge to D

35 ns max SCLK falling edge to D

= 2.7 V to 5.25 V, internal/external reference = 2.5 V, TA = T

DRIVE

MAX

Unit Description

= 1/f

SCLK

= 32 MHz, VDD = 5 V, f

SCLK

= 24 MHz, VDD = 3 V, f

SCLK

SCLK

Minimum time between end of serial read and next falling edge of

= 5 V/3 V, CS to SCLK setup time, TA = −40°C to +85°C

V

DD

= 5 V /3 V, CS to SCLK setup time, TA > 85°C to 125°C

V

DD

CS

Delay from

until D

ns min SCLK low pulse width

CS

rising edge to D

CS

rising edge to falling edge pulse width

OUT

= 2 MSPS

SAMPLE

= 1.5 MSPS

SAMPLE

A and D

OUT

A, D

B, high impedance

OUT

A, D

OUT

OUT

A, D

OUT

OUT

to T

MAX

B are three-state disabled

OUT

, unless otherwise noted1.

MIN

B, high impedance
B, high impedance

CS

Rev. B | Page 5 of 28

AD7266

ABSOLUTE MAXIMUM RATINGS

Table 3.

Parameter Rating

VDD to AGND −0.3 V to +7 V
DVDD to DGND −0.3 V to +7 V
V

to DGND −0.3 V to DVDD

DRIVE

V

to AGND −0.3 V to AVDD

DRIVE

AVDD to DVDD −0.3 V to +0.3 V
AGND to DGND −0.3 V to +0.3 V
Analog Input Voltage to AGND −0.3 V to AVDD + 0.3 V
Digital Input Voltage to DGND −0.3 V to +7 V
Digital Output Voltage to GND −0.3 V to V
V

to AGND −0.3 V to AVDD + 0.3 V

REF

Input Current to Any Pin
Except Supplies

1

±10 mA

DRIVE

+ 0.3 V

Operating Temperature Range −40°C to +125°C
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
LFCSP/TQFP

θJA Thermal Impedance 108.2°C/W (LFCSP)
55°C/W (TQFP)
θJC Thermal Impedance 32.71°C/W (LFCSP)

Lead Temperature, Soldering

Reflow Temperature (10 to 30 sec) 255°C

ESD 1.5 kV

1

Transient currents of up to 100 mA will not cause latch up.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

Rev. B | Page 6 of 28

AD7266

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

B

A

DD

OUT

OUT

DRIVE

DV

32

1

DGND

AV

D

CAP

AGND
AGND

V
V

2
3

DD

4

A

5
6

(Not to Scale)

7

A1

8

A2

9

A3

REF SELECT

NOTES

1. THE EXPOSED M ETAL PADDLE ON THE BOTTO M OF THE LFCSP
PACKAGE SHOULD BE SOLDERED TO PCB GROUND.

SCLK

D

DGND

D

V

31302928272625

PIN 1
INDICATOR

AD7266

TOP VIEW

101112

13

141516

VB5VB4V

VB6VA6VA5VA4V

Figure 2. Pin Configuration (CP-32-2)

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description

1, 29 DGND

Digital Ground. This is the ground reference point for all digital circuitry on the AD7266. Both DGND pins should
connect to the DGND plane of a system. The DGND and AGND voltages should ideally be at the same potential
and must not be more than 0.3 V apart, even on a transient basis.

2 REF SELECT

Internal/External Reference Selection. Logic input. If this pin is tied to DGND, the on-chip 2.5 V reference is used as
the reference source for both ADC A and ADC B. In addition, Pin D
capacitors. If the REF SELECT pin is tied to a logic high, an external reference can be supplied to the AD7266
through the D

3 AV

DD

Analog Supply Voltage, 2.7 V to 5.25 V. This is the only supply voltage for all analog circuitry on the AD7266. The

and DVDD voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a

AV

DD

transient basis. This supply should be decoupled to AGND.

4, 20

A,

D

CAP

B

D

CAP

Decoupling Capacitor Pins. Decoupling capacitors (470 nF recommended) are connected to these pins to
decouple the reference buffer for each respective ADC. Provided the output is buffered, the on-chip reference can
be taken from these pins and applied externally to the rest of a system. The range of the external reference is
dependent on the analog input range selected.

5, 6, 19 AGND

Analog Ground. Ground reference point for all analog circuitry on the AD7266. All analog input signals and any
external reference signal should be referred to this AGND voltage. All three of these AGND pins should connect to
the AGND plane of a system. The AGND and DGND voltages ideally should be at the same potential and must not
be more than 0.3 V apart, even on a transient basis.

7 to 12 V

to VA6

A1

Analog Inputs of ADC A. These may be programmed as six single-ended channels or three true differential analog
input channel pairs. See Tab le 6.

13 to 18 V

to VB1

B6

Analog Inputs of ADC B. These may be programmed as six single-ended channels or three true differential analog
input channel pairs. See Tab le 6.

21 RANGE

Analog Input Range Selection. Logic input. The polarity on this pin determines the input range of the analog input
channels. If this pin is tied to a logic low, the analog input range is 0 V to V
CS

goes low, the analog input range is 2 × V

22

SGL/DIFF

Logic Input. This pin selects whether the analog inputs are configured as differential pairs or single ended. A logic

low selects differential operation while a logic high selects single-ended operation. See the Analog Input
Selection section for details.

23 to 25 A2 to A0

Multiplexer Select. Logic inputs. These inputs are used to select the pair of channels to be simultaneously
converted, such as Channel 1 of both ADC A and ADC B, Channel 2 of both ADC A and ADC B, and so on. The pair
of channels selected may be two single-ended channels or two differential pairs. The logic states of these pins
need to be set up prior to the acquisition time and subsequent falling edge of CS
multiplexer for that conversion. See the section for further details and for
multiplexer address decoding.

26

Chip Select. Active low logic input. This input provides the dual function of initiating conversions on the AD7266

CS

and framing the serial data transfer.

27 SCLK

Serial Clock. Logic input. A serial clock input provides the SCLK for accessing the data from the AD7266. This clock
is also used as the clock source for the conversion process.

A0

CS

B3

A and/or D

CAP

24

A1

23

A2

22

SGL/DIFF

21

RANGE

20

D

19

AGND

18

V

17

V

CAP

B1
B2

1

DGND

REF SELECT

B

04603-002

B pins.

CAP

. See the section for details. Analog Input Selection

REF

2

3

AV

DD

4

D

A

CAP

5

AGND

6

AGND

7

V

A1

8

V

A2

Figure 3. Pin Configuration (SU-32-2)

A and Pin D

CAP

Analog Input Selection Tab le 6

Rev. B | Page 7 of 28

A

DD

DV

V

32

31

PIN 1

9

10

A3

V

V

REF

B

OUT

DRIVE

A4

OUT

D

DGND28D

30

29

AD7266

TOP VIEW

(Not to Scale)

11

12

A5

V

V

CAP

CS

SCLK

A0

27

26 25

24

A1

23

A2

22

SGL/DIFF

21

RANGE

20

D

CAP

19

AGND

18

V

B1

17

V

B2

13

14

15

16

A6

B6

B5

B4

V

B3

V

V

V

B must be tied to decoupling

B

. If this pin is tied to a logic high when

to correctly set up the

04603-041

AD7266

Pin No. Mnemonic Description

28, 30

31 V

D
D

OUT

OUT

DRIVE

B,
A

32 DVDD

EPAD Exposed Pad. The exposed metal paddle on the bottom of the LFCSP package should be soldered to PCB ground.

Serial Data Outputs. The data output is supplied to each pin as a serial data stream. The bits are clocked out on the
falling edge of the SCLK input and 14 SCLKs are required to access the data. The data simultaneously appears on
both pins from the simultaneous conversions of both ADCs. The data stream consists of two leading zeros
followed by the 12 bits of conversion data. The data is provided MSB first. If CS

is held low for 16 SCLK cycles rather
than 14, then two trailing zeros will appear after the 12 bits of data. If CS is held low for a further 16 SCLK cycles on
either D

conversion on both ADCs to be gathered in serial format on either D

OUT

A or D

B, the data from the other ADC follows on the D

OUT

pin. This allows data from a simultaneous

OUT

OUT

A or D

B using only one serial port. See

OUT

the section. Serial Interface
Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the interface operates. This

pin should be decoupled to DGND. The voltage at this pin may be different than that at AV

and DVDD but should

DD

never exceed either by more than 0.3 V.
Digital Supply Voltage, 2.7 V to 5.25 V. This is the supply voltage for all digital circuitry on the AD7266. The DV

and AV

voltages should ideally be at the same potential and must not be more than 0.3 V apart even on a

DD

DD

transient basis. This supply should be decoupled to DGND.

Rev. B | Page 8 of 28

AD7266

TYPICAL PERFORMANCE CHARACTERISTICS

TA = 25°C, unless otherwise noted.

–60

–70

–80

–90

PSRR (dB)

–100

INTERNAL REFERENCE

EXTERNAL REFERENCE

–10

–30

–50

(dB)

–70

4096 POINT FFT

= 5V, V

V

DD

F

SAMPLE

= 52kHz

F

IN

SINAD = 71.4dB
THD = –84.42dB
DIFFERENTIAL MODE

DRIVE

= 2MSPS

= 3V

–110

100mV p-p SINE WAVE ON AV
NO DECOUPLING
SINGLE-ENDED MODE

–120

SUPPLY RIPPLE FREQUENCY (kHz)

DD

20000 200 400 600 800 1000 1200 1400 1600 1800

Figure 4. PSRR vs. Supply Ripple Frequency Without Supply Decoupling

–50

VDD = 5V

–55

–60

–65

–70

–75

–80

ISOLATION (dB)

–85

–90

–95

–100

NOISE FREQUENCY (kHz)

10000 100 200 300 400 500 600 800700 900

Figure 5. Channel-to-Channel Isolation

74

72

70

68

66

SINAD (dB)

64

62

60

VDD = 5V
DIFFERENTIAL MODE

V

DD

DIFFERENTIAL MODE

INPUT FREQUENCY (kHz)

= 3V

RANGE = 0 TO V

REF

30000 1000 2000500 1500 2500

Figure 6. SINAD vs. Analog Input Frequency for Various Supply Voltages

04603-003

04603-004

04603-005

–110

DNL ERROR (LSB)

INL ERROR (LSB)

–90

–0.2

–0.4

–0.6

–0.8

–1.0

–0.2

–0.4

–0.6

–0.8

–1.0

1.0

0.8

0.6

0.4

0.2

1.0

0.8

0.6

0.4

0.2

FREQUENCY ( kHz)

10000 100 200 300 400 500 600 700 800 900

04603-006

Figure 7. FFT

VDD = 5V, V
DIFFERENTIAL MODE

0

CODE

DRIVE

= 3V

40000 1000 2000 3000 3500500 1500 2500

04603-007

Figure 8. Typical DNL

VDD = 5V, V
DIFFERENTIAL MODE

0

CODE

DRIVE

= 3V

40000 500 1000 1500 2000 2500 3000 3500

04603-008

Figure 9. Typical INL

Rev. B | Page 9 of 28

AD7266

1.0

0.8

0.6

0.4

0.2

0

–0.2

–0.4

LINEARITY ERROR (LSB)

–0.6

–0.8

–1.0

12.0

11.5

11.0

10.5

10.0

9.5

9.0

8.5

8.0

EFFECTIVE NUMBER OF BITS

7.5

7.0

2.5010

2.5005

2.5000

POSITIVE DNL

POSITIVE INL

NEGATIVE INL

NEGATIVE DNL

V

(V)

REF

Figure 10. Linearity Error vs. V

VDD = 5V

SINGLE-ENDED MODE

VDD = 3V

SINGLE-ENDED MODE

VDD = 3V

DIFFERENTIAL MODE

V

(V)

REF

Figure 11. Effective Number of Bits vs. V

VDD = 3V/5V
DIFFERENTIAL MODE

REF

VDD = 5V

DIFFERENTIAL MODE

REF

2.50 0.5 1.0 1.5 2.0

04603-009

5.00 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5

04603-010

10000

INTERNAL

REFERENCE

9000

8000

7000

6000

5000

4000

3000

NO. OF OCCURRENCES

2000

1000

0

2046 2047 20492048 2050

10000

CODES

CODE

DIFFERENTIAL

MODE

Figure 13. Histogram of Codes for 10k Samples in Differential Mode

10000

INTERNAL

REFERENCE

9000

8000

7000

6000

5000

4000

3000

NO. OF OCCURRENCES

2000

1000

0

2046 2047 2048 2049 2050

5 CODES 11 CODES

9984

CODES

CODE

SINGLE-ENDED

MODE

Figure 14. Histogram of Codes for 10k Samples in Single-Ended Mode

–60

–65

–70

–75

DIFFERENTIAL MODE

= 3V/5V

V

DD

04603-012

04603-042

(V)

2.4995

REF

V

2.4990

2.4985

2.4980

Figure 12. V

CURRENT LOAD (μA)

vs. Reference Output Current Drive

REF

2000 20 40 60 80 100 120 140 160 180

04603-011

–80

CMRR (dB)

–85

–90

–95

–100

RIPPLE FREQUENCY (kHz)

Figure 15. CMRR vs. Common-Mode Ripple Frequency

12000 200 400 600 800 1000

04603-011

Rev. B | Page 10 of 28

AD7266

TERMINOLOGY

Differential Nonlinearity (DNL)

Differential nonlinearity is the difference between the measured
and the ideal 1 LSB change between any two adjacent codes in
the ADC.

Integral Nonlinearity (INL)

Integral nonlinearity is the maximum deviation from a straight
line passing through the endpoints of the ADC transfer
function. The endpoints of the transfer function are zero scale
with a single (1) LSB point below the first code transition, and
full scale with a 1 LSB point above the last code transition.

Offset Error

Offset error applies to straight binary output coding. It is the
deviation of the first code transition (00 . . . 000) to (00 . . . 001)
from the ideal (AGND + 1 LSB).

Offset Error Match

Offset error match is the difference in offset error across all
12 channels.

Gain Error

Gain error applies to straight binary output coding. It is the
deviation of the last code transition (111 . . . 110) to (111 . . .

111) from the ideal (V

− 1 LSB) after the offset error is

REF

adjusted out. Gain error does not include reference error.

Gain Error Match

Gain error match is the difference in gain error across all
12 channels.

Zero Code Error

Zero code error applies when using twos complement output
coding with, for example, the 2 × V
+V

biased about the V

REF

point. It is the deviation of the

REF

midscale transition (all 1s to all 0s) from the ideal V
(V

).

REF

input range as −V

REF

REF

voltage

IN

to

Zero Code Error Match

Zero code error match refers to the difference in zero code error
across all 12 channels.

Positive Gain Error

This applies when using twos complement output coding with,
for example, the 2 × V
about the V

point. It is the deviation of the last code

REF

transition (011…110) to (011…111) from the ideal (+V

input range as −V

REF

REF

to +V

biased

REF

REF

−

1 LSB) after the zero code error is adjusted out.

Track-and-Hold Acquisition Time

The track-and-hold amplifier returns to track mode after the
end of conversion. Track-and-hold acquisition time is the time
required for the output of the track-and-hold amplifier to reach
its final value, within ±1/2 LSB, after the end of conversion.

Rev. B | Page 11 of 28

Signal-to-(Noise + Distortion) Ratio

This ratio is the measured ratio of signal-to-(noise + distortion)
at the output of the ADC. The signal is the rms amplitude of the
fundamental. Noise is the sum of all non-fundamental signals
up to half the sampling frequency (f

/2), excluding dc. The ratio

S

is dependent on the number of quantization levels in the
digitization process; the more levels, the smaller the quantization
noise. The theoretical signal-to-(noise + distortion) ratio for an
ideal N-bit converter with a sine wave input is given by

Signal-to-(Noise + Distortion) = (6.02N + 1.76) dB

Therefore, for a 12-bit converter, this is 74 dB.

Total Harmonic Distortion (THD)

Total harmonic distortion is the ratio of the rms sum of
harmonics to the fundamental. For the AD7266, it is defined as

2

2

dBTHD

log20)(

=

4

3

V

1

VVVVV

++++

6

5

2

2

2

2

where:

V

is the rms amplitude of the fundamental.

1

, V3, V4, V5, and V6 are the rms amplitudes of the second

V

2

through the sixth harmonics.

Peak Harmonic or Spurious Noise

Peak harmonic, or spurious noise, is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to f

/2, excluding dc) to the rms value of the

S

fundamental. Normally, the value of this specification is
determined by the largest harmonic in the spectrum, but for
ADCs where the harmonics are buried in the noise floor, it is a
noise peak.

Channel-to-Channel Isolation

Channel-to-channel isolation is a measure of the level of
crosstalk between channels. It is measured by applying a full­scale (2 × V

when VDD = 5 V, V

REF

when VDD = 3 V), 10 kHz

REF

sine wave signal to all unselected input channels and
determining how much that signal is attenuated in the selected
channel with a 50 kHz signal (0 V to V

). The result obtained

REF

is the worst-case across all 12 channels for the AD7266.

Intermodulation Distortion

With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities create distortion
products at sum, and difference frequencies of mfa ± nfb where
m, n = 0, 1, 2, 3, and so on. Intermodulation distortion terms
are those for which neither m nor n are equal to zero. For
example, the second-order terms include (fa + fb) and (fa − fb),
while the third-order terms include (2fa + fb), (2fa − fb),
(fa + 2fb), and (fa − 2fb).

AD7266

The AD7266 is tested using the CCIF standard where two input
frequencies near the top end of the input bandwidth are used.
In this case, the second-order terms are usually distanced in
frequency from the original sine waves, while the third-order
terms are usually at a frequency close to the input frequencies.
As a result, the second-order and third-order terms are
specified separately. The calculation of the intermodulation
distortion is as per the THD specification, where it is the ratio
of the rms sum of the individual distortion products to the rms
amplitude of the sum of the fundamentals expressed in dBs.

Common-Mode Rejection Ratio (CMRR)

CMRR is defined as the ratio of the power in the ADC output at
full-scale frequency, f, to the power of a 100 mV p-p sine wave
applied to the common-mode voltage of V
frequency f

as

S

CMRR (dB) = 10 log(Pf/Pf

)

S

IN+

and V

IN−

of

where:

Pf is the power at frequency f in the ADC output.

is the power at frequency fS in the ADC output.

Pf

S

Power Supply Rejection Ratio (PSRR)

Variations in power supply affect the full-scale transition but
not the converter’s linearity. PSRR is the maximum change in
the full-scale transition point due to a change in power supply
voltage from the nominal value (see Figure 4).

Thermal Hysteresis

Thermal hysteresis is defined as the absolute maximum change
of reference output voltage after the device is cycled through
temperature from either

T_HYS+ = +25°C to T

to +25°C

MAX

or

T_HYS− = +25°C to T

to +25°C

MIN

It is expressed in ppm by

−°

=

)( ×

ppmV

HYS

REFREF

°

V

REF

)C25(

)_()C25(

HYSTVV

10

6

where:

V

(25°C) is V

REF

(T_HYS) is the maximum change of V

V

REF

at 25°C.

REF

at T_HYS+ or

REF

T_HYS−.

Rev. B | Page 12 of 28

AD7266

V

V

THEORY OF OPERATION

CIRCUIT INFORMATION

The AD7266 is a fast, micropower, dual, 12-bit, single-supply,
ADC that operates from a 2.7 V to a 5.25 V supply. When
operated from a 5 V supply, the AD7266 is capable of
throughput rates of 2 MSPS when provided with a 32 MHz
clock, and a throughput rate of 1.5 MSPS at 3 V.

The AD7266 contains two on-chip, differential track-and-hold
amplifiers, two successive approximation ADCs, and a serial
interface with two separate data output pins. It is housed in a
32-lead LFCSP or a 32-lead TQFP, offering the user considerable
space-saving advantages over alternative solutions. The serial
clock input accesses data from the part but also provides the
clock source for each successive approximation ADC. The
analog input range for the part can be selected to be a 0 V to
V

input or a 2 × V

REF

input, configured with either single-

REF

ended or differential analog inputs. The AD7266 has an on-chip

2.5 V reference that can be overdriven when an external reference
is preferred. If the internal reference is to be used elsewhere in a
system, then the output needs to buffered first.

The AD7266 also features power-down options to allow power
saving between conversions. The power-down feature is
implemented via the standard serial interface, as described in
the Modes of Operation section.

CONVERTER OPERATION

The AD7266 has two successive approximation ADCs, each
based around two capacitive DACs. Figure 16 and Figure 17
show simplified schematics of one of these ADCs in acquisition
and conversion phase, respectively. The ADC is comprised of
control logic, a SAR, and two capacitive DACs. In Figure 16 (the
acquisition phase), SW3 is closed, SW1 and SW2 are in Position A,
the comparator is held in a balanced condition, and the sampling
capacitor arrays acquire the differential signal on the input.

CAPACITIVE

DAC

C

B

V

IN+

A

A

V

IN–

B

V

S

SW1

C

S

SW2

REF

Figure 16. ADC Acquisition Phase

COMPARATOR

SW3

CONTROL

LOGIC

CAPACITIVE

DAC

04603-013

When the ADC starts a conversion (see Figure 17), SW3 opens
and SW1 and SW2 move to Position B, causing the comparator
to become unbalanced. Both inputs are disconnected once the
conversion begins. The control logic and the charge redistribu­tion DACs are used to add and subtract fixed amounts of charge
from the sampling capacitor arrays to bring the comparator
back into a balanced condition. When the comparator is
rebalanced, the conversion is complete. The control logic
generates the ADC output code. The output impedances of the
sources driving the V

IN+

and V

pins must be matched;

IN−

otherwise, the two inputs will have different settling times,
resulting in errors.

CAPACITIVE

DAC

C

B

IN+

A

A

IN–

B

V

S

SW1

C

S

SW2

REF

Figure 17. ADC Conversion Phase

COMPARATOR

SW3

CONTROL

LOGIC

CAPACITIVE

DAC

04603-014

ANALOG INPUT STRUCTURE

Figure 18 shows the equivalent circuit of the analog input
structure of the AD7266 in differential/pseudo differential
mode. In single-ended mode, V
The four diodes provide ESD protection for the analog inputs.
Care must be taken to ensure that the analog input signals never
exceed the supply rails by more than 300 mV. This causes these
diodes to become forward-biased and starts conducting into the
substrate. These diodes can conduct up to 10 mA without
causing irreversible damage to the part.

The C1 capacitors in Figure 18 are typically 4 pF and can
primarily be attributed to pin capacitance. The resistors are
lumped components made up of the on resistance of the
switches. The value of these resistors is typically about 100 Ω.
The C2 capacitors are the ADC’s sampling capacitors with a
capacitance of 45 pF typically.

For ac applications, removing high frequency components from
the analog input signal is recommended by the use of an RC
low-pass filter on the relevant analog input pins with optimum
values of 47 Ω and 10 pF. In applications where harmonic dis­tortion and signal-to-noise ratio are critical, the analog input
should be driven from a low impedance source. Large source
impedances significantly affect the ac performance of the ADC
and may necessitate the use of an input buffer amplifier. The
choice of the op amp is a function of the particular application.

is internally tied to AGND.

IN−

Rev. B | Page 13 of 28

AD7266

–

–

V

V

IN+

V

IN–

V

DD

D

C1

C1

D

V

DD

D

D

C2

R1

C2

R1

04603-015

Figure 18. Equivalent Analog Input Circuit,

Conversion Phase—Switches Open, Track Phase—Switches Closed

When no amplifier is used to drive the analog input, the source
impedance should be limited to low values. The maximum source
impedance depends on the amount of THD that can be toler­ated. The THD increases as the source impedance increases and
performance degrades. Figure 19 shows a graph of the THD vs.
the analog input signal frequency for different source impedances
in single-ended mode, while Figure 20 shows the THD vs. the
analog input signal frequency for different source impedances
in differential mode.

50

F

= 1.5MSPS

SAMPLE

V

= 3V

DD

–55

–60

–65

–70

THD (dB)

–75

–80

–85

–90

RANGE = 0V TO V

REF

R

SOURCE

R

= 10Ω

SOURCE

INPUT F REQUE NCY (kHz)

Figure 19. THD vs. Analog Input Frequency for Various

Source Impedances, Single-Ended Mode

60

F

= 1.5MSPS

SAMPLE

V

= 3V

DD

–65

–70

–75

THD (dB)

–80

–85

–90

RANGE = 0V TO V

R

REF

= 0Ω

SOURCE

R

= 10Ω

SOURCE

INPUT F REQUE NCY (kHz)

Figure 20. THD vs. Analog Input Frequency for

Various Source Impedances, Differential Mode

R

SOURCE

= 100Ω

= 47Ω

R

SOURCE

R

R

R

SOURCE

R

SOURCE

SOURCE

600 700 800 900 10000 200100 400300 500

= 300Ω

SOURCE

= 47Ω

= 0Ω

6000 200100 400300 500

04603-016

= 300Ω

= 100Ω

04603-017

Rev. B | Page 14 of 28

Figure 21 shows a graph of the THD vs. the analog input
frequency for various supplies while sampling at 2 MSPS. In this
case, the source impedance is 47 Ω.

–50

F

= 1.5MSPS/2MSPS

SAMPLE

V

= 3V/5V

DD

–55

–60

–65

–70

THD (dB)

–75

–80

–85

–90

RANGE = 0 TO V

REF

V

= 3V

DD

DIFFERENTIAL MODE

V

= 5V

DD

SINGLE-ENDED MODE

INPUT FREQUENCY (kHz)

VDD = 3V
SINGLE-ENDED MODE

V

= 5V

DD

DIFFERENTIAL MODE

600 700 800 900 10000 200100 400300 500

04603-018

Figure 21. THD vs. Analog Input Frequency for Various Supply Voltages

ANALOG INPUTS

The AD7266 has a total of 12 analog inputs. Each on-board
ADC has six analog inputs that can be configured as six single­ended channels, three pseudo differential channels, or three
fully differential channels. These may be selected as described
in the Analog Input Selection section.

Single-Ended Mode

The AD7266 can have a total of 12 single-ended analog input
channels. In applications where the signal source has high
impedance, it is recommended to buffer the analog input
before applying it to the ADC. The analog input range can be
programmed to be either 0 to V

If the analog input signal to be sampled is bipolar, the internal
reference of the ADC can be used to externally bias up this
signal to make it correctly formatted for the ADC. Figure 22
shows a typical connection diagram when operating the ADC
in single-ended mode.

+1.25V

0V

–1.25V

V

IN

Figure 22. Single-Ended Mode Connection Diagram

R

3R

R

1

ADDITIONAL PI NS OMIT TED FOR CL ARITY.

or 0 to 2 × V

REF

+2.5

R

0V

.

REF

AD7266

A/D

CAP

0.47µF

1

B

04603-019

V

A1

D

V

CAP

B6

AD7266

Differential Mode

The AD7266 can have a total of six differential analog
input pairs.

Differential signals have some benefits over single-ended
signals, including noise immunity based on the device’s
common-mode rejection and improvements in distortion
performance. Figure 23 defines the fully differential analog
input of the AD7266.

p-p

p-p

V

IN+

AD7266

V

IN–

1

04603-020

V

REF

COMMON

MODE

VOLTAGE

V

REF

1

ADDITIONAL PINS OMITTED FOR CLARITY.

Figure 23. Differential Input Definition

The amplitude of the differential signal is the difference

IN+

and V

IN+

and V

between the signals applied to the V
differential pair (V

IN+

− V

IN−

). V
simultaneously driven by two signals each of amplitude V
(or 2 × V

, depending on the range chosen) that are 180° out

REF

IN−

should be

IN−

pins in each

REF

of phase. The amplitude of the differential signal is, therefore
(assuming the 0 to V
to-peak (2 × V

), regardless of the common mode (CM).

REF

range is selected) −V

REF

REF

to +V

REF

peak-

The common mode is the average of the two signals

+ V

(V

IN+

IN−

)/2

and is, therefore, the voltage on which the two inputs are
centered.

This results in the span of each input being CM ± V

/2. This

REF

voltage has to be set up externally and its range varies with the
reference value, V

. As the value of V

REF

increases, the common-

REF

mode range decreases. When driving the inputs with an amplifier,
the actual common-mode range is determined by the amplifier’s
output voltage swing.

Figure 24 and Figure 25 show how the common-mode range
typically varies with V
V

range or 2 × V

REF

for a 5 V power supply using the 0 to

REF

range, respectively. The common mode

REF

must be in this range to guarantee the functionality of the AD7266.

When a conversion takes place, the common mode is rejected,
resulting in a virtually noise free signal of amplitude −V

corresponding to the digital codes of 0 to 4096. If the

+V

REF

2 × V
from −2 V

range is used, then the input signal amplitude extends

REF

to +2 V

REF

after conversion.

REF

REF

to

3.5
TA = 25°C

3.0

2.5

2.0

1.5

1.0

COMMON-MO DE RANGE (V)

0.5

0

V

(V)

REF

Figure 24. Input Common-Mode Range vs. V

5.0
TA = 25°C

4.5

4.0

3.5

3.0

2.5

2.0

1.5

COMMON-MODE RANGE (V)

1.0

0.5

0

V

(V)

REF

Figure 25. Input Common-Mode Range vs. V

REF

REF

(0 to V

(2 × V

REF

REF

5.00 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5

04603-021

Range, VDD = 5 V)

2.50 0.5 1.0 1.5 2.0

04603-022

Range, VDD = 5 V)

Driving Differential Inputs

Differential operation requires that V

IN+

and V

IN−

be
simultaneously driven with two equal signals that are 180° out
of phase. The common mode must be set up externally. The
common-mode range is determined by V

, the power supply,

REF

and the particular amplifier used to drive the analog inputs.
Differential modes of operation with either an ac or dc input
provide the best THD performance over a wide frequency
range. Because not all applications have a signal preconditioned
for differential operation, there is often a need to perform
single-ended-to-differential conversion.

Rev. B | Page 15 of 28

AD7266

Using an Op Amp Pair

An op amp pair can be used to directly couple a differential
signal to one of the analog input pairs of the AD7266. The
circuit configurations illustrated in Figure 26 and Figure 27
show how a dual op amp can be used to convert a single-ended
signal into a differential signal for both a bipolar and unipolar
input signal, respectively.

The voltage applied to Point A sets up the common-mode
voltage. In both diagrams, it is connected in some way to the
reference, but any value in the common-mode range can be
input here to set up the common mode. The AD8022 is a
suitable dual op amp that can be used in this configuration to
provide differential drive to the AD7266.

Take care when choosing the op amp; the selection depends on
the required power supply and system performance objectives.
The driver circuits in Figure 26 and Figure 27 are optimized for
dc coupling applications requiring best distortion performance.

The circuit configuration shown in Figure 26 converts a
unipolar, single-ended signal into a differential signal.

The differential op amp driver circuit shown in Figure 27 is
configured to convert and level shift a single-ended, ground­referenced (bipolar) signal to a differential signal centered at the

level of the ADC.

V

REF

p-p

V

REF

GND

2 × V

REF

440Ω

220Ω

V+

27Ω

V–

220Ω
220Ω

V+

27Ω

A

V–

10kΩ

1

ADDITIONAL PINS OMITTE D FOR CLARITY.

Figure 26. Dual Op Amp Circuit to Convert a Single-Ended Unipolar Signal

into a Differential Signal

2 × V

GND

REF

p-p

220kΩ

440Ω

20kΩ

220Ω

V+

27Ω

V–

220Ω
220Ω

V+

27Ω

A

V–

10kΩ

1

ADDITIO NAL PINS O MITT ED FOR CL ARITY.

Figure 27. Dual Op Amp Circuit to Convert a Single-Ended Bipolar Signal

into a Differential Unipolar Signal

3.75V

2.5V

1.25V

3.75V

2.5V

1.25V

3.75V

2.5V

1.25V

3.75V

2.5V

1.25V

AD7266

A/D

CAP

CAP

0.47µF

AD7266

A/D

CAP

0.47µF

1

B

1

B

V

IN+

D

V

IN–

V

IN+

D

V

CAP

IN–

Rev. B | Page 16 of 28

04603-023

04603-024

Pseudo Differential Mode

The AD7266 can have a total of six pseudo differential pairs. In
this mode, V
an amplitude of V

is connected to the signal source that must have

IN+

(or 2 × V

REF

, depending on the range

REF

chosen) to make use of the full dynamic range of the part. A dc
input is applied to the V
provides an offset from ground or a pseudo ground for the V

pin. The voltage applied to this input

IN−

IN+

input. The benefit of pseudo differential inputs is that they
separate the analog input signal ground from the ADC’s ground
allowing dc common-mode voltages to be cancelled. The typical
voltage range for the V

pin, while in pseudo differential

IN−

mode, is shown in Figure 28 and Figure 29. Figure 30 shows a
connection diagram for pseudo differential mode.

1.0

0.8

0.6

0.4

(V)

IN–

0.2

V

0

–0.2

–0.4

V

(V)

REF

Figure 28. V

Input Voltage Range vs. V

IN−-

Pseudo Differential Mode with V

2.5
TA = 25°C

2.0

1.5

1.0

(V)

IN–

V

0.5

0

–0.5

V

(V)

REF

Figure 29. V

Input Voltage Range vs. V

IN−

Pseudo Differential Mode with V

V

REF

p–p

DC INPUT
VOLTAGE

1

ADDITIO NAL PINS O MITTE D FOR CLARI TY.

V

V

Figure 30. Pseudo Differential Mode Connection Diagram

IN+

IN–

V

DD

DD

REF

TA = 25°C

REF

= 3 V

REF

= 5 V

AD7266

0.47µF

in

in

3.00 0.5 1.0 1.5 2.0 2.5

04603-043

5.00 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5

04603-044

1

04603-025

AD7266

ANALOG INPUT SELECTION

The analog inputs of the AD7266 can be configured as single­ended or true differential via the SGL/
in . If this pin is tied to a logic low, the analog input

Figure 31
channels to each on-chip ADC are set up as three true
differential pairs. If this pin is at logic high, the analog input
channels to each on-chip ADC are set up as six single-ended
analog inputs. The required logic level on this pin needs to be
established prior to the acquisition time and remain unchanged
during the conversion time until the track-and-hold has returned
to track. The track-and-hold returns to track on the 13

CS

edge of SCLK after the

falling edge (see ). If the
level on this pin is changed, it will be recognized by the
AD7266; therefore, it is necessary to keep the same logic level
during acquisition and conversion to avoid corrupting the
conversion in progress.

For example, in Figure 31 the SGL/
for the duration of both the acquisition and conversion times so
the analog inputs are configured as single ended for that
conversion (Sampling Point A). The logic level of the SGL/
changed to low after the track-and-hold returned to track and
prior to the required acquisition time for the next sampling
instant at Point B; therefore, the analog inputs are configured as
differential for that conversion.

A

t

CS

SCLK

SGL/DIFF

Figure 31. Selecting Differential or Single-Ended Configuration

ACQ

114 141

DIFF

logic pin, as shown

Figure 41

DIFF

pin is set at logic high

B

th

rising

DIFF

04603-026

The channels used for simultaneous conversions are selected via
the multiplexer address input pins, A0 to A2. The logic states of
these pins also need to be established prior to the acquisition
time; however, they may change during the conversion time
provided the mode is not changed. If the mode is changed from
fully differential to pseudo differential, for example, then the
acquisition time would start again from this point. The selected
input channels are decoded as shown in Tab le 6 .

The analog input range of the AD7266 can be selected as 0 V to
V

or 0 V to 2 × V

REF

made in a similar fashion to that of the SGL/
the logic state of the RANGE pin a time t

CS

edge of

. Subsequent to this, the logic level on this pin can be

via the RANGE pin. This selection is

REF

DIFF

pin by setting

prior to the falling

acq

altered after the third falling edge of SCLK. If this pin is tied to a
logic low, the analog input range selected is 0 V to V

. If this

REF

pin is tied to a logic high, the analog input range selected is 0 V
to 2 × V

REF

.

OUTPUT CODING

The AD7266 output coding is set to either twos complement or
straight binary, depending on which analog input configuration
is selected for a conversion. Tab l e 5 shows which output coding
scheme is used for each possible analog input configuration.

Table 5. AD7266 Output Coding

DIFF

SGL/

DIFF
DIFF 0 V to 2 × V
SGL 0 V to V
SGL 0 V to 2 × V
PSEUDO DIFF 0 V to V
PSEUDO DIFF

Range Output Coding

0 V to V

REF

REF

REF

0 V to 2 × V

REF

Straight binary

REF

Straight binary

REF

Twos complement

Twos complement

Twos complement

Twos complement

Table 6. Analog Input Type and Channel Selection

ADC A ADC B

SGL/

DIFF

V

A2 A1 A0

IN+

V

IN−

IN+

V

Comment

IN−

V

1 0 0 0 VA1 AGND VB1 AGND Single ended
1 0 0 1 VA2 AGND VB2 AGND Single ended
1 0 1 0 VA3 AGND VB3 AGND Single ended
1 0 1 1 VA4 AGND VB4 AGND Single ended
1 1 0 0 VA5 AGND VB5 AGND Single ended
1 1 0 1 VA6 AGND VB6 AGND Single ended
0 0 0 0 VA1
0 0 0 1 VA1 VA2 V
0 0 1 0 VA3 VA4 V
0 0 1 1 VA3 VA4 V
0 1 0 0 VA5 VA6 V
0 1 0 1 VA5 V

VA2 V

V

A6

VB2 Fully differential

B1

V

B1

VB4 Fully differential

B3

V

B3

VB6 Fully differential

B5

V

B5

Pseudo differential

B2

Pseudo differential

B4

Pseudo differential

B6

Rev. B | Page 17 of 28

AD7266

TRANSFER FUNCTIONS

The designed code transitions occur at successive integer LSB
values (1 LSB, 2 LSB, and so on). In single-ended mode, the LSB
size is V
LSB size is 2 × V
In differential mode, the LSB size is 2 × V
to V
0 V to 2 × V
for the AD7266 when straight binary coding is output is shown
in Figure 32, and the ideal transfer characteristic for the
AD7266 when twos complement coding is output is shown in
Figure 33 (this is shown with the 2 × V

/4096 when the 0 V to V

REF

/4096 when the 0 V to 2 × V

REF

range is used, and the LSB size is 4 × V

REF

range is used. The ideal transfer characteristic

REF

111...111

111...110

111...000

011...111

ADC CODE

000...010

000...001

000...000

1LSB

0V

range is used, and the

REF

1LSB = V

ANALOG INPUT

range is used.

REF

/4096 when the 0 V

REF

/4096 when the

REF

range).

REF

/4096

REF

V

– 1LSB

REF

DIGITAL INPUTS

The digital inputs applied to the AD7266 are not limited by the
maximum ratings that limit the analog inputs. Instead, the
digital inputs can be applied up to 7 V and are not restricted by
the V

+ 0.3 V limit as are the analog inputs. See the Absolute

DD

Maximum Ratings section for more information. Another
advantage of the SCLK, RANGE, A0 to A2, and
being restricted by the V

+ 0.3 V limit is that power supply

DD

sequencing issues are avoided. If one of these digital inputs is
applied before V

, there is no risk of latch-up, as there would

DD

be on the analog inputs if a signal greater than 0.3 V were
applied prior to V

V

DRIVE

The AD7266 also has a V
which the serial interface operates. V

DD

.

feature to control the voltage at

DRIVE

DRIVE

easily interface to both 3 V and 5 V processors. For example, if
the AD7266 was operated with a V

of 5 V, the V

DD

could be powered from a 3 V supply, allowing a large dynamic
range with low voltage digital processors. Therefore, the
AD7266 could be used with the 2 × V

REF

of 5 V while still being able to interface to 3 V digital parts.

CS

pins not

allows the ADC to

pin

DRIVE

input range, with a VDD

NOTE

1. V

IS EITHER V

REF

REF

OR 2 × V

REF

.

Figure 32. Straight Binary Transfer Characteristic

1LSB = 2

×

V

/4096

REF

011...111

011...110

000...001

000...000

111...111

ADC CODE

100...010

100...001

100...000
+ 1LSB V

REF

– 1LSB

REF

ANALOG INPUT

– 1 LSB–V

+V

REF

Figure 33. Twos Complement Transfer Characteristic with

V

± V

Input Range

REF

REF

04603-027

04603-028

Rev. B | Page 18 of 28

AD7266

MODES OF OPERATION

The mode of operation of the AD7266 is selected by controlling
the (logic) state of the

signal during a conversion. There are

CS

three possible modes of operation: normal mode, partial power­down mode, and full power-down mode. After a conversion is

CS

initiated, the point at which

is pulled high determines which
power-down mode, if any, the device enters. Similarly, if already
in a power-down mode,

can control whether the device

CS

returns to normal operation or remains in power-down. These
modes of operation are designed to provide flexible power
management options. These options can be chosen to optimize
the power dissipation/throughput rate ratio for differing
application requirements.

NORMAL MODE

This mode is intended for applications needing fastest throughput
rates because the user does not have to worry about any power­up times with the AD7266 remaining fully powered at all times.
Figure 34 shows the general diagram of the operation of the
AD7266 in this mode.

CS

110 14

SCLK

A

D

OUT

D

B

OUT

The conversion is initiated on the falling edge of CS, as
described in the section. To ensure that the part
remains fully powered up at all times,
at least 10 SCLK falling edges have elapsed after the falling edge

CS

of

. If CS is brought high any time after the 10th SCLK falling
edge but before the 14
powered up, but the conversion is terminated and D

B go back into three-state. Fourteen serial clock cycles are

D

OUT

required to complete the conversion and access the conversion
result. The D
SCLK cycles have elapsed, but instead does so when

brought high again. If
(for example, if only a 16 SCLK burst is available), two trailing
zeros are clocked out after the data. If
14 (or16) SCLK cycles, the result from the other ADC on board
is also accessed on the same D
(see the section).

Serial Interface

Once 32 SCLK cycles have elapsed, the D
three-state on the 32
prior to this, the D
Therefore,
brought high again sometime prior to the next conversion
(effectively idling
returns to three-state upon completion of the dual result read.

LEADING ZEROS + CONVERSION RESULT

Figure 34. Normal Mode Operation

Serial Interface

CS

must remain low until

th

SCLK falling edge, the part remains

line does not return to three-state after 14

OUT

CS

is left low for another 2 SCLK cycles

CS

is left low for a further

line, as shown in

OUT

line returns to

nd

SCLK falling edge. If CS is brought high

line returns to three-state at that point.

OUT

CS

may idle low after 32 SCLK cycles until it is

CS

low), if so desired, because the bus still

OUT

A and

OUT

CS

is

Figure 42

04603-029

Once a data transfer is complete and D
returned to three-state, another conversion can be initiated after
the quiet time, t

, has elapsed by bringing CS low again

QUIET

(assuming the required acquisition time is allowed).

PARTIAL POWER-DOWN MODE

This mode is intended for use in applications where slower
throughput rates are required. Either the ADC is powered down
between each conversion, or a series of conversions may be
performed at a high throughput rate, and the ADC is then
powered down for a relatively long duration between these
bursts of several conversions. When the AD7266 is in partial
power-down, all analog circuitry is powered down except for
the on-chip reference and reference buffer.

To enter partial power-down mode, the conversion process
must be interrupted by bringing
second falling edge of SCLK and before the 10
SCLK, as shown in . Once Figure 35
window of SCLKs, the part enters partial power-down, the
conversion that was initiated by the falling edge of
terminated, and D
CS

is brought high before the second SCLK falling edge, the

A and D

OUT

part remains in normal mode and does not power down. This
avoids accidental power-down due to glitches on the

CS

SCLK

D

OUT

D

OUT

A
B

1110 42

Figure 35. Entering Partial Power-Down Mode

To exit this mode of operation and power up the AD7266 again,
a dummy conversion is performed. On the falling edge of
the device begins to power up and continues to power up as

CS

long as

is held low until after the falling edge of the 10th
SCLK. The device is fully powered up after approximately 1 μs
has elapsed, and valid data results from the next conversion, as
shown in . If Figure 36

CS

falling edge of SCLK, the AD7266 again goes into partial
power-down. This avoids accidental power-up due to glitches

CS

on the
the falling edge of
of
and

line. Although the device may begin to power up on

CS

, it powers down again on the rising edge

CS

. If the AD7266 is already in partial power-down mode

CS

is brought high between the second and 10th falling

edges of SCLK, the device enters full power-down mode.

CS

B go back into three-state. If

OUT

is brought high before the second

OUT

A and D

OUT

B have

high anywhere after the

th

falling edge of

CS

is brought high in this

CS

is

CS

line.

THREE-STATE

CS

,

04603-030

Rev. B | Page 19 of 28

AD7266

CS

FULL POWER-DOWN MODE

This mode is intended for use in applications where throughput
rates slower than those in the partial power-down mode are
required, as power-up from a full power-down takes substan­tially longer than that from partial power-down. This mode is
more suited to applications where a series of conversions
performed at a relatively high throughput rate are followed by a
long period of inactivity and thus power-down. When the
AD7266 is in full power-down, all analog circuitry is powered
down. Full power-down is entered in a similar way as partial
power-down, except the timing sequence shown in Figure 35
must be executed twice. The conversion process must be
interrupted in a similar fashion by bringing
after the second falling edge of SCLK and before the 10
edge of SCLK. The device enters partial power-down at this
point. To reach full power-down, the next conversion cycle
must be interrupted in the same way, as shown in .

CS

Once

is brought high in this window of SCLKs, the part

completely powers down.

THE PART BEGINS

TO POWER UP.

CS

CS

high anywhere

Figure 37

t

POWER-UP1

th

falling

Note that it is not necessary to complete the 14 SCLKs once
is brought high to enter a power-down mode.

To exit full power-down and power up the AD7266, a dummy
conversion is performed, as when powering up from partial
power-down. On the falling edge of

power up and continues to power up, as long as
until after the falling edge of the 10

CS

, the device begins to

CS

th

SCLK. The required

is held low

power-up time must elapse before a conversion can be initiated,
as shown in . See the section for the

Figure 38 Power-Up Times

power-up times associated with the AD7266.

THE PART IS FULLY
POWERED UP; SEE
POWER-UP TIMES
SECTION.

SCLK

D

OUT

D

OUT

A

B

11014 141

INVALID DATA

VALID DATA

04603-031

Figure 36. Exiting Partial Power-Down Mode

THE PART BEGINS

TO POWER UP.

1102

THE PART ENTERS

FULL POWER DOWN.

INVALID DATAINVALID DATA

THREE-STATE

14

04603-032

SCLK

D

OUT

D

OUT

CS

THE PART ENTERS

PARTIAL POWER DOWN.

110142

A

B

THREE-STATE

Figure 37. Entering Full Power-Down Mode

Rev. B | Page 20 of 28

AD7266

THE PART BEGINS

SCLK

D

OUT

D

OUT

TO POWER UP.

CS

1

A

B

t

POWER-UP2

10

INVALID DATA VALID DATA

Figure 38. Exiting Full Power-Down Mode

POWER-UP TIMES

As described in detail, the AD7266 has two power-down
modes, partial power-down and full power-down. This section
deals with the power-up time required when coming out of
either of these modes. It should be noted that the power-up
times, as explained in this section, apply with the recommended
capacitors in place on the D

A and D

CAP

CAP

B pins.

To power up from full power-down, approximately 1.5 ms

CS

should be allowed from the falling edge of
t

POWER-UP2

in . Powering up from partial power-down

Figure 38

, shown as

requires much less time. The power-up time from partial
power-down is typically 1 μs; however, if using the internal
reference, then the AD7266 must be in partial power-down for
at least 67 μs in order for this power-up time to apply.

When power supplies are first applied to the AD7266, the ADC
may power up in either of the power-down modes or normal
mode. Because of this, it is best to allow a dummy cycle to
elapse to ensure the part is fully powered up before attempting a
valid conversion. Likewise, if it is intended to keep the part in
the partial power-down mode immediately after the supplies are
applied, then two dummy cycles must be initiated. The first
dummy cycle must hold

edge (see ); in the second cycle, Figure 34
high before the 10
falling edge (see ). Alternatively, if it is intended to

Figure 35

CS

low until after the 10th SCLK falling

CS

th

SCLK edge but after the second SCLK

must be brought

place the part in full power-down mode when the supplies are
applied, then three dummy cycles must be initiated. The first
dummy cycle must hold
edge (see ); the second and third dummy cycles place

Figure 34

the part in full power-down (see ).

CS

low until after the 10th SCLK falling

Figure 37

Once supplies are applied to the AD7266, enough time must be
allowed for any external reference to power up and charge the
various reference buffer decoupling capacitors to their final values.

POWER vs. THROUGHPUT RATE

The power consumption of the AD7266 varies with the
throughput rate. When using very slow throughput rates and as
fast an SCLK frequency as possible, the various power-down
options can be used to make significant power savings.
However, the AD7266 quiescent current is low enough that

THE PART IS FULLY POWERED UP,
SEE POWER-UP TIMES SECTION.

14

1

14

04603-033

even without using the power-down options, there is a
noticeable variation in power consumption with sampling rate.
This is true whether a fixed SCLK value is used or if it is scaled
with the sampling rate. Figure 39 and Figure 40 show plots of
power vs. the throughput rate when operating in normal mode
for a fixed maximum SCLK frequency and an SCLK frequency
that scales with the sampling rate with V

= 3 V and VDD = 5 V,

DD

respectively. In all cases, the internal reference was used.

10.0
= 25°C

T

A

9.5

9.0

8.5

8.0

7.5

7.0

POWER (mW)

6.5

6.0

5.5

5.0

Figure 39. Power vs. Throughput in Normal Mode with V

30

T

= 25°C

A

28

26

24

22

20

18

POWER (mW)

16

14

12

10

Figure 40. Power vs. Throughput in Normal Mode with V

VARIABLE SCLK

24MHz SCLK

THROUGHPUT (kSPS)

VARIABLE SCLK

32MHz SCLK

THROUGHPUT (kSPS)

14000 200 400 600 800 1000 1200

DD

DD

= 3 V

20000 200 400 600 800 1000 1200 1400 1600 1800

= 5 V

04603-045

04603-046

Rev. B | Page 21 of 28

AD7266

SERIAL INTERFACE

Figure 41 shows the detailed timing diagram for serial inter­facing to the AD7266. The serial clock provides the conversion
clock and controls the transfer of information from the AD7266
during conversion.

CS

signal initiates the data transfer and conversion process.

The
The falling edge of

CS

puts the track-and-hold into hold mode,
at which point the analog input is sampled and the bus is taken
out of three-state. The conversion is also initiated at this point
and requires a minimum of 14 SCLKs to complete. Once 13
SCLK falling edges have elapsed, the track-and-hold goes back
into track on the next SCLK rising edge, as shown in

Figure 41
at Point B. If a 16 SCLK transfer is used, then two trailing zeros
appear after the final LSB. On the rising edge of
conversion is terminated and D

CS

three-state. If

is not brought high but is instead held low for a
further 14 (or 16) SCLK cycles on D
Conversion B is output on D

CS

Likewise, if
on D

OUT

is illustrated in where the case for D
this case, the D

nd

SCLK falling edge or the rising edge of

32

is held low for a further 14 (or 16) SCLK cycles

B, the data from Conversion A is output on D

Figure 42

line in use goes back into three-state on the

OUT

A and D

OUT

A, the data from

OUT

A (followed by two trailing zeros).

OUT

CS

, the

B go back into

OUT

A is shown. In

OUT

CS

, whichever

OUT

B. This

occurs first.

A minimum of 14 serial clock cycles are required to perform
the conversion process and to access data from one conversion

CS

on either data line of the AD7266.

going low provides the
leading zero to be read in by the microcontroller or DSP. The
remaining data is then clocked out by subsequent SCLK falling
edges, beginning with a second leading zero. Thus, the first
falling clock edge on the serial clock has the leading zero
provided and also clocks out the second leading zero. The 12-bit
result then follows with the final bit in the data transfer valid on

th

the 14

falling edge, having being clocked out on the previous

th

) falling edge. In applications with a slower SCLK, it may be

(13
possible to read in data on each SCLK rising edge depending on
the SCLK frequency. The first rising edge of SCLK after the

CS

falling edge would have the second leading zero provided, and

th

the 13

rising SCLK edge would have DB0 provided.

Note that with fast SCLK values, and thus short SCLK periods,
in order to allow adequately for t

, an SCLK rising edge may

2

occur before the first SCLK falling edge. This rising edge of
SCLK may be ignored for the purposes of the timing
descriptions in this section. If a falling edge of SCLK is coincident
with the falling edge of

CS

, then this falling edge of SCLK is not
acknowledged by the AD7266, and the next falling edge of
SCLK will be the first registered after the falling edge of

CS

.

CS

t

9

SCLK

D

OUT

D

OUT

A
B

THREE­STATE

2 LEADING ZEROS

t

2

2

DB11

34

DB10

1

t

3

0

0

t

6

5

t

7

t

4

DB9 DB8

DB2

B

13

t

5

DB1

t

8

DB0

t

QUIET

THREE-STATE

04603-034

Figure 41. Serial Interface Timing Diagram

CS

t

6

5

14

t

5

t

4

A

t

7

2 TRAILING ZEROS

15

16

17

ZEROZERO ZERO

2 LEADING ZEROS

Line with 32 SCLKs

OUT

DB11

32

t

10

B

ZERO ZERO

2 TRAILING ZEROS

THREE­STATE

04603-035

SCLK

D

OUT

A

THREE­STATE

t

2

1

t

3

ZERO0 ZERO

2 LEADING

ZEROS

2

DB11

A

34

DB10ADB9

Figure 42. Reading Data from Both ADCs on One D

Rev. B | Page 22 of 28

AD7266

MICROPROCESSOR INTERFACING

The serial interface on the AD7266 allows the part to be directly
connected to a range of many different microprocessors. This
section explains how to interface the AD7266 with some of the
more common microcontroller and DSP serial interface
protocols.

AD7266 TO ADSP-218x

The ADSP-218x family of DSPs interface directly to the
AD7266 without any glue logic required. The V
AD7266 takes the same supply voltage as that of the ADSP-218x.
This allows the ADC to operate at a higher supply voltage than
its serial interface and therefore, the ADSP-218x, if necessary.
This example shows both D

A and D

OUT

B of the AD7266

OUT

connected to both serial ports of the ADSP-218x. The SPORT0
and SPORT1 control registers should be set up as shown in
Tabl e 7 and Ta b le 8 .

Table 7. SPORT0 Control Register Setup

Setting Description

TFSW = RFSW = 1 Alternate framing
INVRFS = INVTFS = 1 Active low frame signal
DTYPE = 00 Right justify data
SLEN = 1111

16-bit data-word (or may be set to

1101 for 14-bit data-word)
ISCLK = 1 Internal serial clock
TFSR = RFSR = 1 Frame every word
IRFS = 0
ITFS = 1

Table 8. SPORT1 Control Register Setup

Setting Description

TFSW = RFSW = 1 Alternate framing
INVRFS = INVTFS = 1 Active low frame signal
DTYPE = 00 Right justify data
SLEN = 1111

16-bit data-word (or may be set to

1101 for 14-bit data-word)
ISCLK = 0 External serial clock
TFSR = RFSR = 1 Frame every word
IRFS = 0
ITFS = 1

To implement the power-down modes, SLEN should be set to
1001 to issue an 8-bit SCLK burst.

DRIVE

pin of the

The connection diagram is shown in Figure 43. The ADSP-218x
has the TFS0 and RFS0 of the SPORT0 and the RFS1 of SPORT1
tied together. TFS0 is set as an output, and both RFS0 and RFS1
are set as inputs. The DSP operates in alternate framing mode,
and the SPORT control register is set up as described. The
frame synchronization signal generated on the TFS is tied to
CS

, and as with all signal processing applications, equidistant
sampling is necessary. However, in this example, the timer
interrupt is used to control the sampling rate of the ADC and,
under certain conditions, equidistant sampling may not be
achieved.

AD7266

1

ADDITIONAL PINS OMI TTED FO R CLARITY.

1

SCLK

CS

D

A

OUT

D

B DR1

OUT

V

DRIVE

Figure 43. Interfacing the AD7266 to the ADSP-218x

ADSP-218x

SCLK0

SCLK1

TFS0

RFS0

RFS1

DR0

V

DD

1

04603-036

The timer registers are loaded with a value that provides an
interrupt at the required sample interval. When an interrupt is
received, a value is transmitted with TFS/DT (ADC control
word). The TFS is used to control the RFS, and hence, the
reading of data. The frequency of the serial clock is set in the
SCLKDIV register. When the instruction to transmit with TFS
is given (AX0 = TX0), the state of the SCLK is checked. The
DSP waits until the SCLK has gone high, low, and high again
before transmission starts. If the timer and SCLK values are
chosen such that the instruction to transmit occurs on or near
the rising edge of SCLK, then the data may be transmitted or it
may wait until the next clock edge.

For example, the ADSP-2111 has a master clock frequency of
16 MHz. If the SCLKDIV register is loaded with the value 3,
then an SCLK of 2 MHz is obtained, and eight master clock
periods will elapse for every one SCLK period. If the timer
registers are loaded with the value 803, then 100.5 SCLKs will
occur between interrupts and, subsequently, between transmit
instructions. This situation yields sampling that is not equidistant
as the transmit instruction is occurring on an SCLK edge. If the
number of SCLKs between interrupts is a whole integer figure
of N, then equidistant sampling will be implemented by the DSP.

Rev. B | Page 23 of 28

AD7266

AD7266 TO ADSP-BF53x

The ADSP-BF53x family of DSPs interface directly to the
AD7266 without any glue logic required. The availability of
secondary receive registers on the serial ports of the Blackfin®
DSPs means only one serial port is necessary to read from both
D

pins simultaneously. Figure 44 shows both D

OUT

B of the AD7266 connected to Serial Port 0 of the

D

OUT

ADSP-BF53x. The SPORT0 Receive Configuration 1 register
and SPORT0 Receive Configuration 2 register should be set up
as outlined in Tabl e 9 and Tab l e 1 0 .

1

AD7266

D

A

OUT

SCLK

CS

D

B

OUT

V

DRIVE

1

ADDITIONAL PINS OMITTED FOR CLARITY.

SERIAL

DEVICE A

(PRIMARY)

SERIAL

DEVICE B

(SECONDARY)

Figure 44. Interfacing the AD7266 to the ADSP-BF53x

ADSP-BF53x

SPORT0

DR0PRI

RCLK0

RFS0

DR0SEC

V

DD

Table 9. The SPORT0 Receive Configuration 1 Register
(SPORT0_RCR1)

Setting Description

RCKFE = 1 Sample data with falling edge of RSCLK
LRFS = 1 Active low frame signal
RFSR = 1 Frame every word
IRFS = 1 Internal RFS used
RLSBIT = 0 Receive MSB first
RDTYPE = 00 Zero fill
IRCLK = 1 Internal receive clock
RSPEN = 1 Receive enabled
SLEN = 1111

16-bit data-word (or may be set to 1101
for 14-bit data-word)

TFSR = RFSR = 1

Table 10. The SPORT0 Receive Configuration 2 Register
(SPORT0_RCR2)

Setting Description

RXSE = 1 Secondary side enabled
SLEN = 1111

16-bit data-word ( or may be set to 1101
for 14-bit data-word)

To implement the power-down modes, SLEN should be set to
1001 to issue an 8-bit SCLK burst. A Blackfin driver for the
AD7266 is available to download at www.analog.com.

OUT

A and

1

04603-037

Rev. B | Page 24 of 28

AD7266 TO TMS320C541

The serial interface on the TMS320C541 uses a continuous
serial clock and frame synchronization signals to synchronize
the data transfer operations with peripheral devices like the
AD7266. The
TMS320C541 and the AD7266 without any glue logic required.
The serial ports of the TMS320C541 are set up to operate in
burst mode with internal CLKX0 (TX serial clock on Serial
Port 0) and FSX0 (TX frame sync from Serial Port 0). The serial
port control registers (SPC) must have the following setup.

Table 11. Serial Port Control Register Set Up

SPC FO FSM MCM TXM

SPC0 0 1 1 1
SPC1 0 1 0 0

The format bit, FO, may be set to 1 to set the word length to
8 bits to implement the power-down modes on the AD7266.

The connection diagram is shown in Figure 45. It is imperative
that for signal processing applications, the frame synchroniza­tion signal from the TMS320C541 provides equidistant sampling.
The V

DRIVE

that of the TMS320C541. This allows the ADC to operate at a
higher voltage than its serial interface and therefore, the
TMS320C541, if necessary.

1

ADDITIONAL PINS OMITTED FOR CLARITY.

CS

input allows easy interfacing between the

pin of the AD7266 takes the same supply voltage as

AD7266

1

SCLK

D

A

OUT

D

B

OUT

CS FSX0

V

DRIVE

TMS320C541

CLKX0

CLKR0

CLKX1

CLKR1

DR0

DR1

FSR0

FSR1

V

DD

Figure 45. Interfacing the AD7266 to the TMS320C541

1

04603-038

AD7266

AD7266 TO DSP563xx

The connection diagram in Figure 46 shows how the AD7266
can be connected to the ESSI (synchronous serial interface) of
the DSP563xx family of DSPs from Motorola. There are two
on-board ESSIs, and each is operated in synchronous mode
(Bit SYN = 1 in CRB register) with internally generated word
length frame sync for both TX and RX (Bit FSL1 = 0 and
Bit FSL0 = 0 in CRB).

Normal operation of the ESSI is selected by making MOD = 0
in the CRB. Set the word length to 16 by setting Bit WL1 = 1
and Bit WL0 = 0 in CRA.

To implement the power-down modes on the AD7266, the
word length can be changed to 8 bits by setting Bit WL1 = 0 and
Bit WL0 = 0 in CRA. The FSP bit in the CRB should be set to 1
so the frame sync is negative. It is imperative for signal
processing applications that the frame synchronization signal
from the DSP563xx provides equidistant sampling.

In the example shown in Figure 46, the serial clock is taken
from the ESSI0 so the SCK0 pin must be set as an output,
SCKD = 1, while the SCK1 pin is set as an input, SCKD = 0. The
frame sync signal is taken from SC02 on ESSI0, so SCD2 = 1,
while on ESSI1, SCD2 = 0; therefore, SC12 is configured as an
input. The V

pin of the AD7266 takes the same supply

DRIVE

voltage as that of the DSP563xx. This allows the ADC to operate
at a higher voltage than its serial interface and therefore, the
DSP563xx, if necessary.

1

AD7266

SCLK

D

A

OUT

B

D

OUT

CS

V

DRIVE

1

ADDITIONAL PINS OMITTED FOR CLARITY.

Figure 46. Interfacing the AD7266 to the DSP563xx

DSP563xx

SCK0

SCK1

SRD0

SRD1

SC02

SC12

V

1

DD

04603-039

Rev. B | Page 25 of 28

AD7266

APPLICATION HINTS

GROUNDING AND LAYOUT

The analog and digital supplies to the AD7266 are independent
and separately pinned out to minimize coupling between the
analog and digital sections of the device. The printed circuit
board (PCB) that houses the AD7266 should be designed so
that the analog and digital sections are separated and confined
to certain areas of the board. This design facilitates the use of
ground planes that can be easily separated.

To provide optimum shielding for ground planes, a minimum
etch technique is generally best. All three AGND pins of the
AD7266 should be sunk in the AGND plane. Digital and analog
ground planes should be joined in only one place. If the AD7266
is in a system where multiple devices require an AGND to DGND
connection, the connection should still be made at one point
only, a star ground point that should be established as close as
possible to the ground pins on the AD7266.

Avoid running digital lines under the device as this couples
noise onto the die. However, the analog ground plane should be
allowed to run under the AD7266 to avoid noise coupling. The
power supply lines to the AD7266 should use as large a trace as
possible to provide low impedance paths and reduce the effects
of glitches on the power supply line.

To avoid radiating noise to other sections of the board, fast
switching signals, such as clocks, should be shielded with digital
ground, and clock signals should never run near the analog
inputs. Avoid crossover of digital and analog signals. To reduce
the effects of feedthrough within the board, traces on opposite
sides of the board should run at right angles to each other. A
microstrip technique is the best method but is not always
possible with a double-sided board. In this technique, the
component side of the board is dedicated to ground planes,
while signals are placed on the solder side.

Good decoupling is also important. All analog supplies should
be decoupled with 10 μF tantalum capacitors in parallel with

0.1 μF capacitors to GND. To achieve the best results from these
decoupling components, they must be placed as close as
possible to the device, ideally right up against the device. The

0.1 μF capacitors should have low effective series resistance
(ESR) and effective series inductance (ESI), such as the
common ceramic types or surface-mount types. These low ESR
and ESI capacitors provide a low impedance path to ground at
high frequencies to handle transient currents due to internal
logic switching.

PCB DESIGN GUIDELINES FOR LFCSP

The lands on the chip scale package (CP-32-3) are rectangular.
The PCB pad for these should be 0.1 mm longer than the
package land length, and 0.05 mm wider than the package land
width, thereby having a portion of the pad exposed. To ensure
that the solder joint size is maximized, the land should be
centered on the pad.

The bottom of the chip scale package has a thermal pad. The
thermal pad on the PCB should be at least as large as the
exposed pad. On the PCB, there should be a clearance of at least

0.25 mm between the thermal pad and the inner edges of the
pad pattern to ensure that shorting is avoided.

To improve thermal performance of the package, use thermal
vias on the PCB incorporating them in the thermal pad at

1.2 mm pitch grid. The via diameter should be between 0.3 mm
and 0.33 mm, and the via barrel should be plated with 1 oz.
copper to plug the via. The user should connect the PCB
thermal pad to AGND.

EVALUATING THE AD7266 PERFORMANCE

The recommended layout for the AD7266 is outlined in the
evaluation board documentation. The evaluation board package
includes a fully assembled and tested evaluation board, docu­mentation, and software for controlling the board from the PC
via the evaluation board controller. The evaluation board con­troller can be used in conjunction with the AD7266 evaluation
board, as well as many other Analog Devices, Inc. evaluation
boards ending in the CB designator, to demonstrate/evaluate
the ac and dc performance of the AD7266.

The software allows the user to perform ac (fast Fourier
transform) and dc (histogram of codes) tests on the AD7266.
The software and documentation are on a CD shipped with the
evaluation board.

Rev. B | Page 26 of 28

AD7266

OUTLINE DIMENSIONS

0.08

32

1

8

9

LEAD PITCH

0.60 MAX

25

24

EXPOSED

PAD

(BOTTOM VIEW)

17

16

3.50 REF

9.00 BSC SQ

PIN 1

TOP VIEW

(PINS DOWN)

0.80

BSC

PIN 1

32

9

FORPROPERCONNECTIONOF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.

0.45

0.37

0.30

INDICATOR

1

3.25

3.10 SQ

2.95

8

0.25 MIN

25

24

7.00

BSC SQ

17

16

011708-A

PIN 1

INDICATOR

1.00

0.85

0.80

5.00

BSC SQ

TOP

VIEW

12° MAX

SEATING
PLANE

1.05

1.00

0.95

0.15

SEATING

0.05

PLANE

VIEW A

ROTATED 90° CCW

0.60 MAX

0.50

4.75

BSC SQ

0.80 MAX

0.65 TYP

0.05 MAX

0.30

0.23

0.18

COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2

0.02 NOM

0.20 REF

BSC

0.50

0.40

0.30

COPLANARITY

Figure 47. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

5 mm × 5 mm Body, Very Thin Quad (CP-32-2)

Dimensions shown in millimeters

1.20

0.75
MAX

0.60

0.45

0° MIN

0.20

0.09
7°

3.5°
0°

0.08 MAX
COPLANARITY

VIEW A

COMPLIANT TO JEDEC STANDARDS MS-026-AB A

020607-A

Figure 48. 32-Lead Thin Quad Flat Package [TQFP]

(SU-32-2)

Dimensions shown in millimeters

ORDERING GUIDE

1, 2, 3

Model

AD7266BCPZ –40°C to +125°C 32-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-32-2
AD7266BCPZ-REEL7 –40°C to +125°C 32-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-32-2
AD7266BCPZ-REEL –40°C to +125°C 32-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-32-2
AD7266BSUZ –40°C to +125°C 32-Lead Thin Quad Flat Package (TQFP) SU-32-2
AD7266BSUZ-REEL7 –40°C to +125°C 32-Lead Thin Quad Flat Package (TQFP) SU-32-2
AD7266BSUZ-REEL –40°C to +125°C 32-Lead Thin Quad Flat Package (TQFP) SU-32-2
EVAL-AD7266EDZ
EVAL-CED1Z

1

Z = RoHS Compliant Part.

2

The EVAL-AD7266CB can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL Board for evaluation/demonstration purposes.

3

The EVAL-CED1Z controller board allows a PC to control and communicate with all Analog Devices evaluation boards whose model numbers end in ED.

Temperature Range Package Description Package Option

Evaluation Board
Control Board

Rev. B | Page 27 of 28

AD7266

NOTES

©2005–2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04603-0-5/11(B)

Rev. B | Page 28 of 28