Datasheet AD712 Datasheet (ANALOG DEVICES)

Dual Precision, Low Cost,

A

www.BDTIC.com/ADI

FEATURES

Enhanced replacement for LF412 and TL082 AC performance

Settles to ±0.01% in 1.0 μs 16 V/μs minimum slew rate (AD712J) 3 MHz minimum unity-gain bandwidth (AD712J)

DC performance

200 V/mV minimum open-loop gain (AD712K) Surface mount available in tape and reel in

cordance with the EIA-481A standard

ac MIL-STD-883B parts available Single version available: AD711 Quad version: AD713 Available in PDIP, SOIC_N, and CERDIP packages

GENERAL DESCRIPTION

The AD712 is a high speed, precision, monolithic operational amplifier offering high performance at very modest prices. Its very low offset voltage and offset voltage drift are the results of advanced laser wafer trimming technology. These performance benefits allow the user to easily upgrade existing designs that use older precision BiFETs and, in many cases, bipolar op amps.

The superior ac and dc performance of this op amp makes it s

uitable for active filter applications. With a slew rate of 16 V/µs and a settling time of 1 µs to ±0.01%, the AD712 is ideal as a buffer for 12-bit digital-to-analog and analog-to-digital converters and as a high speed integrator. The settling time is unmatched by any similar IC amplifier.

The combination of excellent noise performance and low input c

urrent also make the AD712 useful for photo diode preamps. Common-mode rejection of 88 dB and open-loop gain of 400 V/mV ensure 12-bit performance even in high speed unity-gain buffer circuits.

The AD712 is pinned out in a standard op amp configuration

nd is available in seven performance grades. The AD712J and

a AD712K are rated over the commercial temperature range of 0°C to 70°C. The AD712A is rated over the industrial temperature range of −40°C to +85°C. The AD712S is rated over the

High Speed BiFET Op Amp

AD712

CONNECTION DIAGRAM

MPLIFIER NO. 1

OUTPUT

INVERTING

NONINVERTI NG

SOIC_

1

2

INPUT

3

INPUT

V–

4

AD712

Figure 1. 8-Lead PDIP (N-Suffix),

N (R-Suffix), and CERDIP (Q-Suffix)

military temperature range of −55°C to +125°C and is available processed to MIL-STD-883B, Rev. C.

Extended reliability PLUS screening is available, specified over t

he commercial and industrial temperature ranges. PLUS screening includes 168-hour burn-in, in addition to other environmental and physical tests.

The AD712 is available in 8-lead PDIP, SOIC_N, and CERDIP pa

ckages.

PRODUCT HIGHLIGHTS

1. The AD712 offers excellent overall performance at very

competitive prices.

2. The Analog Devices, Inc. advanced processing technology

a

nd 100% testing guarantee a low input offset voltage (3 mV maximum, J grade). Input offset voltage is specified in the warmed-up condition.

3. Together with precision dc performance, the AD712 offers exce

llent dynamic response. It settles to ±0.01% in 1 µs and has a minimum slew rate of 16 V/µs. Thus, this device is ideal for applications such as DAC and ADC buffers that require a combination of superior ac and dc performance.

AMPLIFIER NO. 2

8

V+

OUTPUT

7

INVERTING

6

INPUT

NONINVERTI NG

5

INPUT

00823-001

Rev. G

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

AD712

www.BDTIC.com/ADI

REVISION HISTORY

Digital-to-Analog Converter Applications ............................. 14

Noise Characteristics ................................................................. 15

Driving the Analog Input of an

Analog-to-Digital Converter .................................................... 15

Driving a Large Capacitive Load.............................................. 16

Filters ................................................................................................ 17

Active Filter Applications.......................................................... 17

Second-Order Low-Pass Filter.................................................. 17

9-Pole Chebychev Filter............................................................. 18

Outline Dimensions ....................................................................... 19

Ordering Guide .......................................................................... 20

8/06—Rev. F to Rev. G

Edits to Figure 1................................................................................ 1

Change to 9-Pole Chebychev Filter Section................................ 18

6/06—Rev. E to Rev. F

Updated Format..................................................................Universal

Deleted B, C, and T Models...............................................Universal

Changes to General Description .................................................... 1

Changes to Product Highlights....................................................... 1

Changes to Specifications Section.................................................. 3

Changes to Figure 43...................................................................... 15

7/02—Rev. D to Rev. E

Edits to Features.................................................................................1

9/01—Rev. C to Rev. D

Edits to Features.................................................................................1

Edits to General Description ...........................................................1

Edits to Connection Diagram..........................................................1

Edits to Ordering Guide...................................................................3

Deleted Metalization Photograph...................................................3

Edits to Absolute Maximum Ratings .............................................3

Edits to Figure 7.................................................................................9

Edits to Outline Dimensions......................................................... 15

Rev. G | Page 2 of 20

AD712

www.BDTIC.com/ADI

SPECIFICATIONS

VS = ±15 V @ TA = 25°C, unless otherwise noted. Specifications in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. All min and max specifications are guaranteed, although only those shown in boldface are tested on all production units.

Table 1.

AD712J/A/S AD712K Parameter Min Typ Max Min Typ Max Unit

INPUT OFFSET VOLTAGE1

Initial Offset

T

to T

MIN

to T

MIN

MAX

to T

MAX

0.6/1.6/26 1.7/4.8/77 0.5 1.7 nA

MAX

0.3/0.7/11 0.6/1.6/26 0.1 0.6 nA

MAX

to T

MAX

to T

MAX

MIN

vs. Temp 7 vs. Supply

T

Long-Term Offset Stability 15 15 µV/month

INPUT BIAS CURRENT2

VCM = 0 V VCM = 0 V @ T VCM = ±10 V

INPUT OFFSET CURRENT

VCM = 0 V VCM = 0 V @ T

MATCHING CHARACTERISTICS

Input Offset Voltage

T

MIN

Input Offset Voltage Drift Input Bias Current Crosstalk

@ f = 1 kHz 120 120 dB @ f = 100 kHz 90 90 dB

FREQUENCY RESPONSE

Small Signal Bandwidth 3.0 4.0 3.4 4.0 MHz Full Power Response 200 200 kHz Slew Rate Settling Time to 0.01% 1.0 1.2 1.0 1.2 µs Total Harmonic Distortion 0.0003 0.0003 %

INPUT IMPEDANCE

Differential 3×1012||5.5 3×1012||5.5 Ω||pF Common Mode 3×1012||5.5 3×1012||5.5 Ω||pF

INPUT VOLTAGE RANGE

Differential3 ±20 ±20 V Common-Mode Voltage4 +14.5, −11.5 +14.5, −11.5 V

T

MIN

Common-Mode Rejection Ratio

VCM = ±10 V

T

VCM = ±11 V

T INPUT VOLTAGE NOISE 2 2 µV p-p 45 45 nV/√Hz 22 22 nV/√Hz 18 18 nV/√Hz 16 16 nV/√Hz

0.3

76

76/76/76

25

10

16

−V

76 76/76/76 70 70/70/70

+ 4

S

95

20

88 84 84 80

3/1/1

4/2/2 20/20/20

75

100

25

3/1/1

4/2/2 20/20/20

25

+VS − 2 −VS + 4

Rev. G | Page 3 of 20

0.2

7

80 80

20

5

18

80 80 76 74

100 dB dB

20 V/µs

88 dB 84 dB 84 dB 80 dB

1.0

2.0 10

75

100

25

1.0

2.0 10 25

+VS − 2

mV mV V/°C

pA

mV mV µV/°C pA

V

AD712

www.BDTIC.com/ADI

AD712J/A/S AD712K Parameter Min Typ Max Min Typ Max Unit

INPUT CURRENT NOISE 0.01 0.01 pA/√Hz OPEN-LOOP GAIN

OUTPUT CHARACTERISTICS

Voltage

Current +25 +25 mA

POWER SUPPLY

Rated Performance ±15 ±15 V Operating Range Quiescent Current

1

Input offset voltage specifications are guaranteed after 5 minutes of operation at TA = 25°C.

2

Bias current specifications are guaranteed maximum at either input after 5 minutes of operation at TA = 25°C. For higher temperatures, the current doubles every 10°C.

3

Defined as voltage between inputs, such that neither exceeds ±10 V from ground.

4

Typically exceeding −14.1 V negative common-mode voltage on either input results in an output phase reversal.

150 100/100/100

+13, −12.5 ±12/±12/±12

±4.5

+5.0

400

+13.9, −13.3 +13.8, −13.1

±18 ±4.5 +6.8

200 100

+13, −12.5 ±12

+5.0

400 V/mV V/mV

+13.9, −13.3 V +13.8, −13.1 V

±18 +6.0

V mA

Rev. G | Page 4 of 20

AD712

www.BDTIC.com/ADI

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

Supply Voltage ±18 V Internal Power Dissipation Input Voltage Output Short-Circuit Duration Indefinite Differential Input Voltage +VS and −V Storage Temperature Range

Q-Suffix −65°C to +150°C N-Suffix and R-Suffix −65°C to +125°C

Operating Temperature Range

AD712J/K 0°C to 70°C AD712A −40°C to +85°C AD712S −55°C to +125°C

Lead Temperature Range (Soldering 60 sec) 300°C

1

Thermal characteristics:

8-lead PDIP package: θJA = 165°C/W 8-lead CERDIP package: θJC = 22°C/W; θJA = 110°C/W 8-lead SOIC package: θJA = 100°C/W

2

For supply voltages less than ±18 V, the absolute maximum voltage is equal

to the supply voltage.

2

1

±18 V

S

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Rev. G | Page 5 of 20

AD712

V

www.BDTIC.com/ADI

TYPICAL PERFORMANCE CHARACTERISTICS

20

6

15

10

= 2kΩ

R

L

25°C

5

INPUT VOLTAGE SWING (V)

0

0510

SUPPLY VOLTAGE ± V

Figure 2. Input Voltage Swing vs. Supply Voltage

20

15

10

5

OUTPUT VOLTAGE SWING (V)

0

05

SUPPLY VOLTAGE ± V

+V

OUT

RL= 2kΩ 25°C

10 15 20

Figure 3. Output Voltage Swing vs. Supply Voltage

15 20

–V

OUT

5

4

3

QUIESCENT CURRENT (mA)

2

0 5 10 15 20

00823-002

SUPPLY VOLTAGE ± V

00823-005

Figure 5. Quiescent Current vs. Supply Voltage

6

10

7

10

8

= 0) (Amps)

10

CM

9

10

11

10

INPUT BIAS CURRENT (

12

10

–40 –20

00823-003

–60

0 20 40 60 80 100 120 140

TEMPERATURE (° C)

0823-006

Figure 6. Input Bias Current vs. Temperature

30

25

20

±15V SUPPLIES

15

10

OUTPUT VO LTAGE SW ING (V p -p)

5

0

10 100 1k 10k

LOAD RESISTANCE (Ω)

0823-004

Figure 4. Output Voltage Swing vs. Load Resistance

100

OUTPUT IMPEDANCE (Ω)

0.01

1.0

0.1

10

1k

Figure 7. Output Impedan

10k 100k 1M 10M

FREQUENCY (Hz)

Rev. G | Page 6 of 20

ce vs. Frequency

0823-007

AD712

www.BDTIC.com/ADI

100

MAX J GRADE LIMIT

75

= 15V

V

S

50

25

INPUT BIAS CURRENT (pA)

0 –10

–5 0 5 10

COMMON MODE VO LTAGE ( V)

25°C

Figure 8. Input Bias Current vs. Common-Mode Voltage

26

24

22

20

18

16

14

SHORT-CIRCUIT CURRENT LIMI T (mA)

12

– OUTPUT CURRENT

+ OUTPUT CURRENT

80

60

40

20

OPEN-LOOP GAIN (dB)

0

–20

10 100 1k 10k 100k 1M 10M

00823-008

GAIN PHASE 2kΩ 100pF LOAD

FREQUENCY (Hz)

80

60

40

20

0

–20

PHASE MARGIN ( Degrees)

0823-011

Figure 11. Open-Loop Gain and Phase Margin vs. Frequency

125

120

115

= 2kΩ

R

L

110

105

OPEN-LOOP GAIN (dB)

100

25°C

10

–60

–40 –20 0 20 40 60 80 100 120 140

AMBIENT TEMPERATURE (°C)

Figure 9. Short-Circuit Current Limit vs. Temperature

5.0

4.5

4.0

3.5

UNITY-GAIN BANDWIDTH (MHz)

3.0

–40 –20 0 20 40 60 80 100 120 140

–60

TEMPERATURE (°C)

Figure 10. Unity-Gain Bandwidth vs. Temperature

95

0 5 10 15 20

00823-009

SUPPLY VOLTAGE ± V

00823-012

Figure 12. Open-Loop Gain vs. Supply Voltage

110

100

80

60

40

POWER SUPPLY REJECTI ON (dB)

20

VS = ±15V SUPPLIES WITH 1V p-p SINEWAVE 25°C

0

10 100 1k 10k 100k 1M

00823-010

SUPPLY MODUL ATION FREQUENCY (Hz)

Figure 13. Power Supply R

+ SUPPLY

– SUPPLY

ejection vs. Frequency

00823-013

Rev. G | Page 7 of 20

AD712

–

√

www.BDTIC.com/ADI

100

80

60

CMR (dB)

40

VS = ±15V

= 1V p-p

V

CM

25°C

THD (dB)

–80

–90

–100

–110

70

3V rms R

= 2kΩ

L

C

= 100pF

L

20

0

10 100 1k 10k 100k 1M

FREQUENCY (Hz)

Figure 14. Common-Mode Rejection vs. Frequency

30

25

20

15

10

OUTPUT VOLTAGE SWING (V p-p)

5

0

100k 1M 10M

FREQUENCY (Hz)

RL= 2kΩ 25°C

V

= ±15V

S

Figure 15. Large Signal Frequency Response

10

8

6

4

OUTPUT SWING FROM 0V TO ±VOLTS

–10

2

0

–2

–4

–6

–8

0.5

0.6 0.7

0.01%0.1%1%

0.1%1%ERROR

0.01%

SETTLING TIME (µs)

0.8 0.9 1.0

Figure 16. Output Swing and Error vs. Settling Time

–120

–130

100 1k 10k 100k

00823-014

FREQUENCY (Hz)

00823-017

Figure 17. Total Harmonic Distortion vs. Frequency

1k

Hz)

100

10

INPUT NOISE VOLTAGE (nV/

1

00823-015

10 100 1k 10k 100k1

FREQUENCY (Hz)

0823-018

Figure 18. Input Noise Voltage Spectral Density

25

20

15

10

SLEW RATE (V/µ s)

5

0

0 100 2 00 300 400 500 600 700 800 900

00823-016

INPUT ERROR SI GNAL (mV)

(AT SUM MING JUNCTIO N)

00823-019

Figure 19. Slew Rate vs. Input Error Signal

Rev. G | Page 8 of 20

AD712

V

www.BDTIC.com/ADI

25

+V

S

0.1µF

–

20

SLEW RATE (V/µs)

15

–60 –40 –20

0 20 40 60 80 100 120 140

TEMPERATURE ( °C)

Figure 20. Slew Rate vs. Temperature

+

S

0.1µF

8

1/2

AD712

+

IN

SQUARE WAVE INPUT

0823-020

4

0.1µF

–V

S

R 2kΩ

Figure 23. Unity-Gain Follower

V

OUT

C

L

100pF

00823-023

INPUT

–

2

20V p-p

CROSSTALK = 20 log

AD712

+

3

V

IN

8

+

1/2

AD712

–

4

0.1µF

–V

S

2kΩ

Figure 21. THD Test Circuit

OUT

+V

S

8

1/2

1

5kΩ 5kΩ

V

OUT

10V

IN

20kΩ 2.2kΩ

1/2

7

AD712

4

–V

S

Figure 22. Crosstalk Test Circuit

100

90

OUTPUT

100pF

0823-021

10

0%

5V

1µs

00823-024

Figure 24. Unity-Gain Follower Pulse Response (Large Signal)

100

90

–

6

5

+

0823-022

10

0%

50mV

100ns

00823-025

Figure 25. Unity-Gain Follower Pulse Response (Small Signal)

Rev. G | Page 9 of 20

AD712

V

www.BDTIC.com/ADI

5kΩ

+V

S

5kΩ

IN

SQUARE WAVE INPUT

0.1µF

–

8

1/2

AD712

+

4

0.1µF

–V

S

R 2kΩ

Figure 26. Unity-Gain Inverter

V

OUT

C

L

100pF

00823-026

100

90

10

0%

50mV

200ns

Figure 28. Unity-Gain Inverter Pulse Response (Small Signal)

0823-028

100

90

10

0%

5V

1µs

Figure 27. Unity-Gain Inverter Pulse Response (Large Signal)

00823-027

Rev. G | Page 10 of 20

AD712

F

www.BDTIC.com/ADI

SETTLING TIME

OPTIMIZING SETTLING TIME

Most bipolar high speed digital-to-analog converters (DACs) have current outputs; therefore, for most applications, an external op amp is required for a current-to-voltage conversion. The settling time of the converter/op amp combination depends on the settling time of the DAC and output amplifier. A good approximation is

22

()(

+=

The settling time of an op amp DAC buffer varies with the noise gain of the circuit, the DAC output capacitance, and the amount of external compensation capacitance across the DAC output scaling resistor.

Settling time for a bipolar DAC is typically 100 ns to 500 ns. P

reviously, conventional op amps have required much longer settling times than have typical state-of-the-art DACs; therefore, the amplifier settling time has been the major limitation to a high speed, voltage output, digital-to-analog function. The introduction of the AD71x family of op amps with their 1 s (to ±0.01% of final value) settling time permits the full high speed capabilities of most modern DACs to be realized.

R2 100Ω

GAIN

ADJUST

REF

IN

REF

GND

SSS

AMPtDACtTotalt

+

–

REF OUT

19.95kΩ

)

0.1µ

10V

0.5mA

I

REF

20kΩ

V

CC

R1

100Ω

AD565A

BIPOLAR OFFSET ADJUST

BIPOL AR

9.95kΩ

DAC

I

= 4 ×

OUT

I

× CODE

REF

OFF

In addition to a significant improvement in settling time, the lo

w offset voltage, low offset voltage drift, and high open-loop gain of the AD71x family assure 12-bit accuracy over the full operating temperature range.

The excellent high speed performance of the AD712 is shown in th

e oscilloscope photos in Figure 30 and Figure 31. Measurements were taken using a low input capacitance amplifier connected directly to the summing junction of the AD712 and both figures show a worst-case situation: full-scale input transition. The 4 kΩ [10 kΩ||8 kΩ = 4.4 kΩ] output impedance of the DAC, together with a 10 kΩ feedback resistor, produce an op amp noise gain of 3.25. The current output from the DAC produces a 10 V step at the op amp output (0 to −10 V shown in Figure 30, and −10 V to 0 V shown in Figure 31).

Therefore, with an ideal op amp, settling to ±1/2 LSB (±0.01%)

equires that 375 µV or less appears at the summing junction.

r This means that the error between the input and output (that voltage which appears at the AD712 summing junction) must be less than 375 µV. As shown in

e for the AD712/AD565A combination is 1.2 microseconds.

tim

Figure 30, the total settling

20V SPAN

5kΩ

10V SPAN

5kΩ

DAC OUT

I

8kΩ

O

10pF

+15V

–

1/2

AD712

+

0.1µF

8

OUTPUT –10V TO +10V

4

0.1µF

–V

0.1µF

POWER

EE

GND

MSB LSB

Figure 29. ±10 V Voltage Output Bipolar DAC

–15V

Rev. G | Page 11 of 20

0823-029

AD712

–10V

(

www.BDTIC.com/ADI

5V1mV

100

90

SUMMING

JUNCTION

O

= unity-gain frequency of the op amp.

πω2

⎛

= noise gain of circuit

G

N

R

⎜

1

+

⎜

R

⎝

⎞

.

⎟ ⎟

O

⎠

Where

0V

10

0%

–10V

Figure 30. Settling Characteristics for AD712 with AD565A,

100

90

0V

10

0%

Figure 31. Settling Characteristics for AD712 with AD565A,

Ful

l-Scale Negative Transition

SUMMING

JUNCTION

OUTPUT

Ful

l-Scale Positive Transition

OUTPUT

500ns

5V1mV

500ns

0823-030

00823-031

OP AMP SETTLING TIME—A MATHEMATICAL MODEL

The design of the AD712 gives careful attention to optimizing individual circuit components; in addition, a careful trade-off was made: the gain bandwidth product (4 MHz) and slew rate (20 V/µs) were chosen to be high enough to provide very fast settling time but not too high to cause a significant reduction in phase margin (and therefore, stability). Thus designed, the AD712 settles to ±0.01%, with a 10 V output step, in under 1 µs, while retaining the ability to drive a 250 pF load capacitance when operating as a unity-gain follower.

If an op amp is modeled as an ideal integrator with a unity-gain

ossover frequency of ω

cr describes the small signal behavior of the circuit of Figure 32,

nsisting of an op amp connected as an I-to-V converter at the

co output of a bipolar or CMOS DAC. This equation would completely describe the output of the system if not for the finite slew rate and other nonlinear effects of the op amp.

V

O

=

I

IN

)(

CR

X

ω

O

/2π, then Equation 1 accurately

O

−

R

⎛

G

2

N

⎜

+

s

⎜

ω

O

⎝

(1)

⎞ ⎟

1

+

sRC

f

⎟ ⎠

This equation can then be solved for C

−

G

2

N

=

C

X

2

+

R

ω

O

1

X

O

R

ω

O

In these equations, Capacitance C

f

)

−+ω

GRC

N

(2)

is the total capacitance

X

appearing at the inverting terminal of the op amp. When modeling a DAC buffer application, the Norton equivalent circuit shown in

Figure 32 can be used directly; Capacitance C is the total capacitance of the output of the DAC plus the input capacitance of the op amp (because the two are in parallel).

+

1/2

AD712

–

I

ORO

Figure 32. Simplified Model of the AD712 Used as a Current-Out DAC Buffer

C

X

RLC

C

F

R

V

OUT

L

00823-032

When RO and IO are replaced with their Thevenin VIN and RIN equivalents, the general-purpose inverting amplifier shown in Figure 33 is created. Note that when using this general model, Ca

pacitance C

is either the input capacitance of the op amp, if

X

a simple inverting op amp is being simulated, or the combined capacitance of the DAC output and the op amp input if the DAC buffer is being modeled.

+

1/2

AD712

–

R

IN

V

IN

Figure 33. Simplified Model of the AD712 Used as an Inverter

C

X

RLC

C

F

R

V

OUT

L

00823-033

In either case, Capacitance CX causes the system to go from a one-pole to a two-pole response; this additional pole increases settling time by introducing peaking or ringing in the op amp output. Because the value of C

can be estimated with reasonable

X

accuracy, Equation 2 can be used to choose a small capacitor (C

) to cancel the input pole and optimize amplifier response.

F

Figure 34 is a graphical solution of Equation 2 for the AD712

th R = 4 kΩ.

wi

X

Rev. G | Page 12 of 20

AD712

www.BDTIC.com/ADI

60

50

40

X

30

C

20

10

GN= 4.0

G

= 3.0

N

0

100

Figure 34. Value of Capacitor C

GN= 2.0

G

= 1.5

N

G

= 1.0

N

20 30 40 50

C

F

vs. Value of C

F

60

00823-034

X

5V

100

90

10

0%

5mV

500ns

Figure 36. Settling Characteristics 0 V to −10 V Step U

pper Trace: Output of AD712 Under Test (5 V/Div)

Lower Trace: Amplified Error Voltage (0.01%/Div)

00823-036

The photos of Figure 35 and Figure 36 show the dynamic response of the AD712 in the settling test circuit of Figure 37.

5V

100

90

10

0%

5mV

500ns

00823-035

Figure 35. Settling Characteristics 0 V to +10 V Step

Upper Tr

ace: Output of AD712 Under Test (5 V/Div)

Lower Trace: Amplified Error Voltage (0.01%/Div)

HP2835

DATA

DYNAMICS

5109

(OR EQUIVAL ENT FLAT TOP PULSE GENERATION)

4.99kΩ

V

IN

10kΩ

0.1µF

200Ω

10kΩ

–

1/2

AD712

+

4.99kΩ

5 TO 18pF

0.1µF

5kΩ

The input of the settling time fixture is driven by a flat top pulse generator. The error signal output from the false summing node of A1 is clamped, amplified by A2, and then clamped again. The error signal is thus clamped twice: once to prevent overloading Amplifier A2 and then a second time to avoid overloading the oscilloscope preamp. The Tektronix oscilloscope preamp type 7A26 was carefully chosen because it does not overload with these input levels. Amplifier A2 needs to be a very high speed FET-input op amp; it provides a gain of 10, amplifying the error signal output of A1.

0.47µF

–15V +15V

1.1kΩ

10pF

+

1/2

A

D

7

–

V

OUT

5pF

1

2

0.47µF

10kΩ

0.2 TO 0. 6pF

205Ω

V

ERROR

×

HP2835

TEKTRONI X 7A26 OSCILLOSCOPE PREAMP

5

INPUT SECTION

1MΩ

20pF

+15V

–15V

Figure 37. Settling Time Test Circuit

Rev. G | Page 13 of 20

0823-037

AD712

V

www.BDTIC.com/ADI

APPLICATIONS INFORMATION

GUARDING

The low input bias current (15 pA) and low noise characteristics of the AD712 BiFET op amp make it suitable for electrometer applications such as photo diode preamplifiers and picoampere current-to-voltage converters. The use of a guarding technique, such as that shown in

nd construction is critical to minimize leakage currents. The

a guard ring is connected to a low impedance potential at the same level as the inputs. High impedance signal lines should not be extended for any unnecessary length on the printed circuit board.

Figure 38. Board Layout for Guarding Inputs

DIGITAL-TO-ANALOG CONVERTER APPLICATIONS

The AD712 is an excellent output amplifier for CMOS DACs. It can be used to perform both 2-quadrant and 4-quadrant operations. The output impedance of a DAC using an inverted R-2R ladder approaches R for codes containing many 1s, and 3R for codes containing a single 1. For codes containing all 0s, the output impedance is infinite.

For example, the output resistance of the AD7545 modulates betw

een 11 kΩ and 33 kΩ. Therefore, with an 11 kΩ DAC internal feedback resistance, the noise gain varies from 2 to 4/3. This changing noise gain modulates the effect of the input offset voltage of the amplifier, resulting in nonlinear DAC amplifier performance.

The AD712K with guaranteed 700 V offset voltage minimizes t

his effect to achieve 12-bit performance.

Figure 38, in printed circuit board layout

PDIP (N), CERDIP (Q),

AND SOIC (R) PACKAGES.

4

3 2

1

5

6

7

8

00823-038

Figure 39 and Figure 40 show the AD712 and AD7545 (12-bit CMOS D

AC) configured for unipolar binary (2-quadrant multiplication) or bipolar (4-quadrant multiplication) operation. Capacitor C1 provides phase compensation to reduce overshoot and ringing.

R

DGND

R

DGND

FB

OUT1

AGND

FB

OUT1

AGND

R2A*

R2B*

C1A 33pF

ANALOG

COMMON

C1B 33pF

ANALOG

COMMON

+15V

–

1/2

AD712

+

–

1/2

AD712

+

–15V

0.1µF

V

OUTA

OUTB

V

IN

*REFER TO TABLE 3

V

IN

*REFER TO TABLE 3

GAIN

ADJUST

R1A*

GAIN

ADJUST

R1B*

DD

V

DD

AD7545

V

REF

DB11 TO DB0

V

DD

V

DD

AD7545

V

REF

DB11 TO DB0

Figure 39. Unipolar Binary Operation

R1 and R2 calibrate the zero offset and gain error of the DAC. Specific values for these resistors depend upon the grade of AD7545 and are listed in Table 3.

Table 3. Recommended Trim Resistor Values vs. Grades the AD7545 for V

= 5 V

DD

of

Trim Resistor JN/AQ KN/BQ LN GLN

R1 500 Ω 200 Ω 100 Ω 20 Ω R2 150 Ω 68 Ω 33 Ω 6.8 Ω

00823-039

GAIN

ADJUST

V

IN

*FOR VALUES OF R1 AND R2 SEE TABLE 3

R1*

V

DD

V

DD

AD7545

V

REF

DB11 TO DB0

12

DATA INPUT

R

FB

DGND

OUT1

AGND

R2*

C1 33pF

–

+

ANALOG COMMON

+15V

1/2

AD712

0.1µF

R3

10kΩ 1%

R4 20kΩ 1%

–

AD712

+

R5

20kΩ 1%

1/2

0.1µF

–15V

Figure 40. Bipolar Operation

Rev. G | Page 14 of 20

V

OUT

00823-040

AD712

A

www.BDTIC.com/ADI

Figure 41 and Figure 42 show the settling time characteristics of the AD712 when used as a DAC output buffer for the AD7545.

1mV

100

90

10

0%

5V

Figure 41. Positive Settling Characteristics for AD712 with AD7545

500ns

00823-041

DRIVING THE ANALOG INPUT OF AN ANALOG-TO-DIGITAL CONVERTER

An op amp driving the analog input of an ADC, such as that shown in Figure 43, must be capable of maintaining a constant

voltage under dynamically changing load conditions. In

output successive approximation converters, the input current is compared to a series of switched trial currents. The comparison point is diode clamped, but can deviate several hundred millivolts resulting in high frequency modulation of analog-to-digital input current. The output impedance of a feedback amplifier is made artificially low by the loop gain. At high frequencies, where the loop gain is low, the amplifier output impedance can approach its open-loop value. Most IC amplifiers exhibit a minimum open-loop output impedance of 25 Ω due to currentlimiting resistors.

1mV

100

90

10

0%

5V

500ns

00823-042

Figure 42. Negative Settling Characteristics for AD712 with AD7545

NOISE CHARACTERISTICS

The random nature of noise, particularly in the flicker noise region, makes it difficult to specify in practical terms. At the same time, designers of precision instrumentation require certain guaranteed maximum noise levels to realize the full accuracy of their equipment. All grades of the AD712 are sample tested on an AQL basis to a limit of 6 µV p-p, 0.1 Hz to 10 Hz.

±10V

NALOG

INPUT

+15V

–

1/2

AD712

+

–15V

0.1µF

GAIN

ADJUST

R2

100Ω

R1

100Ω

OFFSET ADJUST

ANALOG COM

12/8

CS

A

O

R/C CE

REF IN

REF OUT

BIP OFF

10V

IN

20V

IN

AC DC

AD574A

MIDDLE

STS

HIGH

BITS

LOW

BITS

+5V

+15V

–15V

Figure 43. AD712 as An ADC Unity-Gain Buffer

A few hundred microamps reflected from the change in converter loading can introduce errors in instantaneous input voltage. If the analog-to-digital conversion speed is not excessive and the bandwidth of the amplifier is sufficient, the amplifier output returns to the nominal value before the converter makes its comparison. However, many amplifiers have relatively narrow bandwidth yielding slow recovery from output transients. The AD712 is ideally suited to drive high speed analog-to-digital converters because it offers both wide bandwidth and high open-loop gain.

00823-043

Rev. G | Page 15 of 20

AD712

www.BDTIC.com/ADI

1mV

100

90

10

0%

500mV

Figure 44. ADC Input Unity Gain Buffer Recovery Times, −10 V ADC IN

1mV

100

90

10

0%

500mV

Figure 45. ADC Input Unity Gain Buffer Recovery Times, −5 V ADC IN

PD711 BUFF

–10V ADC IN

PD711 BUFF

–5V ADC IN

200ns

DRIVING A LARGE CAPACITIVE LOAD

The circuit in Figure 46 uses a 100 Ω isolation resistor that enables the amplifier to drive capacitive loads exceeding 1500 pF; the resistor effectively isolates the high frequency feedback from the load and stabilizes the circuit. Low frequency feedback is returned to the amplifier summing junction via the low-pass filter formed by the 100 Ω series resistor and the Load Capacitance C this connection.

00823-044

INPUT

TYPICAL CAPACI TANCE LIMIT FOR VARIOUS LOAD RESISTORS

R

1

2kΩ 1500pF 10kΩ 1500pF 20Ω 1000pF

00823-045

100

. Figure 47 shows a typical transient response for

L

4.99kΩ

30pF

+V

IN

0.1µF +

–

4.99kΩ

C

1

UP TO

–

1/2

AD712

+

–V

IN

0.1µF

–

100Ω

C1 R1

+

Figure 46. Circuit for Driving a Large Capacitive Load

5V

90

1µs

OUTPUT

00823-046

Rev. G | Page 16 of 20

10

0%

Figure 47. Transient Response R

= 2 kΩ, CL = 500 pF

L

00823-047

AD712

www.BDTIC.com/ADI

FILTERS

R2

20kΩ

C2

C1

560pF

+15V

+

1/2

AD712

–

–15V

AD712

0.1µF

OFFSET .0 Hz

0dB

V

OUT

00823-048

ACTIVE FILTER APPLICATIONS

In active filter applications using op amps, the dc accuracy of the amplifier is critical to optimal filter performance. The amplifier offset voltage and bias current contribute to output error. Offset voltage is passed by the filter and can be amplified to produce excessive output offset. For low frequency applications requiring large value input resistors, bias currents flowing through these resistors also generate an offset voltage.

In addition, at higher frequencies, the op amp dynamics must

carefully considered. Here, slew rate, bandwidth, and open-

be loop gain play a major role in op amp selection. The slew rate must be fast as well as symmetrical to minimize distortion. The amplifier bandwidth in conjunction with the filter gain dictates the frequency response of the filter.

The use of a high performance amplifier such as the AD712 mini

mizes both dc and ac errors in all active filter applications.

SECOND-ORDER LOW-PASS FILTER

Figure 48 depicts the AD712 configured as a second-order, Butterworth low-pass filter. With the values as shown, the corner frequency is 20 kHz; however, the wide bandwidth of the AD712 permits a corner frequency as high as several hundred kilohertz. Equations for component selection are as follows:

R1 = R2 = A user selected va

C1 (in farads) =

2RfC

=

()

π

()

π

707.0

()

12

cutoff

lue (10 kΩ to 100 kΩ, typical)

414.1

()

cutoff

()

12

Rf

R1

20kΩ

V

280pF

IN

Figure 48. Second-Order Low-Pass Filter

An important property of filters is their out-of-band rejection. The simple 20 kHz low-pass filter shown in Figure 48, can be us

ed to condition a signal contaminated with clock pulses or sampling glitches that have considerable energy content at high frequencies.

The low output impedance and high bandwidth of the AD712 m

inimize high frequency feedthrough as shown in Figure 49.

he upper trace is that of another low cost BiFET op amp

T showing 17 dB more feedthrough at 5 MHz.

REF 20.0 dBm 10dB/DIV RANGE 15.0dBm

TYPICAL BI FET

CENTER 5 000 000.0Hz RBW 30kHz

Figure 49. High Frequency Feedthrough

Rev. G | Page 17 of 20

VBW 30kHz

SPAN 10 000 000.0Hz

ST .8 SEC

00823-049

AD712

V

www.BDTIC.com/ADI

+15

0.1µF

IN

+

A1

0.001µF

2800Ω 6190Ω 6490Ω 6190Ω 2800Ω

AD711 –

0.1µF

–15V

100kΩ

4.9395E

–15

A

*

5.9276E

SEE TEXT

*

–15

5.9276E

B

*

C

*

4.9395E

–15

D

++++

*

0.001µF

124kΩ

+15V

+

A2

AD711

–

–15V

0.1µF

V

4.99kΩ

OUT

00823-050

Figure 50. 9-Pole Chebychev Filter

9-POLE CHEBYCHEV FILTER

Figure 50 and Figure 51 show the AD712 and its dual counterpart, the AD711, as a 9-pole Chebychev filter using active frequency dependent negative resistors (FDNRs). With a cutoff frequency of 50 kHz and better than 90 dB rejection, it can be used as an antialiasing filter for a 12-bit data acquisition system with 100 kHz throughput.

As shown in Figure 50, the filter is comprised of four FDNRs (A, B

, C, D) having values of 4.9395 × 10 farad-seconds. Each FDNR active network provides a two-pole response for a total of eight poles. The ninth pole consists of a

0.001 F capacitor and a 124 kΩ resistor at Pin 3 of Amplifier A2. Figure 51 depicts the circuits for each FDNR with the proper

election of R. To achieve optimal performance, the 0.001 µF

s capacitors must be selected for 1% or better matching and all resistors should have 1% or better tolerance.

−15

and 5.9276 × 10

–15

+

0.001µF

R

–

1/2

AD712

+

R: 24.9kΩ FOR 4.9395E

29.4kΩ FOR 5.9276E

Figure 51. FDNR for 9-P

REF 5.0dBm 10dB/DIV RANGE –5.0dBm

–15

0.001µF

1.0kΩ

4.99kΩ

ole Chebychev Filter

+15V

0.1µF

+

1/2

AD712

–

0.1µF

–15V

MARKER 96 800.0Hz

–90dBm

0823-051

START.0Hz RBW 300Hz

Figure 52. High Frequency Respons

Rev. G | Page 18 of 20

STOP 200 000. 0Hz

ST 69.6 SECVBW 30Hz

e for 9-Pole Chebychev Filter

00823-052

AD712

www.BDTIC.com/ADI

OUTLINE DIMENSIONS

0.400 (10.16)

0.365 (9.27)

0.355 (9.02)

8

5

0.280 (7.11)

4

0.250 (6.35)

0.240 (6.10)

0.015 (0.38) MIN

SEATING PLANE

0.005 (0.13) MIN

0.060 (1.52) MAX

0.015 (0.38) GAUGE

PLANE

1

PIN 1

0.100 (2.54)

0.210 (5.33)

MAX

0.150 (3.81)

0.130 (3.30)

0.115 (2.92)

0.022 (0.56)

0.018 (0.46)

0.014 (0.36)

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.

BSC

0.070 (1.78)

0.060 (1.52)

0.045 (1.14)

COMPLIANT TO JEDEC STANDARDS MS-001-BA

Figure 53. 8-Lead Plastic Dual In-Line Package [PDIP]

(N-8)

ensions shown in inches and (millimeters)

Dim

0.325 (8.26)

0.310 (7.87)

0.300 (7.62)

0.430 (10.92) MAX

0.195 (4.95)

0.130 (3.30)

0.115 (2.92)

0.014 (0.36)

0.010 (0.25)

0.008 (0.20)

0.005 (0.13)

0.200 (5.08) MAX

0.200 (5.08)

0.125 (3.18)

0.023 (0.58)

0.014 (0.36)

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

0.055 (1.40)

MIN

0.100 (2.54) BSC

0.405 (10.29) MAX

MAX

58

14

0.070 (1.78)

0.030 (0.76)

0.310 (7.87)

0.220 (5.59)

0.060 (1.52)

0.015 (0.38)

0.150 (3.81) MIN

SEATING PLANE

0.320 (8.13)

0.290 (7.37)

15°

0°

0.015 (0.38)

0.008 (0.20)

Figure 54. 8-Lead Ceramic Dual In-Line Package [CERDIP]

(Q-8)

Dim

ensions shown in inches and (millimeters)

5.00 (0.1968)

4.80 (0.1890)

4.00 (0.1574)

3.80 (0.1497)

0.25 (0.0098)

0.10 (0.0040)

COPLANARITY

0.10

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

85

1.27 (0.0500)

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MS-012-AA

BSC

6.20 (0.2440)

5.80 (0.2284)

41

1.75 (0.0688)

1.35 (0.0532)

0.51 (0.0201)

0.31 (0.0122)

0.25 (0.0098)

0.17 (0.0067)

0.50 (0.0196)

0.25 (0.0099)

8°

1.27 (0.0500)

0°

0.40 (0.0157)

× 45°

Figure 55. 8-Lead Standard Small Outline Package [SOIC_N]

Nar

row Body

(R-8)

Dimensions shown in millimeters and (inches)

Rev. G | Page 19 of 20

AD712

www.BDTIC.com/ADI

ORDERING GUIDE

Model Temperature Range Package Description Package Option

AD712AQ −40°C to +85°C 8-Lead CERDIP Q-8 AD712JN 0°C to 70°C 8-Lead PDIP N-8 AD712JNZ1 0°C to 70°C 8-Lead PDIP N-8 AD712JR 0°C to 70°C 8-Lead SOIC_N R-8 AD712JR-REEL 0°C to 70°C 8-Lead SOIC_N R-8 AD712JR-REEL7 0°C to 70°C 8-Lead SOIC_N R-8 AD712JRZ1 0°C to 70°C 8-Lead SOIC_N R-8 AD712JRZ-REEL1 0°C to 70°C 8-Lead SOIC_N R-8 AD712JRZ-REEL71 0°C to 70°C 8-Lead SOIC_N R-8 AD712KN 0°C to 70°C 8-Lead PDIP N-8 AD712KNZ1 0°C to 70°C 8-Lead PDIP N-8 AD712KR 0°C to 70°C 8-Lead SOIC_N R-8 AD712KR-REEL 0°C to 70°C 8-Lead SOIC_N R-8 AD712KR-REEL7 0°C to 70°C 8-Lead SOIC_N R-8 AD712KRZ1 0°C to 70°C 8-Lead SOIC_N R-8 AD712KRZ-REEL1 0°C to 70°C 8-Lead SOIC_N R-8 AD712KRZ-REEL71 0°C to 70°C 8-Lead SOIC_N R-8 AD712SQ/883B −55°C to +125°C 8-Lead CERDIP Q-8

1

Z = Pb-free part.

C00823-0-8/06(G)

Rev. G | Page 20 of 20

Datasheet AD712 Datasheet (ANALOG DEVICES)

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

GENERAL DESCRIPTION

CONNECTION DIAGRAM

PRODUCT HIGHLIGHTS

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

TYPICAL PERFORMANCE CHARACTERISTICS

SETTLING TIME

OPTIMIZING SETTLING TIME

OP AMP SETTLING TIME—A MATHEMATICAL MODEL

APPLICATIONS INFORMATION

GUARDING

DIGITAL-TO-ANALOG CONVERTER APPLICATIONS

DRIVING THE ANALOG INPUT OF AN ANALOG-TO-DIGITAL CONVERTER

NOISE CHARACTERISTICS

DRIVING A LARGE CAPACITIVE LOAD

FILTERS

ACTIVE FILTER APPLICATIONS

SECOND-ORDER LOW-PASS FILTER

9-POLE CHEBYCHEV FILTER

OUTLINE DIMENSIONS

ORDERING GUIDE