Datasheet AD7011 Datasheet (Analog Devices)

CMOS, ADC p/4 DQPSK

a

FEATURES
Single +5 V Supply

On-Chip p/4 DQPSK Modulator
Modulator Bypass Analog Mode
Root-Raised Cosine Tx Filters, a = 0.35
Two 10-Bit D/A Converters
4th Order Reconstruction Filters
Differential Analog Outputs
On-Chip Ramp Up/Down Power Control
On-Chip Tx Offset Calibration
Dual Mode Operation, Analog and Digital

Very Low Power Dissipation, 30 mW typical
Power Down Mode < 10 mA
On-Chip Voltage Reference
24-Pin SSOP

APPLICATIONS
American Digital Cellular Telephony
American Analog Cellular Telephony

Baseband Transmit Port

AD7011

GENERAL DESCRIPTION

The AD7011 is a complete low power, CMOS, π/4 DQPSK
modulator with single +5 V power supply. The part is designed
to perform the baseband conversion of I and Q transmit wave­forms in accordance with the American Digital Cellular Tele­phone system (TIA IS-54).

The on-chip π/4 Differential Quadrature Phase Shift Keying
(DQPSK) digital modulator, which includes the root raised
cosine filters, generates I and Q data in response to the transmit
data stream. The AD7011 also contains ramp control envelope
logic to shape the I and Q output waveforms when ramping up
or down at the beginning or end of a transmit burst.

Besides providing all the necessary logic to perform π/4 DQPSK
modulation, the part also provides reconstruction filters to
smooth the DAC outputs, providing continuous time analog
outputs. The AD7011 generates differential analog outputs for
both the I and Q signals.

As it is a necessity for all digital mobile systems to use the lowest
possible power, the device has transmit and receive power-down
options. The AD7011 is housed in a space efficient 24-pin
SSOP (Shrink Small Outline Package).

MCLK

BIN (Q DATA)

Tx DATA (I DATA)

Tx CLK (FRAME)

READY

POWER

FUNCTIONAL BLOCK DIAGRAM

DGND

ANALOG MODE

SERIAL

INTERFACE

π /4 DQPSK

DIGITAL

MODULATOR

AD7011

I

Q

I

Q

V

DD

MODULATOR

BYPASS

10-BIT

I-DAC

10-BIT

Q-DAC

V

RECONSTRUCTION

CALIBRATION CIRCUITRY

RECONSTRUCTION

2.46V

REFERENCE

BYPASS

AA

FILTERS

FILTERS

AGND

MODE1

ITx
ITx

QTx
QTx

BOUT

MODE2

REV. B

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reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] Fax: [phone]

AD7011–SPECIFICATIONS

f

= 3.1104 MHz; Analog Mode, f

MCLK

Parameter AD7011ARS Units Test Conditions/Comments

DIGITAL MODE TRANSMIT SPECIFICATIONS

Number of Channels 2 (ITx –
Output Signal Range V
Differential Output Range +V

Signal Vector Magnitude
Error Vector Magnitude

Offset Vector Magnitude
IS-54 Spurious Power

2

2

2

2, 3

@ 30 kHz –35 dB typ
@ 60 kHz –70 dB typ
@ 90 kHz, 120 kHz –75 dB typ

ANALOG MODE SPECIFICATIONS

No. of Channels 2 (ITx –
Resolution 10 Bits
Output Signal Range V
Differential Output Range ±2V

DAC Update Rate 160 kHz MCLK/16; f
SNR 60 dB typ Generating a 10 kHz Sine Wave

Differential Offset Error ±15 mV max Post Calibration
Group Delay Matching Between I & Q Outputs 30 ns typ
Coding Twos Complement
Maximum and Minimum DAC Codes

= 2.56 MHz, POWER = VDD. All specifications are T

MCLK

4

(VAA = VDD = +5 V 6 10%; Test = AGND = DGND = 0 V; Digital Mode,

to T

MIN

unless otherwise noted.)

MAX

ITx) and (QTx – QTx)

+ V

REF

REF

/4 Volts For Each Analog Output

REF

/2 Volts I Channel = (ITx – ITx) and

Q Channel = (QTx –

0.875 ± 7.5% Volts max Measured Differentially
1 % rms typ

2.5 % rms max

0.5 % typ

2.5 % max

–30 dB max
–65 dB max
–70 dB max

ITx) and (QTx – QTx)

± V

REF

REF

/3 Volts For Each Analog Output

REF

/3 Volts I Channel = (ITx – ITx) and

Q Channel = (QTx –

MCLK

55 dB min

+450/–450 max/min

QTx)

QTx)

= 2.56 MHz

1

REFERENCE & CHANNEL SPECIFICATIONS

Reference, V

REF

2.46 Volts
Reference Accuracy ±5%
I and Q Gain Matching ±0.2 dB max Measured @ 10 kHz
Power-Down Option Yes Power = 0 V

LOGIC INPUTS

V

, Input High Voltage VDD – 0.9 V min

INH

V

, Input Low Voltage 0.9 V max

INL

I

, Input Current 10 FA max

INH

CIN, Input Capacitance 10 pF max

LOGIC OUTPUTS

V

Output High Voltage VDD – 0.4 V min |I

OH

VOL Output Low Voltage 0.4 V max |I

| ≤ 40 µA

OUT

| ≤ 1.6 mA

OUT

POWER SUPPLIES

V

DD

I

DD

Transmit Section Active 8 mA max POWER = V
Transmit Section Powered Down

5

4.5/5.5 V min/V max

DD

6 mA typ
35 µA max MCLK Active
5 µA max MCLK Inactive

NOTES

1

Operating temperature ranges as follows: A Version: –40°C to +85 °C.

2

See terminology.

3

Measured in continuous transmission and Burst Mode with the I and Q channels ramping up and down at the beginning and end of a burst.

4

Headroom must be allowed for the transmit DACs such that offsets in I & Q transmit channels can be calibrated out. Therefore, the full range of the I and Q DACs
are not available to the user. The user should ensure that binary codes greater than or less than the maximum or minimum are not loaded into the I or Q DACs.

5

Measured while the digital inputs to the transmit interface are static and equal to 0 V or VDD.

Specifications subject to change without notice.

–2–

REV. B

AD7011

TO OUTPUT

PIN

+2.1V

I

OH

C

L

100pF

1.6mA

200µA

I

OL

ITx/QTx

20pF

20k

Ω

AD7011

20k

Ω

Ω

ITx / QTx

20pF

40k

Figure 1. Analog Output Test Load Circuit

MASTER CLOCK TIMING

(VAA = VDD = +5 V 6 10%; AGND = DGND = 0 V. All specifications are T
otherwise noted.)

MIN

to T

MAX

unless

Parameter Limit at TA = –408C to +858C Units Description

t

1

t

2

t

3

t

MCLK

300 ns min MCLK Cycle Time
100 ns min MCLK High Time
100 ns min MCLK Low Time

t

1

2

t

3

Figure 2. Master Clock (MCLK) Timing

Figure 3. Load Circuit for Digital Outputs

REV. B

–3–

AD7011

(VAA = VDD = +5 V 6 10%; AGND = DGND = 0 V, f

TRANSMIT SECTION TIMING

T

to T

MIN

unless otherwise noted.)

MAX

Parameter Limit at TA = –408C to +858C Units Description

t

4

t

5

t

6

t

7

t

8

t

9

t

10

t

11

t

12

t

13

t

14

t

15

t

16

t

17

t

18

t

19

10 ns min Power Setup Time.
t

– 10 ns max

1

4097t1 + 70 ns max MCLK rising edge, after Power high, to READY rising edge.
10 ns min BIN Setup Time.
t

– 10 ns max

1

t1 + 70 ns max MCLK to READY propagation delay.
3t1 + 70 ns MCLK rising edge, after BIN high, to first TxCLK rising edge.
64t
32t
32t

1
1
1

ns TxCLK Cycle Time.
ns TxCLK High Time.

ns TxCLK Low Time.
50 ns min TxCLK falling edge to TxDATA setup time.
0 ns min TxCLK falling edge to TxDATA hold time.
3t

1

124t

7.5t
30t

1

9

1

ns max BIN low setup to Last transmitted symbol after ramp down.

ns max BIN low hold to Last transmitted symbol after ramp down.

ns Ramp Down cycle time after the last transmitted symbol.

ns max Last TxCLK falling edge to READY rising edge.
10 ns max Digital Output Rise Time.
10 ns max Digital Output Fall Time.

= 3.1104 MHz. All specifications are

MCLK

MCLK

POWER

READY

BIN

TxCLK

TxDATA

MCLK

POWER

READY

BIN

TxCLK

TxDATA

t

t

4

t

5

7

t

6

t

t

8

9

t

11

t

12

t

13

X

k

t

10

Y

k

Figure 4. Transmit Timing at the Start of a Tx Burst

t

17

t

14

t

15

t

16

X

N+4

Y

N+4

X

N+5

X

N+8

Y

N+8

Figure 5. Transmit Timing at the End of a Tx Burst

–4–

REV. B

AD7011

(VAA = VDD = +5 V 6 10%. AGND = DGND = 0 V. All specifications are T

ANALOG MODE TIMING

otherwise noted.)

Parameter Limit at TA = –40°C to +85°C Units Description

t

20

t

21

t

22

t

23

t

24

FRAME

I DATA

Q DATA

15 ns min MCLK Rising Edge to FRAME Setup Time.
15 ns min MCLK Rising Edge to FRAME Hold Time.
15t
16t

1
1

ns max

ns FRAME Cycle Time.
15 ns min MCLK Rising Edge to Data Setup Time.
15 ns min MCLK Rising Edge to Data Hold Time.

MCLK

t

t

20

t

23

t

24

DB9 DB8 DB1 DB0

DB9 DB8 DB1 DB0 DB9 DB8 DB7

22

to T

MIN

DB9 DB8 DB7

unless

MAX

t

21

Figure 6. Analog Mode Serial Interface Timing

Q

MODULAR OUTPUT

DURING FTEST

I

Table I.

MODE 1 MODE 2 Operation

0 0 Digital TIA Mode
1 0 Analog Mode
0 1 FTEST

Figure 7. Modulator State During FTEST

1 1 Factory Test, Reserved

Table II.

Mode of Operation MODE 1 MODE 2 MCLK Digital Bit Rate DAC Update Rate

Digital Mode 0 0 3.1104 MHz 48.6 kHz N/A
Analog Mode 1 0 2.56 MHz N/A 160 kHz

REV. B

–5–

AD7011

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS*

(TA = +25°C unless otherwise noted)

VDD Tx, VDD Rx to AGND . . . . . . . . . . . . . . . –0.3 V to +7 V

AGND to DGND . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V

Digital I/O Voltage to DGND . . . . . . . –0.3 V to V

Analog I/O Voltage to AGND . . . . . . . –0.3 V to V

+ 0.3 V

DD

+ 0.3 V

DD

Operating Temperature Range

Industrial (A Version) . . . . . . . . . . . . . . . –40°C to +85°C

Storage Temperature Range . . . . . . . . . . . –65°C to + 150°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . +150°C

SSOP θ

Thermal Impedance . . . . . . . . . . . . . . . . +122°C/W

JA

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . +215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . +220°C

*Stresses above those listed under “Absolute Maximum Ratings” may cause

permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although this device features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

ORDERING GUIDE

Model Temperature Range Package Description Package Option

AD7011ARS –40°C to +85°C Shrink Small Outline Package RS-24

SSOP PIN CONFIGURATION

V

DD

DGND

MCLK

NC

MODE1

NC

MODE2

1

2
3

4

5

AD7011

6

TOP VIEW

7

(Not to Scale)

8
9

10

11

12

NC = NO CONNECT

POWER

BIN (QDATA)

TxCLK (FRAME)

TxDATA (IDATA)

READY

24

23
22

21

20

19

18

17
16

15
14

13

BOUT

AGND
NC
QTx

QTx
V

AA

AGND

ITx
ITx
NC

AGND
BYPASS

–6–

REV. B

AD7011

PIN FUNCTION DESCRIPTION

SSOP Pin
Number Mnemonic Function

POWER SUPPLY

19 V
5VDDPositive power supply for digital section.
14, 18, 23 AGND Analog ground for transmit section.
6 DGND Digital ground for transmit section.

ANALOG SIGNAL AND REFERENCE

13 BYPASS Reference decoupling output. A decoupling capacitor should be connected between this pin and AGND.
16, 17 ITx,

21, 20 QTx,

TRANSMIT INTERFACE AND CONTROL

7 MCLK Master clock, digital input. When operating in Mode 0 (TIA Digital mode), this pin should be driven by a

3 TxCLK This is a dual function digital input/output. When operating in Mode 0 (TIA Digital mode), this pin is

4 TxDATA This is a dual function digital input. When operating in Mode 0 (TIA Digital mode), this pin is used to

2 BIN (QDATA) This is a dual function digital input. When operating in Mode 0 (TIA Digital mode), this input is used to ini-

24 BOUT Burst Out, digital output. This is the BIN input delayed by the pipeline delay, both digital and analog, of the

1 POWER Transmit sleep mode, digital input. When this goes low, the AD7011 goes into sleep mode, drawing minimal

12 READY Transmit ready, digital output. This output goes high once the self-calibration routine is complete.
9, 11 MODE1, Mode control, digital inputs. These are used to enter the AD7011 into three different operating modes,

8, 10, 15, 22 NC No Connects. These pins are no connects and should not be used as routes for other circuit signals.

AA

ITx Differential analog outputs for the I channel, representing true and complementary outputs of the I

QTx Differential analog outputs for the Q channel, representing true and complementary outputs of the Q

(FRAME) configured as a digital output, transmit clock. This may be used to clock in transmit data at 48.6 kHz. When

(IDATA) clock in transmit data on the falling edge of TxCLK at a rate of 48.6 kHz. When operating in Mode 1

MODE2 see Table I.

Positive power supply for analog section.

waveform.

waveform.

3.1104 MHz CMOS compatible clock source in digital mode and by 2.56 MHz CMOS compatible clock
source for analog mode.

operating in Mode 1 (analog mode), this pin is configured as a digital input, FRAME. This is used to frame
the clocking in of 16-bit words when bypassing the π/4 DQPSK modulator and directly loading the I and Q
10-bit DACs.

(Analog mode), I data is clocked in on the rising edge of MCLK. This data bypasses the π/4 DQPSK modu­lator and is loaded into the 10-bit I DAC.

tiate the ramping up (BIN high) or down (BIN low) of the I and Q waveforms. When operating in Mode 1
(Analog mode), Q data is clocked in on the rising edge of MCLK. This data bypasses the π/4 DQPSK modu­lator and is loaded into the 10-bit Q DAC.

AD7011. This can be used to turn on and off the RF amplifiers in synchronization with the I and Q waveforms.

current. When this pin goes high, the AD7011 is brought out of sleep mode and initiates a self-calibration
routine to eliminate the offset between ITx &

ITx and the offset between QTx & QTx.

REV. B

–7–

AD7011

I

Q

ERROR VECTOR

OFFSET
VECTOR

0,0

SIGNAL VECTOR

TERMINOLOGY
Error Vector Magnitude

This is a measure of the rms error vector introduced by the
AD7011 where signal error vector is defined as the rms devia­tion of a transmitted symbol from its ideal position when filtered
by an Ideal RRC Receive filter, as illustrated in Figure 8.

Gain Matching Between Channels

The is the gain matching between the I and Q outputs, measured
when transmitting all zeros.

Offset Vector Magnitude

This is a measure of the offset vector introduced by the AD7011
as illustrated in Figure 8. The offset vector is calculated so as to
minimize the rms error vector for each of the constellation
points.

Output Signal Range and Different Output Range

The output signal range is the output voltage swing and dc bias
level for each of the analog outputs. The different output range
is the difference between ITx and
difference between QTx and

IS-54 Spurious Power

ITx for the I channel and the

QTx for the Q Channel.

This is the rms sum of the spurious power measured at multiples
of 30 kHz, in a root raised cosine window of ± 16.4 kHz, relative
to twice the rms power in a RRC window in the 0 to 16.4 kHz
band.

Signal Vector Magnitude

This is the radius of the IQ constellation diagram as illustrated
in Figure 8.

Signal to (Noise + Distortion) Ratio

This is the measured ratio of signal to (noise + distortion) at the
output of the transmit I and Q DACs. The signal is the rms
amplitude of the fundamental. Noise is the rms sum of all non­fundamental signals up to half the sampling frequency (f

S

/2),
excluding dc. The ratio is dependent upon the number of
quantization levels in the digitization process; the more levels,
the smaller the quantization noise. The theoretical signal to
(noise distortion) ratio for a sine wave is given by:

SNR = (6.02N + 1.76) dB

where N is the number of bits. Thus for an ideal 10-bit con­verter, SNR = 61.96 dB.

Figure 8.

–8–

REV. B

I

Q

–– – –– COS π –––

121

2

t

3T

–– + –– COS π –––

121

2

t

3T

3 SYMBOLS 3 SYMBOLS

CIRCUIT DESCRIPTION

TRANSMIT SECTION

The transmit section of the AD7011 generates π/4 DQPSK I
and Q waveforms in accordance with TIA specification. This is
accomplished by a digital π/4 DQPSK modulator, which
includes the root-raised cosine filters (α = 0.35), followed by
two 10-bit DACs and on-chip reconstruction filters. The π/4
DQPSK (Differential Quadrature Phase Shift Keying) digital
modulator generates 10-bit I and Q data in response to the
transmit data stream. The 10-bit I and Q DACs are filtered by
on-chip reconstruction filters, which also generate differential
analog outputs for both I and Q channels.

The AD7011 transmit channel also provides an analog mode,
where direct access to the I and Q DACs is provided, bypassing
the π/4 DQPSK modulator. This is provided so that the
AD7011 transmit channel can also be used to perform the
conversion and filtering of the analog waveforms required to
emulate the existing analog cellular system.

p/4 DQPSK Modulator

The π/4 DQPSK modulator generates 10-bit I and Q data
(Inphase and Quadrature) which are loaded into the I and Q
10-bit transmit DACs.

Figure 9 shows the functional block diagram of the π/4 DQPSK
modulator. The transmit serial data (TxDATA) is first con­verted into Di-bit symbols [X
converter. The data is then differentially encoded; symbols are
transmitted as changes in phase rather than absolute phases.
Each symbol represents a phase change, as illustrated in Table
III, and this along with the previously transmitted symbol
determines the next symbol to be transmitted. The differential
phase encoder generates I and Q impulses [I
the Di-bit symbols according to:

X

TxDATA

2-BIT
SERIAL TO
PARALLEL

CONVERTER

, Yk], using a 2-bit serial to parallel

k

, Qk] in response to

k

I

= COS [φ

k

= SIN [φ

Q

k

π /4 DQPSK DIGITAL

MODULATOR

k

DIFFERENTIAL

PHASE

Y

ENCODER

k

k–1

k–1

+ ∆φk]
+

∆φ

I

k

COSINE FILTER

Q

k

COSINE FILTER

]

k

ROOT-RAISED

ROOT-RAISED

10

10

I DATA

Q DATA

AD7011

Figure 10.π/4 DQPSK Constellation Diagram

Figure 10 illustrates the π/4 DQPSK constellation diagram as
described above, showing the eight possible states for [I

and Qk impulses are then filtered by FIR raised root

The I

k

cosine filters (α = 0.35), generating 10-bit I and Q data. The
FIR root raised cosine filters have an impulse response of ±4
symbols.

Transmit Calibration

When the transmit section is brought out of sleep mode
(POWER high), the transmit section initiates a self-calibration
routine to remove the offset between ITx and
between QTx and

QTx. READY goes high on the completion

ITx and an offset

of the self-calibration routine. Once READY goes high, BIN
(Burst In) can be brought high to initiate a transmit burst.

Ramp-Up/Down Envelope Logic

The AD7011 provides on-chip envelope shaping logic, providing
power shaping control for the beginning and end of a transmit
burst. When BIN (Burst In) is brought high, the modulator is
reset to a transmitting all zeros state (i.e., X

= Yk = 0) and

k

continues to transmit all zeros for the first three symbols, during
which the ramp-up envelope goes from zero to full scale as
illustrated in Figure 11. The next symbol to be transmitted is
[I

, Q1], which represents the first two data bits clocked in after

1

BIN going high, i.e., [X

, Y1].

1

, Qk].

k

Figure 9.π/4 DQPSK Modulator Functional Block Diagram

REV. B

Table III.

X

k

11

01

00

10

Y

k

∆f

−3π

3π

π

4

−π

k

Figure 11. Ramp Envelope

4

4

When BIN is brought low, indicating the end of a transmit
burst, the current Di-bit symbol [X
is receiving will be the last symbol to be computed for the four
symbol ramp-down sequence. Also the N

, Y

N+4

] that the AD7011

N+4

th

symbol is the last

active symbol prior to ramping down.
However, because the impulse response is equal to ± 4 symbols,

4

outputs when transmitting the (N+4)

four additional symbols are required to fully compute the analog

th

symbol. Hence there will
be eight subsequent TxCLKs, latching four additional Di-bit
symbols: [X

–9–

N + 5

, Y

N + 5

] to [X

N + 8

, Y

N + 8

].

AD7011

BIN

TxCLK

TxDATA

BOUT

X

Y

1

XNY

1

Y

X

N

N+1

= 480

N+1

t

Y

X

N+2

N+2

1

Y

X

N+3

N+3

Y

X

N+4

N+4

Y

X

N+5

N+5

Y

X

N+6

N+6

Y

X

N+7

N+7

Y

X

N+8

N+8

(ITx–ITx),

(QTx–QTx)

SYMBOL

PHASE MAX

EFFECT

0
0

3 SYMBOL

RAMP-UP ENVELOPE

00
00

Figure 12. Transmit Burst

As Figure 12 illustrates, the ramp-down envelope reaches zero
after three symbols, hence the fourth symbol does not actually
get transmitted.

Reconstruction Filters

The reconstruction filters smooth the DAC output signals,
providing continuous time I and Q waveforms at the output
pins. These are 4th order Bessel low-pass filters with a –3dB
frequency of approximately 25 kHz. The filters are designed to
have a linear phase response in the passband and due to the
reconstruction filters being on-chip, the phase mismatch
between the I and Q transmit channels is kept to a minimum.

Transmit Section Digital Interface

MODE1 = MODE2 = DGND: Digital π/4 DQPSK Mode

Figures 4 and 5 shows the timing diagrams for the transmit
interface when operating in TIA π/4 DQPSK mode. POWER is
sampled on the rising edge of MCLK. When POWER is
brought high, the transmit section is brought out of sleep mode
and initiates a self-calibration routine as described above. Once
the self-calibration is complete, the READY signal goes high to
indicate that a transmit burst can now begin. BIN (Burst in) is
brought high to initiate a transmit burst and should only be
brought high if the READY signal is already high.

When BIN goes high, the READY signal goes low on the next
rising edge of MCLK and TxCLK becomes active after a
further three MCLK cycles. TxCLK can be used to clock out
the transmit data from the ASIC or DSP on the rising edge of
TxCLK and the AD7011 will latch TxDATA on the falling
edge of TxCLK.

When BIN is brought low, the AD7011 will continue to clock in
the current Di-bit symbol (X

N + 4

, Y

) and will continue for a

N + 4

further 8 TxCLK cycles (four symbols). After the final TxCLK,
READY goes high waiting for BIN to be brought high to begin
the next transmit burst.

3 SYMBOL

RAMP-DOWN ENVELOPE

I

1

Q

1

I

Q

I

N

N

N+1

Q

N+1

I

N+2

Q

N+2

I

N+3

Q

N+3

I

N+4

Q

N+4

When POWER is brought low this puts the transmit section into
a low power sleep mode, drawing minimal current. The analog
outputs go high impedance while in low power sleep mode.

MODE1 = V

; MODE2 = DGND: Analog Mode

DD

Figure 6 shows the timing diagram for the transmit interface
when operating in analog mode. In this mode the π/4 DQPSK
modulator is bypassed and direct access to the I and Q 10-bit
DACs is provided. Loading of the I and Q DACs is accom­plished using a 4 wire 16-bit serial interface. The pins TxCLK,
TxDATA and BIN are all reconfigured as inputs, with the
functions of FRAME, IDATA and QDATA respectively.

I and Q data are loaded via the IDATA and QDATA pins and
FRAME synchronizes the loading of the 16-bit I and Q words.
FRAME should be brought high one clock cycle prior to the I
and Q MSBs. Data is latched on the rising edge of MCLK,
MSB first, where only the first 10 data bits are significant. Con­tinuous updating of the I and Q DACs is required at a rate of
MCLK/16.

MODE1 = DGND; MODE2 = V

: Frequency Test Mode

DD

A special FTEST (Frequency TEST) mode is provided for the
customer, where no phase modulation takes place and the mod­ulator outputs remain static. ITx is set to zero and QTx is set to
full scale as Figure 7 illustrates. However, the normal ramp-up/
down envelope is still applied during the beginning and end of a
burst.

MODE1 = MODE2 = V

: Factory Test Mode

DD

This mode is reserved for factory test only and should not be
used by the customer for correct device operation.

–10–

REV. B

0

0

–40

–80

1 1000100100.1

–60

–20

–30

–50

–70

–10

FREQUENCY – kHz

MAGNITUDE – dBs

I Channel – Volts

Q Channel – Volts

1.2

–1.2

1.2

0

–0.8

–0.8

–0.4

–1.2

0.8

0.4

0.80.40–0.4

I Channel – Volts

Q Channel – Volts

1.2

–1.2

1.2

0

–0.8

–0.8

–0.4

–1.2

0.8

0.4

0.80.40–0.4

–10

–20

–30

–40

–50

MAGNITUDE – dBs

–60

–70

AD7011

–80

1 1000100100.1

FREQUENCY – kHz

Figure 13. Reconstruction Filter Frequency Response for
the I and Q DACs, MCLK = 2.56 MHz

1.2

1.2

0.8

0.8

0.4

0.4

0

0

–0.4

–0.4

Q Channel – Volts

Q Channel – Volts

–0.8

–0.8

–1.2

–1.2

–1.2

–1.2

–0.8

–0.8

I Channel – Volts

I Channel – Volts

1.2

1.2

0.80.40–0.4

0.80.40–0.4

Figure 14. AD7011 I vs. Q Waveforms When Transmitting
Random Data

1.2

0.8

Figure 16. Reconstruction Filter Frequency Response for
the I and Q DACs, MCLK = 3.1104 MHz

Figure 17. AD7011 I vs. Q Waveforms Filtered by an Ideal
Root Raised Cosine Receive Filter

REV. B

0.4

0

–0.4

Q Channel – Volts

–0.8

–1.2

–1.2

–0.8

I Channel – Volts

1.2

0.80.40–0.4

Figure 15. AD7011 Transmit Constellation Diagram

Figure 18. AD7011 Constellation Diagram When Filtered
by an Ideal Root Raised Cosine Receive Filter

–11–

AD7011

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

24-Lead SSOP (RS-24)

24

PIN 1

1

0.008 (0.203)

0.002 (0.050)

13

0.212 (5.38)

0.205 (5.207)

0.311 (7.9)

0.301 (7.64)

12

0.328 (8.33)

0.318 (8.08)

0.0256 (0.65)
BSC

1. LEAD NO. 1 IDENTIFIED BY A DOT.

2. LEADS WILL BE EITHER TIN PLATED OR SOLDER DIPPED
IN ACCORDANCE WITH MIL-M-38510 REQUIREMENTS

0.07 (1.78)

0.066 (1.67)

0.009 (0.229)

0.005 (0.127)

8°
0°

0.037 (0.94)

0.022 (0.559)

C1780a–5–7/94

–12–

PRINTED IN U.S.A.

REV. B