Datasheet AD7010 Datasheet (Analog Devices)

CMOS

a

FEATURES
Single +5 V Supply

On-Chip p/4 DQPSK Modulator
Root-Raised-Cosine Tx Filters, a = 0.5
Two 10-Bit D/A Converters
4th Order Reconstruction Filters
Differential Analog Outputs
On-Chip Ramp Up/Down Power Control
On-Chip Tx Offset Calibration
Very Low Power Dissipation, 30 mW typ

Power Down Mode < 5 mA
On-Chip Voltage Reference
24-Pin SSOP

APPLICATIONS
Japanese Digital Cellular Telephony

JDC p/4 DQPSK Baseband T ransmit Port

AD7010

GENERAL DESCRIPTION

The AD7010 is a complete low power, CMOS, π/4 DQPSK
modulator with single +5 V power supply. The part is designed
to perform the baseband conversion of I and Q transmit
waveforms in accordance with the Japanese Digital Cellular
Telephone system.

The on-chip π/4 Differential Quadrature Phase Shift Keying
(DQPSK) digital modulator, which includes the Root Raised
Cosine filters, generates I and Q data in response to the transmit
data stream. The AD7010 also contains ramp control envelope
logic to shape the I and Q output waveforms when ramping up
or down at the beginning or end of a transmit burst.

Besides providing all the necessary logic to perform π/4 DQPSK
modulation, the part also provides reconstruction filters to
smooth the DAC outputs, providing continuous time analog
outputs. The AD7010 generates differential analog outputs for
both the I and Q signals.

As it is a necessity for all digital mobile systems to use the lowest
possible power, the device has power down options. The
AD7010 is housed in a space efficient 24-pin SSOP (Shrink
Small Outline Package).

POWER

Tx DATA

Tx CLK

READY

BIN

FUNCTIONAL BLOCK DIAGRAM

V

DGND

π/4 DQPSK

MODULATOR

AD7010

MCLK

DD

10-BIT

I-DAC

10-BIT
Q-DAC

REFERENCE

BYPASS

V

AA

RECONSTRUCTION

FILTERS

CALIBRATION CIRCUITRY

RECONSTRUCTION

FILTERS

2.46V

MODE1

AGND

ITx
ITx

QTx
QTx

BOUT

MODE2

REV. B

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] Fax: [phone]

AD7010–SPECIFICATIONS

(VAA = VDD = +5 V 6 10%; Test = AGND = DGND = 0 V; f

1

Power = VDD. All specifications are T

MIN

to T

MAX

unless otherwise noted.)

= 2.688 MHz;

MCLK

Parameter AD7010ARS Units Test Conditions/Comments

DIGITAL MODE TRANSMIT

No. of Channels 2 (ITx–
Output Signal Range V
Differential Output Range ±V

Signal Vector Magnitude
Error Vector Magnitude

Offset Vector Magnitude
JDC Spurious Power

2

2

2

2, 3

± V

REF

REF

/4 Volts For Each Analog Output

REF

/2 Volts I Channel = (ITx–ITx)

0.875 ± 7.5% Volts max Measured Differentially
1 % rms typ

2.5 % rms max

0.5 % typ

2.5 % max

ITx) and (QTx–QTx)

and Q Channel = (QTx–

QTx)

@ 25 kHz –30 dB typ

–25 dB max

@ 50 kHz –60 dB typ

–55 dB max

@ 75 kHz –70 dB typ

–65 dB max

@ 100 kHz, 150 kHz, 200 kHz –70 dB typ

–65 dB max

REFERENCE & CHANNEL SPECIFICATIONS

Reference, V

REF

2.46 Volts
Reference Accuracy ±5%
I and Q Gain Matching ±0.2 dB max Measured @ 10 kHz
Power Down Option Yes Power = 0 V

LOGIC INPUTS

V

, Input High Voltage VDD–0.9 V min

INH

V

, Input Low Voltage 0.9 V max

INL

I

, Input Current 10 µA max

INH

CIN, Input Capacitance 10 pF max

LOGIC OUTPUTS

V

, Output High Voltage VDD–0.4 V min |I

OH

VOL, Output Low Voltage 0.4 V max |I

| ≤ 40 µA

OUT

| ≤ 1.6 mA

OUT

POWER SUPPLIES

V

DD

I

DD

Transmit Section Active 8 mA max Power = V
Transmit Section Powered Down

4

4.5/5.5 V min/V max

DD

6 mA typ
35 µA max MCLK Active
5 µA max MCLK Inactive

NOTES

1

Operating temperature ranges as follows: A Version: –40°C to +85 °C.

2

See Terminology.

3

Measured in continuous transmission and Burst transmission with the I and Q channels ramping up and down at the beginning and end of each burst.

4

Measured while the digital inputs to the transmit interface are static and equal to 0 V or VDD.

Specifications subject to change without notice.

ORDERING GUIDE

Model Temperature Range Package Description Package Option

AD7010ARS –40°C to +85°C Shrink Small Outline Package RS-24

–2–

REV. B

20kΩ

20kΩ

20pF

20pF

AD7010

ITx/QTx

40kΩ

ITx / QTx

Q

I

MODULAR OUTPUT

DURING FTEST

ABSOLUTE MAXIMUM RATINGS*

WARNING!

ESD SENSITIVE DEVICE

TO OUTPUT

PIN

+2.1V

I

OH

C

L

100pF

1.6mA

200µA

I

OL

(TA = +25°C unless otherwise noted)

VDD Tx, VDD Rx to AGND . . . . . . . . . . . . . . . –0.3 V to +7 V

AGND to DGND . . . . . . . . . . . . . . . . . . . . .–0.3 V to +0.3 V

Digital I/O Voltage to DGND . . . . . –0.3 V to V

Analog I/O Voltage to AGND . . . . . . . –0.3 V to V

to + 0.3 V

DD

+ 0.3 V

DD

Operating Temperature Range

Industrial (A Version) . . . . . . . . . . . . . . . . –40°C to +85°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . +150°C

SSOP θ

Thermal Impedance . . . . . . . . . . . . . . . . +122°C/W

JA

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . +215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . +220°C

*Stresses above those listed under “Absolute Maximum Ratings” may cause

permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

Table I.

MODE 1 MODE 2 Operation

AD7010

Figure 1. Analog Output Load Test Circuit

0 0 Digital JDC Mode
0 1 FTEST

Figure 2. Modulator State During FTEST

1 X Factory Test, Reserved

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7010 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

MASTER CLOCK TIMING

(VAA = VDD = +5 V 6 10%; AGND = DGND = O V. All specifications are T
otherwise noted.)

MIN

to T

MAX

unless

Parameter Limit at TA = –408C to +858C Units Description

t

1

t

2

t

3

300 ns min MCLK Cycle Time
100 ns min MCLK High Time
100 ns min MCLK Low Time

MCLK

Figure 3. Master Clock (MCLK) Timing

REV. B

t

1

t

2

t

3

Figure 4. Load Circuit for Digital Outputs

–3–

AD7010

(VAA = VDD = +5 V 6 10%; AGND = DGND = 0 V, f
T

to T

TRANSMIT SECTION TIMING

MIN

Parameter Limit at TA = –40°C to +85°C Units Description

unless otherwise noted.)

MAX

= 2.688 MHz. All specifications are

MCLK

t

4

t

5

t

6

t

7

t

8

t

9

t

10

t

11

t

12

t

13

t

14

t

15

t

16

t

17

t

18

t

19

10 ns min POWER Setup Time.
t

– 10 ns max

1

4097t1 + 70 ns max MCLK rising edge, after POWER high, to READY rising edge.
10 ns min BIN Setup Time.
t

– 10 ns max

1

t1 + 70 ns max MCLK to READY low propagation delay.
3t1 + 70 ns MCLK rising edge, after BIN high, to first TxCLK rising edge.
64t
32t
32t

1
1
1

ns TxCLK Cycle Time.
ns TxCLK High Time.

ns TxCLK Low Time.
50 ns min TxCLK falling edge to TxDATA setup time.
0 ns min TxCLK falling edge to TxDATA hold time.
3t

1

124t

7.5t
30t

1

9

1

ns max BIN low setup to last transmitted symbol after ramp down.

ns max BIN low hold to last transmitted symbol after ramp down.

ns Ramp down cycle time after the last transmitted symbol.

ns max Last TxCLK falling edge to READY rising edge.
10 ns max Digital Output Rise Time.
10 ns max Digital Output Fall Time.

MCLK

POWER

READY

BIN

TxCLK

TxDATA

t

4

t

5

t

7

t

6

t

t

8

9

t

11

t

12

t

13

X

k

t

10

Y

k

MCLK

POWER

READY

BIN

TxCLK

TxDATA

Figure 5. Transmit Timing at the Start of a Tx Burst

t

17

t

14

t

15

t

16

X

N+4

Y

N+4

X

N+5

X

N+8

Y

N+8

Figure 6. Transmit Timing at the End of a Tx Burst

–4–

REV. B

AD7010

PIN FUNCTION DESCRIPTION

SSOP Pin
Number Mnemonic Function

POWER SUPPLY

19 V
5V

AA
DD

14, 18, 23 AGND Analog ground for transmit section.
6 DGND Digital ground for transmit section, both grounds should be externally tied together.

ANALOG SIGNAL AND REFERENCE

13 BYPASS Reference decoupling output. A decoupling capacitor should be connected between this pin a

16, 17 ITx,

21, 20 QTx,

ITx Differential analog outputs for the I channel, representing true and complementary outputs

QTx Differential analog outputs for the Q channel, representing true and complementary outputs

TRANSMIT INTERFACE AND CONTROL

7 MCLK Master clock, digital input. This pin should be driven by a 2.688 MHz CMOS compatible

3 TxCLK This is a digital output, transmit clock. This may be used to clock in transmit data at 42 kHz.
4 TxDATA This is a digital input. This pin is used to clock in transmit data on the falling edge of TxCLK

2 BIN This is a digital input. This input is used to initiate the ramping up (BIN high) or down (BIN

24 BOUT Burst out, digital output. This is the BIN input delayed by the pipeline delay, both digital and

1 POWER Transmit sleep mode, digital input. When this goes low, the AD7010 goes into sleep mode,

12 READY Transmit ready, digital output. This output goes high once the self-calibration routine is complete.
9, 11 MODE1, Mode control, digital inputs. These are used to enter the AD7010 into three different

MODE2 operating modes, see Table I.

8, 10, 15, 22 NC No Connects. These pins are no connects and should not be used as routes for other circuit signals.

Positive power supply for analog section.
Positive power supply for digital section, both supplies should be externally tied together.

and AGND.

of the I waveform.

of the Q waveform.

clock source in digital mode.

at a rate of 42 kHz.

low) of the I and Q waveforms.

analog, of the AD7010. This can be used to turn on and off the RF amplifiers in synchroniza­tion with the I and Q waveforms.

drawing minimal current. When this pin goes high, the AD7010 is brought out of sleep mode
and initiates a self-calibration routine to eliminate the offset between ITx &
between QTx &

QTx.

ITx and the offset

REV. B

SSOP PIN CONFIGURATION

POWER

BIN

TxCLK

TxDATA

V
DGND

MCLK

NC

MODE1

NC

MODE2

READY

1

2
3

4

5

DD

AD7010

619

TOP VIEW

7

(Not to Scale)

8
9

10

11

12

24

23
22

21

20

18

17

16

15
14

13

BOUT

AGND

NC

QTx

QTx
V

AA

AGND

ITx
ITx

NC

AGND

BYPASS

–5–

AD7010

I

Q

TERMINOLOGY
Error Vector Magnitude

This is a measure of the rms error vector introduced by the
AD7010 where signal error vector is defined as the rms devia­tion of a transmitted symbol from its ideal position, as illustrated
in Figure 7, when filtered by an ideal RRC filter.

Gain Matching Between Channels

This is the Gain matching between the I and Q outputs, mea­sured when transmitting all zeros.

Offset Vector Magnitude

This is a measure of the offset vector introduced by the AD7010
as illustrated in Figure 7. The offset vector is calculated so as to
minimize the rms error vector for each of the constellation points.

Output Signal Range and Differential Output Range

The output signal range is the output voltage swing and dc bias
level for each of the analog outputs. The Differential Output
Range is the difference between ITx and
and the difference between QTx and

ITx for the I channel

QTx for the Q Channel.

JDC Spurious Power

This is the rms sum of the spurious power measured at multi­ples of 25 kHz, in a rectangular window of ± 10.5 kHz, relative
to twice the rms power in a RRC window in the 0 kHz to

10.5 kHz band.

Signal Vector Magnitude

This is the radius of the IQ constellation diagram as illustrated
in Figure 7.

Q

ERROR VECTOR

SIGNAL VECTOR

OFFSET

VECTOR

0,0

I

Table II.

X

k

Y

k

Df

k

1 1 –3 π/4
013 π/4
00π/4
10–π/4

Figure 8 shows the functional block diagram of the π/4 DQPSK
modulator. The transmit serial data (TxDATA) is first con­verted into Di-bit symbols [X

, Yk], using a 2-bit serial to paral-

k

lel converter. The data is then differentially encoded; symbols
are transmitted as changes in phase rather than absolute phases.
Each symbol represents a phase change, as illustrated in Table
II, and this along with the previously transmitted symbol deter­mines the next symbol to be transmitted. The differential phase
encoder generates I and Q impulses [I

, Qk] in response to the

k

Di-bit symbols according to:

I

TxDATA

= COS[φ

k

= SIN[φ

Q

k

π/4 DQPSK DIGITAL MODULATOR

X

k

2-BIT
SERIAL TO
PARALLEL

CONVERTER

DIFFERENTIAL

Y

k

PHASE

ENCODER

+ ∆φk]

k–1

+ ∆φk]

k–1

I

k

ROOT-RAISED

COSINE FILTER

Q

k

ROOT-RAISED

COSINE FILTER

I DATA

10

Q DATA

10

Figure 8.π/4 DQPSK Modulator Functional Block Diagram

Figure 9 illustrates the π/4 DQPSK constellation diagram as de­scribed above, showing the eight possible states for [I

and Qk impulses are then filtered by FIR Root-Raised

The I

k

, Qk].

k

Cosine Filters (α = 0.5), generating 10-bit I and Q data. The
FIR Root-Raised Cosine Filters have an impulse response of
±4 symbols.

Figure 7.

CIRCUIT DESCRIPTION

TRANSMIT SECTION

The transmit section of the AD7010 generates π/4 DQPSK I
and Q waveforms in accordance with JDC specification. This is
accomplished by a digital π/4 DQPSK modulator, which in­cludes the Root-Raised Cosine filters (α = 0.5), followed by two
10-bit DACs and on-chip reconstruction filters. The π/4
DQPSK (Differential Quadrature Phase Shift Keying) digital
modulator generates 10-bit I and Q data in response to the
transmit data stream. The 10-bit I and Q DACs are filtered by
on-chip reconstruction filters, which also generate differential
analog outputs for both I and Q channels.

p/4 DQPSK Modulator

The π/4 DQPSK modulator generates 10-bit I and Q data (In­phase and Quadrature) which are loaded into the I and Q 10-bit
transmit DACs.

–6–

Figure 9. π/4 DQPSK Constellation Diagram

Transmit Calibration

When the transmit section is brought out of sleep mode (Power
high), the transmit section initiates a self-calibration routine to
remove the offset between ITx and
QTx and

QTx. READY goes high on the completion of the self-

ITx and the offset between

calibration routine. Once READY goes high, BIN (Burst In)
can be brought high to initiate a transmit burst.

REV. B

AD7010

0

–40

–80

1 1000100100.1

–60

–20

–30

–50

–70

–10

FREQUENCY – kHz

MAGNITUDE – dBs

X1Y

1

XNY

N

Y

N+1

X

N+1

Y

N+2

X

N+2

Y

N+3

X

N+3

Y

N+4

X

N+4

2 SYMBOL

RAMP-UP ENVELOPE

2 SYMBOL

RAMP-DOWN ENVELOPE

I

1

Q

1

I

N

Q

N

I

N+1

Q

N+1

I

N+2

Q

N+2

I

N+3

Q

N+3

I

N+4

Q

N+4

00

00

SYMBOL

PHASE MAX

EFFECT

BIN

TxCLK

TxDATA

BOUT

(ITx–ITx),

(QTx–QTx)

Y

N+5

X

N+5

Y

N+6

X

N+6

Y

N+7

X

N+7

Y

N+8

X

N+8

= 480

t

1

Ramp-Up/Down Envelope Logic

The AD7010 provides on-chip envelope shaping logic, providing
power shaping control for the beginning and end of a transmit
burst. When BIN (Burst In) is brought high, the modulator is
reset to a transmitting all zeros state (i.e., X

= Yk = 0) and

k

continues to transmit all zeros for the first two symbols, during
which the ramp-up envelope goes from zero to full scale as illus­trated in Figure 10. The next symbol to be transmitted is [I
Q

], which represents the first two data bits clocked in after

1

BIN going high, i.e., [X

1

1

–

COS π

2

2

2T

, Y1].

1

2 SYMBOLS 2 SYMBOLS

t

1

1

+

COS π

2

2

2T

,

1

t

Figure 10. Ramp Envelope

When BIN is brought low, indicating the end of a transmit
burst, the current Di-bit symbol [X
is receiving will be the last symbol to be computed for the 4
symbol ramp-down sequence. Also the N

, Y

N+4

] that the AD7010

N+4

th

symbol is the last

active symbol prior to ramping down.
However, because the impulse response is equal to ± 4 symbols,

four additional symbols are required to fully compute the analog
outputs when transmitting the (N+4)

th

symbol. Hence there will
be eight subsequent TxCLKs, latching four additional Di-bit
symbols: [X

N+5

, Y

N+5

] to [X

N+8

, X

N+8

].

As Figure 11 illustrates, the ramp-down envelope reaches zero
after two symbols, hence the third and fourth symbols do not
actually get transmitted.

Reconstruction Filters

The reconstruction filters smooth the DAC output signals, pro­viding continuous time I and Q waveforms at the output pins.

These are 4th order Bessel low-pass filters with a –3 dB fre­quency of approximately 22 kHz, the frequency response is
illustrated in Figure 12. The filters are designed to have a linear
phase response in the passband and due to the reconstruction
filters being on-chip, the phase mismatch between the I and Q
transmit channels is kept to a minimum.

Figure 12. Reconstruction Filter Frequency Response for
I and Q DACs, MCLK = 2.688 MHz

Transmit Section Digital Interface

MODE1 = MODE2 = DGND: Digital π/4 DQPSK Mode

Figures 5 and 6 show the timing diagrams for the transmit
interface when operating in JDC π/4 DQPSK mode. Power is
sampled on the rising edge of MCLK. When Power is brought
high, the transmit section is brought out of sleep mode and ini­tiates a self-calibration routine as described above. Once the
self-calibration is complete, the READY signal goes high to
indicate that a transmit burst can now begin. BIN (Burst in) is
brought high to initiate a transmit burst and should only be
brought high if the READY signal is already high.

REV. B

Figure 11. Transmit Burst

–7–

AD7010

I Channel – Volts

Q Channel – Volts

1.2

–1.2

1.2

0

–0.8

–0.8

–0.4

–1.2

0.8

0.4

0.80.40–0.4

I Channel – Volts

Q Channel – Volts

1.2

–1.2

1.2

0

–0.8

–0.8

–0.4

–1.2

0.8

0.4

0.80.40–0.4

1. LEAD NO. 1 IDENTIFIED BY A DOT.

2. LEADS WILL BE EITHER TIN PLATED OR SOLDER DIPPED
IN ACCORDANCE WITH MIL-M-38510 REQUIREMENTS

0.009 (0.229)

0.005 (0.127)

0.037 (0.94)

0.022 (0.559)

8°
0°

0.0256 (0.65)
BSC

0.07 (1.78)

0.066 (1.67)

0.328 (8.33)

0.318 (8.08)

0.008 (0.203)

0.002 (0.050)

PIN 1

0.311 (7.9)

0.301 (7.64)

0.212 (5.38)

0.205 (5.207)

1

24

13

12

1.2

1.2

0.8

0.8

0.4

0.4

0

0

–0.4

–0.4

Q Channel – Volts

Q Channel – Volts

–0.8

–0.8

–1.2

–1.2

–1.2

–1.2

–0.8

–0.8

I Channel – Volts

I Channel – Volts

C1779a–5–7/94

1.2

0.80.40–0.4

1.2

0.80.40–0.4

Figure 13. AD7010 I vs. Q Waveforms when Transmitting
Random Data

Figure 14. AD7010 I vs. Q Waveforms Filtered by an Ideal
Root Raised Cosine Receive Filter

When BIN goes high, the READY signal goes low on the next
rising edge of MCLK and TxCLK becomes active after a further
two MCLK cycles. TxCLK can be used to clock out the trans­mit data from the ASIC or DSP on the rising edge of TxCLK
and the AD7010 will latch TxDATA on the falling edge of
TxCLK.

When BIN is brought low, the AD7010 will continue to clock in
the current Di-bit symbol (X
further eight TxCLK cycles (four symbols). After the final
TxCLK, READY goes high waiting for BIN to be brought high
to begin the next transmit burst.

When Power is brought low, this puts the transmit section into a
low power sleep mode, drawing minimal current. The analog
outputs go high impedance while in low power sleep mode.

MODE1 = DGND; MODE2 = V

A special FTEST (Frequency TEST) mode is provided for the
customer, where no phase modulation takes place and the
modulator outputs remain static. ITx is set to zero and QTx is

ramp-up/down envelope is still applied during the beginning and
end of a burst.

MODE1 = V

set to full scale as Figure 2 illustrates. However, the normal

MODE1 = MODE2 = V
These modes are reserved for factory test only and should not be

used by the customer for correct device operation.

1.2

0.8

0.4

0

–0.4

Q Channel – Volts

–0.8

–1.2

DD

–0.8

–1.2

I Channel – Volts

, Y

N+4

DD

; MODE2 = DGND: Factory Test Mode

: Factory Test Mode

DD

1.2

0.80.40–0.4

) and will continue for a

N+4

: Frequency Test Mode

Figure 15. AD7010 Transmit Constellation Diagram

Figure 16. AD7010 Constellation Diagram when Filtered
by an Ideal Root Raised Cosine Receive Filter

OUTLINE DIMENSIONS

Dimensions are shown in inches and (mm).

24-Lead SSOP (RS-24)

–8–

PRINTED IN U.S.A.

REV. B