Datasheet AD688 Datasheet (ANALOG DEVICES)

Page 1

High Precision

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FEATURES

±10 V tracking outputs Kelvin connections Low tracking error: 1.5 mV Low initial error: 2.0 mV Low drift: 1.5 ppm/°C Low noise: 6 µV p-p Flexible output force and sense terminals High impedance ground sense Wide body SOIC and CERDIP packages

GENERAL DESCRIPTION

The AD688 is a high precision ±10 V tracking reference. Low tracking error, low initial error, and low temperature drift give the AD688 reference absolute ±10 V accuracy performance previously unavailable in monolithic form. The AD688 uses a proprietary ion-implanted buried Zener diode, and laser wafer drift trimming of high stability thin-film resistors to provide outstanding performance.

±10 V Reference

FUNCTIONAL BLOCK DIAGRAM

NOISE

REDUCTION

7 6 4 3

5 9 10 8 12 11 13

GND

GAIN

SENSE

ADJ

+IN

HIGH

LOW

NC = NO CONNECT

Figure 1.

A3 IN

BAL ADJ

+10V OUT

AD688

SENSE

A4 IN

AD688

+10V OUT

FORCE

–10V OUT

SENSE

–10V OUT

FORCE

–V

00815-001

The AD688 includes the basic reference cell and three additional amplifiers. The amplifiers are laser-trimmed for low offset and low drift and maintain the accuracy of the reference. The amplifiers are configured to allow Kelvin connections to the load and/or boosters for driving long lines or high current loads, delivering the full accuracy of the AD688 where it is required in the application circuit.

The low initial error allows the AD688 to be used as a system reference in precision measurement applications requiring 12-bit absolute accuracy. In such systems, the AD688 can provide a known voltage for system calibration; the cost of periodic recalibration can therefore be eliminated. Furthermore, the mechanical instability of a trimming potentiometer and the potential for improper calibration can be eliminated by using the AD688 and calibration software.

The AD688 is available in commercial version. Specified over

the −40

C to +85oC temperature range, the AD688 is offered in

wide body 16-lead SOIC and 16-lead CERDIP packages,

Covered by Patent Number 4,644,253

PRODUCT HIGHLIGHTS

1. Precision Tracking. The AD688 offers precision tracking ±10 V Kelvin output connections with no external components. Tracking error is less than 1.5 mV and finetrim is available for applications requiring exact symmetry between the +10 V and −10 V outputs.

2. Accuracy. The AD688 offers 12-bit absolute accuracy without any user adjustments. Optional fine-trim connections are provided for applications requiring higher precision. The fine-trimming does not alter the operating conditions of the Zener or the buffer amplifiers and thus does not increase the temperature drift.

3. Low output noise. Output noise of the AD688 is low— typically 6 µV p-p. A pin is provided for broadband noise filtering using an external capacitor.

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

Page 2

AD688

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TABLE OF CONTENTS

Specifications..................................................................................... 3

Turn On Ti me ................................................................................8

Absolute Maximum Ratings............................................................ 4

ESD Caution.................................................................................. 4

Pin Configuration and Function Descriptions............................. 5

Theory of Operation ........................................................................ 6

Applications....................................................................................... 7

Calibration..................................................................................... 7

Noise Performance and Reduction ............................................ 8

REVISION HISTORY

3/05—Rev. A to Rev. B

Updated Format..................................................................Universal

Added AD688ARWZ.........................................................Universal

Removed AD688SQ ...........................................................Universal

Updated Outline Dimensions....................................................... 13

Changes to Ordering Guide.......................................................... 13

Temperature Performance............................................................9

Kelvin Connections.......................................................................9

Dynamic Performance............................................................... 11

Bridge Driver Circuit ................................................................. 12

Outline Dimensions....................................................................... 13

Ordering Guide .......................................................................... 13

Rev. B | Page 2 of 16

Page 3

AD688

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SPECIFICATIONS

Typical @ 25°C, +10 V output, VS = ±15 V unless otherwise noted.1 Specifications shown in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. All min and max specifications are guaranteed.

Table 1.

AD688AQ AD688BQ AD688ARWZ Min Typ Max Min Typ Max Min Typ Max Unit

OUTPUT VOLTAGE ERROR

+10 V, −10 V Outputs −5 +5 −2 +2 −4 +4

±10 V TRACKING ERROR

−3 +3 −1.5 +1.5 −1.5 +1.5

OUTPUT VOLTAGE DRIFT

+10 V, −10 V Outputs

0°C to +70°C (A, B) ±2

−40°C to +85°C (A, B)

−3 +3 –3 +3 –8

–1.5 +1.5

ppm/°C

GAIN ADJ AND BAL ADJ2

Trim Range ± 5 ±5 ±5 mV Input Resistance 150 150 150 kΩ

LINE REGULATION

to T

MAX

–200 +200 –200 +200 –200 +200

MIN

LOAD REGULATION

to T

MIN

MAX

+10 V Output, 0<I

−10 V Output, −10<I

<10 mA ±50 ±50 ±50 µV/mA

OUT

<0 mA ±50 ±50 ±50 µV/mA

OUT

SUPPLY CURRENT

to T

MIN

MAX

Power Dissipation 270 360 270 360 360 mW

OUTPUT NOISE (ANY OUTPUT)

0.1 Hz to 10 Hz 6 6 6 µV p-p

Spectral Density, 100 Hz 140 140 140 nV√Hz LONG-TERM STABILITY (@ 25°C) 15 15 15 ppm/1000 hours BUFFER AMPLIFIERS

Offset Voltage 100 100 100 µV

Offset Voltage Drift 1 1 1 µV/°C

Bias Current 20 20 20 nA

Open-Loop Gain 110 110 110 dB

Output Current A3, A4

−10 +10 −10 +10 −10 +10

Common-Mode Rejection (A3, A4)

VCM = 1 V p-p 100 100 100 dB

Short-Circuit Current 50 50 50 mA TEMPERATURE RANGE

Specified Performance

A, B Grades −40 +85 −40 +85 −40 +85 °C

See for output configuration. Figure 4

Gain and balance adjustments guaranteed capable of trimming output voltage error and symmetry error to zero.

Test Conditions: +VS = +18 V, −VS = –18 V; +VS = +13.5 V, −VS = −13.5 V.

mV mV

ppm/°C

µV/V

Rev. B | Page 3 of 16

Page 4

AD688

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ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

+VS to −V Power Dissipation (25°C)

Storage Temperature −65°C to +150°C Lead Temperature

(Soldering, 10 s) Package Thermal Resistance

Output Protection:

Q Package 600 mW

Q (θJA/θJC) 120/35°C/W

All outputs safe if shorted to ground

36 V

+300°C

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Rev. B | Page 4 of 16

Page 5

AD688

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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

+10V OUT FORCE

+10V OUT SENSE

GAIN ADJ

NOISE REDUCTION

A3 IN

4 5

HIGH

LOW

NC = NO CONNECT

AD688

TOP VIEW

(Not to Scale)

–V

–10V OUT FORCE

15 14

–10V OUT SENSE A4 IN

BAL ADJ

11 10

NC GND SENSE +IN

00815-002

Figure 2. Pin Configuration

Table 3. Pin Function Descriptions

Pin No. Mnemonic Description

1 +10 V OUT FORCE +10 V Output with Kelvin Force. Connect to Pin 3. 2 +V

Positive Power Supply. 3 +10 V OUT SENSE +10 V Output with Kelvin Sense. Connect to Pin 1. 4 A3 IN + Input to A3. Connect to V

HIGH

, Pin 6. 5 GAIN ADJ Reference Gain Adjustment for Calibration. See the Calibration section. 6 V

HIGH

7 NOISE REDUCTION

Unbuffered Reference High Output. Noise Filtering Pin. Connect external 1 µF capacitor to ground to reduce output noise, see the

Noise Performance and Reduction section. May be left open.

8 V

LOW

Unbuffered Reference Low Output. 9 GND SENSE +IN Gound with Kelvin Sense. 10 NC No Connection. Leave floating. 11 NC No Connection. Leave floating. 12 BAL ADJ Reference Centering Adjustment for Calibration. See the Calibration section. 13 A4 IN + Input to A4. Connect to V

LOW

, Pin 8. 14 −10 V OUT SENSE −10 V Output with Kelvin Sense. Connect to Pin 15. 15 −10 V OUT FORCE −10 V Output with Kelvin Force. Connect to Pin 14. 16 −V

Negative Power Supply.

Rev. B | Page 5 of 16

Page 6

AD688

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THEORY OF OPERATION

The AD688 consists of a buried Zener diode reference, amplifiers and associated thin-film resistors as shown in Figure 3. The temperature compensation circuitry provides the device with a temperature coefficient of 1.5 ppm/°C or less.

Amplifier A1 performs several functions. A1 primarily acts to amplify the Zener voltage to the required 20 V. In addition, A1 also provides for external adjustment of the 20 V output through Pin 5 (GAIN ADJ). Using the bias compensation resistor between the Zener output and the noninverting input to A1, a capacitor can be added at the noise reduction pin (Pin 7) to form a low-pass filter and reduce the noise contribution of the Zener to the circuit. Two matched 12 kΩ nominal thin-film resistors (R4 and R5) divide the 20 V output in half.

Ground sensing for the circuit is provided by amplifier A2. The noninverting input (Pin 9) senses the system ground and forces the midpoint of resistors R4 and R5 to be a virtual ground. Pin 12 (BAL ADJ) can be used for fine adjustment of this midpoint transfer.

Amplifiers A3 and A4 are internally compensated and are used to buffer the voltages at Pin 6 and Pin 8 as well as to provide a full Kelvin output. Thus, the AD688 has a full Kelvin capability by providing the means to sense a system ground, and forced and sensed outputs referenced to that ground.

NOISE

REDUCTION

7 6 4 3

5 9 10 8 12 11 13

GND

GAIN

SENSE

ADJ

+IN

HIGH

LOW

NC = NO CONNECT

Figure 3. Functional Block Diagram

BAL ADJ

+10V OUT

AD688

SENSEA3 IN

A4 IN

+10V OUT

FORCE

–10V OUT

SENSE

–10V OUT

FORCE

–V

00815-003

Rev. B | Page 6 of 16

Page 7

AD688

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APPLICATIONS

The AD688 can be configured to provide ±10 V reference outputs as shown in Figure 4. The architecture of the AD688 provides ground sense and uncommitted output buffer amplifiers which offer the user a great deal of functional flexibility. The AD688 is specified and tested in the configuration shown in Figure 4. The user may choose to take advantage of other configuration options available with the AD688; however performance in these configurations is not guaranteed to meet the stringent data sheet specifications.

Unbuffered outputs are available at Pin 6 and Pin 8. Loading of these unbuffered outputs will impair circuit performance.

Amplifiers A3 and A4 can be used interchangeably. However, the AD688 is tested (and the specifications are guaranteed) with the amplifiers connected as indicated in Figure 4. When either A3 or A4 is unused, its output force and sense pins should be connected and the input tied to ground.

Two outputs of the same voltage polarity may be obtained by connecting both A3 and A4 to the appropriate unbuffered output on Pin 6 or Pin 8. Performance in these dual output configurations will typically meet data sheet specifications.

voltage and the position of the center tap within the span. The gain adjustment should be performed first. Although the trims are not interactive within the device, the gain trim will move the balance trim point as it changes the magnitude of the span.

Figure 5 shows the gain and balance trims of the AD688. A 100 kΩ 20-turn potentiometer is used for each trim. The potentiometer for the gain trim is connected between Pin 6 (V

HIGH

) and Pin 8 (V

) with the wiper connected to Pin 5

LOW

(GAIN ADJ). The potentiometer is adjusted to produce exactly 20 V between Pin 1 and Pin 15, the amplifier outputs. The balance potentiometer, also connected between Pin 6 and Pin 8 with the wiper to Pin 12 (BAL ADJ), is then adjusted to center the span from +10 V to −10 V.

Input impedance on both the GAIN ADJ and the BAL ADJ pins is approximately 150 kΩ. The gain adjustment trim network effectively attenuates the 20 V across the trim potentiometer by a factor of about 1150 to provide a trim range of –5.8 mV to +12.0 mV with a resolution of approximately 900 µV/turn (20-turn potentiometer). The balance adjustment trim network attenuates the trim voltage by a factor of about 1250, providing a trim range of ±8 mV with a resolution of 800 µV/turn.

5 9

SYSTEM

GROUND

R1R2R4

AD688

0.1

SYSTEM GROUND

+10V

–10V

+15V SUPPLY

–15V SUPPLY

Figure 4. +10 V and −10 V Outputs

CALIBRATION

Generally, the AD688 will meet the requirements of a precision system without additional adjustment. Initial output voltage error of 2 mV and output noise specs of 6 µV p-p allow for accuracies of 12 to 16 bits. However, in applications where an even greater level of accuracy is required, additional calibration may be called for. The provision for trimming has been made through the use of the GAIN ADJ and BAL ADJ pins (Pin 5 and Pin 12, respectively).

The AD688 provides a precision 20 V span with a center tap which is used with the buffer and ground sense amplifiers to achieve the ±10 V output configuration. GAIN ADJ and BAL ADJ can be used to trim the magnitude of the 20 V span

Trimming the AD688 introduces no additional errors over temperature, so precision potentiometers are not required.

When balance adjustment is not necessary, Pin 12 should be left floating. If gain adjustment is not required, Pin 5 should also be left floating.

20kΩ

NOISE

1µF

REDUCTION

SYSTEM

BALANCE

100k

ADJUST

20T

Ω

00815-004

GROUND

100kΩ

20T

GAIN ADJUST

AD688

12 11

Figure 5. Gain and Balance Adjustment with Noise Reduction

+15V

0.1

+10V

–10V

+15V SUPPLY

SYSTEM GROUND

–15V SUPPLY

00815-005

Rev. B | Page 7 of 16

Page 8

AD688

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NOISE PERFORMANCE AND REDUCTION

The noise generated by the AD688 is typically less than 6 µV p-p over the 0.1 Hz to 10 Hz band. Noise in a 1 MHz bandwidth is approximately 840 µV p-p. The dominant source of this noise is the buried Zener which contributes approximately 140 nV/√Hz. In comparison, the op amp’s contribution is negligible. Figure 6 shows the 0.1 Hz to 10 Hz noise of a typical AD688.

any thermal tails when the horizontal scale is expanded to 2 ms/cm in Figure 9.

10V

100 90

–V

1mV

100µs

00815-006

1µV

1mV

100 90

10 0%

Figure 6. 0.1 Hz to 10 Hz Noise

If further noise reduction is desired, an optional capacitor can be added between the noise reduction pin and ground as shown in Figure 5. This will form a low-pass filter with the 5 kΩ R

on the output of the Zener cell. A 1 µF capacitor will have a 3 dB point at 32 Hz and will reduce the high frequency noise (to 1 MHz) to about 250 µV p-p. Figure 7 shows the 1 MHz noise of a typical AD688 both with and without a 1 µF capacitor.

= 1µF

200µV

50µs

OUT

10 0%

10V

00815-008

Figure 8. Turn On Characteristics: Electrical Turn On

100 90

–V

OUT

10 0%

10V

1mV

2ms

00815-009

Figure 9. Turn On Characteristics: Extended Time Scale

Output turn on time is modified when an external noise reduction capacitor is used. When present, this capacitor presents an additional load to the internal Zener diode’s current source, resulting in a somewhat longer turn on time. In the case of a 1 µF capacitor, the initial turn on time is approximately 100 ms (Figure 10).

When the noise reduction feature is used, a 20 kΩ resistor between Pin 6 and Pin 2 is required for proper startup.

NO C

10V

100 90

Figure 7. Effect of 1 µF Noise Reduction Capacitor on Broadband Noise

00815-007

TURN ON TIME

–V

Upon application of power (cold start), the time required for

the output voltage to reach its final value within a specified

error is the turn on settling time. Two components normally associated with this are: time for active circuits to settle and

OUT

10 0%

time for thermal gradients on the chip to stabilize. Figure 8 and Figure 9 show the turn on characteristics of the AD688. They show the settling time to be about 600 µs. Note the absence of

Rev. B | Page 8 of 16

10V

Figure 10. Turn On With 1 µF C

1mV

20ms

00815-010

Page 9

AD688

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TEMPERATURE PERFORMANCE

The AD688 is designed for precision reference applications where temperature performance is critical. Extensive temperature testing ensures that the device’s high level of performance is maintained over the operating temperature range.

Figure 11 shows the typical output voltage drift and illustrates the test methodology. The box in Figure 11 is bounded on the sides by the operating temperature extremes, and on top and bottom by the maximum and minimum +10 V output error voltages measured over the operating temperature range. The slopes of the diagonals drawn for both the +10 V and –10 V outputs determine the performance grade of the device.

– E

MAX

+10V OUTPUT SLOPE = T.C. =

–10V OUT

5 4 3 2 1 0

–1

+10V OUT

–2 –3 –4

ERROR VOLTAGE FROM ±10V (mV)

–5 –6

–60 –50 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 100 110 120 130

MIN

TEMPERATURE (°C)

+10V E

MAX

MIN

MAX

(85°C––40°C) × 10 × 10

Figure 11. Typical AD688AQ Temperature Drift

Each AD688A and B grade unit is tested at −40°C, −25°C, 0°C, +25°C, +50°C, +70°C, and +85°C. This approach ensures that the variations of output voltage that occur as the temperature changes within the specified range will be contained within a box whose diagonal has a slope equal to the maximum specified drift. The position of the box on the vertical scale will change from device to device as initial error and the shape of the curve vary. Maximum height of the box for the appropriate temperature range is shown in Figure 12.

MIN

– T

) × 10 × 10

MIN

2.2mV – –3.2mV

= 3ppm/°C

MAX

–6

SLOPE

00815-011

MAXIMUM OUTPUT CHANGE (mV)

DEVICE GRADE

AD688AQ

AD688BQ

AD688ARWZ

0 TO +70°C

1.40 (TYP) 3.75

1.05

–40°C TO +85°C

3.75

4.0

00815-012

Figure 12. Maximum + 10 V or −10 V Output Change

Duplication of these results requires a combination of high accuracy and stable temperature control in a test system. Evaluation of the AD688 will produce curves similar to those in Figure 11, but output readings may vary depending on the test methods and equipment utilized.

KELVIN CONNECTIONS

Force and sense connections, also referred to as Kelvin connections, offer a convenient method of eliminating the effects of voltage drops in circuit wires. As seen in Figure 13a, the load current and wire resistance produce an error (V R × I

) at the load. The Kelvin connection of Figure 13b

overcomes the problem by including the wire resistance within the forcing loop of the amplifier and sensing the load voltage. The amplifier corrects for any errors in the load voltage. In the circuit shown, the output of the amplifier would actually be at 10 V + V

and the voltage at the load would be the desired

ERROR

10 V.

10V

i = 0

+ –

LOAD

V = 10V – RI

i = 0

V = 10V + RI

V = 10V

LOAD

Figure 13. Advantage of Kelvin Connection

The AD688 has three amplifiers which can be used to implement Kelvin connections. Amplifier A2 is dedicated to the ground force-sense function while uncommitted amplifiers A3 and A4 are free for other force-sense chores.

In some applications, one amplifier may be unused. In such cases, the unused amplifier should be connected as a unity-gain follower (force and sense pins tied together) and the input should be connected to ground.

An unused amplifier may be used for other circuit functions as well. Figure 14 through Figure 19 show the typical performance of A3 and A4.

ERROR

00815-014

Rev. B | Page 9 of 16

Page 10

AD688

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100

OPEN-LOOP GAIN (dB)

–20

10 10M100

110

100

CMRR (dB)

GAIN

PHASE

1k 10k 100k 1M

FREQUENCY (Hz)

Figure 14. A3, A4 Open-Loop Frequency Response

VS =±15V



= 1V p-p 25°C

–30

–60

–90

–120

–150

–180

PHASE (Degrees)

00815-015

100

NOISE SPECTRAL DENSITY (nV/ Hz)

1 10k10

100 1k

FREQUENCY (Hz)

Figure 17. Input Noise Voltage Spectral Density

100 90

00815-018

10 10M100

110

100

POWER SUPPLY REJECTION (dB)

10 10M100

1k 10k 100k 1M

FREQUENCY (Hz)

Figure 15. A3, A4 CMR vs. Frequency

VS = ±15V WITH 1V p-p SINE WAVE

+SUPPLY

–SUPPLY

1k 10k 100k 1M

FREQUENCY (Hz)

Figure 16. A3, A4 PSR vs. Frequency

00815-016

00815-017

10 0%

Figure 18. Unity-Gain Follower Pulse Response (Large Signal)

50mV

100 90

10 0%

Figure 19. Unity-Gain Follower Pulse Response (Small Signal)

00815-019

00815-020

Rev. B | Page 10 of 16

Page 11

AD688

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10V

1mV

–

A3 OR A4

200mV

OUT

Ω

10V 0V

Ω

00815-024

1µs

00815-025

DYNAMIC PERFORMANCE

The output buffer amplifiers (A3 and A4) are designed to provide the AD688 with static and dynamic load regulation superior to less complete references.

Many A/D and D/A converters present transient current loads to the reference, and poor reference response can degrade the converter’s performance.

Figure 20, Figure 21, and Figure 22 display the characteristic of the AD688 output amplifier driving a 0 mA to 10 mA load.

A3 OR A4

10V

Figure 20. Transient Load Test Circuit

200mV

100 90

OUT

1kΩ

10V

00815-021

500ns

Figure 23. Transient and Constant Load Test Circuit

100

OUT

1mV/CM

OUT

200mV/

10 0%

Figure 24. Transient Response 5 mA to 10 mA Load

In some applications, a varying load may be both resistive and capacitive in nature, or may be connected to the AD688 by a long capacitive cable. Figure 25 and Figure 26 display the output amplifier characteristics driving a 1000 pF, 0 mA to 10 mA load.

Figure 21. Large-Scale Transient Response

1mV

100 90

OUT

10 0%

2µs

Figure 22. Fine-Scale Settling for Transient Load

Figure 23 and Figure 24 display the output amplifier characteristic driving a 5 mA to 10 mA load, a common situation found when the reference is shared among multiple converters or is used to provide bipolar offset current.

00815-022

00815-023

OUT

1kΩ

10V

00815-026

10V

1000pF

Figure 25. Capacitive Load Transient Response Test Circuit

= 0

1000pF

200mV

100 90

10 0%

1µs

00815-027

Figure 26. Output Response with Capacitive Load

Figure 27 and Figure 28 display the crosstalk between output amplifiers. The top trace shows the output of A4, dc-coupled and offset by 10 V, while the output of A3 is subjected to a 0 mA to 10 mA load current step. The transient at A4 settles in about 1 µs, and the load-induced offset is about 100 µV.

Rev. B | Page 11 of 16

Page 12

AD688

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10V

–

OUT

Figure 27. Load Crosstalk Test Circuit

1kΩ

10V 0V

10V

–

00815-028

100 90

1mV

100 90

OUT

10 0%

2µs

00815-029

Figure 28. Load Crosstalk

Attempts to drive a large capacitive load (in excess of 1000 pF) may result in ringing or oscillation, as shown in the step response photo (Figure 29). This is due to the additional pole formed by the load capacitance and the output impedance of the amplifier, which consumes phase margin. The recommended method of driving capacitive loads of this magnitude is shown in Figure 30. The 150 Ω resistor isolates the capacitive load from the output stage, while the 10 kΩ resistor provides a dc feedback path and preserves the output accuracy. The 1 µF capacitor provides a high frequency feedback loop. The performance of this circuit is shown in Figure 31.

100 90

OUT

10V

200µs

00815-032

Figure 31. Output Amplifier Step Response Using Figure 30 Compensation

BRIDGE DRIVER CIRCUIT

The Wheatstone bridge is a common transducer. In its simplest form, a bridge consists of four 2-terminal elements connected to form a quadrilateral, a source of excitation connected along one of the diagonals and a detector comprising the other diagonal.

In this unipolar drive configuration, the output voltage of the bridge is riding on a common-mode voltage signal equal to approximately V necessarily be limited to high common-mode rejection techniques such as instrumentation or isolation amplifiers. However, if the bridge is driven from a pair of bipolar supplies, then the common-mode voltage is ideally eliminated and the restrictions on any processing elements that follow are relaxed.

As shown in Figure 32, the AD688 is an excellent choice for the control element in a bipolar bridge driver scheme. Transistors Q1 and Q2 serve as series pass elements to boost the current drive capability to the 57 mA required by the typical 350 Ω bridge. A differential gain stage may still be required if the bridge balance is not perfect.

/2. Further processing of this signal may

220Ω

+15V

Q1 = 2N3904

OUT

10 0%

10V

Figure 29. Output Amplifier Step Response, C

10k

Ω

1µF

150

–

Figure 30. Compensation for Capacitive Loads

200µs

00815-030

= 1 µF

Ω

C 1µF

OUT

00815-031

Figure 32. Bipolar Bridge Drive

Rev. B | Page 12 of 16

AD688

12 11

–

220Ω

2N3906

–15V

–V

00815-033

Page 13

AD688

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OUTLINE DIMENSIONS

0.005

(0.13)

MIN

PIN 1

0.200 (5.08) MAX

0.200 (5.08)

0.125 (3.18)

0.023 (0.58)

0.014 (0.36)

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

Figure 33. 16-Lead Ceramic Dual In-Line Package [CERDIP]

0.098 (2.49)

0.840 (21.34) MAX

MAX

0.100

0.070 (1.78)

(2.54)

0.030 (0.76)

BSC

0.310 (7.87)

0.220 (5.59)

0.060 (1.52)

0.015 (0.38)

0.150 (3.81) MIN

SEATING PLANE

(Q-16)

Dimensions shown in inches and (millimeters)

10.50 (0.4134)

10.10 (0.3976)

15°

0°

0.320 (8.13)

0.290 (7.37)

0.015 (0.38)

0.008 (0.20)

1.27 (0.0500) BSC

0.30 (0.0118)

0.10 (0.0039)

COPLANARITY

0.10

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

0.51 (0.0201)

0.31 (0.0122)

COMPLIANT TO JEDEC STANDARDS MS-013AA

7.60 (0.2992)

7.40 (0.2913)

2.65 (0.1043)

2.35 (0.0925)

SEATING PLANE

10.65 (0.4193)

10.00 (0.3937)

0.33 (0.0130)

0.20 (0.0079)

0.75 (0.0295)

0.25 (0.0098)

8° 0°

× 45°

1.27 (0.0500)

0.40 (0.0157)

Figure 34. 16-Lead Standard Small Outline Package [SOIC]

Wide Body

(RW-16)

Dimensions shown in millimeter and (inches)

ORDERING GUIDE

Temperature Range

Package Description Package Option

Model

Initial Error

Temperature Coefficient

AD688AQ 5 mV 3 ppm/°C −40°C to + 85°C 16-Lead CERDIP Q-16 AD688BQ 2 mV 3 ppm/°C −40°C to + 85°C 16-Lead CERDIP Q-16 AD688ARWZ1 4 mV 8 ppm/°C −40°C to + 85°C 16-Lead SOIC RW-16

Z = Pb-free part.

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NOTES

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NOTES

C00815-0-3/05(B)

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