Datasheet AD6644 Datasheet (Analog Devices)

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Page 1

14-Bit, 40 MSPS/65 MSPS

FEATURES 65 MSPS Guaranteed Sample Rate 40 MSPS Version Available Sampling Jitter < 300 fs 100 dB Multitone SFDR

1.3 W Power Dissipation Differential Analog Inputs Digital Outputs

Two’s Complement Format

3.3 V CMOS-Compatible Data Ready for Output Latching

APPLICATIONS Multichannel, Multimode Receivers AMPS, IS-136, CDMA, GSM, Third Generation Single Channel Digital Receivers Antenna Array Processing Communications Instrumentation Radar, Infrared Imaging Instrumentation

PRODUCT DESCRIPTION

The AD6644 is a high-speed, high-performance, monolithic 14-bit analog-to-digital converter. All necessary functions, including track-and-hold (T/H) and reference, are included onchip to provide a complete conversion solution. The AD6644 provides CMOS-compatible digital outputs. It is the third generation in a wideband ADC family, preceded by the AD9042 (12-bit 41 MSPS) and the AD6640 (12-bit 65 MSPS, IF sampling.)

A/D Converter

AD6644

Designed for multichannel, multimode receivers, the AD6644 is part of ADI’s new SoftCell™ transceiver chipset. The AD6644 achieves 100 dB multitone, spurious-free dynamic range (SFDR) through the Nyquist band. This breakthrough performance eases the burden placed on multimode digital receivers (software radios) which are typically limited by the ADC. Noise performance is exceptional; typical signal-to-noise ratio is 74 dB.

The AD6644 is also useful in single channel digital receivers designed for use in wide-channel bandwidth systems (CDMA, W-CDMA). With oversampling, harmonics can be placed outside the analysis bandwidth. Oversampling also facilitates the use of decimation receivers (such as the AD6620), allowing the noise floor in the analysis bandwidth to be reduced. By replacing traditional analog filters with predictable digital components, modern receivers can be built using fewer “RF” components, resulting in decreased manufacturing costs, higher manufacturing yields, and improved reliability.

The AD6644 is built on Analog Devices’ high-speed complementary bipolar process (XFCB) and uses an innovative, multipass circuit architecture. Units are packaged in a 52-terminal LowProfile Quad Plastic Flatpack (LQFP) specified from –25°C to +85°C.

PRODUCT HIGHLIGHTS

1. Guaranteed sample rate is 65 MSPS.

2. Fully differential analog input stage.

3. Digital outputs may be run on 3.3 V supply for easy interface to digital ASICs.

4. Complete Solution: reference and track-and-hold.

5. Packaged in small, surface-mount, plastic, 52-terminal LQFP.

FUNCTIONAL BLOCK DIAGRAM

AVCCDV

AIN

2.4V

REF

ENCODE

SoftCell is a trademark of Analog Devices, Inc.

INTERNAL

TIMING

TH2TH1A1

ADC1 DAC1

MSB LSB

GND D8D9D10D11D12D13DRYOVRDMID D0D1D2D3D4D5D6D7

REV. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

TH3

DIGITAL ERROR CORRECTION LOGIC

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2000

TH4

ADC2 DAC2

TH5

ADC3

AD6644

Page 2

AD6644–SPECIFICATIONS

DC SPECIFICATIONS

Parameter Temp Level Min Typ Max Min Typ Max Unit

RESOLUTION 14 14 Bits

ACCURACY

No Missing Codes Full II Guaranteed Guaranteed Offset Error Full II –10 3 +10 –10 3 +10 mV Gain Error Full II –10 –6 +10 –10 –6 +10 % FS Differential Nonlinearity (DNL) Full II –1.0 ± 0.25 +1.5 –1.0 ± 0.25 +1.5 LSB Integral Nonlinearity (INL) Full V ± 0.50 ±0.50 LSB

TEMPERATURE DRIFT

Offset Error Full V 10 10 ppm/°C Gain Error Full V 95 95 ppm/°C

POWER SUPPLY REJECTION (PSRR) Full V ± 1.0 ±1.0 mV/V

REFERENCE OUT (V ANALOG INPUTS (AIN, AIN)

Differential Input Voltage Range Full V 2.2 2.2 V p-p Differential Input Resistance Full V 1 1 kΩ Differential Input Capacitance 25°C V 1.5 1.5 pF

POWER SUPPLY

Supply Voltage

Supply Current

(AVCC = 5.0 V) Full II 245 276 245 276 mA

VCC

(DVCC = 3.3 V) Full II 30 36 30 36 mA

VCC

POWER CONSUMPTION Full II 1.3 1.5 1.3 1.5 W

NOTES

AVCC may be varied from 4.85 V to 5.25 V. However, rated ac (harmonics) performance is valid only over the range AVCC = 5.0 V to 5.25 V.

Specifications subject to change without notice.

REF

(AVCC = 5 V, DVCC = 3.3 V; T

Test AD6644AST-40 AD6644AST-65

) Full V 2.4 2.4 V

Full II 4.85 5.0 5.25 4.85 5.0 5.25 V Full II 3.0 3.3 3.6 3.0 3.3 3.6 V

= –25ⴗC, T

MIN

= +85ⴗC)

MAX

DIGITAL SPECIFICATIONS

Parameter Temp Level Min Typ Max Min Typ Max Unit

ENCODE INPUTS (ENC, ENC)

Differential Input Voltage Differential Input Resistance 25°C V 10 10 kΩ Differential Input Capacitance 25°C V 2.5 2.5 pF

LOGIC OUTPUTS (D13–D0, DRY, OVR)

Logic Compatibility CMOS CMOS Logic “1” Voltage Logic “0” Voltage Output Coding Two’s Complement Two’s Complement DMID Full V DVCC/2 DVCC/2 V

NOTES

All ac specifications tested by driving ENCODE and ENCODE differentially. Reference Figure 22 for performance versus encode power.

Digital output logic levels: DVCC = 3.3 V, C

Specifications subject to change without notice.

SWITCHING SPECIFICATIONS

Parameter Temp Level Min Typ Max Min Typ Max Unit

Maximum Conversion Rate Full II 40 65 MSPS Minimum Conversion Rate Full IV 15 15 MSPS ENCODE Pulsewidth High Full IV 10 6.5 ns ENCODE Pulsewidth Low Full IV 10 6.5 ns

Specifications subject to change without notice.

(AVCC = 5 V, DVCC = 3.3 V; T

Test AD6644AST-40 AD6644AST-65

Full IV 0.4 0.4 V p-p

Full V 2.5 2.5 V Full V 0.4 0.4 V

= 10 pF. Capacitive loads >10 pF will degrade performance.

LOAD

= –25ⴗC, T

MIN

= +85ⴗC)

MAX

(AVCC = 5 V, DVCC = 3.3 V; ENCODE and ENCODE = Maximum Conversion Rate MSPS; T –25ⴗC, T

= +85ⴗC)

MAX

Test AD6644AST-40 AD6644AST-65

MIN

–2–

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Page 3

AD6644

AC SPECIFICATIONS

(AVCC = 5 V, DVCC = 3.3 V; ENCODE and ENCODE = Maximum Conversion Rate MSPS; T

Test AD6644AST-40 AD6644AST-65

Parameter Temp Level Min Typ Max Min Typ Max Unit

SNR

Analog Input 2.2 MHz 25°C II 74.5 72 74.5 dB @ –1 dBFS 15.5 MHz 25°C II 74.0 72 74.0 dB

30.5 MHz 25°C II 73.5 72 73.5 dB

SINAD

Analog Input 2.2 MHz 25°C II 74.5 72 74.5 dB @ –1 dBFS 15.5 MHz 25°C II 74.0 72 74.0 dB

30.5 MHz 25°C V 73.0 73.0 dB

WORST HARMONIC

(2ND

or 3RD)

Analog Input 2.2 MHz 25°CII 92 83 92 dBc @ –1 dBFS 15.5 MHz 25°CII 90 83 90 dBc

30.5 MHz 25°C V 85 85 dBc

WORST HARMONIC (4

or Higher)

Analog Input 2.2 MHz 25°CII 93 85 93 dBc @ –1 dBFS 15.5 MHz 25°CII 92 85 92 dBc

30.5 MHz 25°C V 92 92 dBc

TWO-TONE SFDR2,

TWO-TONE IMD REJECTION

3, 4

Full V 100 100 dBFS

2, 4

F1, F2 @ –7 dBFS Full V 90 90 dBc

ANALOG INPUT BANDWIDTH 25°C V 250 250 MHz

NOTES

All ac specifications tested by driving ENCODE and ENCODE differentially.

AVCC = 5 V to 5.25 V for rated ac performance.

Analog input signal power swept from –7 dBFS to –100 dBFS.

F1 = 15 MHz, F2 = 15.5 MHz.

Specifications subject to change without notice.

= –25ⴗC, T

MIN

= +85ⴗC)

MAX

SWITCHING SPECIFICATIONS

(AVCC = 5 V, DVCC = 3.3 V; ENCODE and ENCODE = Maximum Conversion Rate MSPS; T –25ⴗC, T

= +85ⴗC, C

MAX

LOAD

= 10 pF)

MIN

Test AD6644AST-40/65

Parameter Name Temp Level Min Typ Max Unit

ENCODE INPUT PARAMETERS

Encode Period1 @ 65 MSPS t Encode Period Encode Pulsewidth High

@ 40 MSPS t

Encode Pulsewidth Low @ 65 MSPS t

@ 65 MSPS t

ENC

ENCH

ENCL

Full V 15.4 ns Full V 25 ns Full IV 6.2 7.7 9.2 ns Full IV 6.2 7.7 9.2 ns

ENCODE/DATA READY

Encode Rising to Data Ready Falling t Encode Rising to Data Ready Rising t

E_DR

Full IV 2.6 3.4 4.6 ns

+ t

ENCH

@ 65 MSPS (50% Duty Cycle) Full IV 10.3 11.1 12.3 ns @ 40 MSPS (50% Duty Cycle) Full IV 15.1 15.9 17.1 ns

ENCODE/DATA (D13:0), OVR

ENC to DATA Falling Low t ENC to DATA Rising Low t ENCODE to DATA Delay (Hold Time) ENCODE to DATA Delay (Setup Time)

E_FL

E_RL

H_E

S_E

Full IV 3.8 5.5 9.2 ns Full IV 3.0 4.3 6.4 ns Full IV 3.0 4.3 6.4 ns

– t

ENC

E_FL

Encode = 65 MSPS (50% Duty Cycle) Full IV 6.2 9.8 11.6 ns Encode = 40 MSPS (50% Duty Cycle) Full IV 15.9 19.4 21.2 ns

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–3–

Page 4

AD6644–SPECIFICATIONS

Test AD6644AST-40/65

Parameter Name Temp Level Min Typ Max Unit

DATA READY (DRY

Data Ready to DATA Delay (Hold Time)

Encode = 65 MSPS (50% Duty Cycle) Full IV 8.0 8.6 9.4 ns Encode = 40 MSPS (50% Duty Cycle) Full IV 12.8 13.4 14.2 ns

Data Ready to DATA Delay (Setup Time)

@ 65 MSPS (50% Duty Cycle) Full IV 3.2 5.5 6.5 ns @ 40 MSPS (50% Duty Cycle) Full IV 8.0 10.3 11.3 ns

APERTURE DELAY t

APERTURE UNCERTAINTY (JITTER) t

NOTES

Several timing parameters are a function of t

To compensate for a change in duty cycle for t

Newt

= (t

H_DR

Newt

ENCODE to DATA Delay (Hold Time) is the absolute minimum propagation delay through the analog-to-digital converter.

ENCODE to DATA Delay (Setup Time) is calculated relative to 65 MSPS (50% duty cycle). In order to calculate t

Newt

DRY is an inverted and delayed version of the encode clock. Any change in the duty cycle of the clock will correspondingly change the duty cycle of DRY.

Data Ready to DATA Delay(t and t

Newt Newt

Specifications subject to change without notice.

H_DR

= (t

S_DR

= t

S_E

ENC(NEW)

for a given encode use the following equations:

S_DR

= t

H_DR

ENC(NEW)

= t

S_DR

ENC(NEW)

)/DATA, OVR

– % Change(t

– t

+ t

ENC

/2 – t

ENCH

/2 – t

ENCH

and t

ENC

)) × t

ENCH

)) × t

ENCH

(i.e., for 40 MSPS: Newt

S_E

and t

H_DR

+ t

H_DR

+ t

S_DR

H_DR

ENC

/2.

ENC

) is calculated relative to 65 MSPS (50% duty cycle) and is dependent on t

S_DR

(i.e., for 40 MSPS: Newt (i.e., for 40 MSPS: Newt

and t

H_DR

S_DR

ENCH

use the following equation:

S_DR

= 25 × 10–9 – 15.38 × 10–9 + 9.8 × 10–9 = 19.4 × 10 –9).

S_E(TYP)

= 12.5 × 10–9 – 7.69 × 10–9 + 8.6 × 10–9 = 13.4 × 10

H_DR(TYP)

= 12.5 × 10–9 – 7.69 × 10–9 + 5.5 × 10–9 = 10.3 × 10–9.

S_DR(TYP)

Note 6

25°C V 100 ps

25°C V 0.2 ps rms

for a given encode use the following equation:

S_E

and duty cycle. In order to calculate t

ENC

–9

H_DR

AIN

ENC, ENC

D[13:0], OVR

DRY

Nⴙ3

Nⴙ1

Nⴙ2

E_FL

E_RL

ENC

N–3

ENCH

Nⴙ1

ENCL

N–2

Nⴙ2Nⴙ3Nⴙ4

E_DR

N–1

S_DR

H_DR

S_E

Nⴙ4

H_E

Figure 1. Timing Diagram

–4–

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Page 5

AD6644

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS

EXPLANATION OF TEST LEVELS Test Level

Parameter Min Max Unit

ELECTRICAL

Voltage 0 7 V

Analog Input Voltage 0 AV

V Analog Input Current 25 mA Digital Input Voltage 0 AV

V Digital Output Current 4 mA

ENVIRONMENTAL

I 100% production tested. II 100% production tested at 25°C, and guaranteed by

design and characterization at temperature extremes. III Sample tested only. IV Parameter is guaranteed by design and characterization

testing. V Parameter is a typical value only.

Operating Temperature Range

(Ambient) –25 +85 °C Maximum Junction Temperature 150 °C Lead Temperature (Soldering, 10 sec) 300 °C Storage Temperature Range (Ambient) –65 +150 °C

NOTES

Absolute maximum ratings are limiting values to be applied individually, and beyond which the serviceability of the circuit may be impaired. Functional operability is not necessarily implied. Exposure to absolute maximum rating conditions for an extended period of time may affect device reliability.

Typical thermal impedances (52-terminal LQFP); θJA = 33°C/W; θJC = 11°C/W. These measurements were taken on a 6 layer board in still air with a solid ground plane.

ORDERING GUIDE

Model Temperature Range Package Description Package Option

AD6644AST-40 –25°C to +85°C (Ambient) 52-Terminal LQFP (Low-Profile Quad Plastic Flatpack) ST-52 AD6644AST-65 –25°C to +85°C (Ambient) 52-Terminal LQFP (Low-Profile Quad Plastic Flatpack) ST-52 AD6644ST/PCB Evaluation Board with AD6644AST–65

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD6644 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

REV. 0

–5–

Page 6

AD6644

PIN FUNCTION DESCRIPTIONS

Pin No. Name Function

1, 33, 43 DV

2, 4, 7, 10, 13, 15, 17, 19, 21, 23, GND Ground. 25, 27, 29, 34, 42

REF

5 ENCODE Encode Input; conversion initiated on rising edge. 6 ENCODE Complement of ENCODE; differential input. 8, 9, 14, 16, 18, 22, 26, 28, 30 AV

11 AIN Analog Input. 12 AIN Complement of AIN; Differential Analog Input. 20 C1 Internal Voltage Reference; bypass to ground with 0.1 µF microwave

24 C2 Internal Voltage Reference; bypass to ground with 0.1 µF microwave

31 DNC Do not connect this pin. 32 OVR Overrange Bit; high indicates analog input exceeds ±FS. 35 DMID Output Data Voltage Midpoint; approximately equal to (DVCC)/2. 36 D0 (LSB) Digital Output Bit (Least Significant Bit); Two’s Complement 37–41, 44–50 D1–D5, D6–D12 Digital Output Bits in Two’s Complement. 51 D13 (MSB) Digital Output Bit (Most Significant Bit); Two’s Complement. 52 DRY Data Ready Output.

3.3 V Power Supply (Digital) Output Stage Only.

2.4 V (Analog Reference). Bypass to ground with 0.1 µF microwave chip capacitor.

5 V Analog Power Supply.

chip capacitor.

GND V

REF

GND

ENCODE

GND

AIN

GND

PIN CONFIGURATION

D10

D11

D12

D13 (MSB)

DRY

PIN 1 IDENTIFIER

14 151617 18

GND

AD6644

TOP VIEW

(Not to Scale)

19 20 21 22 23 24 25 26

DNC = DO NOT CONNECT

GND

40414243444546474849505152

D3 D2

D1 D0 (LSB)

DMID

GND DV

OVR

DNC AV

GND AV

GND

–6–

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Page 7

AD6644

DEFINITIONS OF SPECIFICATIONS Analog Bandwidth

The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB.

Aperture Delay

The delay between the 50% point of the rising edge of the ENCODE command and the instant at which the analog input is sampled.

Aperture Uncertainty (Jitter)

The sample-to-sample variation in aperture delay.

Differential Analog Input Resistance, Differential Analog Input Capacitance, and Differential Analog Input Impedance

The real and complex impedances measured at each analog input port. The resistance is measured statically and the capacitance and differential input impedances are measured with a network analyzer.

Differential Analog Input Voltage Range

The peak-to-peak differential voltage that must be applied to the converter to generate a full-scale response. Peak differential voltage is computed by observing the voltage on a single pin and subtracting the voltage from the other pin, which is 180 degrees out of phase. Peak-to-peak differential is computed by rotating the inputs phase 180 degrees and taking the peak measurement again. The difference is then computed between both peak measurements.

Differential Nonlinearity

The deviation of any code width from an ideal 1 LSB step.

Encode Pulsewidth/Duty Cycle

Pulsewidth high is the minimum amount of time that the ENCODE pulse should be left in Logic 1 state to achieve rated performance; pulsewidth low is the minimum time ENCODE pulse should be left in low state. See timing implications of changing t

in text. At a given clock rate, these specs define

ENCH

an acceptable ENCODE duty cycle.

Full-Scale Input Power

Expressed in dBm. Computed using the following equation:

Power

Harmonic Distortion, 2nd

Full Scale

log



    

Full Scalerms

0 001

Input

     

The ratio of the rms signal amplitude to the rms value of the second harmonic component, reported in dBc.

Harmonic Distortion, 3rd

The ratio of the rms signal amplitude to the rms value of the third harmonic component, reported in dBc.

Integral Nonlinearity

The deviation of the transfer function from a reference line measured in fractions of 1 LSB using a “best straight line” determined by a least-square curve fit.

Minimum Conversion Rate

The encode rate at which the SNR of the lowest analog signal frequency drops by no more than 3 dB below the guaranteed limit.

Maximum Conversion Rate

The encode rate at which parametric testing is performed.

Output Propagation Delay

The delay between a differential crossing of ENCODE and ENCODE and the time when all output data bits are within valid logic levels.

Noise (For Any Range Within the ADC)

=××

NOISE

|| .–0 001 10



FS Signal

dBm dBFS

 

 



Where Z is the input impedance, FS is the full scale of the device for the frequency in question, SNR is the value for the particular input level and Signal is the signal level within the ADC reported in dB below full scale. This value includes both thermal and quantization noise.

Power Supply Rejection Ratio

The ratio of a change in input offset voltage to a change in power supply voltage.

Signal-to-Noise-and-Distortion (SINAD)

The ratio of the rms signal amplitude (set 1 dB below full scale) to the rms value of the sum of all other spectral components, including harmonics, but excluding dc.

Signal-to-Noise Ratio (Without Harmonics)

The ratio of the rms signal amplitude (set at 1 dB below full scale) to the rms value of the sum of all other spectral components, excluding the first five harmonics and dc.

Spurious-Free Dynamic Range (SFDR)

The ratio of the rms signal amplitude to the rms value of the peak spurious spectral component. The peak spurious component may or may not be a harmonic. May be reported in dBc (i.e., degrades as signal level is lowered), or dBFS (always related back to converter full scale).

Two-Tone Intermodulation Distortion Rejection

The ratio of the rms value of either input tone to the rms value of the worst third order intermodulation product; reported in dBc.

Two-Tone SFDR

The ratio of the rms value of either input tone to the rms value of the peak spurious component. The peak spurious component may or may not be an IMD product. May be reported in dBc (i.e., degrades as signal level is lowered), or in dBFS (always related back to converter full scale).

Worst Other Spur

The ratio of the rms signal amplitude to the rms value of the worst spurious component (excluding the 2nd and 3rd harmonic) reported in dBc.

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–7–

Page 8

AD6644

EQUIVALENT CIRCUITS

AIN

500⍀

AIN

Figure 2. Analog Input Stage

10k⍀

ENCODE

10k⍀

LOADS

BUF

10k⍀

CURRENT

MIRROR

T/H

REF

CURRENT

MIRROR

REF

D0–D13, OVR, DRY

Figure 5. Digital Output Stage

ENCODE

2.4V

100␮A

REF

LOADS

Figure 3. ENCODE Inputs

REF

CURRENT

MIRROR

C1 OR C2

Figure 4. Compensation Pin, C1 or C2

Figure 6. 2.4 V Reference

10k⍀

DMID

Figure 7. DMID Reference

–8–

REV. 0

Page 9

Typical Performance Characteristics–

AD6644

ENCODE = 65MSPS

–10

AIN = 2.2MHz @ –1dBFS SNR = 74.5dB

–20

SFDR = 92dBc

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

–130

5 101520

FREQUENCY – MHz

Figure 8. Single Tone at 2.2 MHz

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

–130

5 101520

FREQUENCY – MHz

ENCODE = 65MSPS AIN = 15.5MHz @ –1dBFS SNR = 74dB SFDR = 90dBc

Figure 9. Single Tone at 15.5 MHz

25 30

75.0

ENCODE = 65MSPS, AIN = –1dBFS

SNR – dB

74.5

74.0

73.5

73.0

72.5

72.0

TEMP = –25

T = ⴙ85 C

5 10152025

FREQUENCY – MHz

C, ⴙ25 C, ⴙ85 C

T = –25 C

T = ⴙ25 C

Figure 11. Noise vs. Analog Frequency (Nyquist)

WORST-CASE HARMONIC – dBc

T = ⴚ25 C, ⴙ85 C

510152025

ENCODE = 65MSPS, AIN = –1dBFS

TEMP = ⴚ25

ANALOG INPUT FREQUENCY – MHz

C, ⴙ25 C, ⴙ85 C

T = ⴙ25 C

Figure 12. Harmonics vs. Analog Frequency (Nyquist)

REV. 0

ENCODE = 65MSPS

–10

AIN = 30MHz @ –1dBFS SNR = 73.5dB

–20

SFDR = 85dBc

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

–130

5 101520

FREQUENCY – MHz

Figure 10. Single Tone at 30 MHz

25 30

–9–

PHASE NOISE OF ANALOG SOURCE

SNR – dB

DEGRADES PERFORMANCE

10 20 50 70 80

LOW NOISE ANALOG SOURCE

AIN = –1dBFS ENCODE = 65MSPS

30 40 60 90 ANALOG FREQUENCY – MHz

Figure 13. Noise vs. Analog Frequency (IF)

100

Page 10

AD6644

100

WORST OTHER SPUR

HARMONICS – dBc

HARMONICS (2nd, 3rd)

10 20 50 70 80

30 40 60 90 ANALOG FREQUENCY – MHz

ENCODE = 65MSPS AIN = –1dBFS

100

Figure 14. Harmonics vs. Analog Frequency (IF)

120

110

100

ENCODE = 65MSPS

AIN = 15.5MHz

WORST-CASE SPURIOUS – dBFS and dBc

–70

–80 0

–60 –50 –30

ANALOG INPUT POWER LEVEL – dBFS

–40

dBFS

dBc

SFDR = 90dB REFERENCE LINE

–20 –10

Figure 15. Single Tone SFDR

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

–130

5 101520

FREQUENCY – MHz

ENCODE = 65MSPS AIN = 15MHz,

15.5MHz @ –7dBFS NO DITHER

25 30

Figure 17. Two Tones at 15 MHz and 15.5 MHz

110

100

ENCODE = 65MSPS

F1 = 15MHz

F2 = 15.5MHz

WORST-CASE SPURIOUS – dBFS and dBc

–67 –27 –17

–77

dBc

–57 –47 –37

INPUT POWER LEVEL – (F1 = F2) dBFS

dBFS

SFDR = 90dB REFERENCE LINE

–7

Figure 18. Two-Tone SFDR

ENCODE = 65MSPS

–10

AIN = 19MHz,

19.5MHz @ –7dBFS

–20

NO DITHER

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

–130

5 101520

FREQUENCY – MHz

25 30

Figure 16. Two Tones at 19 MHz and 19.5 MHz

–10–

100

SNR, WORST SPURIOUS – dB and dBc

10 60 70

WORST SPUR

20 40 50

30 80 90

ENCODE FREQUENCY – MHz

AIN = 2.2MHz @ –1dBFS

SNR

Figure 19. SNR, Worst Spurious vs. Encode

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Page 11

AD6644

ENCODE = 65MSPS

–10

AIN = 15.5MHz @ –29.5dBFS NO DITHER

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

–130

0 5 10 15 20

FREQUENCY – MHz

25 30

Figure 20. 1M FFT Without Dither

100

ENCODE = 65MSPS

AIN = 15.5MHz NO DITHER

WORST-CASE SPURIOUS – dBc

–90 0

–80 –30 –10

–60 –20

–70 –50 –40

ANALOG INPUT POWER LEVEL – dBFS

SFDR = 90dB REFERENCE LINE

Figure 21. SFDR Without Dither

ENCODE = 65MSPS

–10

AIN = 15.5MHz @ –29.5dBFS DITHER @ –19dBm

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

–130

5 101520

Figure 23. 1M FFT with Dither

100

ENCODE = 65MSPS

AIN = 15.5MHz DITHER = –19dBm

WORST-CASE SPURIOUS – dBc

–80 –30 –10

–90

Figure 24. SFDR with Dither

FREQUENCY – MHz

SFDR = 90dB REFERENCE LINE

–60 –20

–70 –50 –40

ANALOG INPUT POWER LEVEL – dBFS

25 30

SFDR = 100dB REFERENCE LINE

WORST SPUR

SNR, WORST SPURIOUS – dB and dBc

65 –15.0

30.5MHz

–10.0

ENCODE INPUT POWER – dBm

2.2MHz

ENCODE = 65MSPS

2.2MHz

30.5MHz

–5.0 10.0

SNR

5.0

15.0

Figure 22. SNR, Worst Spurious vs. Clamped Encode Power (See Figure 25)

REV. 0

–11–

Page 12

AD6644

THEORY OF OPERATION

The AD6644 analog-to-digital converter (ADC) employs a three stage subrange architecture. This design approach achieves the required accuracy and speed while maintaining low power and small die size.

As shown in the functional block diagram, the AD6644 has complementary analog input pins, AIN and AIN . Each analog input is centered at 2.4 V and should swing ± 0.55 V around this reference (Figure 2). Since AIN and AIN are 180 degrees out of phase, the differential analog input signal is 2.2 V peakto-peak.

Both analog inputs are buffered prior to the first track-and-hold, TH1. The high state of the ENCODE pulse places TH1 in hold mode. The held value of TH1 is applied to the input of a 5-bit coarse ADC1. The digital output of ADC1 drives a 5-bit digitalto-analog converter, DAC1. DAC1 requires 14 bits of precision which is achieved through laser trimming. The output of DAC1 is subtracted from the delayed analog signal at the input of TH3 to generate a first residue signal. TH2 provides an analog pipeline delay to compensate for the digital delay of ADC1.

The first residue signal is applied to a second conversion stage consisting of a 5-bit ADC2, 5-bit DAC2, and pipeline TH4. The second DAC requires 10 bits of precision which is met by the process with no trim. The input to TH5 is a second residue signal generated by subtracting the quantized output of DAC2 from the first residue signal held by TH4. TH5 drives a final 6-bit ADC3.

The digital outputs from ADC1, ADC2, and ADC3 are added together and corrected in the digital error correction logic to generate the final output data. The result is a 14-bit parallel digital CMOS-compatible word, coded as two's complement.

APPLYING THE AD6644 Encoding the AD6644

The AD6644 encode signal must be a high quality, extremely low phase noise source to prevent degradation of performance. Maintaining 14-bit accuracy places a premium on encode clock phase noise. SNR performance can easily degrade by 3 dB to 4 dB with 70 MHz input signals when using a high-jitter clock source. See Analog Devices’ Application Note AN-501, “Aperture Uncertainty and ADC System Performance” for complete details.

For optimum performance, the AD6644 must be clocked differentially. The encode signal is usually ac-coupled into the ENCODE and ENCODE pins via a transformer or capacitors. These pins are biased internally and require no additional bias.

Shown below is one preferred method for clocking the AD6644. The clock source (low jitter) is converted from single-ended to differential using an RF transformer. The back-to-back Schottky diodes across the transformer secondary limit clock excursions into the AD6644 to approximately 0.8 V p-p differential. This helps prevent the large voltage swings of the clock from feeding through to the other portions of the AD6644, and limits the noise presented to the ENCODE inputs. A crystal clock oscillator can also be used to drive the RF transformer if an appropriate limiting resistor (typically 100 Ω) is placed in the series with the primary.

CLOCK

SOURCE

0.1␮F

100⍀

T1–4T

HSMS2812

DIODES

ENCODE

AD6644

ENCODE

Figure 25. Crystal Clock Oscillator – Differential Encode

If a low jitter ECL/PECL clock is available, another option is to ac-couple a differential ECL/PECL signal to the encode input pins as shown below. A device that offers excellent jitter performance is the MC100LVEL16 (or same family) from Motorola.

ECL/

PECL

0.1␮F

ENCODE

AD6644

ENCODE

Figure 26. Differential ECL for Encode

Analog Input

As with most new high-speed, high dynamic range analog-todigital converters, the analog input to the AD6644 is differential. Differential inputs allow much improvement in performance on-chip as signals are processed through the analog stages. Most of the improvement is a result of differential analog stages having high rejection of even order harmonics. There are also benefits at the PCB level. First, differential inputs have high commonmode rejection to stray signals such as ground and power noise. Also, they provide good rejection to common-mode signals such as local oscillator feedthrough.

The AD6644 input voltage range is offset from ground by 2.4 V. Each analog input connects through a 500 Ω resistor to a 2.4 V bias voltage and to the input of a differential buffer (Figure 2). The resistor network on the input properly biases the followers for maximum linearity and range. Therefore, the analog source driving the AD6644 should be ac-coupled to the input pins. Since the differential input impedance of the AD6644 is 1 kΩ, the analog input power requirement is only –2 dBm, simplifying the driver amplifier in many cases. To take full advantage of this high-input impedance, a 20:1 transformer would be required. This is a large ratio and could result in unsatisfactory performance. In this case, a lower step-up ratio could be used. The recommended method for driving the analog input of the AD6644 is to use a 4:1 RF transformer. For example, if R

were set to 60.4 Ω and RS were set

to 25 Ω, along with a 4:1 transformer, the input would match to a 50 Ω source with a full-scale drive of 4.8 dBm. Series resistors (R

) on the secondary side of the transformer should be

used to isolate the transformer from A/D. This will limit the amount of dynamic current from the A/D flowing back into the secondary of the transformer. The terminating resistor (RT) should be placed on the primary side of the transformer.

ANALOG INPUT

SIGNAL

T1–4T

0.1␮F

AIN

AD6644

AIN

–12–

Figure 27. Transformer-Coupled Analog Input Circuit

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Page 13

AD6644

JITTER – ps

SNR – dB

0.1550.2 0.3 0.4 0.5 0.6

AIN = 190MHz

AIN = 150MHz

AIN = 110MHz

AIN = 30MHz

AIN = 70MHz

In applications where dc-coupling is required, a new differential output op amp from Analog Devices, the AD8138, can be used to drive the AD6644 (Figure 28). The AD8138 op amp provides single-ended-to-differential conversion, which reduces overall system cost and minimizes layout requirements.

499⍀

0.1␮F

Figure 28. DC-Coupled Analog Input Circuit

Power Supplies

Care should be taken when selecting a power source. Linear supplies are strongly recommended. Switching supplies tend to have radiated components that may be “received” by the AD6644. Each of the power supply pins should be decoupled as closely to the package as possible using 0.1 µF chip capacitors.

The AD6644 has separate digital and analog power supply pins. The analog supplies are denoted AV pins are denoted DV power supplies. This is because the fast digital output swings can couple switching current back into the analog supplies. Note that AV fied for DV

must be held within 5% of 5 V. The AD6644 is speci-

= 3.3 V as this is a common supply for digital ASICs.

Output Loading

Care must be taken when designing the data receivers for the AD6644. It is recommended that the digital outputs drive a series resistor (e.g. 100 Ω) followed by a gate like 74LCX574. To minimize capacitive loading, there should only be one gate on each output pin. An example of this is shown in the evaluation board schematic shown in Figure 30. The digital outputs of the AD6644 have a constant output slew rate of 1 V/ns. A typical CMOS gate combined with a PCB trace will have a load of approximately 10 pF. Therefore, as each bit switches, 10 mA (10 pF ⫻ 1 V ⫼ 1 ns) of dynamic current per bit will flow in or out of the device. A full scale transition can cause up to 140 mA (14 bits ⫻ 10 mA/bit) of current to flow through the output stages. The series resistors should be placed as close to the AD6644 as possible to limit the amount of current that can flow into the output stage. These switching currents are confined between ground and the DV

pin. Standard TTL gates should be avoided since

they can appreciably add to the dynamic switching currents of the AD6644. It should also be noted that extra capacitive loading will increase output timing and invalidate timing specifications. Digital output timing is guaranteed with 10 pF loads.

Layout Information

The schematic of the evaluation board (Figure 30) represents a typical implementation of the AD6644. A multilayer board is recommended to achieve the best results. It is highly recommended that high-quality, ceramic chip capacitors be used to decouple each supply pin to ground directly at the device. The pinout of the AD6644 facilitates ease of use in the implementa-

REV. 0

499⍀

OCM

499⍀

. AVCC and DV

AD8138

25⍀

AIN

AD6644

AIN

25⍀

and the digital supply

should be separate

REF

DIGITAL OUTPUTS

tion of high frequency, high resolution design practices. All of the digital outputs are segregated to two sides of the chip, with the inputs on the opposite side for isolation purposes.

Care should be taken when routing the digital output traces. To prevent coupling through the digital outputs into the analog portion of the AD6644, minimal capacitive loading should be placed on these outputs. It is recommended that a fan-out of only one gate be used for all AD6644 digital outputs.

The layout of the Encode circuit is equally critical. Any noise received on this circuitry will result in corruption in the digitization process and lower overall performance. The Encode clock must be isolated from the digital outputs and the analog inputs.

Jitter Considerations

The signal-to-noise ratio (SNR) for an ADC can be predicted. When normalized to ADC codes, Equation 1 accurately predicts the SNR based on three terms. These are jitter, average DNL error, and thermal noise. Each of these terms contributes to the noise within the converter.

– log

SNR f t

=×





ANALOG

J RMS



= analog input frequency.

= rms jitter of the encode (rms sum of encode

()

+×× × +





ANALOG RMS





()





NOISE RMS

 





  

(1)





source and internal encode circuitry).

ε = average DNL of the ADC (typically 0.41 LSB).

N = Number of bits in the ADC.

NOISE RMS

= V rms thermal noise referred to the analog input

of the ADC (typically 2.5 LSB).

For a 14-bit analog-to-digital converter like the AD6644, aperture jitter can greatly affect the SNR performance as the analog frequency is increased. The chart below shows a family of curves that demonstrates the expected SNR performance of the AD6644 as jitter increases. The chart is derived from the above equation.

For a complete discussion of aperture jitter, please consult Analog Devices’ Application Note AN-501, “Aperture Uncertainty and ADC System Performance.”

Figure 29. SNR vs. Jitter

–13–

Page 14

AD6644

EVALUATION BOARD

The evaluation board for the AD6644 is straightforward, containing all required circuitry for evaluating the device. The only external connections required are power supplies, clock, and the analog inputs. The evaluation board includes the option for an onboard clock oscillator for ENCODE.

Power to the analog supply pins of the AD6644 is connected via the power terminal block (PCTB2). Power for the digital interface is supplied via pin 1 of J6. The J2 connector mates directly with SoftCell boards, allowing complete evaluation of system performance.

The analog input is connected via a BNC connector AIN, which is transformer-coupled to the AD6644 inputs. The transformer has a turns ratio of 1:4 to reduce the amount of input power required to drive the AD6644.

Item Quantity Reference Description

1 2 C1, C2 Tantalum Chip Capacitor 10 µF 2 19 C3, C7, C8, C9, C10, C11, C16, C30, C31, Ceramic Chip Capacitor 0508, 0.1 µF

3 8 C12, C13, C14, C17, C18, C19, C20, C21 Ceramic Chip Capacitor 0508, 0.01 µF 4 1 CR1 HSMS2812 Surface Mount Diode 5 1 E3, E4, E5 3-Pin Header 6 4 F1, F2, F3, F4 Ferrite (Optional) 7 2 J1, J6 PCTB2 8 1 J2 50-Pin Double Row Header 9 1 J3 SMA Connector 10 2 J4, J5 BNC Connector 11 1 R1 Surface-Mount Resistor 1206, 100 Ω 12 1 R2 Surface-Mount Resistor 1206, 60.4 Ω 13 4 R3, R4, R5, R8 Surface-Mount Resistor 0805, 499 Ω (Optional,

14 2 R6, R7 Surface-Mount Resistor 0805, 25 Ω 15 1 R9 Surface-Mount Resistor 0805, 348 Ω 16 1 R10 Surface-Mount Resistor 0805, 615 Ω 17 1 R35 Surface-Mount Resistor 0805, 49.9 Ω 18 30 R36, R37, R38, R39, R40, R41, R42, R43, Surface-Mount Resistor 0402, 100 Ω

19 2 T2, T3 Surface-Mount Transformer Mini-Circuits T4–1, 1:4 Ratio 20 1 U1 AD6644AST 14-Bit 65 MSPS A/D Converter 21 2 U2, U7 74LCX574 Octal Latch 22 1 U3 AD8138 Single-to-Differential Amplifier (Optional – DC

23 2 U4, U6 NC7SZ32 Two Input OR Gate 24 1 U5 CTS Reeves Full-Size MX045 Crystal Clock Oscillator

Receive Signal Processor (AD6620, AD6624) evaluation

AD6644ST/PCB Bill of Material

C32, C4, C22, C23, C24, C25, C26, C27, C28, C29

R44, R45, R46, R47, R48, R49, R50, R51, R52, R53, R54, R55, R56, R57, R58, R59, R60, R61, R62, R63, R64, R65

The Encode signal may be generated using an onboard crystal oscillator, U5. The on-board oscillator may be replaced by an external encode source via the SMA connector labeled OPT_CLK or BNC connector labeled ENCODE. If an external source is used, it must be a high-quality and very low-phase noise source.

The AD6644 output data is latched using 74LCX574 (U7, U2) latches. The clock for these latches is determined by selecting jumper E3–E4 or E4–E5. E3 to E5 is a just a gate delayed version of the clock, while connecting E4 to E5 utilizes the Data Ready of the AD6644 to latch the output data. A clock is also distributed with the output data (J2) that is labeled BUFLAT (Pin 19 and 20, J2).

DC-Coupling Only)

Coupling Only)

–14–

REV. 0

Page 15

AD6644

OPT_CLK

SMA

348⍀

R10

615⍀

100nF

3P3V

GND

OUT

C22

100nF

FERRITE

5VA

GND

ⴙV

3P3VD

NC7SZ32

OPT_LAT

DR_OUT

BUFLATE4

K1115

GND

5VA

GND

5VA

GND

100nF

5VA

GND

5VA

100nF

GND

15 16 17 18 19 20 25

AD6644ST

5051

DR_OUT

48 47 45 44 43

3P3V

GND

52 46 41 40

5VA

GND

5VA

GND

PREF

3P3V

AIN

GND

AIN

GND

654

GND

5VA

GND

3P3V

DRY

D13

D12

D11

D10

GND

D3D2D1

DMID

GND

OVR

DNC

GND

DVCCGND

REF

GND

ENC

GND

AVCCAVCCGND

AIN

GND

100⍀

R41

100⍀

R40

100⍀

R39

100⍀

R38

100⍀

R36

GND10GND

GND

100⍀

R42

100⍀

R43

OUT_EN

D0 Q0

D1 Q1

D2 Q2

D3Q3D4 Q4

D5 Q5

D6 Q6

D7 Q7

GND CLOCK

74LCX574

AD8138

REF

GND

499⍀

V–

Vⴙ

499⍀

T1–4T

564

1:4

213

C30

100nF

60.4⍀

BNC

499⍀

5VA

499⍀

AIN

25⍀

ENC

CR1

C28

100nF

C27

100nF

123

C29

100nF

R35

49.9⍀

ENC

BNC

100⍀

100nF

T1–4T

1:4

HSMS2812

C32

100NF

REF

R61

100⍀

R60

100⍀

R59

100⍀

R58

100⍀

R37

100⍀

BUFLAT

3P3VD

R62

100⍀

R63

100⍀

OVR

B02

B03

B04

B05

GND

B00

B01

GND

ⴙV

3P3VD

NC7SZ32

BUFLAT

B08

B07

B06

B10

B09

B11

B13

B12

100⍀

R47

100⍀

R48

100⍀

R49

100⍀

R50

100⍀

R51

GND

100⍀

R46

100⍀

R45

OUT_EN

D0 Q0

D1 Q1

D2 Q2

D3 Q3

D4 Q4

D5 Q5

D6 Q6

D7 Q7

GND CLOCK

74LCX574

R53

100⍀

R54

100⍀

R55

100⍀

R56

100⍀

R57

100⍀

BUFLAT

3P3VD

R52

100⍀

R65

100⍀

R64 100⍀100⍀R44

13579

11131517192123252729313335373941434547

HEADR50

246

101214161820222426283032343638404244464850

GND

FERRITE

3P3V

GND

PCTB2

FERRITE

5VA

GND

PCTB2

10␮F

C16

100nF

C17

10nF

C18

10nF

C19

10nF

C20

10nF

C21

10nF

10␮F

100nF

C10

100nF

C11

100nF

C12

10nF

C13

10nF

C14

10nF

3P3V

FERRITE

C23

100nF

C24

100nF

C25

100nF

C26

100nF

3P3VD

H4H3H2

MOUNTING HOLES

NOTE: THE DOTTED LINE REPRESENTS AN OPTIONAL ANALOG DRIVE INPUT

REV. 0

Figure 30. AD6644ST/PCB Schematic (GS02357D Schematic)

–15–

Page 16

AD6644

Figure 31. AD6644ST/PCB Top Side Silkscreen

Figure 32. AD6644ST/PCB Top Side Copper

–16–

REV. 0

Page 17

AD6644

Figure 33. AD6644ST/PCB Bottom Side Silkscreen

REV. 0

Figure 34. AD6644ST/PCB Bottom Side Copper

–17–

Page 18

AD6644

Figure 35. AD6644ST/PCB Ground Layer – Layers 2 and 5 (Negative)

Figure 36. AD6644ST/PCB “Split” Power Layer – Layers 3 and 4 (Negative)

–18–

REV. 0

Page 19

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

52-Terminal Plastic Low Profile Quad Flatpack

(ST-52)

0.063 (1.60)

0.030 (0.75)

0.018 (0.45)

SEATING

PLANE

MAX

0.472 (12.00) SQ

TOP VIEW

(PINS DOWN)

0.394

(10.0)

AD6644

C3812–5–4/00 (rev. 0)

0.006 (0.15)

0.002 (0.05)

0.057 (1.45)

0.053 (1.35)

0.026 (0.65) BSC

0.015 (0.38)

0.009 (0.22)

REV. 0

PRINTED IN U.S.A.

–19–