Datasheet AD6630 Datasheet (Analog Devices)

Differential, Low Noise IF Gain

a

FEATURES
24 dB Gain
4 dB Noise Figure
Easy Match to SAW Filters
Output Limiter Adjustable +8.5 dBm to +12 dBm
700 MHz Bandwidth
10 V Single or Dual 5 V Power Supply
300 mW Power Dissipation

APPLICATIONS
ADC IF Drive Amp
Communications Receivers
PCS/Cellular Base Stations

GSM, CDMA, TDMA

PRODUCT DESCRIPTION

The AD6630 is an IF gain block designed to interface between
SAW filters and differential input analog-to-digital converters.
The AD6630 has a fixed gain of 24 dB and has been optimized
for use with the AD6600 and AD6620 in digitizing narrowband
IF carriers in the 70 MHz to 250 MHz range.

Taking advantage of the differential nature of SAW filters, the
AD6630 has been designed as a differential in/differential out
gain block. This architecture allows 100 dB of adjacent channel
blocking using low cost SAW filters. The AD6630 provides

output limiting for ADC and SAW protection with ⬍10° phase

variation in recovery from overdrive situations.

Designed for “narrow-band” cellular/PCS receivers, the high
linearity and low noise performance of the AD6630 allows for
implementation in a wide range of applications ranging from

Block with Output Clamping

AD6630

FUNCTIONAL BLOCK DIAGRAM

AD6630

1

NC

2

NC

+

3

IP2

4

IP1

IP1

IP2

CLLO

CLHI

+

5

6

7

8

NC = NO CONNECT

GSM to CDMA to AMPS. The clamping circuitry also main­tains the phase integrity of an overdriven signal. This allows
phase demodulation of single carrier signals with an overrange
signal.

While the AD6630 is optimized for use with the AD6600 Dual
Channel, Gain Ranging ADC with RSSI, it can also be used in
many other IF applications. The AD6630 is designed with an

input impedance of 200 Ω and an output of 400 Ω. In the typi-

cal application shown below, these values match the real portion
of a typical SAW filter. Other devices can be matched using
standard matching network techniques.

The AD6630 is built using Analog Devices’ high speed comple­mentary bipolar process. Units are available in a 300 mil SOIC
(16 leads) plastic surface mount package and specified to operate

over the industrial temperature range (–40°C to +85°C).

16

V

CC

15

CD1

14

+

OP

13

V

EE

12

CMD

11

OP

10

CD2

9

V

CC

LOCAL

OSCILLATOR

Figure 1. Reference Design

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Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

AD6630

MAIN

AD6600

AD6630

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 1998

DIVERSITY

AD6620 DSP

AD6620

AD6630–SPECIFICATIONS

NORMAL OPERATING CONDITIONS

Parameter (Conditions) Min Typ Max Units

SINGLE SUPPLY VOLTAGE 8.5 10.5 V

POSITIVE SUPPLY VOLTAGE 4.25 5.0 5.25 V

NEGATIVE SUPPLY VOLTAGE –5.25 –5.0 –4.25 V

AMBIENT TEMPERATURE –40 +85 °C
PACKAGE THERMAL RESISTANCE 80 °C/W

OPERATING FREQUENCY

DC SPECIFICATIONS

Parameter Temp Level Min Typ Max Units

SUPPLY CURRENT Full II 30 48 mA

OUTPUT DC LEVEL Full II VM–150 VM+150 mV

AC SPECIFICATIONS

1

(T

MIN

= –40ⴗC, T

= +85ⴗC. Output dc levels are nominally at VM, where VM = VCC + VEE = [+5 V + (–5 V)] = 0.

MAX

70 250 MHz

Inputs should be AC coupled.)

Test

(T

= –40ⴗC, T

MIN

= +85ⴗC. All AC production tests are performed at 5 MHz. 70 MHz and 250 MHz

MAX

performance limits are correlated to 5 MHz testing based on characterization data.)

Test

Parameter

1

Temp Level Min Typ Max Units

GAIN (POWER) @ 70 MHz Full II 23 24 25 dB

GAIN (POWER) @ 250 MHz Full II 22 23 24 dB

–3 dB BANDWIDTH +25°C V 700 MHz

OUTPUT REFERRED IP3 @ 70 MHz

OUTPUT REFERRED IP3 @ 250 MHz

OUTPUT REFERRED IP2 @ 70 MHz

OUTPUT REFERRED IP2 @ 250 MHz

OUTPUT REFERRED 1 dB COMPRESSION POINT

@ 70 MHz LOW LEVEL CLAMP

OUTPUT REFERRED 1 dB COMPRESSION POINT

@ 250 MHz LOW LEVEL CLAMP

OUTPUT REFERRED 1 dB COMPRESSION POINT

@ 70 MHz HIGH LEVEL CLAMP

OUTPUT REFERRED 1 dB COMPRESSION POINT

@ 250 MHz HIGH LEVEL CLAMP

2

2

2

2

3

3

4

4

Full V 22 dBm

Full V 19 dBm

Full V 45 dBm

Full V 45 dBm

Full II 8.5 dBm

Full II 7.5 dBm

Full II 11 dBm

Full II 9 dBm

OUTPUT SLEW RATE +25°C V 3700 V/µs
INPUT IMPEDANCE (REAL) +25°C V 200 Ω
INPUT CAPACITANCE +25°CV 2 pF
OUTPUT IMPEDANCE (REAL) +25°C V 400 Ω
OUTPUT CAPACITANCE +25°CV 2 pF
NOISE FIGURE +25°CV 4 dB

LOW LEVEL CLAMP MAXIMUM OUTPUT @ 70 MHz

HIGH LEVEL CLAMP MAXIMUM OUTPUT @ 70 MHz

LOW LEVEL CLAMP MAXIMUM OUTPUT @ 250 MHz

3, 5

4, 5

3, 5

Full IV 11 12.5 dBm

Full IV 13.8 14.3 dBm

Full IV 9.25 10.6 dBm

–2– REV. 0

AD6630

WARNING!

ESD SENSITIVE DEVICE

Test

Parameter Temp Level Min Typ Max Units

HIGH LEVEL CLAMP MAXIMUM OUTPUT @ 250 MHz

PHASE VARIATION

7

CMRR

8

PSRR

NOTES

1

All specifications are valid across the operating frequency range when the source and load impedance are a conjugate match to the amplifier’s input and output
impedance.

2

Test is for two tones separated by 1 MHz for IFs at 70 MHz and 250 MHz at –23 dBm per tone input.

3

Low Level Clamp is selected by connecting pin CLLO to the negative supply, while pin CLHI is left floating. Clamping can be set at lower levels by connecting pin
CLLO and CLHI to the negative supply through an external resistor.

4

High Level Clamp is selected by connecting pin CLHI to the negative supply, while pin CLLO is left floating, this allows the maximum linear range of the device to
be utilized.

5

Output clamp levels are measured for hard clamping with a +3 dBm input level. Valid for a maximum input level of +8 dBm/200 Ω = 3.2 V p-p—differential.

6

Measured as the change in output phase when the input level is changed from –53 dBm to +8 dBm (i.e., from linear operation to clamping).

7

Ratio of the differential output signal (referenced to the input) to the common-mode input signal presented to all input pins.

8

Ratio of signal on supply to differential output (<500 kHz).

Specifications subject to change without notice.

6

4, 5

Full IV 11.2 12.2 dBm

+25°C V 9 Degree
+25°CV 50 dB
+25°CV 30 dB

ABSOLUTE MAXIMUM RATINGS

EXPLANATION OF TEST LEVELS

I. 100% production tested.

Parameter Min Max Units

Single Supply Voltage –0.5 11.5 V
Positive Supply Voltage –0.5 5.75 V
Negative Supply Voltage –5.75 0.5 V
Input Power +8 dBm

Storage Temperature –65 +150 °C
Junction Temperature +150 °C

ESD Protection 1 kV

II. 100% production tested at +25°C, and guaranteed by

design and analysis at temperature extremes.

III. Sample tested only.

IV. Parameter guaranteed by design and analysis.

V. Parameter is typical value only.

VI. 100% production tested at +25°C, and sample tested at

temperature extremes.

ORDERING GUIDE

Model Temperature Range Package Description Package Option

AD6630AR –40°C to +85°C (Ambient) 16-Lead Wide Body SOIC R-16
AD6630AR-REEL –40°C to +85°C (Ambient) AD6630AR on 1000 PC Reel

AD6630R/PCB Evaluation Board with AD6630AR

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD6630 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

–3–REV. 0

AD6630

TOP VIEW

(Not to Scale)

16

15

14

13

12

11

10

9

1

2

3

4

5

6

7

8

NC

NC
IP2
IP1

IP1

IP2

CLLO

CLHI

V

CC

CD1
OP
V

EE

CMD

OP

CD2
V

CC

AD6630

NC = NO CONNECT

PIN FUNCTION DESCRIPTION

Pin No Pin Name Description

1, 2 NC No Connect
3 IP2 Input
4 IP1 Input
5 IP1 Input
6 IP2 Input
7 CLLO Clamp Level Low Pin
8 CLHI Clamp Level High Pin
9V

CC

+VCC Supply

10 CD2 Clamp Decoupling
11 OP Output
12 CMD DC Feedback Decoupling
13 V

EE

–VEE Supply
14 OP Output
15 CD1 Clamp Decoupling
16 V

CC

+VCC Supply

Typical Performance Characteristics

24

PIN CONFIGURATION

13

23

22

21

20

19

INTERCEPT POINT – dBm

18

17

16

70

100 300

INPUT FREQUENCY – MHz

Figure 2. 3rd Order Intercept (IP3) vs. Frequency

25

–408C

+258C

+858C

100 300

INPUT FREQUENCY – MHz

24

GAIN – dB

23

22

70

Figure 3. Gain vs. Frequency

12

11

10

1dB COMPRESSION POINT

9

8

70

100 300

INPUT FREQUENCY – MHz

HIGH CLAMP

LOW CLAMP

Figure 4. 1 dB Compression Point (Typical)

14

13

12

11

OUTPUT AMPLITUDE – dBm

10

9

70

HIGH CLAMP

LOW CLAMP

100 300

INPUT FREQUENCY – MHz

Figure 5. Clamp Level vs. Frequency

–4– REV. 0

–1dB 15dB –9dB –2dB 15dB –5dB 24dB –5dB

400V

3pF

47nH

9.7V

15.2pF

AD6630

–14dBm

AD6630 INPUT

–23dBm

–91dBm
–30dBm
–15dBm

–3dBm
–2dBm

–25dBm

–29dBm

–28dBm

OSCILLATOR

ANTENNA

–104dBm

–43dBm
–28dBm
–16dBm
–15dBm

LOCAL

Figure 6. GSM Design Example

THEORY OF OPERATION

The AD6630 amplifier consists of two stages of gain. The first
stage is differential. This differential amplifier provides good
common-mode rejection to common-mode signals passed by
the SAW filter. The second stage consists of matched current
feedback amplifiers on each side of the differential pair. These
amplifiers provide additional gain as well as output drive capa­bility. Gain set resistors for these stages are internal to the de­vice and cannot be changed, allowing fixed compensation for
optimum performance.

Clamping levels for the device are normally set by tying CLLO
or CLHI pins to the negative supply. This internally sets bias
points that generate symmetric clamping levels. Clamping is
achieved primarily in the output amplifiers. Additional input
stage clamping is provided for additional protection. Clamping
levels may be adjusted to lower levels as discussed below.

APPLICATIONS

The AD6630 provides several useful features to meet the needs
of radio designers. The gain and low noise figure of the device
make it perfect for providing interstage gain between differential
SAW filters and/or analog-to-digital converters (ADC). Addi­tionally, the on-board clamping circuitry provides protection for
sensitive SAW filters or ADCs. The fast recovery of the clamp
circuit permits demodulation of constant envelope modulated
IF signals by preserving the phase response during clamping.

The following topics provide recommendations for using the
AD6630 in narrowband, single carrier applications.

Adjusting Output Clamp Levels

Normally, the output clamp level is set by tying either CLLO or
CLHI to ground or V

. It is possible to set the limit between

EE

8.5 dBm and 12 dBm levels by selecting the appropriate exter­nal resistor.

To set to a different level, CLLO and CLHI should be tied
together and then through a resistor to ground. The value of the
resistor can be selected using the following equation.

OUTPUT

14 4

R

. –

=

0 0014

CLAMP

dBm

.

()

–15dBm

–10dBm

SAW SAW

AD6630 OUTPUT

–67dBm

–6dBm
+9dBm
+9dBm
+9dBm

–5–REV. 0

4dBm

AD6600 INPUT

MAIN

AD6600

DIVERSITY

–71dBm
–10dBm

+4dBm
+4dBm
+4dBm

AD6620

DSP

9dBm

AD6630

This equation is derived from measured data at 170 MHz. Clamp
levels vary with frequency, see Figure 5. Output clamp levels
less than 8.5 dBm will result in damage to the clamp circuitry
unless the absolute maximum input power is derated. Similarly,
the output clamp level cannot be set higher than 12 dBm.

R

V

EE

CLAMP

GENERATOR

Figure 7. Clamp Level Resistor

Matching SAW Filters

The AD6630 is designed to easily match to SAW filters. SAW
filters are largely capacitive in nature. Normally a conjugate
match to the load is desired for maximum power transfer.

Another way to treat the problem is to make the SAW filter look
purely resistive. If the SAW filter load looks resistive there is no
lead or lag in the current vs. voltage. This may not preserve
maximum power transfer, but maximum voltage swing will
exist. All that is required to make the SAW filter input or output
look real is a single inductor shunted across the input. When the
correct value is used, the impedance of the SAW filter becomes
real.

Figure 8. Saw Filter Model (170 MHz)

EVALUATION BOARD

Figures 9, 10 and 12 refer to the schematic and layout of the
AD6630AR as used on Analog Devices’ GSM Diversity Re­ceiver Reference Design (only the IF section is shown). Figure
14 references the schematic of the stand-alone AD6630 evalua­tion board and uses a similar layout. The evaluation board uses
center tapped transformers to convert the input to a differential
signal and AD6630 outputs to a single connector to simplify
evaluation. C8, C9 and L2 are optional reactive components to
tune the load for a particular IF frequency if desired.

AD6630

TO OUTPUT

AMPLIFIER

TO OUTPUT

AMPLIFIER

V

EE

V

CC

200V

200V

200V200V

IP1

IP2

IP1

IP2

BIAS

SMA

CHNA

+10V

U100A

NC1

L1A L1

C2

C1

11

V

I

SAW1

12

V

I

GND

1 2 3 4 7 8 9 10

5

V

O

6

V

O

C100

0.1mF

L2

C101

0.1mF

NC2
IP2
IP1
IP1B
IP2B
CL1
CL2

AD6630

V

CC

CD1

OP

V
CMD
OPB

CD2

VCC2

1

11

V

EE

C103

0.1mF

C102

0.1mF

L4

C104

0.1mF

I

12

SAW2

V

I

GND

1 2 3 4 7 8 9 10

5

V

O

V

O

TO

L6

AD6600

6

Figure 9. Reference Design Schematic (One Channel)

Figure 10. Reference Design PCB Layout

OUTPUT
AMP

+

+

DIFF
AMP

–

–

CLP

CLN

CLHI

CLLO

CLAMP

GENERATOR

Figure 11. Functional Block Diagram

OUTPUT
AMP

Figure 12. Reference Design Component Placement (Two
Channels Shown)

+

–

Figure 13. Equivalent Input Circuit

–6– REV. 0

SMA

SMA

J6

J7

AGND

AD6630

J1

PCTB3

2

1

3

C13

AGND

1mF

1

+

C16

10nF

R3

AGND

2

–

AGND

R1
200V

C8

C3
10nF

R2
200V

C2
10nF

TP1

1

C9

1

L2

TP2

TEST

TEST

T2

3

2

1

TC 8-1
AT224

P

J8

1

4

6

P

SMA

2

AGND

11

C5

C6

C7

C14

1nF

C19
100nF

AGND

J3

C15
1nF

AGND

AGND

10nF

10nF

10nF

2

C10
100nF

C4
100nF

AGND

C18
1mF

+

V

CC

CD1

V
CMD
OPB

CD2

V

CC

OP

EE

10nF

1

2

C20
1nF

–

C21

16
15

14
13
12
11
10

9

AGND

C17

J2

1
2
3
4
5
6
7
8

10nF

AD6630

NC1
NC2
IP2
IP1
IP1B
IP2B
CL1
CL2

U1

1

2

AGND

T1

1

L1
470nH

C12

10nF

C11

10nF

2

4

TC4–1W

AT224

AGND

2

3

C1
10nF

1

6

Figure 14. Evaluation Board Schematic

Table I. Typical S Parameters

Frequency
(MHz) S

11

S

12

S

21

S

22

70 224.5 ∠ –4.52° –41.0 ∠ –3.0° 24.1 ∠ –8.8° 394.3 ∠ –8.6°
170 264.8 ∠ –32.9° –31.4 ∠ 0° 23.5 ∠ –22.5° 382.4 ∠ –21.9°
200 227.9 ∠ –34.8° –41.0 ∠ –5° 23.2 ∠ –26.4° 353.0 ∠ –25.4°
250 209.5 ∠ –36.2° –40.6 ∠ –2.3° 22.9 ∠ –38.9° 328.9 ∠ –29.2°

–7–REV. 0

AD6630

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

16-Lead Wide Body SOIC

(R-16)

0.4133 (10.50)

0.3977 (10.00)

16 9

0.2992 (7.60)

0.2914 (7.40)

81

0.4193 (10.65)

0.3937 (10.00)

C3412–8–10/98

0.0118 (0.30)

0.0040 (0.10)

PIN 1

0.0500
(1.27)

BSC

0.1043 (2.65)

0.0926 (2.35)

0.0192 (0.49)

0.0138 (0.35)

SEATING
PLANE

0.0125 (0.32)

0.0091 (0.23)

0.0291 (0.74)

0.0098 (0.25)

0.0500 (1.27)

88

0.0157 (0.40)

08

x 458

–8–

PRINTED IN U.S.A.

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