Page 1
16-BIT LATCH
16-BIT DAC
CONTROL
LOGIC
+10V REF
16-BIT LATCH
20
24
22
21
51112
16
15
14
13
17
18
19
23
AD660
10k
10.05k
10k
SIN/
DB0
DB7
S
OUT
SPAN/
BIP
OFFSET
V
OUT
AGND
REF OUT
REF IN
LDAC
SER
DGND
–V
EE+VCC+VLL
1 2 3 4
LBE
CS
HBE
CLR
MSB/LSB/
DB1
UNI/BIP CLR/
Monolithic 16-Bit
a
FEATURES
Complete 16-Bit D/A Function
On-Chip Output Amplifier
On-Chip Buried Zener Voltage Reference
61 LSB Integral Linearity
15-Bit Monotonic over Temperature
Microprocessor Compatible
Serial or Byte Input
Double Buffered Latches
Fast (40 ns) Write Pulse
Asynchronous Clear (to 0 V) Function
Serial Output Pin Facilitates Daisy Chaining
Unipolar or Bipolar Output
Low Glitch: 15 nV-s
Low THD+N: 0.009%
PRODUCT DESCRIPTION
The AD660 DACPORT is a complete 16-bit monolithic D/A
converter with an on-board voltage reference, double buffered
latches and output amplifier. It is manufactured on Analog Devices’ BiMOS II process. This process allows the fabrication of
low power CMOS logic functions on the same chip as high precision bipolar linear circuitry.
The AD660’s architecture ensures 15-bit monotonicity over
time and temperature. Integral and differential nonlinearity is
maintained at ±0.003% max. The on-chip output amplifier provides a voltage output settling time of 10 µs to within 1/2 LSB
for a full-scale step.
The AD660 has an extremely flexible digital interface. Data can
be loaded into the AD660 in serial mode or as two 8-bit bytes.
This is made possible by two digital input pins which have dual
functions. The serial mode input format is pin selectable to be
MSB or LSB first. The serial output pin allows the user to daisy
chain several AD660s by shifting the data through the input
latch into the next DAC thus minimizing the number of control
lines required to SIN,
mat is also flexible in that the high byte or low byte data can be
loaded first. The double buffered latch structure eliminates data
skew errors and provides for simultaneous updating of DACs in
a multi-DAC system.
The AD660 is available in five grades. AN and BN versions are
specified from –40°C to +85°C and are packaged in a 24-pin
300 mil plastic DIP. AR and BR versions are also specified from
–40°C to +85°C and are packaged in a 24-pin SOIC. The SQ
version is packaged in a 24-pin 300 mil cerdip package and is
also available compliant to MIL-STD-883. Refer to the AD660/
883B data sheet for specifications and test conditions.
DACPORT is a registered trademark of Analog Devices, Inc.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
CS and LDAC. The byte mode input for-
Serial/Byte DACPORT
AD660
FUNCTIONAL BLOCK DIAGRAM
PRODUCT HIGHLIGHTS
1. The AD660 is a complete 16-bit DAC, with a voltage reference, double buffered latches and output amplifier on a single chip.
2. The internal buried Zener reference is laser trimmed to
10.000 volts with a ± 0.1% maximum error and a temperature drift performance of ± 15 ppm/°C. The reference is
available for external applications.
3. The output range of the AD660 is pin programmable and can
be set to provide a unipolar output range of 0 V to +10 V or
a bipolar output range of –10 V to +10 V. No external components are required.
4. The AD660 is both dc and ac specified. DC specifications
include ±1 LSB INL and ±1 LSB DNL errors. AC specifications include 0.009% THD+N and 83 dB SNR.
5. The double buffered latches on the AD660 eliminate data
skew errors and allow simultaneous updating of DACs in
multi-DAC applications.
6. The CLEAR function can asynchronously set the output to
0 V regardless of whether the DAC is in unipolar or bipolar
mode.
7. The output amplifier settles within 10 µs to ±1/2 LSB for a
full-scale step and within 2.5 µs for a 1 LSB step over tem-
perature. The output glitch is typically 15 nV-s when a fullscale step is loaded.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700 Fax: 617/326-8703
Page 2
AD660–SPECIFICATIONS
(TA = +258C, VCC = +15 V, VEE = –15 V, VLL = +5 V unless otherwise noted)
Parameter Min Typ Max Min Typ Max Units
AD660AN/AR/SQ AD660BN/BR
RESOLUTION 16 16 Bits
DIGITAL INPUTS (T
V
(Logic “1”) 2.0 5.5 * * Volts
IH
V
(Logic “0”) 0 0.8 * * Volts
IL
I
(VIH = 5 5 V) ±10 * µA
IH
IIL (VIL = 0 V) ±10 * µA
MIN
to T
TRANSFER FUNCTION CHARACTERISTICS
MAX
)
1
Integral Nonlinearity ±2 ±1 LSB
to T
T
MIN
Differential Nonlinearity ±2 ±1 LSB
T
MIN
Monotonicity Over Temperature 14 15 Bits
Gain Error
Gain Drift (T
DAC Gain Error
DAC Gain Drift
to T
2, 3
MAX
MAX
MIN
to T
4
4
) 25 15 ppm/°C
MAX
±4 ±2 LSB
±4 ±2 LSB
±0.10 * % of FSR
±0.05 * % of FSR
10 * ppm/°C
Unipolar Offset ±2.5 * mV
Unipolar Offset Drift (T
Bipolar Zero Error ±7.5 * mV
Bipolar Zero Error Drift (T
MIN
to T
MIN
) 3 * ppm/°C
MAX
to T
) 5 * ppm/°C
MAX
REFERENCE INPUT
Input Resistance 7 10 13 * * * kΩ
Bipolar Offset Input Resistance 7 10 13 * * * kΩ
REFERENCE OUTPUT
Voltage 9.99 10.00 10.01 * * * Volts
Drift 25 15 ppm/°C
External Current
5
24 ** mA
Capacitive Load 1000 * pF
Short Circuit Current 25 * mA
OUTPUT CHARACTERISTICS
Output Voltage Range
Unipolar Configuration 0 +10 * * Volts
Bipolar Configuration –10 +10 * * Volts
Output Current 5 * mA
Capacitive Load 1000 * pF
Short Circuit Current 25 * mA
POWER SUPPLIES
Voltage
6
V
CC
6
V
EE
V
LL
Current (No Load)
I
CC
I
EE
I
LL
+13.5 +16.5 * * Volts
–13.5 –16.5 * * Volts
+4.5 +5.5 * * Volts
+12 +18 * * mA
–12 –18 * * mA
@ VIH, VIL = 5, 0 V 0.3 2 * * mA
@ V
, VIL = 2.4, 0.4 V 3 7.5 * * mA
IH
Power Supply Sensitivity 1 2 * * ppm/%
Power Dissipation (Static, No Load) 365 625 * * mW
TEMPERATURE RANGE
Specified Performance (A, B) –40 +85 * * °C
Specified Performance (S) –55 +125 °C
NOTES
1
For 16-bit resolution, 1 LSB = 0.0015% of FSR. For 15-bit resolution, 1 LSB = 0.003% of FSR. For 14-bit resolution, 1 LSB = 0.006% of FSR. FSR stands for
Full-Scale Range and is 10 V in a Unipolar Mode and 20 V in Bipolar Mode.
2
Gain error and gain drift are measured using the internal reference. The internal reference is the main contributor to gain drift. If lower gain drift is required, the
AD660 can be used with a precision external reference such as the AD587, AD586 or AD688.
3
Gain Error is measured with fixed 50 Ω resistors as shown in the Application section. Eliminating these resistors increases the gain error by 0.25% of FSR (Unipolar
mode) or 0.50% of FSR (Bipolar mode).
4
DAC Gain Error and Drift are measured with an external voltage reference. They represent the error contributed by the DAC alone, for use with an external reference.
5
External current is defined as the current available in addition to that supplied to REF IN and SPAN/BIPOLAR OFFSET on the AD660.
6
Operation on ±12 V supplies is possible using an external reference such as the AD586 and reducing the output range. Refer to the Internal/External Reference section.
*Indicates that the specification is the same as AD660AN/AR/SQ.
Specifications subject to change without notice.
–2–
REV. A
Page 3
AD660
WARNING!
ESD SENSITIVE DEVICE
AC PERFORMANCE CHARACTERISTICS
(With the exception of Total Harmonic Distortion + Noise and Signal-to-Noise
Ratio, these characteristics are included for design guidance only and are not subject to test. THD+N and SNR are 100% tested.
T
≤ TA ≤ T
MIN
Parameter Limit Units Test Conditions/Comments
Output Settling Time 13 µs max 20 V Step, TA = +25°C
(Time to ±0.0008% FS 8 µs typ 20 V Step, T
with 2 kΩ, 1000 pF Load) 10 µs typ 20 V Step, T
Total Harmonic Distortion + Noise
A, B, S Grade 0.009 % max 0 dB, 990.5 Hz; Sample Rate = 96 kHz; T
A, B, S Grade 0.056 % max –20 dB, 990.5 Hz; Sample Rate = 96 kHz; T
A, B, S Grade 5.6 % max –60 dB, 990.5 Hz; Sample Rate = 96 kHz; T
Signal-to-Noise Ratio 83 dB min T
Digital-to-Analog Glitch Impulse 15 nV-s typ DAC Alternately Loaded with 8000H and 7FFF
Digital Feedthrough 2 nV-s typ DAC Alternately Loaded with 0000H and FFFFH; CS High
, VCC = +15 V, VEE = –15 V, VLL = +5 V except where noted.)
MAX
6 µs typ 10 V Step, TA = +25°C
8 µs typ 10 V Step, T
2.5 µs typ 1 LSB Step, T
= +25°C
A
= +25°C
A
≤ TA ≤ T
MIN
≤ TA ≤ T
MIN
≤ TA ≤ T
MIN
MAX
MAX
MAX
= +25°C
A
= +25°C
A
= +25°C
A
H
Output Noise Voltage 120 nV/√
Hz typ Measured at V
; 20 V Span; Excludes Reference
OUT
Density (1 kHz – 1 MHz)
Reference Noise 125 nV/√Hz typ Measured at REF OUT
Specifications subject to change without notice.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD660 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
ABSOLUTE MAXIMUM RATINGS*
PIN CONFIGURATION
VCC to AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +17.0 V
–V
+V
+V
DGND
DB7, 15
DB6, 14
DB5, 13
DB4, 12
DB3, 11
DB2, 10
EE
CC
LL
1
2
3
4
5
6
7
8
9
10
11
12
AD660
TOP VIEW
(Not to Scale)
V
to AGND . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –17.0 V
EE
V
to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
LL
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±1 V
Digital Inputs (Pins 5 through 23) to DGND . . . . . . –1.0 V to
+7.0 V
REF IN to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±10.5 V
Span/Bipolar Offset to AGND . . . . . . . . . . . . . . . . . . . ±10.5 V
Ref Out, V
. . . . . . . Indefinite Short to AGND, DGND,
OUT
V
, VEE, and V
CC
LL
Power Dissipation (Any Package)
To +60°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1000 mW
Derates above +60°C . . . . . . . . . . . . . . . . . . . . 8.7 mW/°C
Storage Temperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature Range
(Soldering 10 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . +300°C
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
DB1, 9, MSB/LSB
DB0, 8, SIN
24
REF OUT
23
REF IN
SPAN,
22
BIPOLAR OFFSET
V
21
OUT
20
AGND
19
LDAC
18
CLR
17
SER
16
HBE
15
LBE, UNI/BIP CLEAR
14
CS
13
S
OUT
REV. A
–3–
Page 4
AD660
ORDERING GUIDE
Temperature Linearity Error Max Linearity Error Max Gain TC max Package Package
Model Range +25°CT
AD660AN –40°C to +85°C ±2 LSB ±4 LSB 25 Plastic DIP N-24
AD660AR –40°C to +85°C ±2 LSB ±4 LSB 25 SOIC R-24
AD660BN –40°C to +85°C ±1 LSB ±2 LSB 15 Plastic DIP N-24
AD660BR –40°C to +85°C ±1 LSB ±2 LSB 15 SOIC R-24
AD660SQ –55°C to +125°C ±2 LSB ±4 LSB 25 Cerdip Q-24
AD660SQ/883B** –55°C to +125°C ±2 LSB ** ** ** **
*N = Plastic DIP; Q = Cerdip; R = SOIC.
**Refer to AD660/883B military data sheet.
MIN
– T
MAX
ppm/°C Description Option*
TIMING CHARACTERISTICS
VCC = +15 V, VEE = –15 V, VLL = +5 V, VHI = 2.4 V, VLO = 0.4 V
Parameter Limit +25°C Limit –55°C to +125°C Units
(Figure la)
t
CS
t
DS
t
DH
t
BES
t
BEH
t
LH
t
LW
40 50 ns min
40 50 ns min
0 10 ns min
40 50 ns min
0 10 ns min
80 100 ns min
40 50 ns min
(Figure lb)
t
CLK
t
LO
t
HI
t
SS
t
DS
t
DH
t
SH
t
LH
t
LW
80 100 ns min
30 50 ns min
30 50 ns min
0 10 ns min
40 50 ns min
0 10 ns min
0 10 ns min
80 100 ns min
40 50 ns min
(Figure lc)
t
CLR
t
SET
t
HOLD
80 110 ns min
80 110 ns min
0 10 ns min
(Figure ld)
t
PROP
t
DS
Specifications subject to change without notice.
50 100 ns min
50 80 ns min
BIT 0–7
HBE OR
LBE
CS
LDAC
t
t
DH
BEH
t
LH
t
DS
t
BES
t
CS
Figure 1a. AD660 Byte Load Timing
t
LW
REV. A–4–
Page 5
SER
AD660
VALID 1 VALID 16BIT0
t
DS
t
SS
t
DH
t
SH
BIT1
CS
LDAC
CLR
LBE
BIT0
SER
BIT 1
(MSB/LSB)
CS
SERIAL
OUT
"1" = MSB FIRST, "0" = LSB FIRST
t
LO
t
HI
t
t
CLK
LH
Figure 1b. AD660 Serial Load Timing
t
CLR
t
SET
"1" = BIP 0, "0" = UNI 0
Figure 1c. Asynchronous Clear to Bipolar or Unipolar Zero
VALID 16 VALID 17
t
DS
t
PROP
VALID S
OUT
1
t
HOLD
t
LW
Figure 1d. Serial Out Timing
DEFINITIONS OF SPECIFICATIONS
INTEGRAL NONLINEARITY: Analog Devices defines
integral nonlinearity as the maximum deviation of the actual,
adjusted DAC output from the ideal analog output (a straight
line drawn from 0 to FS–1 LSB) for any bit combination. This
is also referred to as relative accuracy.
DIFFERENTIAL NONLINEARITY: Differential nonlinearity
is the measure of the change in the analog output, normalized to
full scale, associated with a 1 LSB change in the digital input
code. Monotonic behavior requires that the differential linearity
error be greater than or equal to –1 LSB over the temperature
range of interest.
MONOTONICITY: A DAC is monotonic if the output either
increases or remains constant for increasing digital inputs with
the result that the output will always be a single-valued function
of the input.
GAIN ERROR: Gain error is a measure of the output error be-
tween an ideal DAC and the actual device output with all 1s
loaded after offset error has been adjusted out.
OFFSET ERROR: Offset error is a combination of the offset
errors of the voltage-mode DAC and the output amplifier and is
measured with all 0s loaded in the DAC.
BIPOLAR ZERO ERROR: When the AD660 is connected for
bipolar output and 10 . . . 000 is loaded in the DAC, the deviation of the analog output from the ideal midscale value of 0 V is
called the bipolar zero error.
DRIFT: Drift is the change in a parameter (such as gain, offset
and bipolar zero) over a specified temperature range. The drift
temperature coefficient, specified in ppm/°C, is calculated by
measuring the parameter at T
, 25°C and T
MIN
and dividing
MAX
the change in the parameter by the corresponding temperature
change.
TOTAL HARMONIC DISTORTION + NOISE: Total harmonic distortion + noise (THD+N) is defined as the ratio of the
square root of the sum of the squares of the values of the harmonics and noise to the value of the fundamental input frequency. It is usually expressed in percent (%).
THD+N is a measure of the magnitude and distribution of linearity error, differential linearity error, quantization error and
noise. The distribution of these errors may be different, depending upon the amplitude of the output signal. Therefore, to be
the most useful, THD+N should be specified for both large and
small signal amplitudes.
REV. A
–5–
Page 6
AD660
16-BIT LATCH
16-BIT DAC
CONTROL
LOGIC
+10V REF
16-BIT LATCH
20
24
22
21
51112
16
15 14
13
17
18
19
23
AD660
10k
10.05k
10k
HBE
LBE CS
SIN/
DB0
MSB/LSB/
DB1
DB7
S
OUT
SPAN/
BIP OFF
REF OUT
REF IN
LDAC
CLR
SER
DGND
–V
EE+VCC+VLL
1 2 3 4
OUTPUT
R2
50
R3 16k
R4
10k
+V
CC
–V
EE
R1 100
AGND
UNI/BIP CLR/
Ω
Ω
SIGNAL-TO-NOISE RATIO: The signal-to-noise ratio is defined as the ratio of the amplitude of the output when a fullscale signal is present to the output with no signal present. This
is measured in dB.
DIGITAL-TO-ANALOG GLITCH IMPULSE: This is the
amount of charge injected from the digital inputs to the analog
output when the inputs change state. This is measured at half
scale when the DAC switches around the MSB and as many
as possible switches change state, i.e., from 011 . . . 111 to
100 . . . 000.
DIGITAL FEEDTHROUGH: When the DAC is not selected
(i.e.,
CS is held high), high frequency logic activity on the digital inputs is capacitively coupled through the device to show up
as noise on the V
pin. This noise is digital feedthrough.
OUT
THEORY OF OPERATION
The AD660 uses an array of bipolar current sources with MOS
current steering switches to develop a current proportional to
the applied digital word, ranging from 0 to 2 mA. A segmented
architecture is used, where the most significant four data bits are
thermometer decoded to drive 15 equal current sources. The
lesser bits are scaled using a R-2R ladder, then applied together
with the segmented sources to the summing node of the output
amplifier. The internal span/bipolar offset resistor can be connected to the DAC output to provide a 0 V to +10 V span, or it
can be connected to the reference input to provide a –10 V to
+10 V span.
HBE
SER
CLR
LDAC
REF IN
UNI/BIP CLR/
LBE
15
16
CONTROL
17
LOGIC
18
19
23
CS
14
10k
REF OUT
SIN/
DB0
16-BIT LATCH
16-BIT LATCH
16-BIT DAC
+10V REF
24
MSB/LSB/
DB7
DB1
51112
1 2 3 4
–V
EE+VCC+VLL
AD660
10k
10.05k
DGND
13
22
21
20
S
OUT
SPAN/
BIP
OFFSET
V
OUT
AGND
Figure 2. AD660 Functional Block Diagram
(Pin 21), and between REF OUT (Pin 24) and REF IN (Pin
23). It is possible to use the AD660 without any external components by tying Pin 24 directly to Pin 23 and Pin 22 directly to
Pin 21. Eliminating these resistors will increase the gain error by
0.25% of FSR.
HBE
SER
CLR
LDAC
UNI/BIP CLR/
LBE
15 14
16
CONTROL
17
LOGIC
18
19
23
REF IN
Ω
R1 50
CS
10k
+10V REF
REF OUT
SIN/
MSB/LSB/
DB0
DB1 DB7
16-BIT LATCH
16-BIT LATCH
16-BIT DAC
24
51112
AD660
10.05k
1 2 3 4
–V
EE+VCC+VLL
10k
DGND
13
22
21
20
S
OUT
SPAN/
BIP OFF
V
OUT
OUTPUT
AGND
R2
50Ω
Figure 3a. 0 V to +10 V Unipolar Voltage Output
If it is desired to adjust the gain and offset errors to zero, this can
be accomplished using the circuit shown in Figure 3b. The adjustment procedure is as follows:
STEP 1 . . . ZERO ADJUST
Turn all bits OFF and adjust zero trimmer, R4, until the output
reads 0.000000 volts (1 LSB = 153 µV).
STEP 2 . . . GAIN ADJUST
Turn all bits ON and adjust gain trimmer, R1, until the output is
9.999847 volts. (Full scale is adjusted to 1 LSB less than the
nominal full scale of 10.000000 volts).
ANALOG CIRCUIT CONNECTIONS
Internal scaling resistors provided in the AD660 may be connected to produce a unipolar output range of 0 V to +10 V or a
bipolar output range of –10 V to +10 V. Gain and offset drift
are minimized in the AD660 because of the thermal tracking of
the scaling resistors with other device components.
UNIPOLAR CONFIGURATION
The configuration shown in Figure 3a will provide a unipolar
0 V to +10 V output range. In this mode, 50 Ω resistors are tied
between the span/bipolar offset terminal (Pin 22) and V
Figure 3b. 0 V to +10 V Unipolar Voltage Output with Gain
and Offset Adjustment
OUT
REV. A–6–
Page 7
AD660
BIPOLAR CONFIGURATION
The circuit shown in Figure 4a will provide a bipolar output
voltage from –10.000000 V to +9.999694 V with positive full
scale occurring with all bits ON. As in the unipolar mode, resis-
tors R1 and R2 may be eliminated altogether to provide AD660
bipolar operation without any external components. Eliminat-
ing these resistors will increase the gain error by 0.50% of FSR
in the bipolar mode.
Ω
R2 50
HBE
SER
CLR
LDAC
R1 50
UNI/BIP CLR/
16
17
18
19
23
REF IN
Ω
LBE
15 14
CONTROL
LOGIC
CS
10k
+10V REF
REF OUT
SIN/
MSB/LSB/
DB0
DB1 DB7
16-BIT LATCH
16-BIT LATCH
16-BIT DAC
24
51112
AD660
10.05k
1 2 3 4
–VEE+VCC+V
LL
10k
DGND
13
22
21
20
S
OUT
SPAN/
BIP OFF
V
OUT
OUTPUT
AGND
Figure 4a.±10 V Bipolar Voltage Output
Gain offset and bipolar zero errors can be adjusted to zero us-
ing the circuit shown in Figure 4b as follows:
STEP I . . . OFFSET ADJUST
Turn OFF all bits. Adjust trimmer R2 to give 10.000000 volts
output.
STEP II . . . GAIN ADJUST
Turn all bits ON and adjust R1 to give a reading of +9.999694
volts.
STEP III . . . BIPOLAR ZERO ADJUST (Optional)
In applications where an accurate zero output is required, set
the MSB ON, all other bits OFF, and readjust R2 for zero volts
output.
R2
100Ω
HBE
SER
CLR
R1
100Ω
UNI/BIP CLR/
LBE
15 14
16
CONTROL
17
LOGIC
18
LDAC
19
23
REF IN
CS
10k
+10V REF
REF OUT
SIN/
MSB/LSB/
DB0
DB1 DB7
16-BIT LATCH
16-BIT LATCH
16-BIT DAC
24
51112
AD660
10.05k
1 2 3 4
–VEE+VCC+V
LL
10k
DGND
13
22
21
20
S
OUT
SPAN/
BIP OFF
V
OUT
OUTPUT
AGND
Figure 4b.±10 V Bipolar Voltage Output with Gain and
Offset Adjustment
It should be noted that using external resistors will introduce a
small temperature drift component beyond that inherent in the
AD660. The internal resistors are trimmed to ratio-match and
temperature-track other resistors on chip, even though their absolute tolerances are ±20% and absolute temperature coefficients are approximately –50 ppm/°C . In the case that external
resistors are used, the temperature coefficient mismatch between internal and external resistors, multiplied by the sensitivity of the circuit to variations in the external resistor value, will
be the resultant additional temperature drift.
INTERNAL/EXTERNAL REFERENCE USE
The AD660 has an internal low noise buried Zener diode reference which is trimmed for absolute accuracy and temperature
coefficient. This reference is buffered and optimized for use in a
high speed DAC and will give long-term stability equal or superior to the best discrete Zener diode references. The performance of the AD660 is specified with the internal reference
driving the DAC and with the DAC alone (for use with a precision external reference ).
The internal reference has sufficient buffering to drive external
circuitry in addition to the reference currents required for the
DAC (typically 1 mA to REF IN and 1 mA to BIPOLAR
OFFSET). A minimum of 2 mA is available for driving external
loads. The AD660 reference output should be buffered with an
external op amp if it is required to supply more than 4 mA total
current. The reference is tested and guaranteed to ±0.2% max
error.
It is also possible to use external references other than 10 volts
with slightly degraded linearity specifications. The recommended range of reference voltages is +5 V to +10.24 V, which
allows 5 V, 8.192 V and 10.24 V ranges to be used. For example, by using the AD586 5 V reference, outputs of 0 V to
+5 V unipolar or ±5 V bipolar can be realized. Using the
AD586 voltage reference makes it possible to operate the
AD660 with ±12 V supplies with 10% tolerances.
REV. A
–7–
Page 8
AD660
Figure 5 shows the AD660 using the AD586 precision 5 V reference in the bipolar configuration. The highest grade AD586MN
is specified with a drift of 2 ppm/°C which is a 7.5× improvement over the AD660’s internal reference. This circuit includes
two optional potentiometers and one optional resistor that can
be used to adjust the gain, offset and bipolar zero errors in a
manner similar to that described in the BIPOLAR CONFIGURATION section. Use –5.000000 V and +4.999847 as the output values.
+V
AD586
GND
4
2
CC
V
OUT
TRIM
UNI/BIP CLR/
16
HBE
17
SER
18
CLR
LDAC
19
100Ω
R2
10kΩ
23
REF IN
R1
6
5
LBE
15 14
CONTROL
LOGIC
CS
10k
+10V REF
REF OUT
The AD660 can also be used with the AD587 10 V reference,
using the same configuration shown in Figure 5 to produce a
±10 V output. The highest grade AD587LR, N is specified at
5 ppm/°C, which is a 3× improvement over the AD660’s internal reference.
Figure 6 shows the AD660 using the AD680 precision ± 10 V
reference, in the unipolar configuration. The highest grade
AD688BQ is specified with a temperature coefficient of
1.5 ppm/°C. The ±10 V output is also ideal for providing precise biasing for the offset trim resistor R4.
R2
50Ω
SIN/
MSB/LSB/
DB0
DB1
DB7
51112
16-BIT LATCH
16-BIT LATCH
16-BIT DAC
24
–V
AD660
10k
10.05k
1 2 3 4
EE+VCC+VLL
DGND
13
22
21
20
S
OUT
SPAN/
BIP OFF
V
OUT
OUTPUT
AGND
R
S
R2
R3
5 10
Figure 5. Using the AD660 with the AD586 5 V Reference
UNI/BIP CLR/
LBE CS
HBE
16
CONTROL
17
SER
CLR
LDAC
R1
4
67
A1
R1
R5
A2
89
3
A3
1
AD688
R4
R6
12
11 13
14
A4
15
2
16
100Ω
+V
CC
–V
EE
18
19
23
LOGIC
REF IN
10k
+10V REF
REF OUT
SIN/
MSB/LSB/
DB0
DB1
16-BIT LATCH
16-BIT LATCH
16-BIT DAC
24
–VEE+VCC+V
DB7
5111215 14
AD660
10k
10.05k
1 2 3 4
LL
DGND
SPAN/
BIP OFF
S
13
OUT
R3
10k
Ω
22
21
20
V
OUT
AGND
R2
100Ω
R4
10kΩ
OUTPUT
0 TO +10V
Figure 6. Using the AD660 with the AD688 High Precision ±10 V Reference
REV. A–8–
Page 9
AD660
OUTPUT SETTLING AND GLITCH
The AD660’s output buffer amplifier typically settles to within
0.0008% FS (1/2 LSB) of its final value in 8 µs for a full-scale
step. Figures 7a and 7b show settling for a full-scale and an LSB
step, respectively, with a 2 kΩ, 1000 pF load applied. The guaranteed maximum settling time at +25°C for a full-scale step is
13 µs with this load. The typical settling time for a 1 LSB step is
2.5 µs.
The digital-to-analog glitch impulse is specified as 15 nV-s typi-
cal. Figure 7c shows the typical glitch impulse characteristic at
the code 011 . . . 111 to 100 . . . 000 transition when loading
the second rank register from the first rank register.
600
+10
0
VOLTS
–10
0
10
µs
400
200
µV
0
–200
–400
–600
20
a. –10 V to +10 V Full-Scale Step Settling
600
400
200
µV
0
–200
–400
–600
234
1
µs
50
b. LSB Step Settling
+10
0
mV
–10
23 4
1
µs
50
c. D-to-A Glitch Impulse
DIGITAL CIRCUIT DETAILS
The AD660 has several “dual-use” pins which allow flexible operation while maintaining the lowest possible pin count and consequently the smallest package size. The user should, therefore,
pay careful attention to the following information when applying
the AD660.
Data can be loaded into the AD660 in serial or byte mode as
described below.
Serial Mode Operation is enabled by bringing
SER (Pin 17)
low. This changes the function of DB0 (Pin 12) to that of the
serial input pin, SIN. It also changes the function of DB1 (Pin
11) to a control input that tells the AD660 whether the serial
data is going to be loaded MSB or
In serial mode
HBE and LBE are effectively disabled except for
LSB first.
LBE’s dual function which is to control whether the user wishes
to have the asynchronous clear function go to unipolar or bipolar zero. (A low on
LBE, when CLR is strobed, sends the DAC
output to unipolar zero, a high to bipolar zero.) The AD660
does not care about the status of HBE when in serial mode.
Data is clocked into the input register on the rising edge of
CS
as shown in Figure 1b. The data is then resident in the first rank
latch and can be loaded into the DAC latch by taking LDAC
high. This will cause the DAC to change to the appropriate output value.
It should be noted that the clear function clears the DAC latch
but does not clear the first rank latch. Therefore, the data that
was previously resident in the first rank latch can be reloaded
simply by bringing LDAC high after the event that necessitated
CLR to be strobed has ended. Alternatively, new data can be
loaded into the first rank latch if desired.
The serial out pin (SOUT) can be used to daisy chain several
DACs together in multi-DAC applications to minimize the
number of isolators being used to cross an intrinsic safety barrier. The first rank latch simply acts like a 16-bit shift register,
and repeated strobing of
CS will shift the data out through
SOUT and into the next DAC. Each DAC in the chain will
require its own LDAC signal unless all of the DACs are to be
updated simultaneously.
Byte Mode Operation is enabled simply by keeping
which configures DB0–DB7 as data inputs. In this mode
and
LBE are used to identify the data as either the high byte or
SER high,
HBE
low byte of the 16-bit input word. (The user can load the data,
in any order, into the first rank latch.) As in the serial mode
case, the status of
LBE, when CLR is strobed determines
whether the AD660 clears to unipolar or bipolar zero. Therefore, when in byte mode, the user must take care to set
the desired status before strobing
can simply hardware
NOTE:
CS is edge triggered. HBE, LBE and LDAC are level
LBE to the desired state.)
CLR. (In serial mode the user
LBE to
triggered.
REV. A
Figure 7. Output Characteristics
–9–
Page 10
AD660–Microprocessor Interface Section
AD660 TO MC68HC11 (SPI BUS) INTERFACE
The AD660 interface to the Motorola SPI (serial peripheral interface) is shown in Figure 8. The MOSI, SCK, and
the HC11 are respectively connected to the BIT0,
LDAC pins of the AD660. The
SER pin of the AD660 is tied
SS pins of
CS and
low causing the first rank latch to be transparent. The majority
of the interfacing issues are taken care of in the software initialization. A typical routine such as the one shown below begins by
initializing the state of the various SPI data and control registers.
The most significant data byte (MSBY) is then retrieved from
memory and processed by the SENDAT subroutine. The
SS
pin is driven low by indexing into the PORTD data register and
clear Bit 5. This causes the 2nd rank latch of the AD660 to become transparent. The MSBY is then set to the SPI data register where it is automatically transferred to the AD660.
The HC11 generates the requisite 8 clock pulses with data valid
on the rising edges. After the most significant byte is transmitted, the least significant byte (LSBY) is loaded from memory
and transmitted in a similar fashion. To complete the transfer,
the LDAC pin is driven high latching the complete 16-bit word
into the AD660.
INIT LDAA #$2F ;SS = I; SCK = 0; MOSI = I
NEXTPT LDAA MSBY ;LOAD ACCUM W/UPPER 8 BITS
SENDAT LDY #$1000 ;POINT AT ON-CHIP REGISTERS
WAIT1 LDAA SPSR ;CHECK STATUS OF SPIE
WAIT2 LDAA SPSR ;CHECK STATUS OF SPIE
STAA PORTD ;SEND TO SPI OUTPUTS
LDAA #$38 ;SS, SCK,MOSI = OUTPUTS
STAA DDRD ;SEND DATA DIRECTION INFO
LDAA #$50 ;DABL INTRPTS,SPI IS MASTER & ON
STAA SPCR ;CPOL=0, CPHA = 0,1MHZ BAUD RATE
BSR SENDAT ;JUMP TO DAC OUTPUT ROUTINE
JMP NEXTPT ;INFINITE LOOP
BCLR $08,Y,$20 ;DRIVE SS (LDAC) LOW
STAA SPDR ;SEND MS-BYTE TO SPI DATA REG
BPL WAIT1 ;POLL FOR END OF X-MISSION
LDAA LSBY ;GET LOW 8 BITS FROM MEMORY
STAA SPDR ;SEND LS-BYTE TO SPI DATA REG
BPL WAIT2 ;POLL FOR END OF X-MISSION
BSET $08,Y,$20 ;DRIV SS HIGH TO LATCH DATA
RTS
68HC11
MDSI
SCK
SS
BIT0
CS
LDAC
SER
AD660
Figure 8. AD660 to 68HC11 (SPI) Interface
MICROWIRE
SO
SK
G1
BIT0
CS
LDAC
SER
AD660
Figure 9. AD660 to MICROWIRE Interface
AD660 TO ADSP-210x FAMILY INTERFACE
The serial mode of the AD660 minimizes the number of control
and data lines required to interface to digital signal processors
(DSPs) such as the ADSP-210x family. The application in Figure 10 shows the interface between an ADSP-2101 and the
AD660. Both the TFS pin and the DT pins of the ADSP-2101
should be connected to the
SER and BIT0 pins of the AD660,
respectively. An inverter is required between the SCLK output
and the
transmitted to the BIT0 pin is valid on the rising edge of
CS input of the AD660 in order to assure that data
CS.
The serial port (SPORT) of the DSP should be configured for
alternate framing mode so that TFS complies with the wordlength framing requirement of
SER. Note that the INVTFS bit
in the SPORT control register should be set to invert the TFS
signal so that
which must meet the minimum hold specification of t
generated by delaying the rising edge of
flip-flop. The
of approximately one
SER is the correct polarity. The LDAC signal,
, is easily
IH
SER with a 74HC74
CS signal clocks the flip-flop resulting in a delay
CS clock cycle.
In applications such as waveform generation, accurate timing of
the output samples is important to avoid noise that would be induced by jitter on the LDAC signal. In this example, the
ADSP-2101 is set up to use the internal timer to interrupt the
processor at the precise and desired sample rate. When the
timer interrupt occurs, the processors’s 16-bit data word is written to the transmit register (TXn). This causes the DSP to automatically generate the TFS signal and begin transmission of the
data.
ADSP-210x
SCLK
DT
TFS SER
74HC04
74HC74
CS
BIT0
AD660
D
Q
LDAC
Figure 10. AD660 to ADSP-210x Interface
AD660 TO MICROWIRE INTERFACE
The flexible serial interface of the AD660 is also compatible
with the National Semiconductor MICROWIRE interface.
The MICROWIRE interface is used on microcontrollers such as
the COP400 and COP800 series of processors. A generic interface to the MICROWIRE interface is shown in Figure 9. The
G1, SK, And SO pins of the MICROWIRE interface are respectively connected to the LDAC,
CS and BIT0 pins of the
AD660.
MICROWIRE is a registered trademark of National Semiconductor.
–10–
AD660 TO Z80 INTERFACE
Figure 11 shows a Zilog Z-80 8-bit microprocessor connected to
the AD660 using the byte mode interface. The double-buffered
capability of the AD660 allows the microprocessor to independently write to the low and high byte registers, and update the
DAC output. Processor speeds up to 6 MHz on Z-80B require
no extra wait states to interface with the AD660 using a
74ALS138 as the address decoder.
REV. A
Page 11
Applications Information–AD660
The address decoder analyzes the input-output address produced by the processor to select the function to be performed by
the AD660, qualified by the coincidence of the Input-Output
Request (IORQ*) and Write (WR*) pins. The least significant
address bit (A0) determines if the low or high byte register of
the AD660 is active. More significant address bits select between input register loading, DAC output update, and unipolar
or bipolar clear.
A typical Z-80 software routine begins by writing the low byte of
the desired 16-bit DAC data to address 0, followed by the high
byte to address 1. The DAC output is then updated by activating LDAC with a write to address 2 (or 3). A clear to unipolar
zero occurs on a write to address 4, and a clear to bipolar zero is
performed by a write to address 5. The actual data written to
addresses 2 through 5 is irrelevant. The decoder can easily be
expanded to control as many AD660s as required.
SER
+5V
V
LL
AD660
D0-D7
IORQ
Z80
A0-A15
WR
ADDRESS
DECODE
E2
E1
A1–A15
DB0-DB7
Y2
Y1
Y0
A0
CLR
LDAC
CS
HBE LBE DGND
Figure 11. Connections for 8-Bit Bus Interface
NOISE
In high resolution systems, noise is often the limiting factor. A
16-bit DAC with a 10 volt span has an LSB size of 153 µV
(–96 dB). Therefore, the noise floor must remain below this
level in the frequency range of interest. The AD660’s noise
spectral density is shown in Figures 12 and 13. Figure 12 shows
the DAC output noise voltage spectral density for a 20 V span
excluding the reference. This figure shows the 1/f corner
frequency at 100 Hz and the wideband noise to be below
120 nV/√
Hz. Figure 13 shows the reference noise voltage spec-
tral density. This figure shows the reference wideband noise to
be below 125 nV/√
1000
NOISE VOLTAGE – nV/ Hz
100
Hz.
10
1
10 100k
1
FREQUENCY – Hz
1M
10k1k100
10M
Figure 12. DAC Output Noise Voltage Spectral Density
1000
100
10
NOISE VOLTAGE – nV/ Hz
1
10 100k
1
FREQUENCY – Hz
10k1k100
1M
10M
Figure 13. Reference Noise Voltage Spectral Density
BOARD LAYOUT
Designing with high resolution data converters requires careful
attention to board layout. Trace impedance is the first issue. A
306 µA current through a 0.5 Ω trace will develop a voltage
drop of 153 µV, which is 1 LSB at the 16-bit level for a 10 V
full-scale span. In addition to ground drops, inductive and
capacitive coupling need to be considered, especially when high
accuracy analog signals share the same board with digital signals. Finally, power supplies need to be decoupled in order to
filter out ac noise.
Analog and digital signals should not share a common path.
Each signal should have an appropriate analog or digital return
routed close to it. Using this approach, signal loops enclose a
small area, minimizing the inductive coupling of noise. Wide PC
tracks, large gauge wire, and ground planes are highly recommended to provide low impedance signal paths. Separate analog
and digital ground planes should also be used, with a single interconnection point to minimize ground loops. Analog signals
should be routed as far as possible from digital signals and
should cross them at right angles.
One feature that the AD660 incorporates to help the user layout
is that the analog pins (V
BIP OFFSET, V
OUT
, VEE, REF OUT, REF IN, SPAN/
CC
and AGND) are adjacent to help isolate
analog signals from digital signals.
SUPPLY DECOUPLING
The AD660 power supplies should be well filtered, well regulated, and free from high frequency noise. Switching power supplies are not recommended due to their tendency to generate
spikes which can induce noise in the analog system.
Decoupling capacitors should be used in very close layout proximity between all power supply pins and ground. A 10 µF tanta-
lum capacitor in parallel with a 0.1 µF ceramic capacitor
provides adequate decoupling. V
to analog ground, while V
LL
and VEE should be bypassed
CC
should be decoupled to digital
ground.
An effort should be made to minimize the trace length between
the capacitor leads and the respective converter power supply
and common pins. The circuit layout should attempt to locate
the AD660, associated analog circuitry and interconnections as
far as possible from logic circuitry. A solid analog ground plane
around the AD660 will isolate large switching ground currents.
For these reasons, the use of wire wrap circuit construction
is not recommended; careful printed circuit construction is
preferred.
REV. A
–11–
Page 12
AD660
GROUNDING
The AD660 has two pins, designated analog ground (AGND)
and digital ground (DGND.) The analog ground pin is the
“high quality” ground reference point for the device. Any external loads on the output of the AD660 should be returned to
analog ground. If an external reference is used, this should also
be returned to the analog ground.
If a single AD660 is used with separate analog and digital
ground planes, connect the analog ground plane to AGND and
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
N-24
24-Lead Plastic DIP
2
4
PIN 1
1
1.275 (32.30)
1.125 (28.60)
0.210
(5.33)
MAX
0.200 (5.05)
0.125 (3.18)
0.022 (0.558)
0.014 (0.356)
0.100
(2.54)
BSC
the digital ground plane to DGND keeping lead lengths as short
as possible. Then connect AGND and DGND together at the
AD660. If multiple AD660s are used or the AD660 shares analog supplies with other components, connect the analog and
digital returns together once at the power supplies rather than at
each chip. This single interconnection of grounds prevents large
ground loops and consequently prevents digital currents from
flowing through the analog ground.
13
0.280 (7.11)
0.240 (6.10)
12
0.325 (8.25)
0.150
(3.81)
MIN
0.300 (7.62)
0.015 (0.381)
0.008 (0.204)
0.195 (4.95)
0.115 (2.93)
0.070 (1.77)
0.045 (1.15)
0.060 (1.52)
0.015 (0.38)
SEATING
PLANE
C1813a–15–7/93
0.005 (0.13) MIN
PIN 1
0.200
(5.08)
MAX
0.200 (5.08)
0.125 (3.18)
PIN 1
2
4
1
0.023 (0.58)
0.014 (0.36)
24
1
Q-24
24-Lead Cerdip
0.098 (2.49) MAX
1
3
0.310 (7.87)
0.220 (5.59)
12
1.060 (26.92) MAX
0.100
(2.54)
BSC
0.070 (1.78)
0.030 (0.76)
0.060 (1.52)
0.015 (0.38)
SEATING
PLANE
R-24
24-Lead Small Outline (SOIC)
13
0.2992 (7.60)
0.2914 (7.40)
0.4193 (10.65)
0.3937 (10.00)
12
0.6141 (15.60)
0.5985 (15.20)
0.1043 (2.65)
0.0926 (2.35)
0.150
(3.81)
MIN
0.0291 (0.74)
0.0098 (0.25)
0.320 (8.13)
0.290 (7.37)
0.015 (0.38)
0.008 (0.20)
15°
0°
x 45
°
PRINTED IN U.S.A.
0.0118 (0.30)
0.0040 (0.10)
0.0500
(1.27)
BSC
0.0192 (0.49)
0.0138 (0.35)
0.0125 (0.32)
0.0091 (0.23)
0.0500 (1.27)
8
°
0
°
0.0157 (0.40)
REV. A–12–
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