Datasheet AD6458 Datasheet (Analog Devices)

a

GSM 3 V Receiver IF Subsystem

AD6458

FEATURES
Fully Compliant with Standard and Enhanced GSM

Specification

–12 dBm Input 1 dB Compression Point
–2 dBm Input Third Order Intercept
10 dB SSB Noise Figure (330 V)

DC–400 MHz RF and LO Bandwidths

Linear IF Amplifier

Linear-in-dB and Stable over Temperature Voltage
Gain Control
Quadrature Demodulator

Onboard Phase-Locked Quadrature Oscillator

Demodulates IFs from 5 MHz to 50 MHz
Low Power

9 mA at Midgain

1 mA Sleep Mode Operation

3.0 V to 3.6 V Operation

Interfaces to AD7013, AD7015 and AD6421 Baseband

Converters
20-Lead SSOP

GENERAL DESCRIPTION

The AD6458 is a 3 V, low power receiver IF subsystem for
operation at input frequencies as high as 400 MHz and IFs from
5 MHz up to 50 MHz. It is optimized for operation in GSM,
DCS1800 and PCS1900 receivers. It consists of a mixer, IF
amplifier, I and Q demodulators, a phase-locked quadrature
oscillator, precise AGC subsystem, and a biasing system with
external power-down.

The low noise, high intercept mixer of the AD6458 is a
doubly-balanced Gilbert cell type. It has a nominal –12 dBm
input-referred 1 dB compression point and a –2 dBm input­referred third-order intercept. The mixer section of the AD6458
also includes a local oscillator (LO) preamplifier, which lowers
the required LO drive to –16 dBm.

The gain control input accepts an external gain-control voltage
input from an external AGC detector or a DAC. It provides an
80 dB gain range with 27 mV/dB gain scaling.

The I and Q demodulators provide inphase and quadrature
baseband outputs to interface with Analog Devices’ AD7013
(IS54, TETRA, MSAT) and AD7015 and AD6421 (GSM,
DCS1800, PCS1900) baseband converters. An onboard

FUNCTIONAL BLOCK DIAGRAM

LO

I

RF

AGC

FREF

quadrature VCO which is externally phase-locked to the IF
signal drives the I and Q demodulators. This locked reference
signal is normally provided by an external VCTCXO under the
control of the radio’s digital processor. The AD6458 can also
provide demodulation of N-PSK and N-QAM in many non­TDMA systems when used with external analog carrier recovery
systems such as the Costas Loop. Finally, the VCO can be
phase-locked to a frequency which is deliberately offset from the
IF, as in the case of a Beat-Frequency Oscillator (BFO), result­ing in the product detection of CW or SSB.

The AD6458 uses supply voltages from 3.0 V to 3.6 V over the
temperature range of –40°C to +85°C. Operation is enabled by
a CMOS logical level; response time is typically <80 µs. When
disabled, the standby current is reduced to 1 µA.

The AD6458 comes in a 20-lead shrink small outline (SSOP)
surface-mount package.

BPF

AD6458

PLO

Q

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 1997

AD6458–SPECIFICATIONS

(@ TA = +258C, VP = 3.0 V, GREF = 1.2 V, unless otherwise noted)

Parameter Conditions Min Typ Max Units

MIXER

Maximum RF and LO Frequency 400 MHz
AGC Conversion Gain Variation 0.2 V < V

< 2.25 V, ZS = 50 Ω, Z

G

= 330 Ω –8.5 to +9.5 dB

LOAD

Input RF Signal Range –95 –15 dBm
Input 1 dB Compression Point @ V
Input Third-Order Intercept @ V
SSB Noise Figure

1

Mixer Output Bandwidth at MXOP @ –3 dB, Z

= 0.2 V, ZS = 50 Ω, Z

G

= 0.2 V, ZS = 50 Ω, Z

G

= 330 Ω –11 dBm

LOAD

= 330 Ω –2 dBm

LOAD

@ ZS =1 kΩ, FRF = 83 MHz, FLO = 96 MHz at –16 dBm 9 dB

= 330 Ω 55 MHz

LOAD

IF AMPLIFIERS

AGC Gain Variation 0.2 V < V

< 2.25 V –9 to +48 dB

G

Input Referred Noise AC Short Circuit Input 3 nV/Hz
Input Resistance @ V

= 0.2 V 5 kΩ

G

Bandwidth @ –3 dB 50 MHz

I AND Q DEMODULATORS

Demodulation Gain 17 dB
Output Voltage Range IRXP, IRXN, QRXP, QRXN 0.3 V

– 0.2 V

P

Output Voltage Common-Mode Level (Not Power Supply Dependant) 1.5 V
Output Offset Voltage Differential –150 +150 mV
Output Offset Voltage Variation Differential, over Gain and Temperature Range
Output Offset Voltage Variation Differential, for 0.5 V < V

–25°C < T

< +85°C (See Note 2) 0.5 mV

A

< 2.4 V and

G

2

1mV

Error in Quadrature IF = 13 MHz 1.5 3.7 Degree
Amplitude Match 0.25 dB
I/Q Output Bandwidth C

= 10 pF 2 MHz

LOAD

Output Resistance Each Pin 4.7 kΩ

GAIN CONTROL

Total Gain Control Range Mixer + IF + Demod, 0.2 V < V

< 2.25 V 75 dB

G

Control Voltage Range at GAIN 0.2 2.4 V
Gain Scaling 23 27 32 mV/dB
Gain Law Conformance ±0.5 dB
Bias Current at GREF 0.5 µA
Input Resistance at GAIN 20 kΩ

PLL

Frequency Range 5 40 MHz
Phase Noise 0.5 Degree rms
Acquisition Time IF = 13 MHz, Using Ceramic Filter 80 µs
Input Drive Level (FREF) 100 VPOS mV

POWER-DOWN INTERFACE

Logical Threshold Power-Up On Logical High 1.5 V
Input Current for Logical High 75 µA
Turn On Response Time To Fully Meet Specifications 80 150 µs
Stand By Current (See Note 3) 1 8 µA

POWER SUPPLY

Supply Range 3.0 3.3 3.6 V
Worst Case Supply Current @ V
Supply Current @ V

= 0.2 V, TA = +85°C, VP = 3.6 V

GAIN

= 1.2 V 9 mA

GAIN

4

16.5 22 mA

OPERATING TEMPERATURE

T

to T

MIN

MAX

NOTES

1

Including IF noise and using 13 MHz ceramic filter, at V

2

Histograms of Demodulator Offset Voltage Variation in Gain and Temperature can be found in Figures 23 to 27.

3

Max value represent the value at six times the standard deviation, in the worst case condition (TA = +85°C). The value at three times the standard deviation is 5 µA.

4

Max value represent the value at six times the standard deviation. The value at three times the standard variation is 19 mA.

Specifications subject to change without notice.

GAIN

= 0.2 V.

–40 to +85 °C

–2–

REV. 0

AD6458

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS

Supply Voltage VPS1, VPS2 to COM1, COM2 . . . . . +3.6 V

Internal Power Dissipation

2

. . . . . . . . . . . . . . . . . . . . 600 mW

Operating Temperature Range . . . . . . . . . . . –40°C to +85°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Lead Temperature, Soldering (60 sec) . . . . . . . . . . . +300°C

NOTES

1

Stresses above those listed under Absolute Maximum Ratings may cause perma­nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended rating conditions for extended periods may affect device
reliability.

2

Thermal Characteristics: 20-Lead SSOP Package: θJA = 126°C/W.

ORDERING GUIDE

1

PIN CONNECTION

20-Lead SSOP (RS-20)

1

FREF

2

COM1

3

PRUP

4

LOIP

5

AD6458

TOP VIEW

6

RFHI

(Not to Scale)

7

COM2

8

GREF

9

MXOP

NC IFIP

10

NC = NO CONNECT

20

VPS1

19

FLTR

18

VPS2

17

IRXP

16

IRXNRFLO

15

QRXP

14

QRXN
GAIN

13

IFIM

12
11

Temperature Package Package

Model Range Description Option

AD6458ARS –40°C to +85°C 20-Lead Shrink Small Outline RS-20

PIN FUNCTION DESCRIPTIONS

Pin Pin
Number Label Description Function

1 FREF Frequency Reference Input Demodulation LO Input. May be 3 V CMOS input or >100 mV ac coupled for

lowest stand by current.
2 COM1 Common 1 Ground.
3 PRUP Power-Up Input CMOS compatible power up control; 0 = OFF, 3 V = ON.
4 LOIP Local Oscillator Input AC coupled LO input. Only 50 mV drive needed, 500 mV max.
5 RFLO RF “Low” Input Usually connected to ac ground.
6 RFHI RF “High” Input AC coupled, –109 dBV to –29 dBV RF input from 1 kΩ filter for optimal operation.
7 COM2 Common 2 Ground.
8 GREF Gain Reference Input High impedance input, sets gain scaling, typically 1.2 V.
9 MXOP Mixer Output Output of the Mixer.
10 NC Not internally connected. Should be grounded.
11 IFIP IF Input “Plus” Differential Input of variable gain amplifier.
12 IFIM IF Input “Minus” Differential Input of variable gain amplifier.
13 GAIN Gain Control Input 0.2 V–2.4 V using 3 V supply. Max gain at 0.2 V.
14 QRXN Q Output “Negative” Differential Q Output.
15 QRXP Q Output “Positive” Differential Q Output.
16 IRXN I Output “Negative” Differential I Output.
17 IRXP I Output “Positive” Differential I Output.
18 VPS2 VPOS Supply 2 Supply Voltage.
19 FLTR PPL Loop Filter Series RC loop filter, connected to VPS2.
20 VPS1 VPOS Supply 1 Supply Voltage.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD6458 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

REV. 0

–3–

AD6458

R1

20kΩ

C12

C2

1nF

C3

1nF

OPEN

220pF

C4 1nF

R5

C6

1nF

FREF

1

COM1

2

PRUP

3

LOIP

4

AD6458

RFLO

5

RFHI

6

COM2

7

GREF

8

MXOP

9

10

FREF

R9

50Ω

PRUP

LOIP

RFHI

GREF

R2

50Ω

R3

50Ω

R10

301Ω

R4

54.9Ω

MXOP IFIP IFIM

VSP1

FLTR

VSP2

IRXP

IRXN

QRXP

QRXN

GAIN

IFIM

IFIP

VPOS

20

19

18

17

16

15

14

13

12

11

C10 1nF

C7

0.01µF

C1

0.1µF

R8 1kΩ

C8

0.01µF

R6

50ΩR750Ω

Figure1. Characterization Board

C11

0.1µF

C10

0.1µF
(BOTTOM)

VPOS

IRXP

IRXN

QRXP

QRXN

GAIN

VPOS

FREF

PRUP

LOIP

RFIP

GREF

MXOP

IFIN

FREF

PRUP

LOIP

CHARACTERIZATION

RFIP

GREF

MXOP IFIP IFIM

AD830

R1
100Ω

A=1

V

P

V

N

1

Gm

2

3

Gm

4

AD6458

BOARD

8

7

6

5

VPOS

C11

0.1pF

C10

0.1pF

IRXP

IRXN

QRXP

QRXN

GAIN

V

P

V

N

R6
50Ω

V

P

C6

8

0.1pF

7

6

5

C7

0.1pF

C4

8

0.1pF

7

6

5

C5

0.1pF

C9

8

0.1pF

7

6

5

C8

0.1pF

R4

50Ω

I

OUT

V

N

V

P

R3

50Ω

Q

OUT

V

N

GAIN

V

P

R5
50Ω

V

N

AD830

AD830

AD830

A=1

A=1

A=1

V

P

V

N

V

P

V

N

V

P

V

N

1

Gm

2

3

Gm

4

1

Gm

2

3

Gm

4

1

Gm

2

3

Gm

4

Figure 2. Characterization Test Set

–4–

REV. 0

AD6458

HP8657B

10MHz OUT
10MHz IN
SYNC
I

EEE

SYNTHESIZER

HP8657B

10MHz OUT
10MHz IN
SYNC
I

EEE

SYNTHESIZER

HP8657B

10MHz OUT
10MHz IN
SYNC
I

EEE

SYNTHESIZER

DP8200

I

EEE

DC SOURCE

RF OUT

MOD I/O

RF OUT

MOD I/O

RF OUT

MOD I/O

HI F

HI S
LO F
LO S
GND

I

EEE

HP663X

POWER

SUPPLY

LO

HP34401

HI

HI

LO
I HI

PRUP VPOS VIN VP

FREF

LOIP

RFIP

GREF

I

EEE

DMM

AD6458

MOTHER BOARD

MXOP IFIN

IOUT

QOUT

GAIN

HP8593E

I

CAL OUT
RF I/P

ANALYSER

SPECTRUM

EEE

28 VOLT

SWEEP OUT

+5V
–5V
COM
+15V

HP6237

HI F
HI S
LO F
LO S
GND

DP8200

DC SOURCE

I

EEE

FREF

LOIP

RFHI

GREF

50Ω

50Ω

R2

R1

0.1µF

Figure 3. Mixer Characterization Setup

PRUP

VPOS

R5
330Ω

C1

0.1µF

R8 1kΩ

C11

0.1µF

C9
10nF

VPOS

IRXP

IRXN

QRXP

QRXN

GAIN

C12

220pF

C4 1nF

C2

1nF

C7

1nF

C5

FREF

1

COM1

2

PRUP

3

LOIP

4

AD6458

RFLO

5

RFHI

6

COM2

7

GREF

8

MXOP

9

10

BPF2

VSP1

FLTR

VSP2

IRXP

IRXN

QRXP

QRXN

GAIN

IFIM

IFIP

20

19

18

17

16

15

14

13

12

11

C13
10nF

C10 1nF

REV. 0

Figure 4. Typical Connection Diagram

–5–

AD6458

22

20

18

16

14

FIF = 13MHz, ZS = 50Ω

12

NOISE FIGURE – dB

10

FIF = 26MHz, ZS = 50Ω

8

6

80 120

160 200 240 280 320 360 400 440

FIF = 13MHz, ZS = 400Ω

RF FREQUENCY – MHz

Figure 5. Mixer Noise Figure vs. RF Frequency

35

30

25

20

15

PERCENTAGE

10

5

0

7.0 8.47.2 7.4 7.6 7.8 8.0 8.2
NOISE FIGURE – dB

= 7.7dB
= 0.26dB

15

V

= 0.2V

10

5

0

–5

CONVERSION GAIN – dB

–10

–15

50 550100 150 200 250 300 350 400 450 500

GAIN

V

= 1.2V

GAIN

V

= 2.2V

GAIN

RF FREQUENCY – MHz

Figure 8. Mixer Conversion Gain vs. RF Frequency,

= +25°C, V

T

A

12
10

8
6
4
2
0

GAIN – dB

–2
–4
–6
–8

–10

10 5414 18 22 26 30 34 38 42 46 50

= 3.0 V, V

POS

=1.2 V, FIF =13 MHz

REF

V

= 0.2V

GAIN

V

= 1.5V

GAIN

V

= 2.2V

GAIN

IF FREQUENCY – MHz

Figure 6. Mixer Noise Figure Histogram, RS = 1 kΩ,

= 83 MHz, FIF = 13 MHz

F

RF

2.0

1.6
RSH, V

= 1.0V

GAIN

1.2

0.8

RESISTANCE – kΩ

0.4

0

50 550100 150 200 250 300 350 400 450 500

RSH, V

RSH, V

GAIN

= 2.2V

GAIN

= 0.2V

RF FREQUENCY – MHz

CSH, V

CSH, V

GAIN

GAIN

CSH, V

= 0.2V

= 1.0V

GAIN

5.5

5.0

4.5

4.0

= 2.2V

3.5

3.0

Figure 7. Mixer Input Impedance vs. RF Frequency,

= 3.0 V, TA = +25°C

V

POS

CAP – pF

Figure 9. Mixer Conversion Gain vs. IF Frequency,

= +25°C, V

T

A

15

10

5

0

GAIN – dB

–5

–10

–15

0 2.50.5 1.0 1.5 2.0

Figure 10. Mixer Conversion Gain vs V

=13 MHz, FRF = 83 MHz

F

IF

= 3 V, V

POS

= 1.2 V, FRF = 250 MHz

REF

V

= 3V TO 3.6V

POS

T

= –25°C TO +85°C

A

V

– Volts

GAIN

, V

GAIN

REF

= 1.2 V,

–6–

REV. 0

AD6458

IF INPUT – dBm (REFERRED TO 50Ω)

V

GAIN

– Volts

–5

–10

–60

0 2.50.5 1.0 1.5 2.0

–25

–40
–45
–50

–15
–20

–35

–30

–55

TA = –40°C

TA = –25°C

TA = +25°C

TA = +85°C

IF FREQUENCY – MHz

12000

6000

0

0 10010

RESISTANCE – Ω

20 30 40 50 60 70 80 90

10000

8000

4000

2000

R SHUNT, V

GAIN

= 2.2V

C SHUNT, V

GAIN

= 1.0V

R SHUNT, V

GAIN

= 1.0V

R SHUNT, V

GAIN

= 0.2V

C SHUNT, V

GAIN

= 2.2V

C SHUNT, V

GAIN

= 0.2V

3.5

3.0

2.5

2.0

1.5

1.0

0.5

CAPACITANCE – pF

–8

–9

–10

V

= 3.6V

POS

T

= +25°C

A

–11

–12

V

= 3.0V

POS

T

= +25°C

A

–13

INPUT – dBm (REFERRED TO 50Ω)

–14

–15

0 2.50.5 1.0 1.5 2.0

V

POS

T

A

V

= 3.0V

= –40°C

GAIN

V
T

– Volts

= 3.0V

POS

= +85°C

A

V
T

A

= 3.6V

POS

= +85°C

V

POS

T

= –25°C

A

= 3.0V

Figure 11. Mixer Input 1 dB Compression Point vs. V
V

= 1.2 V, FRF = 83 MHz, FIF = 13 MHz

REF

70

60

50

40

30

20

IF AMP/DEMOD GAIN – dB

10

0

54510 15 20 25 30 35 40

INTERMEDIATE FREQUENCY – dB

V

V

V

V

GAIN

GAIN

GAIN

GAIN

= 0.2V

= 1.0V

= 1.5V

= 2.25V

GAIN

,

Figure 14. IF Amplifier/Demodulator Input 1 dB Compres­sion Point vs. V
V

= 3.0 V

POS

, FIF =13 MHz, V

GAIN

= 1.2 V, TA = +25°C,

REF

Figure 12. IF Amplifier and Demodulator Gain vs.
Frequency, T

70

60

50

40

30

GAIN – dB

20

Figure 13. IF Amplifier and Demodulator Gain vs.
V

REV. 0

10

0

–10

, TA = +25°C, V

GAIN

0 2.50.5 1.0 1.5 2.0

= +25°C, V

A

POS

POS

TA = –40°C TO +85°C

V

– Volts

GAIN

= 3.0 V, FIF = 13 MHz, V

= 3.0 V, V

REF

=1.2 V

= 1.2 V

REF

Figure 15. IF Amplifier Input Impedance vs. Frequency,

= +25°C, V

T

A

0.8

0.6

0.4

0.2

–0.2

ERROR – dB

–0.4

–0.6

–0.8

–1

1

0

0 2.50.5 1 1.5 2

= 3.0 V, V

POS

IF AMP/DEMOD

= 1.2 V

REF

MIXER

GAIN VOLTAGE – Volts

Figure 16. AD6458 Gain Error vs. Gain Control Voltage,
Representative Part

–7–

AD6458

4.0

3.5

3.0

2.5

2.0

1.5

QUAD_ERROR

1.0

0.5

0

10 5515 20 25 30 35 40 45 50

F

FREQUENCY – MHz

REF

Figure 17. Demodulator Quadrature Error vs. F
Frequency, TA = +25°C, V

16

14

12

10

8

6

PERCENTAGE

4

2

0

1.5 2.91.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 3.0

= 3.0 V

POS

ERROR – Degrees

= 2.1d
= 0.3d

°
°

REF

–0.1

–0.3

–0.5

– Volts

POS

–0.7

–0.9

FLTR PIN VOLTAGE

–1.1

REFERENCED TO V

–1.3

–1.5

55510 15 20 25 30 35 40 45 50

PLL FREQUENCY – MHz

Figure 20. PLL Loop Voltage at FLTR Pin (kVCO) vs. Frequency

–10
–15
–20
–25
–30
–35
–40

INPUT – dBm

–45
–50
–55
–60

(REFERRED TO 50Ω - ie. +10dBm -> 2V p-p)

–65

0 2.50.5 1.0 1.5 2.0

V

GAIN

– Volts

Figure 18. Demodulator Quadrature Error Histogram

= +25°C, V

T

A

–90

–95

–100

–105

–110

PHASE NOISE – dBc

–115

–120

0.1 10k1 10 100 1k

Figure 19. PLL Phase Noise vs. Frequency, V
C

= 1 nF, R

FLTR

= 3.0 V. FIF = 13 MHz

POS

CARRIER FREQUENCY – kHz

= 1 kΩ, F

FLTR

= 13 MHz

REF

POS

= 3 V,

Figure 21. System [(Mixer + IF Ceramic Filter + IF Ampli­fier + Demodulator)] Input 1 dB Compression Point vs.
V

, TA = +25°C, V

GAIN

= 1.2 V

V

REF

80

70

60

50

40

30

GAIN – dB

20

10

0

–10

–20

0 2.50.5 1.0 1.5 2.0

= 3.0 V, FIF = 13 MHz, FRF = 83 MHz,

POS

V

– Volts

GAIN

Figure 22. System (Mixer + IF Ceramic Filter + IF Amplifier
+ Demodulator) Conversion Gain vs. V

= 3.0 V, FIF = 13 MHz, FRF = 83 MHz, V

V

POS

, TA = +25°C,

GAIN

= 1.2 V

REF

–8–

REV. 0

AD6458

100

90

80

70

60

50

40

PERCENTAGE

30

20

10

0

–4.9 –3.9 –2.9 –1.9 –0.9 0.1 1.1 2.1 3.1 4.1

VARIATION – mV

= 0.03mV

= 0.4mV

Figure 23. Demodulation Output Offset Voltage Variation
Histogram with Variation Referred to Offset at V
and T

= +25°C, V

A

80

70

60

50

40

30

PERCENTAGE

20

10

0
–2.9 3.1–2.4 –1.9 –1.4 –0.9 –0.4 0.1 0.6 1.1 1.6 2.1 2.6

= 2.25 V and TA = +25°C

GAIN

= 0.1mV
= 0.6mV

VARIATION – mV

GAIN

= 1.2 V

16

14

12

10

8

6

PERCENTAGE

4

2

0

–10 10–8 –6 –4 –2 0 2 4 6 8

OFFSET DRIFT – mV

= 0.9mV

= 3.4mV

Figure 26. Demodulation Output Offset Voltage Variation
Histogram with Variation Referred to Offset at V

1.2 V and T

= +25°C, V

A

30

25

20

15

PERCENTAGE

10

5

0
–10 10–8–6–4–202468

= 0.2 V and TA = –25°C

GAIN

= –0.04mV
= 3.6mV

OFFSET DRIFT – mV

GAIN

=

Figure 24. Demodulation Output Offset Voltage Variation
Histogram with Variation Referred to Offset at V
and T

= +25°C, V

A

50

50

45

45

40

40

35

35

30

30

25

25

20

20

PERCENTAGE

PERCENTAGE

15

15

10

10

5

5
0

0
–4.9 5.1–3.9 –2.9 1.1–1.9 –0.9 0.1 2.1 3.1 4.1

–4.9 5.1–3.9 –2.9 1.1–1.9 –0.9 0.1 2.1 3.1 4.1

= 0.5 V and TA = +25°C C

GAIN

VARIATION – mV

VARIATION – mV

= 0.04mV

= 0.04mV

GAIN

= 1.1mV

= 1.1mV

= 1.2 V

Figure 25. Demodulation Output Offset Voltage Variation
Histogram with Variation Referred to Offset at V

1.2 V and T

= +25°C, V

A

= 0.2 V and TA = +25°C

GAIN

GAIN

=

REV. 0

Figure 27. Demodulation Output Offset Voltage Variation
Histogram with Variation Referred to Offset at V

1.2 V and T

18

16

14

12

10

SUPPLY CURRENT – mA

= +25°C, V

A

V

= 3.6V, TA = +25°C

POS

8

6

V

POS

0 2.50.5 1.0 1.5 2.0

= 0.2 V and TA = +85°C

GAIN

V

= 3.6V, TA = +85°C

POS

V

= 3.0V, TA = +85°C

POS

= 3.6V, TA = –40°C

V

– Volts

GAIN

GAIN

Figure 28. Power Supply Current vs. Gain Control Volt­age, V

= 1.2 V

REF

–9–

=

AD6458

2.0

1.9

1.8

1.7

1.6

– Volts

1.5

PRUP

1.4

V

1.3

1.2

1.1

1.0
0 2.50.5 1.0 1.5 2.0

Figure 29. Minimum Power-Up Voltage vs V

3.0 V, V

REF

= 1.2 V

TA = –40°C

TA = –25°C

TA = +25°C

TA = +85°C

V

– Volts

GAIN

, V

POS

=

GAIN

PRODUCT OVERVIEW

The AD6458 provides most of the active circuitry required to
realize a complete low power, single-conversion superhetero­dyne receiver, or the latter part of a double-conversion receiver,
at input frequencies up to 400 MHz, with an IF from 5 MHz to
50 MHz. The internal I/Q demodulators, and their associated
phase-locked loop, support a wide variety of modulation modes,
including n-PSK, n-QAM, and GMSK. A single positive supply
voltage of 3.3 V is required (3.0 V minimum, 3.6 V maximum)
at a typical supply current of 9 mA at midgain. In the following
discussion, V

will be used to denote the power supply volt-

POS

age, which will be assumed to be 3.3 V.
Figure 31 shows the main sections of the AD6458. It consists of

a variable-gain UHF mixer and linear two-stage IF strip, which
together provide a calibrated voltage-controlled gain range of
more than 76 dB, followed by dual quadrature demodulators.
These are driven by inphase and quadrature clocks generated by
a Phase-Locked Loop (PLL), which is locked to a corrected
external reference. A CMOS-compatible power-down interface
completes the AD6458.

Mixer

The UHF mixer is an improved Gilbert-cell design, and can
operate from low frequencies (it is internally dc-coupled) up to
an RF input of 400 MHz. The dynamic range at the input of the
mixer is determined at the upper end by the maximum input
signal level of ±56 mV (–15 dBm in 50 Ω between RFHI and
RFLO) up to which the mixer remains linear and, at the lower
end, by the noise level. It is customary to define the linearity of
a mixer in terms of the 1 dB gain-compression point and third­order intercept, which for the AD6458 are –12 dBm and
–2 dBm, respectively, in a 50 Ω system.

The mixer’s RF input port is differential; that is, pin RFLO is
functionally identical to RFHI, and these nodes are internally
biased. The RF port can be modeled as a parallel RC circuit as
shown in Figure 30.

RFHI

C

R

SH

SH

RFLO

Figure 30. Mixer Port Modeled as a Parallel RC Network

The local oscillator (LO) input is internally biased at VP– 0.8 V
and must be ac coupled. The LO interface includes a preampli­fier which minimizes the drive requirements, thus simplifying
the oscillator design and reducing LO leakage from the RF port.
The LO requires a single-sided drive of ± 50 mV, or –16 dBm in
a 50 Ω system. For operation above 300 MHz noise figure can
be improved by increasing the LO level.

The output of the mixer is single ended with a 330 Ω impedance
for driving ceramic filters.

The conversion gain is measured between the mixer input and
the input of this filter, and varies between –9 dB and +10 dB as
a function of the voltage at Pin GAIN.

The maximum permissible signal level at Pin MXOP is deter­mined by the maximum gain control voltage.

The mixer output port is shown in Figure 32.

RF INPUT

–95dBm TO

–15dBm

RFHI

RFLO

VPS1
VPS2

PRUP

6
5

20
18

3

LO INPUT

–16dBm

LOIP

4

MXOP

BIAS

CIRCUIT

13MHz

CERAMIC

9

BANDPASS

FILTER

2

COM1 COM2

330Ω

0.1µF

AGC VOLTAGE

7

Figure 31. Functional Block Diagram

–10–

4.7kΩ

17

IRXP

16

IFIP

11

12

IFIM

0

°

PLL

90

°

GAIN TC

COMPENSATION

4.7kΩ

4.7kΩ

4.7kΩ

AD6458

IRXN

1

FREF

19

FLTR

15

QRXP

14

QRXN

GAIN

13

8

GREF

REV. 0

AD6458

VPOS

MXP

FROM

MIXER

CORE

MXM

V

160kΩ

BIAS

25kΩ

275Ω

MXOP

330Ω

275Ω

Figure 32. Mixer Output Port

IF Amplifier

Most of the gain in the AD6458 resides in the IF amplifier strip,
which comprises two stages. Both are fully differential and each
has a gain span of 26 dB for the AGC voltage range of 0.2 V to

2.25 V. Thus, in conjunction with the variable gain of the mixer,
the total gain span is 76 dB. The overall IF gain varies from –9
dB to 48 dB for the nominal AGC voltage of 0.2 V to 2.25 V.
Maximum gain is at V

GAIN

= 0.2 V.

The IF input is differential at IFIP and IFIM. Figure 33 shows a
simplified schematic of the IF interface modeled as parallel RC
network.

The IF’s small-signal bandwidth is approximately 50 MHz from
IFIP and IFIM through the demodulator.

IFHI

IFLO

C

SH

R

SH

Figure 33. IF Amplifier Port Modeled as a Parallel RC
Network

Gain Scaling

The AD6458’s overall gain, expressed in decibels, is linear with
respect to the AGC voltage V
sections is maximum when V
is increased to V

= 2.25 and is independent of the power

GAIN

at pin GAIN. The gain of all

GAIN

is 0.2, and falls off as the bias

GAIN

supply voltage. The gain of all stages changes simultaneously.
The AD6458’s gain scaling is also temperature compensated.

The GAIN pin of the AD6458 is an input driven by an external
low impedance voltage source, normally a DAC, under the
control of radio’s digital processor.

The gain-control scaling is directly proportional to the reference
voltage applied to the pin GREF and is independent of the
power supply voltage. When this input is set to the nominal
value of 1.2 V, the scale is nominally 27 mV/dB (37 dB/V).
Under these conditions, 76 dB of gain range (mixer plus IF)
corresponds to a control voltage of 0.2 V <= V

<= 2.25 V. The

G

final centering of this 2.05 V range depends on the insertion
losses of the IF filters used.

Pin GREF can be tied to an external voltage reference, V

REF

,

provided, for example, by a AD1580 (1.21 V) voltage reference.

IRXP
IRXN

QRXP
QRXN

AD6421

BREFOUT

BREFCAP

AGC DAC

AFC DAC

AD6458

IRXP
IRXN

100pF 100pF

QRXP
QRXN

100pF 100pF

GREF

GAIN

FREF

0.1µF

160Ω

1nF

VCTCXO

Figure 34. Interfacing the AD6458 to the AD6421
Baseband Converter

When using the Analog Devices AD7013 (IS54, TETRA and
satellite receiver applications) and AD7015 or AD6421 (GSM,
DCS1800, PCS1900) baseband converters, the external ref­erence may also be provided by the reference output of the
baseband converters. The interface between the AD6458 and
the AD6421 baseband converter is shown in Figure 34. The
AD6421 baseband converter provides a V

of 1.23 V; an

REF

auxiliary DAC in the AD6421 can be used to generate the AGC
voltage. Since it uses the same reference voltage, the numerical
input to this DAC provides an accurate RSSI value in digital
form, no longer requiring the reference voltage to have high
absolute accuracy.

I/Q Demodulators

Both demodulators (I and Q) receive their inputs internally
from the IF amplifiers. Each demodulator comprises a full-wave
synchronous detector followed by an 8 MHz, two-pole low-pass
filter, producing differential outputs at pins IRXP and IRXN,
and QRXP and QRXN. Using the I and Q demodulators for IFs
above 50 MHz is precluded by the 5 MHz to 50 MHz range of
the PLL used in the demodulator section.

The I and Q outputs are differential and can swing up to

2.2 V p-p at the low supply voltage of 3.0 V. They are nominally
centered at 1.5 V independently of power supply. They can
therefore directly drive the RX ADCs in the AD6421 baseband
converter, which require an amplitude of 1.23 V to fully load
them when driven by a differential signal. The conversion gain
of the I and Q demodulators is 17 dB.

For IFs of less than 8 MHz, the on-chip low-pass filters (8 MHz
cutoff) do not adequately attenuate the IF or feedthrough prod­ucts; the maximum input voltage must thus be limited to allow
sufficient headroom at the I and Q outputs, not only for the de­sired baseband signal but also the unattenuated higher order
demodulation products. These products can be removed by an
external low-pass filter. A simple 1-pole RC filter, with its cor­ner above the modulation bandwidth, is sufficient to attenuate
undesired outputs. The design of the RC filter is eased by the

4.7 kΩ resistor integrated at each I and Q output pin.

REV. 0

–11–

AD6458

I/Q Convention

The AD6458 is a complete IF receive subsystem. Although not
a requirement for using the AD6458, most applications will use
a high-side LO injection on pin LOIP (Pin 4) of the mixer. The
I and Q convention is such that when a spectrum with I leading
Q is presented to the input of the mixer, and a high-side LO is
presented on pin LOIP, I still leads Q at the baseband output of
the AD6458.

Phase-Locked Loop

The demodulators are driven by quadrature signals provided by
a variable frequency quadrature oscillator (VFQO), phase­locked to a reference signal applied to Pin FREF. When this
signal is at the IF, in-phase and quadrature baseband outputs
are generated at the I output (IRXP and IRXN) and Q output
(QRXP and QRXN), respectively. The quadrature accuracy of
this VFQO is typically 2° at 13 MHz. A simplified diagram of
the FREF input is shown in Figure 35.

V

POS

FREF

5kΩ

20kΩ

5kΩ

50µA PTAT

The VFQO operates from 5 MHz to 50 MHz and is controlled
by the voltage between V

and FLTR. In normal operation, a

POS

series RC network, forming the PLL loop filter, is connected
from FLTR to V

. The use of an integral sample-hold system

POS

ensures that the frequency-control voltage on pin FLTR re­mains held during power-down, so reacquisition of the carrier
occurs in less than 80 µs.

In practice, the probability of a phase mismatch at power-up is
high, so the worst-case linear settling period to full lock needs to
be considered in making filter choices. This is typically < 80 µs
for a quadrature phase error of ±3° at an IF of 13 MHz. Note
that the VFQO always provides quadrature between its own I
and Q outputs, but the phasing between it and the reference
carrier will swing around the final value during the PLL’s set­tling time.

Bias System

The AD6458 operates from a single supply, V
at a typical supply current of 9 mA at midgain and T

, usually 3.3 V,

POS

= +25°C.

A

Any voltage from 3.0 V to 3.6 V may be used.
The bias system includes a fast acting active high CMOS-

compatible power-up switch, allowing the part to idle at 1 µA
when disabled. Biasing is generally proportional-to-absolute­temperature (PTAT) to ensure stable gain with temperature.
Other special biasing techniques are used to ensure very accu­rate gain, stable over the full temperature range.

C3052–2–4/97

Figure 35. Simplified Schematic of the FREF Interface

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

20-Lead Plastic SSOP

0.295 (7.50)

0.271 (6.90)

20 11

0.311 (7.9)

0.301 (7.64)

0.078 (1.98)

0.068 (1.73)

0.008 (0.203)

0.002 (0.050)

PIN 1

0.0256
(0.65)

BSC

SEATING

(RS-20)

101

0.07 (1.78)

0.066 (1.67)

PLANE

0.212 (5.38)

0.205 (5.21)

0.009 (0.229)

0.005 (0.127)

8°
0°

0.037 (0.94)

0.022 (0.559)

PRINTED IN U.S.A.

–12–

REV. 0