Datasheet AD6432 Datasheet (Analog Devices)

a

GSM 3 V Transceiver IF Subsystem

AD6432

FEATURES
Fully Compliant with Standard and Enhanced GSM
Specification

DC-350 MHz RF Bandwidths
80 dB Gain Control Range
I/Q Modulation and Demodulation
Onboard Phase Locked Tunable Oscillator
On-Chip Noise Roofing IF Filters

Ultralow Power Design

2.7 V–3.6 V Operating Voltage

User-Selectable Power-Down Modes
Small 44-Lead TQFP Package
Interfaces Directly with AD20msp410 and AD20msp415

GSM Baseband Chipsets

APPLICATIONS
I/Q Modulated Digital Wireless Systems
GSM Mobile Radios
GSM PCMCIA Cards

GENERAL DESCRIPTION

The AD6432 IF IC provides the complete transmit and receive
IF signal processing, including I/Q modulation and demodula­tion, necessary to implement a digital wireless transceiver such
as a GSM handset. The AD6432 may also be used for other
wireless TDMA standards using I/Q modulation.

The AD6432’s receive signal path is based on the proven archi­tecture of the AD607 and the AD6459. It consists of a mixer,
gain-controlled amplifiers, integrated roofing filter and I/Q
demodulators based on a PLL. The low noise, high-intercept
variable-gain mixer is a doubly-balanced Gilbert-cell type. It has
a nominal –13 dBm input-referred 1 dB compression point and
a 0 dBm input-referred third-order intercept.

The gain-control input accepts an external control voltage input
from an external AGC detector or a DAC. It provides an 80 dB
gain range with 27.5 mV/dB gain scaling, where the mixer and
the IF gains vary together.

The I and Q demodulators provide inphase and quadrature
baseband outputs to interface with Analog Devices’ AD7015
and AD6421 (GSM, DCS1800, PCS1900) baseband convert­ers. An onboard quadrature VCO, externally phase-locked to
the IF signal, drives the I and Q demodulators. The quadrature
phase-locked oscillator (QPLO) requires no external compo­nents for frequency control or quadrature generation, and de­modulates signals at standard GSM system IFs of 13 MHz, or
26 MHz with a reference input frequency of 13 MHz; or, in
general, 1X or 2X the reference frequency. Maximum reference
frequency is 25 MHz.

FUNCTIONAL BLOCK DIAGRAM

BP

SAW

PLO

AD6432

This reference signal is normally provided by an external
VCTCXO under the control of the radio’s digital signal
processor. The transmit path consists of an I/Q modulator
and buffer amplifier, suitable for carrier frequencies up to
300 MHz and provides an output power of –17.5 dBm in
a 50 Ω system. The quadrature LO signals driving the
I and Q modulator are generated internally by dividing by
two the frequency of the signal presented at the differential
LO port of the AD6432. In both the transmit and receive
paths, onboard filters provide 30 dB of stopband attenuation.

The AD6432 comes in a 44-lead plastic thin quad flatpack
(TQFP) surface mount package.

OP AMP

IF

SYNTH

RF

SYNTH

PA

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 1997

AD6432–SPECIFICATIONS

(TA = +258C, VP = 3.0 V, GREF = 1.25 V unless otherwise noted)

Parameter Conditions Min Typ Max Units

RX RF MIXER

RF Input Frequency 350 MHz
AGC Conversion Gain Variation Z
Input 1 dB Compression Point At V
Input Third-Order Intercept At V
SSB Noise Figure At Z

= 150 Ω: 0.2 V < V

IN

= 2.4 V, Z

GAIN

= 0.2 V, RFIN = –25 dBm 0 dBm

GAIN

= 150 Ω, F

IN

RF

FLO = 272 MHz, V

< 2.4 V –3 to +15 dB

GAIN

= 150 Ω –13 dBm

IN

= 246 MHz,

= 0.2 V 10 dB

GAIN

RX IF AMPLIFIER

AGC Gain Variation 0.2 V < V
Input Resistance at V

GAIN

< 2.4 V –14 to 48 dB

GAIN

= 0.2 V 5 kΩ

Operating Frequency Range 10 50 MHz

GAIN CONTROL

Total Gain Control Range Mixer+IF+Demod, 0.2 V < V

< 2.4 V 80 dB

GAIN

Control Voltage Range at GAIN 0.2 2.4 V
Gain Scaling 27.5 mV/dB
Gain Law Conformance ±0.1 dB
Bias Current at GREF –0.5 µA
Input Resistance at Gain 20 kΩ

INTEGRATED IF FILTER

BPF Center Frequency f

IFS0 = 1 “0” = Connect to Ground, “1” = Connect to V
IFS0 = 0 “0” = Connect to Ground, “1” = Connect to V

BPF –3 dB BW f

IFS0 = 1 “0” = Connect to Ground, “1” = Connect to V
IFS0 = 0 “0” = Connect to Ground, “1” = Connect to V

= 13 MHz

REF

= 13 MHz

REF

P
P

P
P

13 MHz
26 MHz

5 MHz
10 MHz

I AND Q DEMODULATOR

Demodulation Gain 17 dB
Output Voltage Range Differential 0.3 V

– 0.2 V

POS

Output Voltage Common-Mode Level Not Power Supply Independent 1.5 V
Output Offset Voltage Differential, V

= GREF –150 +150 mV

GAIN

Error in Quadrature Differential from I to Q, IF = 13 MHz 1 3.5 Degrees
Amplitude Match 0.25 dB
I/Q Output BW C

= 10 pF 3 MHz

LOAD

Output Resistance Each Pin 4.7 kΩ

QUADRATURE IF PLL

Operating Frequency Range 10 50 MHz
Reference Frequency Voltage Level 200 mV p-p
Reference Frequency Range 25 MHz
Acquisition Time Using 1 kΩ, 1 nF Loop Filter 80 µs

TRANSMIT MODULATOR

Carrier Output Frequency 300 MHz
Output Power R

Input 1 dB Compression Point R

= 150 Ω, Power at Final 50 Ω,

LOAD

F

= 272 MHz –17.5 dBm

IF

= 150 Ω (Differential) 14 dBm

LOAD

I/Q Input Signal Amplitude Differential 2.056 V p-p
I/Q Input Signal Required DC Bias 1.2 V
I/Q Input BW 1 MHz
I/Q Input Resistance 100 kΩ
I/Q Phase Balance With LOs 2nd Harmonic 30 dBc

Bellow Fundamental ±1.5 Degrees

I/Q Amplitude Balance With LOs 2nd Harmonic 30 dBc

Bellow Fundamental ±0.1 dB

Output Harmonic Content R

= 150 Ω –45 (3rd) dBc

LOAD

–65 (5th) dBc

Carrier Feedthrough F

= 272 MHz –33 dBc

CARRIER

Sideband Suppression I and Q Inputs Driven In Quadrature –37 dBc

–2–

REV. 0

AD6432

WARNING!

ESD SENSITIVE DEVICE

Parameter Conditions Min Typ Max Units

LO PORT (LOLO and LOHI)

Input Frequency 200 600 MHz
Input Signal Voltage Range Differential 200 mV p-p
Input Resistance Input Pull-Up Resistors to V

AUXILIARY OP AMPLIFIER

Small Signal –3 dB Bandwidth 50 MHz
Input Signal Voltage Range 0.1 V
Input Offset Voltage ±4mV
Input Bias Current –150 nA
Output Signal Voltage Range With R

> 4 kΩ 0.1 V

LOAD

POWER CONSUMPTION

Supply Voltage 2.7 3 3.6 V
Transmit Mode 13 mA
Receive Mode At V

= 1.2 V 13 mA

GAIN

Sleep Mode < 5 µA

OPERATING TEMPERATURE RANGE –25 +85 °C

NOTES
All reference to dBm is relative to 50 Ω.

Specifications subject to change without notice.

ABSOLUTE MAXIMUM RATINGS

1

Supply Voltage VPDV, VPPX, VPDM, VPFL, VPPC, VPRX,

to CMTX, CMRX, CMIF, CMD . . . . . . . . . . . . . . +3.6 V

Internal Power Dissipation

2

. . . . . . . . . . . . . . . . . . . 600 mW

Operating Temperature Range . . . . . . . . . . . –25°C to +85°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Lead Temperature, Soldering (60 sec) . . . . . . . . . . . +300°C

NOTES

1

Stresses above those listed under Absolute Maximum Ratings may cause perma­nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

2

Thermal Characteristics: 44-lead TQFP package: θJA = 126°C.

ORDERING GUIDE

Temperature Package Package

Model Range Description Option*

(Each Pin) 500 Ω

POS

– 2.1 V

POS

– 0.2 V

POS

PIN CONFIGURATION

VPTX

ITXP

ITXN

QTXP

QTXN

TXPU

PCAP

PCAM

GND

VPPC

CMIF

20

RXPU

21 22

GAIN

PCAO

GREF

33
32
31
30
29
28
27
26
25
24
23

GND

GND

MODO

VPDV
CMTX
LOLO

LOHI

CMRX

GND

RFLO

RFHI

GND

1
2
3
4
5
6
7
8

9
10
11

121314 15 16 17 18 19

VPRX

MXHI

MXLO

(Pins Down)

40 39 3841424344 36353437

AD6432

TOP VIEW

IFHI

IFLO

CMIF

FREF
GND
IFS0
CMDM
FLTR
VPFL
VPDM
IRXP
IRXN
QRXP
QRXN

AD6432AST –25°C to +85°C 44-Pin Plastic ST-44

*ST = Thin Quad Flatpack.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD6432 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

REV. 0

TQFP

–3–

AD6432

PIN FUNCTION DESCRIPTIONS

Pin Label Description Function

1 GND PCB Ground Not Bonded to IC
2 MODO TX Modulator Output AC Coupled, Drives 150 Ω into 50 Ω
3 VPDV LO2 Divided by 2 Supply Voltage V
4 CMTX On-Chip TX Mixer Common Ground
5 LOLO Differential RX Mixer LO2 Input Negative AC Coupled, V
6 LOHI Differential RX Mixer LO2 Input Positive AC Coupled, V
7 CMRX On-Chip RX Mixer Common Ground
8 GND PCB Ground Not Bonded to IC

9 RFLO Differential RX Mixer IF1 Input Negative AC Coupled
10 RFHI Differential RX Mixer IF1 Input Positive AC Coupled
11 GND PCB Ground Not Bonded to IC
12 VPRX RX Section Supply Voltage V
13 MXHI Differential RX IF1/IF2 Mixer Output Positive See Figure 30
14 MXLO Differential RX IF1/IF2 Mixer Output Negative See Figure 30
15 CMIF On-Chip RX IF2 Common Ground
16 IFLO Differential RX IF2 Input Negative AC Coupled
17 IFHI Differential RX IF2 Input Positive AC Coupled
18 CMIF On-Chip RX IF2 Common Ground
19 RXPU RX Enable (Power-Up) Off = Low < 0.6 V, On = High > 2.5 V
20 GAIN RX VGA Gain Control Input 0.2 V–2.4 V Using 3 V Supply. Max Gain at 0.2 V
21 GREF RX VGA Reference Voltage 1.2 V typ
22 GND PCB Ground Not Bonded to IC
23 QRXN Differential Demodulator Q Output Negative Internal 4.7 kΩ Resistor in Series with the Output
24 QRXP Differential Demodulator Q Output Positive Internal 4.7 kΩ Resistor in Series with the Output
25 IRXN Differential Demodulator I Output Negative Internal 4.7 kΩ Resistor in Series with the Output
26 IRXP Differential Demodulator I Output Positive Internal 4.7 kΩ Resistor in Series with the Output
27 VPDM Demodulator Supply Voltage V
28 VPFL I/Q LO PLL Filter Cap. Supply Voltage To V
29 FLTR I/Q LO PLL Filter Referenced to VPFL
30 CMDM On-Chip Demodulator Common Ground
31 IFS0 IF2 Frequency Select Bit “0” = Low < 0.6 V, “1” = High > 2.5 V
32 GND PCB Ground Not Bonded to IC
33 FREF Reference Input (13 MHz for GSM) AC Coupled. Use 200 mV p-p Input Signal
34 VPPC Auxiliary Op Amp Supply Voltage V
35 PCAO Auxiliary Op Amp Output Active when TXPU Is High
36 GND PCB Ground Not Bonded to IC
37 PCAM Differential Auxiliary Op Amp Input Negative 0.1 V to V
38 PCAP Differential Auxiliary Op Amp Input Positive 0.1 V to V
39 TXPU TX Enable (Power-Up) Low < 0.6 V, High > 2.5 V
40 QTXN Differential Modulator Q Input Negative DC Coupled, 1.2 V ± 514 mV
41 QTXP Differential Modulator Q Input Positive DC Coupled, 1.2 V ± 514 mV
42 ITXN Differential Modulator I Input Negative DC Coupled, 1.2 V ± 514 mV
43 ITXP Differential Modulator I Input Positive DC Coupled, 1.2 V ± 514 mV
44 VPTX TX Section Supply Voltage V

POS

POS

POS

POS

POS

with Good Decoupling

POS

POS

– 2.1 V

POS

– 2.1 V

POS

POS

to V

– 100 mV

POS

– 100 mV to V

POS

–4–

REV. 0

PCAP

TXPU

QTXN

QTXP

ITXN

ITXP

MODO

LOLO

RFHI

TXPU

IFS0

RXPU

4.7

DECOUPLING

VS1

C7

F

VS1

J1

J3

J4

J5

VPDV

6

4

AD6432

R30

49.9Ω

C9

F

0.1

R12

100pF

0Ω

C28

0.1

C2

F

R23
123Ω

C15
100pF

GND

MODO

VPDV
CMTX
LOLO

LOHI

CMRX

GND

RFLO

RFHI

GND

C5

0.01

F

VPTX

ITXP

1

2
3
4
5

6

7

8
9
10

11

121314 15 16 17 18 19

MXHI

VPRX

ITXN

QTXP

QTXN

40 39 3841424344 363534

AD6432

TOP VIEW

(Pins Down)

IFLO

CMIF

MXLO

VS1

VPTX

DECOUPLING

R9
84Ω

R2
0Ω

C29

0.1

T1

C18

1

F

0.1

2
3

R3

49.9Ω

C14

F

0.01 F

R14
249Ω

C1

100pF

VS2

C7

4.7 F

GREF

GAIN

GND

VS1

MXHI

MXLO

0.1

C30

R31

C3

0Ω

0.01

C44

F

F

C4

0.047 F

R4

49.9Ω

F

C43

F

0.047

0.047

IFLO

TXPU

IFHI

0.047

PCAP

37

CMIF

C7

R11
1kΩ

R10

500Ω

R25
1kΩ

PCAM

GND

20

GAIN

RXPU

F

R5

49.9Ω

R39

OPEN

PCAO

21 22

GREF

C40

0.01

C39

0.01

VPPC

33
32
31
30
29
28
27
26
25
24
23

GND

F

F

FREF
GND
IFS0
CMDM
FLTR
VPFL
VPDM
IRXP
IRXN
QRXP
QRXN

GREF

GAIN

RXPU

IFHI

VS1

C36

1000pF

C10

1000pF

R34

0Ω

C11

0.01

C8
47pF

R1

1kΩ

PCAM

PCAO

R8
0Ω

F

IFS0

0.01

C41

0.01

C32

0.1

C23

F

F

VPPC
DECOUPLING

R32

49.9Ω

R6
0Ω

F

VS2

R7
0Ω

C17

0.1 F

FREF

VS1

IRXP

C6
47pF

IRXN

QRXP

QXRN

REV. 0

Figure 1. Characterization Board

–5–

AD6432

QTX

VDC

ITX

VDC

VP

10kΩ

0.1µF

INTERFACE BOX TO TEST INSTR

R29

C13

ITX

QTX

MODO

LOIP

RFHI

MXOUT

R22
50Ω

R21
50Ω

1

2

V+

AD1580

V–

R3
20kΩ

R4
20kΩ

NC

VGREF

3

IFIN

FREF

IRX

QRX

PCAP

PCAO

R8
20kΩ

R6
20kΩ

R2

10kΩ

C1 0.1µF

VP

R7

10kΩ

10kΩ

10kΩ

QRX

R1

R5

IRX

QTXN

R9

R10

25Ω

R12
25Ω

C4

0.1µF

C3

0.1µF

C5

0.1µF

C6

0.1µF

10kΩ

C2 1pF

VN

R13

10kΩ

R11

10kΩ

R14

10kΩ

5

V

N

6

A=1

7

8

V

P

5

V

N

6

A=1

7

8

V

P

VN

VN

14

13

12

11

VN

10

9

8

VP

VP

1

2

3

AD824

VP

4

5

6

7

R23
50Ω

R24
50Ω

AD830

AD830

Gm

Gm

Gm

Gm

R17
10kΩ

R15

10kΩ

R16

10kΩ

R18
10kΩ

R20
25Ω

R19
25Ω

4

3

2

1

4

3

2

1

QTXP

VDC

ITXP

ITXN

IRXN

IRXP

QRXN

QRXP

VS1
VS2
GND
VP
VN
GAIN

INTERFACE BOX TO CHAR BOARD

ITXP

ITXN

QTXP

QTXN

MODO

LOIP

VS2
IFS1
IFS0

RXPU

VS1

3

3

J1

2 TXPU

1

2 RXPU

1

RFHI

MXHI

MXLO

IFLO

IFHI

FREF

GND
TXPU
GAIN
GREF
GND

IRXP

IRXN

QRXP

QRXN

PCAP

PCAO

MXOUT

IFIN

NOTES:

VP = +5V
VN = –5V

R25
50Ω

R26
50Ω

VN

AD830

5

V

C8

0.1µF

VP

C7

0.1µF

VP

N

6

A=1

7

8

V

P

1

Gm

2

3

Gm

4

AD830

1

Gm

2

3

Gm

4

AD830

Gm

Gm

A=1

A=1

IFS0

4

3

R30
20kΩ

2

1

R31
20kΩ

V

8

7

6

5

V

8

P

7

6

5

V

N

C9

0.1µF

C11

0.1µF

C10

0.1µF

C12

0.1µF

P

V

N

V

P

V

N

R27
50Ω

R28
50Ω

MXLO

MXHI

IFHI

IFLO

Figure 2. Characterization Test Set

–6–

REV. 0

AD6432

11

10.5
RIN = 50Ω, IF = 45MHz

10

RIN = 50Ω, IF = 26MHz

9.5

9

8.5
RIN = 50Ω, IF = 13MHz

8

7.5

7

6.5

SINGLE SIDEBAND Rx MIXER NOISE FIGURE – dB

6

150 450200 250 300 350 400

RF FREQUENCY – MHz

RIN = 400Ω, IF = 13MHz

Figure 3. Rx Mixer Noise Figure vs. RF Frequency,

= +25°C, V

T

A

900

800

700

600

500

400

SHUNT RESISTANCE – Ω

300

200

100

50 550100 150 200 250 300 350 400 450 500

= 3 V, V

POS

R

S

V

= 2.4V

GAIN

GREF

R

S

V

= 1.2V

GAIN

R

S

V

= 0.2V

GAIN

FREQUENCY – MHz

= 1.2 V, V

C

S

V

= 0.2V

GAIN

GAIN

C

S

V

GAIN

C
V

S
GAIN

= 0.2 V

= 1.2V

= 2.4V

5.0

4.5

4.0

3.5

3.0

2.5

GAIN – dB

Figure 6. Mixer Conversion Gain vs. IF Frequency,
T

= +25°C, V

A

GAIN – dB

SHUNT CAPACITANCE – pF

20

V

= 2.7V TO 3.6V

POS

= 2.7V TO 3.6V

GAIN

V

V

50 60

15

10

5

0

–5

10 14 18 26 34 42

70

60

50

40

30

20

10

–40 –30 –20 0 20 40

22 30 38 46 50

IF FREQUENCY – MHz

= 3 V, V

POS

AMP/DEMOD, V

–10 10 30

= 1.2 V, FRF = 250 MHz

GREF

MIXER, V

POS

TEMPERATURE – C

GAIN

GAIN

= 0.2V

= 1.5V

= 2.4V

70 80 90

Figure 4. Rx Mixer Input Impedance vs. RF Frequency,

= 3 V, TA = +25°C, V

V

POS

16
14
12
10

8
6
4

GAIN – dB

2

0
–2
–4
–6

150 175 200 250 300 350

RF FREQUENCY – MHz

= 1.2 V

GREF

V

= 0.2V

GAIN

V

= 1.5V

GAIN

V

= 2.4V

GAIN

225 275 325

Figure 5. Rx Mixer Conversion Gain vs. RF Frequency,

= +25°C, V

T

A

= 3 V, V

POS

= 1.2 V, FIF = 26 MHz

GREF

Figure 7. Rx Mixer Conversion Gain and IF Amplifier/
Demodulator Gain vs. Temperature, V
V

= 1.2 V, FIF = 26 MHz, FRF = 250 MHz

GREF

–10

–11

–12

–13

–14

INPUT – dBm (REFERRED TO 50Ω)

–15

–16

0

V

POS

0.5 1.0 1.5 2.0 2.5

V

POS

V

= 3.6V, TA = +85 C

POS

= 3.6V, TA = –40 C

V

– Volts

GAIN

= 2.7V, TA = +85 C

V

POS

V

POS

= 0.2 V,

GAIN

= 2.7V, TA = +25 C

= 2.7V, TA = –25 C

Figure 8. Rx Mixer Input 1 dB Compression Point vs.

, V

V

GAIN

= 1.2 V, FRF = 250 MHz, FIF = 26 MHz

GREF

REV. 0

–7–

AD6432

70

60

50

40

30

20

IF AMP/DEMOD GAIN – dB

10

0

–10

10

15 20 25 30 35

INTERMEDIATE FREQUENCY – MHz

V

V

V

V

GAIN

GAIN

GAIN

GAIN

= 0.2V

= 0.5V

= 1.5V

= 2.4V

40 45

Figure 9. IF Amplifier and Demodulator Gain vs. IF
Frequency, T

13000

12000

11000

10000

9000

8000

7000

RESISTANCE – Ω

6000

5000

4000

3000

10 15 20 25 30 35

= +25°C, V

A

C
V

GAIN

C

S

V

GAIN

R

S

V

GAIN

IF INPUT FREQUENCY – MHz

= 3 V, V

POS

S

= 0.2V

C

S

V

GAIN

= 2.4V

= 0.2V

= 1.2 V

GREF

R
V

= 1.2V

R

S

V

GAIN

40 45 50

S

GAIN

= 1.2V

= 2.4V

4.0

3.8

3.6

3.4

3.2

3.0

2.8

2.6

2.4

2.2

2.0

Figure 12. Gain Error vs. Gain Control Voltage, TA = +25°C,
V

POS

CAPACITANCE – pF

0.4

0.3

0.2
IF AMP/DEMOD

0.1

GAIN ERROR – dB

0

–0.1

–0.2

0 0.5 1.0 1.5 2.0 2.5

= 3 V, V

GREF

0.6

0.4

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

–1.2

DEMODULATOR QUADRATURE ERROR – Degrees

–1.4

10 15 20 25 30 35

MIXER

V

– Volts

GAIN

= 1.2 V, FRF = 250 MHz, FIF = 26 MHz

DEMODULATOR VCO FREQUENCY – MHz

40 45

Figure 10. IF Amplifier Input Impedance vs. Frequency,

= +25°C, V

T

A

0

–10

–20

–30

–40

TO 50 OHMS – dBm

–50

IF INPUT 1dB COMPRESSION REFERRED

–60

= 3 V, V

POS

0 0.5 1.0 1.5 2.0 2.5

GREF

V

= 1.2 V

– Volts

GAIN

Figure 11. IF Amplifier/Demodulator Input 1 dB
Compression Point vs. V
V

= 1.2 V, TA = +25°C, V

GREF

, FIF = 26 MHz,

GAIN

= 3 V

POS

Figure 13. Demodulator Quadrature Error vs. FREF
Frequency, T

–80

–85

–90

–95

–100

PHASE NOISE – dBc/Hz

–105

–110

0.1 1.0 10 100 1000

Figure 14. PLL Phase Noise vs. Frequency, V
C

=1 nF, R

FLTR

= +25°C, V

A

FREQUENCY OFFSET – kHz

=1 kΩ, FREF = 13 MHz

FLTR

POS

= 3 V

IF = 26MHz

IF = 13MHz

POS

= 3 V,

–8–

REV. 0

AD6432

0

–0.2

–0.4

– Volts

POS

–0.6

–0.8

FILTER PIN VOLTAGE

–1.0

REFERENCED TO V

–1.2

–1.4

10 40 50

15 20 25 30 35 45

FREQUENCY OF VCO – MHz

TA = –40 C

TA = +25 C

TA = +85 C

Figure 15. PLL Loop Voltage at FLTR Pin (KVCO) vs.
Frequency

–10

–20

–30

–40

–50

REFERRED TO 50 OHMS – dBm

INPUT 1dB COMPRESSION POINT

–60

16

14

12

10

8

6

4

2

CONVERSION GAIN – dB

0

–2

–4

0

0.5 1.0 1.5 2.0 2.5
V

GAIN

– Volts

Figure 18. Rx Mixer Conversion Gain vs V

= 3 V, FRF = 250 MHz, FIF = 26 MHz, V

V

POS

70

60

50

40

30

20

IF AMP/DEMODULATOR GAIN – dB

10

, TA = +25°C,

GAIN

= 1.2 V

GREF

–70

0

0.5 1.0 1.5 2.0 2.5
GAIN VOLTAGE – Volts

Figure 16. System (Mixer + IF LC Filter + IF Amplifier +
Demodulator) 1 dB Compression Point vs. V

= 3 V, FRF = 250 MHz, FIF = 26 MHz, V

V

POS

0

–10

–20

–30

–40

SYSTEM INPUT IP3

–50

REFERRED TO 50 OHMS – dBm

–60

–70

0

0.5 1.0 1.5 2.0 2.5
GAIN VOLTAGE – Volts

GAIN

GREF

= 1.2 V

, TA = +25°C,

Figure 17. System (Mixer + IF LC Filter + IF Amplifier +
Demodulator) IP3 vs. V

= 26 MHz, FRF = 250 MHz, V

F

IF

, TA = +25°C, V

GAIN

GREF

= 1.2 V

POS

= 3 V,

0

0

Figure 19. IF Amplifier/Demodulator Gain vs. V

= +25°C, V

T

A

V

= 1.2 V

GREF

80

70

60

50

40

30

SYSTEM GAIN – dB

20

10

0

0

0.5 1.0 1.5 2.0 2.5

= 3 V, FRF = 250 MHz, FIF = 26 MHz,

POS

0.5 1.0 1.5 2.0 2.5

V

– Volts

GAIN

GAIN VOLTAGE – Volts

GAIN

,

Figure 20. System (Mixer + IF LC Filter + IF Amplifier +
Demodulator) Gain vs. V
F

=26 MHz, FRF = 250 MHz, V

IF

, TA = +25°C, V

GAIN

GREF

= 1.2 V

POS

= 3 V,

REV. 0

–9–

AD6432

–16.0

–16.5

–17.0

–17.5

–18.0

–18.5

–19.0

–19.5

TRANSMIT DESIRED SIDEBAND GAIN – dB

–20.0

–40

–20 0 20 40 60

TEMPERATURE – C

80 100

Figure 21. Tx Desired Sideband Gain vs. Temperature,

= +25°C, V

T

A

= 3 V, F

POS

= 280 MHz, I and Q Inputs

CARRIER

Driven in Quadrature

–13.5
–14.0
–14.5
–15.0
–15.5
–16.0
–16.5
–17.0
–17.5
–18.0
–18.5

TRANSMIT DESIRED SIDEBAND GAIN – dB

–19.0

100

120 140 160 180 200

CARRIER FREQUENCY – MHz

220 240

260 280 300

–35.0

–35.5

–36.0

–36.5

–37.0

–37.5

–38.0

–38.5

TYPICAL UNDESIRED

–39.0

SIDEBAND SUPPRESSION – dBc

–39.5

–40.0

100

120 140 160 180 200

CARRIER FREQUENCY – MHz

240 260

280 300220

Figure 24. Tx Typical Undesired Sideband Suppression
vs. F

, TA = +25°C, V

CARRIER

22

20

18

16

14

SUPPLY CURRENT – mA

12

V

POS

10

T

0

= 3 V

POS

V

= 3.6V, TA = +85 C

POS

V

= 2.7V, TA = +85 C

POS

V

= 3.6V, TA = +25 C

POS

V

= 3V, TA = +25 C

POS

V

= 2.7V, TA = +25 C

POS

V

= 3.6V

= 2.7V

= –40 C

A

0.5 1.0 1.5 2.0 2.5
GAIN VOLTAGE – Volts

POS

T

A

= –40 C

Figure 22. Tx Desired Sideband Gain vs. F
T

= +25°C, V

A

–35.0

–35.5

–36.0

–36.5

–37.0

–37.5

–38.0

TYPICAL UNDESIRED

–38.5

–39.0

SIDEBAND SUPPRESSION – dBc

–39.5

–40.0

–40

= 3 V

POS

–20 0 20 40 60

TEMPERATURE – C

CARRIER

80 100

,

Figure 23. Tx Typical Undesired Sideband Suppression
vs. Temperature, T

= +25°C, V

A

POS

= 3 V

Figure 25. Rx Mode Supply Current vs. V

15.0

14.5

14.0

13.5

13.0

12.5

12.0

11.5

Tx MODE SUPPLY CURRENT – mA

11.0

10.5
–20 0 20 40 60

–40

V

V

= 3V

POS

TEMPERATURE – C

POS

Figure 26. Tx Mode Supply Current vs. Temperature

–10–

= 3.6V

GAIN

V

, V

= 2.7V

POS

80 100

GREF

= 1.2 V

REV. 0

AD6432

PRODUCT OVERVIEW

The AD6432 provides most of the active circuitry required to
realize a complete low power, single-conversion superhetero­dyne time division transceiver, or the latter part of a double­conversion transceiver, at input receive frequencies up to
350 MHz with an IF from 10 MHz to 50 MHz and transmit
frequencies up to 300 MHz. The internal I/Q demodulators,
with their associated phase-locked loop and the internal I/Q
modulator, support a wide variety of modulation modes, includ­ing n-PSK, n-QAM, and GMSK. A single positive supply volt­age of 3 V is required (2.7 V minimum, 3.6 V maximum) at a
typical supply current of 13 mA at midgain in receive mode and
13 mA in transmit mode. In the following discussion, V

POS

will
be used to denote the power supply voltage, which will be as­sumed to be 3 V.

RFHI

RFLO

10

9

MXOP

MXOM

13

14

LC

BANDPASS

FILTER

GAIN TEMP. COMPENSATION

IFIP

16

17

IFIM

Figure 27 shows the main sections of the AD6432. In the re­ceive path, it consists of a variable-gain UHF mixer and linear
two-stage IF strip, both of which together provide a calibrated
voltage-controlled gain range of more than 80 dB, followed by a
tunable IF bandpass filter and dual quadrature demodulators.
These are driven by inphase and quadrature clocks generated
by a Phase-Locked Loop (PLL) locked to a corrected external
reference. In the transmit path it consists of a quadrature modu­lator followed by a low-pass filter. The quadrature modulator is
driven by quadrature frequencies that are generated internally
by dividing the external local oscillator frequency by two. A
CMOS-compatible power-down interface completes the AD6432.

4.7kΩ

25

IRXN

26

IRXP

23

QRXN

24

QRXP

31

IFS0

33

FREF
FLTR

29

20

GAIN

90 0

QUADRATURE

VCO

DIVIDE BY

1 OR 2

PHASE

DETECTOR

3MHz

4.7kΩ

4.7kΩ

4.7kΩ

LOHI

LOLO

MODO

PCAO

21

6

2

5

2

35

0

90

AD6432

RX, TX

BIAS

GREF

RXPU

19

39

TXPU

42

ITXN

43

ITXP

40

QTXN

41

QTXP

38

PCAP

37

PCAM

Figure 27. Functional Block Diagram

REV. 0

–11–

AD6432

Receive Mixer

The UHF mixer is an improved Gilbert-cell design that can
operate from low frequencies (it is internally dc-coupled) up to
an RF input of 350 MHz. The dynamic range at the input of the
mixer is determined, at the upper end, by the maximum input
signal level of ±71 mV (–13 dBm in 50 Ω between RFHI and
RFLO) up to which the mixer remains linear and, at the lower
end, by the noise level. It is customary to define the linearity of
a mixer in terms of the 1 dB gain-compression point and third­order intercept, which for the AD6432 are –13 dBm and 0 dBm,
respectively, in a 50 Ω system.

The mixer’s RF input port is differential, that is, pin RFLO is
functionally identical to RFHI, and these nodes are internally
biased. The RF port can be modeled as a parallel RC circuit as
shown in Figure 29. The local oscillator input of the receive
mixer is internally provided by the LO divided by two.

RFHI

R

SH

RFLO

C

SH

Figure 28. Mixer Port Modeled as a Parallel RC Network
At V
R

= 1.2 V and FRF = 250 MHz, CSH = 3.5 pF and

GAIN

= 400 Ω (See Figure 4)

SH

The output of the mixer is differential. The nominal conversion
gain is specified for operation into a 26 MHz LC IF bandpass
filter, as shown in Figure 29 and Table I.

MXOP

MXOM

C1

C2

C1

L1

IFIP

IFIM

Figure 29. Suggested IF Filter Inserted Between the
Mixer’s Output Port and the Amplifier’s Input Port

The conversion gain is measured between the mixer input and
the input of this filter, and varies between –3 dB and +15 dB.

Table I. Filter Component Values for Selected Frequencies

Frequency C1 L1 C2

13 MHz 27 pF 0.82 µH 180 pF
26 MHz 22 pF 0.39 µH 82 pF

The maximum permissible signal level between MXOP and
MXOM is determined by the maximum gain control voltage.
The mixer output port, having pull-up resistors of 250 Ω to
VPRX, is shown in Figure 30.

250Ω

VPRX

250Ω

MXOP

MXOM

Figure 30. Mixer Output Port

IF Amplifier

Most of the gain in the AD6432 receive section is provided by
the IF amplifier strip, which comprises two stages. Both are fully
differential and each has a gain span of 31 dB for the AGC volt­age range of 0.2 V to 2.4 V. Thus, in conjunction with the vari­able gain of the mixer, the total gain span is 80 dB. The overall IF
gain varies from –14 dB to +48 dB for the nominal AGC voltage of

0.2 V to 2.4 V. Maximum gain is at V

GAIN

= 0.2 V.

The IF input is differential, at IFHI and IFLO. Figure 32 shows
a simplified schematic of the IF interface modeled as parallel
RC network.

The operative range of the IF amplifier is approximately 50 MHz
from IFHI and IFLO through the demodulator.

IFHI

IFLO

C

SH

R

SH

Figure 31. IF Amplifier Port Modeled as a Parallel RC
Network for V

= 8.5 kΩ (See Figure 10)

R

SH

= 1.2 V and FIF = 26 MHz, CSH = 3 pF,

GAIN

Gain Scaling

The overall gain of the AD6432, expressed in decibels, is linear
with respect to the AGC voltage V
of all sections is maximum when V
bias is increased to V

= 2.4 V and is independent of the

GAIN

at Pin GAIN. The gain

GAIN

is 0.2, and falls off as the

GAIN

power supply voltage. The gain of all stages changes simulta­neously. The AD6432’s gain scaling is also temperature­compensated. Note that GAIN pin of the AD6432 is an input
driven by an external low impedance voltage source, normally a
DAC, under the control of radio’s digital processor.

The gain-control scaling is directly proportional to the reference
voltage applied to the Pin GREF and is independent of the
power supply voltage. When this input is set to the nominal
value of 1.2 V, the scale is nominally 27.5 mV/dB (36.4 dB/V).
Under these conditions, 80 dB of gain range (mixer plus IF)
corresponds to a control voltage of 0.2 V < = V

< = 2.4 V. The

G

final centering of this 2.2 V range depends on the insertion losses of
the IF filters used.

Pin GREF can be tied to an external voltage reference, V

REF

,

provided, for example, by a AD1580 (1.21 V) voltage reference.
When using the Analog Devices AD7013 (IS54, TETRA and

satellite receiver applications) and AD7015 or AD6421 (GSM,
DCS1800, PCS1900) baseband converters, the external refer­ence may also be provided by the reference output of the

–12–

REV. 0

AD6432

baseband converters. The interface between the AD6432 and
the AD6421 baseband converter is shown in Figure 35. The
AD7015 baseband converter provides a V

of 1.23 V; an auxil-

R

iary DAC in the AD7015 can be used to generate the AGC
voltage. Since it uses the same reference voltage, the numerical
input to this DAC provides an accurate RSSI value in digital
form, no longer requiring the reference voltage to have high
absolute accuracy.

Tunable Filter and I/Q Demodulators

The demodulators (I and Q) receive their inputs internally from
the IF amplifier through a two-pole tunable-frequency bandpass
filter. This filter is centered on the IF frequency and its band­width is approximately equal to forty per cent of the IF fre­quency. The filter attenuates the amount of noise present at the
input of the demodulators.

Each demodulator comprises a full-wave synchronous detector
followed by a 3 MHz, two-pole low-pass filter, producing differ­ential outputs at pins IRXP and IRXN, and QRXP and QRXN.
Using the I and Q demodulators for IFs above 50 MHz is pre­cluded by the 10 MHz to 50 MHz range of the PLL used in the
Demodulator section.

The I and Q outputs are differential and can swing up to 2 V p-p
at the low supply voltage of 2.7 V. They are nominally centered
at 1.5 V independent of power supply. They can therefore
directly drive the receive ADCs in the AD7015 or AD6421
baseband converters, which require an amplitude of 1.23 V to
fully load them when driven by a differential signal. The conver­sion gain of the I and Q demodulators is 17 dB.

A simple 1-pole RC filter at the I and Q outputs, with its corner
above the modulation bandwidth is sufficient to attenuate un­desired outputs. The design of the RC filter is eased by the

4.7 kΩ resistor integrated into each I and Q output pin.

Phase-Locked Loop

The demodulators are driven by quadrature signals that are
provided by a variable-frequency quadrature oscillator (VFQO),
phase-locked to the reference frequency. This frequency is equal
or double the frequency of the signal applied to Pin FREF.
When the quadrature signals are at the IF, inphase and quadra­ture baseband outputs are generated at the I output (IRXP
and IRXN) and Q output (QRXP and QRXN), respectively.
The quadrature accuracy of the VFQO is typically within ± 1° at
26 MHz. A simplified diagram of the FREF input is shown in
Figure 32.

FREF

20kΩ

5kΩ

50

VPOS

5kΩ

A PTAT

integral sample-hold system ensures that the frequency­control voltage on Pin FLTR remains held during power­down, so reacquisition of the carrier occurs in less than
80 µs.

In practice, the probability of a phase mismatch at power­up is high, so the worst-case linear settling period to full
lock needs to be considered in making filter choices. This
is typically < 80 µs for a locking error of ±3° at an IF of
26 MHz. Note that the VFQO always provides quadrature
between its own I and Q outputs, but the phasing between
it and the reference carrier will swing around the final value
during the PLL’s settling time.

I and Q Transmit Modulator

The transmit modulator uses two standard mixer cells
whose linear inputs are the differential voltages at the input
Pins ITXP/ITXN and QTXP/QTXN, respectively and whose
local oscillator inputs are derived from a divide-by-two cell,
driven from the input applied to pins LOHI/LOLO. The
outputs of the mixers are summed and converted to single­sided form. The output stage also filters the higher harmon­ics, minimizing the need for filtering before this signal is
presented to the up-converter in a typical transmitter
configuration.

The I and Q inputs are intended to be driven using a
fully-differential drive (for example from an AD7015 or
AD6421) and need to be biased to a common-mode dc
level of 1.2 V, with a typical differential amplitude of
± 1.028 V (that is, ±514 mV at each input). Some small
variation in the drive conditions is allowable, but will result
in nonoptimal performance. The minimum instantaneous
input should not go below 0.6 V and the maximum voltage
should not exceed 1.8 V using a 2.7 V supply (in general,
VP – 0.9 V). The impedance at these inputs is several MΩ
in parallel with approximately 1 pF; the bias currents flow
out of the pins and are ~100 nA. These conditions permit
the use of a high impedance low-pass filter if desired ahead
of the modulator inputs.

The dc modulator output is at a constant dc level of 1.5 V,
independent of temperature and supply voltage. It is de­signed to drive a 150 Ω load and should either be matched
into a 50 Ω load, using a simple LC network, or padded to
150 Ω with a series 100 Ω resistor (Figure 33). The output
is short-circuit-proof. The output modulated signal at pin
MODO has a power of –16 dBm when driving a 50 Ω load
with a 100 Ω series resistor, as shown in Figure 33. This
power is specified at a carrier frequency of 272 MHz with a
maximum dc differential signal applied to the I or Q chan­nel while the other channel has no differential signal ap­plied. The transmit modulator is enabled only when the
TXPU input (Pin 39) is taken HI.

100pF

MODO

100Ω

50Ω

Figure 32. Simplified Schematic of the FREF Interface

The VFQO is controlled by the voltage between V

POS

and
FLTR. In normal operation, a series RC network, forming the
PLL loop filter, is connected from FLTR to V

REV. 0

. The use of an

POS

–13–

Figure 33. Output Impedance of Pin MODO Is

Ω

Designed to Drive a 50

Load with a 100 Ω Series

Resistor

AD6432

Local Oscillator Input

The Local Oscillator (LO) input port is differential and consists
of two functionally identical pins, LOHI and LOLO. It accepts
a signal of 200 mV p-p at a frequency between 200 MHz and
600 MHz. Inputs LOHI and LOLO are internally biased to the
positive supply (Pin 3) through 500 Ω resistors. While not usu­ally needed, these inputs may be driven through a simple match­ing network to lower the LO power required from a 50 Ω source.
Single-sided drives are not recommended. The most noticeable
effects will be degradation of phase balance and an increase in
phase noise.

This signal is fed internally to a divider by two that generates the
mixing signals for the receive mixer and the transmit modulator.
In order to meet the phase and amplitude balance of the trans­mit quadrature modulator, as stated in the specification table,
the duty cycle of the LO signal must be such that the second
harmonic is at least 30 dBc below the fundamental.

I/Q Convention

The AD6432 is a complete IF subsystem. Although not a re­quirement for using the AD6432, most applications will use a
high side LO injection on the receive mixer. The I and Q con­vention on the receive section is such that when a spectrum with
I leading Q is presented to the input of the receive mixer and a
high side LO is presented to the receive mixer, I still leads Q at
the baseband output of the AD6432.

Likewise, the I and Q convention on the transmit section is
such that when a spectrum with I leading Q is presented at the
baseband input of the modulator, I still leads Q at the output of
the modulator.

Auxiliary Op Amp

An auxiliary operational amplifier is available although it is im­portant to remember that it is active only when TXPU is high.
The positive and negative input terminals are PCAP and PCAM
with PCAO being the output pin. The inputs are the bases of
PNP transistors with a typical bias current of approximately
150 nA. The input offset voltage is typically < 4 mV and the
open loop gain of the amplifier is 60 dB. The amplifier is unity
gain stable with a –3 dB Bandwidth greater than 40 MHz. The
input signal voltage range is from 0.1 V to V

Bias System

The AD6432 operates from a single supply, V

– 2.1 V.

POS

, usually 3 V, at

POS

a typical supply current in receive mode of 13 mA at midgain
and T

= +25°C, corresponding to a power consumption of

A

39 mW. Any voltage from 2.7 V to 3.6 V may be used.
The bias system includes a fast-acting active high CMOS-com-

patible power-up switch, allowing the part to idle at less than
100 µA when disabled. Biasing is generally proportional-to-
absolute temperature (PTAT) to ensure stable gain with tem­perature. Other special biasing techniques are used to ensure
very accurate gain, stable over the full temperature range.

USING THE AD6432

In this section, we will focus on a few areas of special impor­tance through the real life example of interfacing the AD6432
to the AD6421 Base Band converter. As is true of any wideband
high gain components, great care is needed in PC board layout.
The location of the particular grounding points must be considered
with due regard for the possibility of unwanted signal coupling.

The high sensitivity of the AD6432 leads to the possibility
that unwanted local EM signals may have an effect on the per­formance. During system development, carefully-shielded test
assemblies should be used. The best solution is to use a fully
enclosed box enclosing all components, with the minimum
number of needed signal connectors (RF, LO, I and Q outputs)
in miniature coax form.

Interfacing the AD6432 to the AD6421 Baseband Converter

The AD6421 Baseband Converter contains all the necessary
elements to drive the AD6432.

Receive Interface

The interface between the two devices provides for quadrature
I and Q channels that can be driven either differentially or in the
single-ended configuration. Figure 35 shows the interface be­tween the AD6432 and the AD6421 for the differential configu­ration. The respective pins (IRXP, IRXN, QRXP and QRXN)
are dc coupled through 4.7 kΩ resistors, which are integrated
within the AD6432. Balanced coupling may be used with a
single 50 pF capacitor between the complementary signals as
illustrated in Figure 35. This low-pass filter is the only external
filter required to prevent aliasing of the baseband analog signal
prior to sampling within the AD6421.

The AD6421 has an external autocalibration mode that can
calibrate out any offsets resulting from the IF demodulation
circuitry.

Transmit Interface

The corresponding transmit (ITXP, ITXN, QTXP and QTXN)
pins of the AD6421 and AD6432 are directly connected as these
have compatible bias levels for dc coupling. To meet the more
stringent phase two filter mask requirements, an external low­pass filter may be required, depending on the filtering capabili­ties of the radio section. A passive second order low-pass
filter network with a cutoff frequency to 600 kHz is suggested
as shown in Figure 34. Resistor values should range from

1.5 kΩ–3.0 kΩ to minimize AD6432 offsets.

ITXP

ITXN

AD6432 AD6421

QTXP

QTXN

ITXP

ITXN

QTXP

QTXN

–14–

Figure 34. GSM Phase II Transmit Interface

REV. 0

AD6432

Gain Control

The AD6432 contains a Gain TC Compensation circuit that
provides a nominal 80 dB dynamic range of automatic gain
control. The GAIN input pin of the gain circuit is driven by
the AD6421 Automatic Gain Control DAC (AGCDAC), an
integrated auxiliary DAC of the AD6421, controllable by the
radio’s digital processor. This connection should be made
through a single pole RC to reduce high frequency noise into
the gain control circuit. The values shown in Figure 35 provide
a –3 dB point at approximately 1 MHz, sufficient for the gain
control.

Gain control scaling is directly proportional to the reference
voltage applied to Pin GREF and is independent of the power
supply voltage. A nominal 1.2 V reference for GREF can be
provided by the AD6421 through BREFOUT. BREFOUT is
a buffered output version of BREFCAP reference. This refer­ence output feature is enabled on the AD6421 by setting Bit 2
in control register BCRB (BCRB2). See AD6421 data sheet.

The V
gain is maximum at 0.2 V and falls off as V

input range for this control signal is 0.2 V– 2.4 V where

GAIN

is increased to

GAIN

2.4 V. To avoid saturating the input to the baseband converter,
the automatic gain control function of the receiver must limit
the output signal swing of the AD6432 to ±1.2 V, the full signal
range of the input.

Phase-Lock Loop Control

The AD6432 PLL/QVCO circuits require an external frequency
reference for coherent modulation and demodulation of the
baseband and IF signal. The external frequency reference con­trol for the AD6432 PLL/QVCOs is typically generated through
a 13 MHz voltage controlled temperature compensated crystal
oscillator (VCTCXO). The control voltage for the VCTCXO is
generated by an auxiliary DAC in the AD6421 designated as
the Automatic Frequency Control DAC (AFCDAC). The PLL
loop is closed through the radio’s algorithm signal processor,
which drives the AD6421 AFCDAC.

The AD6432 FREF pin provides the VCTCXO reference sig­nal to the AD6432 RX quadrature VCO (QVCO) circuit.
The AD6432 FREF input must be an ac coupled signal
200 mV p-p or greater. The reference for the UHF TX QVCO
and RX IF down converter is synthesized from the VCTCXO
output reference signal through an external frequency synthe­sizer and VCO. This UHF reference is an ac coupled input into
AD6432 LOHI and LOLO pins.

An external series RC network connected between FLTR (Pin

29) and the VPOS supply pin provides the proper loop filter for
the VCO/PLL as shown in Figure 35.

AD6432

MXHI

MXLO

BAND-

PASS

FILTER

ITXP

ITXN

QTXP

QTXN

IRXP

IRXN
QRXP
QRXN

IFLO

IFHI

1nF

FREQUENCY

SYNTHESIZER

1nF

FREF

LOHI

LOLO
GREF

GAIN

LC

50pF

50pF

VCTCXO

160Ω

POWER CONTROL

100nF

0.1

1kΩ

ITXP
ITXN
QTXP
QTXN
IRXP
IRXN

AD6421

QRXP
QRXN
MCLK
AFCDAC
BREFCAP

F

BREFOUT
AGCDAC
RAMDAC

Figure 35. AD6432 to AD6421 Interface

Transmit Power Control

A general purpose amplifier is available on the AD6432, which
may be useful as part of an automatic control circuit for the
power amplifier. Open ended, this amplifier will swing full scale
from rail to rail. It is recommended that this amplifier be con­nected in the unity feedback configuration when not being used
by connecting PCAO to PCAM.

AD6432 EVALUATION BOARD

The AD6432 Evaluation Board is designed to enable measure­ments of key parameters on the AD6432 IFIC, a device that
provides the complete transmit and receive IF signal processing,
including I/Q modulation and demodulation, necessary to imple­ment a digital wireless transceiver.

Many of the signal paths into and out of the AD6432 are differ­ential, which is the preferred interface to and from single supply
CODECS. To facilitate an interface to traditional lab equip­ment, the following interface circuitry is included on the board.

A 20-pin Berg strip for bias, gain and Inphase and Quadrature
signal interface. End Launch SMA connectors for RF, LO,
MODO and FREF signals and provisions for breaking out
MXOP and IFHI with RF transformers.

A single-ended to differential RF transformer provides a bal­anced LO drive.

An onboard 1.2 V dc reference IC is provided for application to
GREF.

REV. 0

–15–

AD6432

Evaluation Board Description

This four layer board demonstrates both the transmit and
receive functions of the AD6432. The top internal layer is a
ground plane and the bottom internal layer is a strategically
partitioned power plane with DUT power and bipolar support
device power.

A 20-pin Berg strip connector provides the external power and
dc signal interface, which includes power-up, gain and external
reference bias options. The various high frequency IF, LO, TX
Modulation output (MODO) and the Demodulator Reference
(FREF) are brought in and out of the board via end-launch
SMA connectors. Appropriate terminations are provided for
each signal. Several hardware jumpers are provided for bias and
IF selection options. Figure 36 shows the placement of the
different connectors used on the evaluation board.

FREFMODO

LOINP

OPTLO

RFHI

AD6432 EVAL.
REV. B

U1

T1

MXOP IFIP

J23

Q1

J22

J21

1

J26
J24

J25

INTERFACE CONNECTOR

Interface Connector (Berg Strip) Pin Description

Building up a simple IDC connector/ribbon cable breakout to a
vector board or box with banana plugs will facilitate testing.
Figure 37 shows the signal’s placement and Table II describes
each signal.

GND

ITXP

ITXN

QTXP

QTXN

TXPU

PCAM

PCAP

VS2

VS1

PCAO

GND

IFS0

IRXP

IRXN

QRXP

QRXN

GREF

GAIN

RXPU

BOARD

EDGE

Figure 37. Evaluation Board Interface Connector

Figure 36. Evaluation Board Layout (Top View)

Note: MXOP, IFHI, OPTLO are optional SMA connectors not
supplied with the evaluation board.

–16–

REV. 0

AD6432

Table II. Connector Signal Description

Pin
Name Description

GND Analog and Power Ground.
ITXP I Channel Transmit Plus Modulation Input.
ITXN I Channel Transmit Minus Modulation Input.
QTXP Q Channel Transmit Plus Modulation Input.
QTXN Q Channel Transmit Minus Input.
TXPU Transmit Section Power-Up. This function is

also jumper selectable with J21.

PCAM Auxiliary Op Amp Minus Input.
PCAP Auxiliary Op Amp Plus Input.
VS2 Power control op amp supply 2.7 V dc–3.6 V dc.

The jumper, J26, connects VS1 and VS2 together.
VS1 AD6432 main supply 2.7 V dc–3.6 V dc.
PCAO Auxiliary Op Amp Output.
IFS0 Selects IF Pin. This function is also jumper pro-

grammable with J25.
IRXP I Channel Receive Plus Modulation Output.
IRXN I Channel Receive Minus Modulation Output.
QRXP Q Channel Receive Plus Modulation Output.
QRXN Q Channel Receive Plus Modulation Output.
GREF The AD6432 gain reference bias which is optimized

for 1.2 V dc. This may be externally supplied; or by

shorting J23, supplied directly from the AD1580

SOT-23 onboard, 1.2 V reference.
GAIN Max RX gain occurs at 0.2 V dc. Minimum gain

occurs at 2.4 V dc.
RXPU Receive Section Power-Up. This function is also

jumper selectable with J22.

Table III. SMA End-Launch Connectors

SMA Connector Description

MODO Transmit Modulator Output. This pin, which is

designed to drive a 150 Ω filter, has been resistively
matched (loss) onboard to drive a 50 Ω instrument
such as a spectrum analyzer.

LOIP Local Oscillator Input pin. This is actually fed with

twice the LO frequency from a generator for both
transmit and receive. The nominal LO level is
–16 dBm (50 Ω).

OPTLO Optional differential minus local oscillator input

(transformer can be removed).
RFHI RF input
MXOP Mixer Output (optional output that may be converted

to single ended output with an RF transformer).
IFHI IF Input (optional single ended input that may be

converted to differential with an RF transformer).
FREF Frequency Reference for phase locked receive de-

modulator. The internal VCO frequency is equal to

FREF in the 1X mode and equal to two times FREF

in the 2X mode.

Power Requirements

The evaluation board uses two supplies, VS1 and VS2.
VS1—2.7 V dc–3.6 V dc, 13 mA typical. This is the main sup-

ply for the AD6432.
VS2—2.7 V dc–3.6 V dc, 2 mA typical. This is the supply for

the on-chip op amp which is normally used in RF power control
circuits.

The op amp is active only in the Transmit mode.

REV. 0

–17–

AD6432

J21

VS1

R19

20kΩ

TXPU

PCAP

R30
1kΩ

OPTLO

C50

4.7

MODO

LOIP

F

C12

4.7

DECOUPLING

R20

OPEN

F

VS1

R21

0Ω

ITXP

ITXN
QTXP
QTXP

TXPU

PCAM

PCAP

PCAO

GND

IFS0
IRXP
IRXN

QRXP
QRXN

GREF

GAIN

RXPU

VPDV

6

4

GND

VS2
VS1

QTXN
QTXP

ITXN
ITXP

VS1

DECOUPLING

C29

0.1

T1

1

125Ω

2

3

125Ω

RFHI

TX

20B

20A

R35

R14

VPTX

R2
0Ω

F

C18

0.1

R3

49.9Ω

C28

0.1

R9
84Ω

C14

0.01

F

C1

100pF

VS1

R12

0Ω

F

F

100pF

0.1

MXOP

R39

OPEN

R8
0Ω

GREF

J23

F

C36
1nF

C10
1nF

R34

VS1

0Ω

R1

1kΩ

R16
10kΩ

C32

0.1

VS2

F

IFS1

IFS0

C8
47pF

TP1580

J26

Q1

VS1

C6
47pF

C41

0.01

R18

20kΩ

R17
20kΩ

J25

R6
0Ω

PCAO

FREF

J24

R7
0Ω

C23

0.01

C17

0.1

F

VS1

F

F

IRXP

IRXN

QRXP

QXRN

R25
1kΩ

C5

0.01

F

R23
123Ω

VPTX

ITXP

ITXN

QTXP

QTXN

TXPU

PCAP

PCAM

IFHI

RXPU

37

CMIF

20

RXPU

GAIN

GND

GAIN

C15
100pF

1

GND

2

MODO

3

VPDV

4

CMTX

5

LOLO

6

LOHI

7

CMRX

GND

8

9

RFLO

10

C2

RFHI

GND

11

121314 15 16 17 18 19

VPRX

R31

0Ω

C30

F

C3

0.01

F

40 39 3841424344 363534

AD6432

TOP VIEW

(Pins Down)

IFLO

CMIF

MXHI

MXLO

J22

R15
20kΩ

PCAO

21 22

GREF

C21

0.1

VPPC

GND

F

0.01

33
32
31
30
29
28
27
26
25
24
23

C11

F

FREF
GND
IFS0
CMDM
FLTR
VPFL
VPDM
IRXP
IRXN
QRXP
QRXN

C44

0.01

VS1

C16

L2

PCAM

22pF

C20

C19

L3

22pF

82pF

L4

0.39

R13
OPEN

H

C43

F

0.01

123

T3

IFIP

46

OPEN

R6

123

T2

SHORT

0.01

C42

L1
OPEN

F

C18
OPEN

SHORT

46

Figure 38. Evaluation Board Schematics

–18–

REV. 0

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

44-Lead Plastic Thin Quad Flatpack (TQFP)

(ST-44)

0.063 (1.60)

0.030 (0.75)

0.018 (0.45)

SEATING

PLANE

MAX

33

34

0.472 (12.00) SQ

TOP VIEW

(PINS DOWN)

23

22

0.394

(10.0)

AD6432

SQ

0.006 (0.15)

0.002 (0.05)

0.057 (1.45)

0.053 (1.35)

44

1

0.031 (0.80)
BSC

12

11

0.018 (0.45)

0.012 (0.30)

REV. 0

–19–

C3061–12–4/97

–20–

PRINTED IN U.S.A.