Datasheet AD633 Datasheet (ANALOG DEVICES)

Low Cost

Y1Y

Data Sheet

FEATURES

4-quadrant multiplication
Low cost, 8-lead SOIC and PDIP packages
Complete—no external components required
Laser-trimmed accuracy and stability
Total error within 2% of full scale
Differential high impedance X and Y inputs
High impedance unity-gain summing input
Laser-trimmed 10 V scaling reference

APPLICATIONS

Multiplication, division, squaring
Modulation/demodulation, phase detection
Voltage-controlled amplifiers/attenuators/filters

GENERAL DESCRIPTION

The AD633 is a functionally complete, four-quadrant, analog
multiplier. It includes high impedance, differential X and Y inputs,
and a high impedance summing input (Z). The low impedance
output voltage is a nominal 10 V full scale provided by a buried
Zener. The AD633 is the first product to offer these features in
modestly priced 8-lead PDIP and SOIC packages.

The AD633 is laser calibrated to a guaranteed total accuracy of
2% of full scale. Nonlinearity for the Y input is typically less
than 0.1% and noise referred to the output is typically less than
100 μV rms in a 10 Hz to 10 kHz bandwidth. A 1 MHz bandwidth,
20 V/μs slew rate, and the ability to drive capacitive loads make
the AD633 useful in a wide variety of applications where
simplicity and cost are key concerns.

The versatility of the AD633 is not compromised by its simplicity.
The Z input provides access to the output buffer amplifier, enabling
the user to sum the outputs of two or more multipliers, increase
the multiplier gain, convert the output voltage to a current, and
configure a variety of applications.

Analog Multiplier

AD633

FUNCTIONAL BLOCK DIAGRAM

X1
X2

The AD633 is available in 8-lead PDIP and SOIC packages. It is
specified to operate over the 0°C to 70°C commercial temperature
range (J Grade) or the −40°C to +85°C industrial temperature
range (A Grade).

PRODUCT HIGHLIGHTS

1. The AD633 is a complete four-quadrant multiplier offered

in low cost 8-lead SOIC and PDIP packages. The result is a
product that is cost effective and easy to apply.

2. No external components or expensive user calibration are

required to apply the AD633.

3. Monolithic construction and laser calibration make the

device stable and reliable.

4. High (10 MΩ) input resistances make signal source

loading negligible.

5. Power supply voltages can range from ±8 V to ±18 V. The

internal scaling voltage is generated by a stable Zener diode;
multiplier accuracy is essentially supply insensitive.

1

A

1

10V

1

2

Figure 1.

W

Z

00786-023

Rev. I

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Tel: [phone] www.analog.com
Fax: [phone] ©2012 Analog Devices, Inc. All rights reserved.

AD633 Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1 

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Absolute Maximum Ratings ............................................................ 4

Thermal Resistance ...................................................................... 4

ESD Caution .................................................................................. 4

Pin Configurations and Function Descriptions ........................... 5

Typical Performance Characteristics ............................................. 6

Functional Description .................................................................... 7

Error Sources ................................................................................. 7

Applications Information .................................................................8

Multiplier Connections ................................................................8

Squaring and Frequency Doubling .............................................8

Generating Inverse Functions .....................................................8

Variable Scale Factor .....................................................................9

Current Output ..............................................................................9

Linear Amplitude Modulator ......................................................9

Voltage-Controlled, Low-Pass and High-Pass Filters ...............9

Voltage-Controlled Quadrature Oscillator ................................... 10

Automatic Gain Control (AGC) Amplifiers ........................... 10

Outline Dimensions ....................................................................... 14

Ordering Guide .......................................................................... 15

REVISION HISTORY

2/12—Rev. H to Rev. I

Changes to Figure 1 .......................................................................... 1

Changes to Figure 2 .......................................................................... 5

Changes to Generating Inverse Functions Section ...................... 8

Changes to Figure 15 ........................................................................ 9

Added Evaluation Board Section and Figure 23 to Figure 29,

Renumbered Sequentially .............................................................. 12

Changes to Ordering Guide .......................................................... 15

4/11—Rev. G to Rev. H

Changes to Figure 1, Deleted Figure 2 ........................................... 1

Added Figure 2, Figure 3, Table 4, Table 5 .................................... 5

Deleted Figure 9, Renumbered Subsequent Figures .................... 6

Changes to Figure 15 ........................................................................ 9

4/10—Rev. F to Rev. G

Changes to Equation 1 ...................................................................... 6

Changes to Equation 5 and Figure 14 ............................................. 7

Changes to Figure 21 ......................................................................... 9

10/09—Rev. E to Rev. F

Changes to Format ............................................................. Universal

Changes to Figure 21 ......................................................................... 9

Updated Outline Dimensions ....................................................... 11

Changes to Ordering Guide .......................................................... 12

10/02—Rev. D to Rev. E

Edits to Title of 8-Lead Plastic SOIC Package (RN-8) ................. 1

Edits to Ordering Guide ................................................................... 2

Change to Figure 13 .......................................................................... 7

Updated Outline Dimensions .......................................................... 8

Rev. I | Page 2 of 16

Data Sheet AD633

( )( )

Z

Y2Y1X2X1

W +

−−

=

V10

T

to T

±3 % full scale

SPECIFICATIONS

TA = 25°C, VS = ±15 V, RL ≥ 2 kΩ.

Table 1.

AD633J, AD633A
Parameter Conditions Min Typ Max Unit

TRANSFER FUNCTION

MULTIPLIER PERFORMANCE

Total Error −10 V ≤ X, Y ≤ +10 V ±1 ±21 % full scale

MIN

MAX

Scale Voltage Error SF = 10.00 V nominal ±0.25% % full scale
Supply Rejection VS = ±14 V to ±16 V ±0.01 % full scale
Nonlinearity, X X = ±10 V, Y = +10 V ±0.4 ±11 % full scale
Nonlinearity, Y Y = ±10 V, X = +10 V ±0.1 ±0.41 % full scale
X Feedthrough Y nulled, X = ±10 V ±0.3 ±11 % full scale
Y Feedthrough X nulled, Y = ±10 V ±0.1 ±0.41 % full scale
Output Offset Voltage ±5 ±501 mV

DYNAMICS

Small Signal Bandwidth VO = 0.1 V rms 1 MHz
Slew Rate VO = 20 V p-p 20 V/µs
Settling Time to 1% ΔVO = 20 V 2 µs

OUTPUT NOISE

Spectral Density 0.8 µV/√Hz
Wideband Noise f = 10 Hz to 5 MHz 1 mV rms

f = 10 Hz to 10 kHz 90 µV rms

OUTPUT

Output Voltage Swing ±111 V
Short Circuit Current RL = 0 Ω 30 401 mA

INPUT AMPLIFIERS

Signal Voltage Range Differential ±101 V
Common mode ±101 V
Offset Voltage (X, Y ) ±5 ±301 mV
CMRR (X, Y) VCM = ±10 V, f = 50 Hz 601 80 dB
Bias Current (X, Y, Z) 0.8 2.01 µA
Differential Resistance 10 MΩ

POWER SUPPLY

Supply Voltage

Rated Performance ±15 V
Operating Range ±81 ±181 V

Supply Current Quiescent 4 61 mA

1

This specification was tested on all production units at electrical test. Results from those tests are used to calculate outgoing quality levels. All minimum and maximum

specifications are guaranteed; however, only this specification was tested on all production units.

Rev. I | Page 3 of 16

AD633 Data Sheet

Internal Power Dissipation

500 mW

AD633A

−40°C to +85°C

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

Supply Voltage ±18 V

Input Voltages1 ±18 V
Output Short-Circuit Duration Indefinite
Storage Temperature Range −65°C to +150°C
Operating Temperature Range

AD633J 0°C to 70°C

Lead Temperature (Soldering, 60 sec) 300°C
ESD Rating 1000 V

1

For supply voltages less than ±18 V, the absolute maximum input voltage is

equal to the supply voltage.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.

Table 3.

Package Type θJA Unit

8-Lead PDIP 90 °C/W
8-Lead SOIC 155 °C/W

ESD CAUTION

Rev. I | Page 4 of 16

Data Sheet AD633

AD633JN/AD633AN

1

1

A

1

10V

1

X1

2X2

3

Y1

4Y2

8 +V

S

7 W

Z

6

5 –V

S

00786-001

W = + Z

(X1 – X2)(Y1 – Y2)

10V

AD633JR/AD633AR

1

1

1

10V

1

Y1

2

Y2

3

–V

S

4Z

8 X2

7 X1

+V

S

6

5 W

00786-002

A

W = + Z

(X1 – X2)(Y1 – Y2)

10V

2

X2

X Multiplicand Inverting Input

7 W Product Output

2

Y2

Y Multiplicand Inverting Input

7

X1

X Multiplicand Noninverting Input

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

Figure 2. 8-Lead PDIP

Table 4. 8-Lead PDIP Pin Function Descriptions

Pin No. Mnemonic Description

1 X1 X Multiplicand Noninverting Input

3 Y1 Y Multiplicand Noninverting Input
4 Y2 Y Multiplicand Inverting Input
5 −VS Negative Supply Rail
6 Z Summing Input

8 +VS Positive Supply Rail

Figure 3. 8-Lead SOIC

Table 5. 8-Lead SOIC Pin Function Descriptions

Pin No. Mnemonic Description

1 Y1 Y Multiplicand Noninverting Input

3 −VS Negative Supply Rail
4 Z Summing Input
5 W Product Output
6 +VS Positive Supply Rail

8 X2 X Multiplicand Inverting Input

Rev. I | Page 5 of 16

AD633 Data Sheet

FREQUENCY (Hz)

OUTPUT RESPONSE (dB)

0

–10

–20

–30

10k 100k 1M 10M

00786-003

NORMAL

CONNECTION

0dB = 0.1V rms, RL = 2kΩ

C

L

= 1000pF

C

L

= 0dB

TEMPERATURE (°C)

BIAS CURRENT (nA)

700

500

600

400

300

200

–60 –40 –20 0 14012010080604020

00786-004

PEAK POSITIVE OR NEGATIVE SUPPLY (V)

PEAK POSITIVE OR NEGATIVE SIGNAL (V)

14

10

12

8

6

4

8 10 12 14 201816

00786-005

OUTPUT, R

L

≥ 2kΩ

ALL INPUTS

FREQUENCY (Hz)

CMRR (dB)

100

60

50

90

80

70

40

30

20

100 1k 1M

100k10k

00786-006

TYPICAL
FOR X, Y
INPUTS

FREQUENCY (Hz)

NOISE SPECTRAL DENSITY (µV/ Hz)

1.5

1.0

0.5

0

10 100 1k 100k10k

00786-007

FREQUENCY (Hz)

PEAK-TO-PE AK FEEDTHROUGH (mV)

1k

10

100

1

0.1
10 100 1k 10M10k 100k 1M

00786-008

Y-FEEDTHROUGH

X-FEEDTHROUGH

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 4. Frequency Response

Figure 7. CMRR vs. Frequency

Figure 5. Input Bias Current vs. Temperature (X, Y, or Z Inputs)

Figure 6. Input and Output Signal Ranges vs. Supply Voltages

Figure 8. Noise Spectral Density vs. Frequency

Figure 9. AC Feedthrough vs. Frequency

Rev. I | Page 6 of 16

Data Sheet AD633

( )( )

Z

V

Y2Y1X2X1

W +

−−

=

10

±50mV
TO APPROPRIATE
INPUT TERM INAL
(FOR EXAMPLE, X2, Y2, Z)

50kΩ

1kΩ

300kΩ

+V

S

–V

S

00786-010

FUNCTIONAL DESCRIPTION

The AD633 is a low cost multiplier comprising a translinear
core, a buried Zener reference, and a unity-gain connected
output amplifier with an accessible summing node. Figure 1
shows the functional block diagram. The differential X and Y
inputs are converted to differential currents by voltage-to­current converters. The product of these currents is generated
by the multiplying core. A buried Zener reference provides an
overall scale factor of 10 V. The sum of (X × Y)/10 + Z is then
applied to the output amplifier. The amplifier summing node Z
allows the user to add two or more multiplier outputs, convert
the output voltage to a current, and configure various analog
computational functions.

Inspection of the block diagram shows the overall transfer
function is

(1)

ERROR SOURCES

Multiplier errors consist primarily of input and output offsets,
scale factor error, and nonlinearity in the multiplying core. The
input and output offsets can be eliminated by using the optional
trim of Figure 10. This scheme reduces the net error to scale
factor errors (gain error) and an irreducible nonlinearity
component in the multiplying core. The X and Y nonlinearities
are typically 0.4% and 0.1% of full scale, respectively. Scale
factor error is typically 0.25% of full scale. The high impedance
Z input should always reference the ground point of the driven
system, particularly if it is remote. Likewise, the differential X
and Y inputs should reference their respective grounds to
realize the full accuracy of the AD633.

Figure 10. Optional Offset Trim Configuration

Rev. I | Page 7 of 16

AD633 Data Sheet

V

V





V



APPLICATIONS INFORMATION

The AD633 is well suited for such applications as modulation
and demodulation, automatic gain control, power measurement,
voltage-controlled amplifiers, and frequency doublers. These
applications show the pin connections for the AD633JN (8-lead
PDIP), which differs from the AD633JR (8-lead SOIC).

MULTIPLIER CONNECTIONS

Figure 11 shows the basic connections for multiplication. The X
and Y inputs normally have their negative nodes grounded, but
they are fully differential, and in many applications, the grounded
inputs may be reversed (to facilitate interfacing with signals of a
particular polarity while achieving some desired output polarity),
or both may be driven.

+15

0.1µF

8

+V

X1

1

+

X

INPUT

Y

INPUT

X2

2

–

+

–

AD633JN

Y1

3

Y2

4

Figure 11. Basic Multiplier Connections

SQUARING AND FREQUENCY DOUBLING

As is shown in Figure 12, squaring of an input signal, E, is
achieved simply by connecting the X and Y inputs in parallel to
produce an output of E
but the output is positive. However, the output polarity can be
reversed by interchanging the X or Y inputs. The Z input can be
used to add a further signal to the output.

E

Figure 12. Connections for Squaring

When the input is a sine wave E sin ωt, this squarer behaves as a
frequency doubler, because

2

tE



sin

V

Equation 2 shows a dc term at the output that varies strongly
with the amplitude of the input, E. This can be avoided using
the connections shown in Figure 13, where an RC network is
used to generate two signals whose product has no dc term. It
uses the identity

sincos 

S

W

7

Z

6

5

–V

S

0.1µF

–15V

2

/10 V. The input can have either polarity,

8

+V

X1

1

2

X2

AD633JN

3

Y1

Y2

4

2

E

V

2010

1



2

S

W

7

6

Z

5

–V

S

–15V



θθθ 2sin



2cos1

(3)

(X1 – X2)(Y1 – Y 2)

W = + Z

OPTIONAL SUMMING
INPUT, Z

+15

0.1µF

0.1µF

(2)

t

W =

10V

10V

00786-011

2

E

00786-012

+15

X1

X2

AD633JN

Y1

Y2

+V

W

–V

E

R

C

1

2

3

4

0.1µF

8

S

7

R1

1kΩ

6

Z

5

S

0.1µF

–15V

R2
3kΩ

W =

E

10V

2

00786-013

Figure 13. Bounceless Frequency Doubler

At ωo = 1/CR, the X input leads the input signal by 45° (and is
attenuated by √2), and the Y input lags the X input by 45° (and
is also attenuated by √2). Because the X and Y inputs are 90° out of
phase, the response of the circuit is (satisfying Equation 3)

1

W



10

V

2

E



V

E

t

2



(4)

t

2sin40

0

E

 

45sin

2

 45sin

t

00

which has no dc component. Resistors R1 and R2 are included
to restore the output amplitude to 10 V for an input amplitude
of 10 V.

The amplitude of the output is only a weak function of frequency;
the output amplitude is 0.5% too low at ω = 0.9 ω

and ω0 = 1.1 ω0.

0

GENERATING INVERSE FUNCTIONS

Inverse functions of multiplication, such as division and square
rooting, can be implemented by placing a multiplier in the feedback
loop of an op amp. Figure 14 shows how to implement square
rooting with the transfer function for the condition E < 0.

The 1N4148 diode is required to prevent latchup, which can
occur in such applications if the input were to change polarity,
even momentarily.



VEW 10

(5)

10kΩ

+15V

W

S

Z

S

W =

8

7

6

5

0.1µF

1N4148

10V)E

–15V

0.1µF

000786-014

+V

–V

E < 0V

+15V

1

2

6

3

4

10kΩ

2

3

AD711

–15V

0.1µF

7

4

0.1µF

Figure 14. Connections for Square Rooting

X1

X2

AD633JN

Y1

Y2

Rev. I | Page 8 of 16

Data Sheet AD633

( )

X

E

E

VW 10−=

′

AD633JN

X1

1

X2

2

Y1

3

Y2

4

+V

S

8

W

7

Z

6

–V

S

5

0.1µF

0.1µF

+15V

0.1µF

+15V

0.1µF

–15V

–15V

00786-015

7

4

3

6

2

AD711

E

R

10kΩ

R

10kΩ

E

X

W' = –10V

E

E

X

AD633JN

X1

1

X2

2

Y1

3

Y2

4

+V

S

8

W

7

Z

6

–V

S

5

0.1µF

0.1µF

+15V

–15V

W =

00786-016

S

R1

R2

1kΩ ≤ R1, R2 ≤ 100kΩ

+ S

(X1 – X2)(Y1 – Y2)

10V

R1 + R2

R1

X

INPUT

Y

INPUT

+

–

+

–

AD633JN

X1

1

X2

2

Y1

3

Y2

4

+V

S

8

W

7

Z

6

–V

S

5

0.1µF

0.1µF

+15V

–15V

I

O

=

1
R

00786-017

(X1 – X2)(Y1 – Y2)

10V

1kΩ ≤ R ≤ 100kΩ

R

X

INPUT

Y

INPUT

+

–

+

–

( )( )

V

Y2Y1X2X1

R

I

O

10

1 −−

=

AD633JN

X1

MODULATION

INPUT

±E

M

CARRIER

INPUT

E

C

sin ωt

1

X2

2

Y1

3

Y2

4

+V

S

8

W

7

Z

6

–V

S

5

+

–

0.1µF

0.1µF

+15V

–15V

W = E

C

sin ωt

00786-018

E

M

10V

1+

( )

RCV

E

f

C

2

π

=

20

AD633JN

X1

1

X2

2

Y1

3

Y2

4

+V

S

8

W

7

Z

6

–V

S

5

CONTROL

INPUT E

C

SIGNAL

INPUT E

S

0.1µF

0.1µF

+15V

–15V

00786-019

R

C

1 + T

1

P

1 + T

2

P

OUTPUT B =

1

1 + T

2

P

OUTPUT A =

1

W

1

T1 = = R

C

1

W

2

10

ECR

C

T2 = =

dB

f

2f1

f

–6dB/OCTAVE

OUTPUT A

OUTPUT B

0

RCfπ=2

1

1

Likewise, Figure 15 shows how to implement a divider using a
multiplier in a feedback loop. The transfer function for the
divider is

This arrangement forms the basis of voltage-controlled integrators
and oscillators as is shown later in this section. The transfer
function of this circuit has the form

(6)

Figure 15. Connections for Division

VARIABLE SCALE FACTOR

In some instances, it may be desirable to use a scaling voltage
other than 10 V. The connections shown in Figure 16 increase
the gain of the system by the ratio (R1 + R2)/R1. This ratio is
limited to 100 in practical applications. The summing input, S,
can be used to add an additional signal to the output, or it can
be grounded.

(7)

LINEAR AMPLITUDE MODULATOR

The AD633 can be used as a linear amplitude modulator with no
external components. Figure 18 shows the circuit. The carrier
and modulation inputs to the AD633 are multiplied to produce
a double sideband signal. The carrier signal is fed forward to the
Z input of the AD633 where it is summed with the double
sideband signal to produce a double sideband with the carrier
output.

Figure 18. Linear Amplitude Modulator

VOLTAGE-CONTROLLED, LOW-PASS AND HIGH­PASS FILTERS

Figure 19 shows a single multiplier used to build a voltage­controlled, low-pass filter. The voltage at Output A is a result
of filtering, E
input. The break frequency, f

. The break frequency is modulated by EC, the control

S

, equals

2

Figure 16. Connections for Variable Scale Factor

CURRENT OUTPUT

The voltage output of the AD633 can be converted to a current
output by the addition of a resistor, R, between the W and Z pins of
the AD633 as shown in Figure 17.

Figure 17. Current Output Connections

and the roll-off is 6 dB per octave. This output, which is at a
high impedance point, may need to be buffered.

The voltage at Output B, the direct output of the AD633, has the

Rev. I | Page 9 of 16

same response up to frequency f
filter, and then levels off to a constant attenuation of f

(8)

Figure 19. Voltage-Controlled, Low-Pass Filter

, the natural breakpoint of RC

1

= EC/10.

1/f2

(9)

AD633 Data Sheet

AD633JN

X1

1

X2

2

Y1

3

Y2

4

+V

S

8

W

7

Z

6

–V

S

5

CONTROL

INPUT E

C

SIGNAL

INPUT E

S

0.1µF

0.1µF

+15V

–15V

00786-020

R

C

OUTPUT B

OUTPUT A

dB

f1f

2

f

+6dB/OCTAVE

OUTPUT A

OUTPUT B

0

AD633JN

X1

1

X2

2

Y1

3

Y2

4

+V

S

8

W

7

Z

6

–V

S

5

0.1µF

0.1µF

C1

0.01µF

+15V

–15V

AD633JN

X1

1

X2

2

Y1

3

Y2

4

+V

S

8

W

7

Z

6

–V

S

5

0.1µF

+15V

–15V

R5

16kΩ

R3

330kΩ

R4

16kΩ

C3

0.01µF

C2

0.01µF

(10V) sin ωt

0.1µF

R2

16kΩ

R1

1kΩ

D5

1N5236

D1

1N914

D2

1N914

D3
1N914

D4
1N914

f =

E

C

10V

= kHz

(10V) cos ωt

E

C

00786-021

For example, if R = 8 kΩ and C = 0.002 µF, the n Output A has a
pole at frequencies from 100 Hz to 10 kHz for E

ranging from

C

100 mV to 10 V. Output B has an additional 0 at 10 kHz (and
can be loaded because it is the low impedance output of the
multiplier). The circuit can be changed to a high-pass filter Z
interchanging the resistor and capacitor as shown in Figure 20.

Figure 20. Voltage-Controlled, High-Pass Filter

VOLTAGE-CONTROLLED QUADRATURE OSCILLATOR

Figure 21 shows two multipliers being used to form integrators
with controllable time constants in second-order differential
equation feedback loop. R2 and R5 provide controlled current
output operation. The currents are integrated in capacitors C1
and C2, and the resulting voltages at high impedance are applied
to the X inputs of the next AD633. The frequency control input,

E

, connected to the Y inputs, varies the integrator gains with a

C

calibration of 100 Hz/V. The accuracy is limited by the Y input
offsets. The practical tuning range of this circuit is 100:1. C2
(proportional to C1 and C3), R3, and R4 provide regenerative
feedback to start and maintain oscillation. The diode bridge, D1
through D4 (1N914s), and Zener diode D5 provide economical
temperature stabilization and amplitude stabilization at ±8.5 V
by degenerative damping. The output from the second integrator
(10 V sin ωt) has the lowest distortion.

AUTOMATIC GAIN CONTROL (AGC) AMPLIFIERS

Figure 22 shows an AGC circuit that uses an rms-to-dc
converter to measure the amplitude of the output waveform.
The AD633 and A1, ½ of an AD712 dual op amp, form a
voltage-controlled amplifier. The rms-to-dc converter, an
AD736, measures the rms value of the output signal. Its output
drives A2, an integrator/comparator whose output controls the
gain of the voltage-controlled amplifier. The 1N4148 diode
prevents the output of A2 from going negative. R8, a 50 kΩ
variable resistor, sets the output level of the circuit. Feedback
around the loop forces the voltages at the inverting and
noninverting inputs of A2 to be equal, thus the AGC.

Figure 21. Voltage-Controlled Quadrature Oscillator

Rev. I | Page 10 of 16

Data Sheet AD633

AD633JN

X1

1

X2

2

Y1

3

Y2

4

+V

S

8

W

7

Z

6

–V

S

5

0.1µF

0.1µF

+15V

–15V

A1

0.1µF

0.1µF

0.1µF

+15V

+15V

+15V

–15V

8

3

1

2

1/2

AD712

AGC THRESHO LD

ADJUSTMENT

R2

1kΩR310kΩR410kΩ

C3

0.2µF

R10

10kΩ

R9

10kΩ

R8

50kΩ

1/2

AD712

A2

0.1µF

–15V

4

5

7

6

C2

0.02µF

C4

33µF

C1

1µF

1N4148

AD736

C

C

1

V

IN

2

C

F

3

–V

S

4

+V

S

8

COMMON

OUTPUT

7

6

C

AV

5

OUTPUT
LEVEL
ADJUST

R5

10kΩ

R6

1kΩ

E

OUT

E

00786-022

Figure 22. Connections for Use in Automatic Gain Control Circuit

Rev. I | Page 11 of 16

AD633 Data Sheet

00786-024

00786-026

00786-027

00786-028

EVALUATION BOARD

The evaluation board of the AD633 enables simple bench-top
experimenting to be performed with easy control of the
AD633. Built-in flexibility allows convenient configuration
to accommodate most operating configurations. Figure 23 is
a photograph of the AD633 evaluation board.

Figure 23. AD633 Evaluation Board

Any dual-polarity power supply capable of providing 10 mA
or greater is all that is required, in addition to whatever test
equipment the user wishes to perform the intended tests.

Referring to the schematic in Figure 30, inputs to the multiplier are
differential and dc-coupled. Three-position slide switches enhance
flexibility by enabling the multiplier inputs to be connected to
an active signal source, to ground, or to a test loop connected
directly to the device pin for direct measurements, such as bias
current. Inputs may be connected single ended or differentially,
but must have a dc path to ground for bias current. If an input
source’s impedance is non-zero, an equal value impedance must
be connected to the opposite polarity input to avoid introducing
additional offset voltage.

The AD633-EVALZ can be configured for multiplier or divider
operation by switch S1. Refer to Figure 15 for divider circuit
connections.

Figure 24 through Figure 27 are the signal, power, and ground­plane artworks, and Figure 28 shows the component and circuit
side silkscreen. Figure 29 shows the assembly.

Figure 24. Component Side Copper

Figure 25. Circuit Side Copper

Figure 26. Inner Layer Ground Plane

Rev. I | Page 12 of 16

Data Sheet AD633

00786-029

00786-030

00786-031

+

+

X2
X1

+V

S

W

Y1
Y2
–V

S

Z

Z1

1

AD633ARZ

C6
10µF
25V

C2

0.1µF

C3

0.1µF

C4

0.1µF

C5

10µF

25V

1

3

2

4

7

6

2
3

4

8

7
6

5

C1

0.1µF

GND

R2

10kΩ

R3

10kΩ

R1

100Ω

MULTIPLICATION:
[(X1-X2)(Y1-Y2)/10V] + Z

DIVISION:
–10V (NUM/DENO M )

Y1_IN X2_IN

X1_IN (DENOM )

X2_TP

SEL_Y1

SEL_X1

SEL_X2

SEL_Y2

SEL_Z

Y2_IN

Z_IN

NUMERATOR

–V

S

Y2_TP X1_TP

OUT_TP

OUT

+V

Y1_TP

D

M

D

M

D

M

Z_TP

NOM_TP

G1 G2 G3 G4 G6G5

+V –V

+V –V

NOTES

1. Z1 TO HAVE DUAL FOOTPRINT FOR
SOLDER MOUNT OR THRUHO LE SOCKET .

IN

GND

TEST

IN

GND

TEST

IN

GND

TEST

FUNCT(1)

FUNCT(2)

FUNCT(3)

IN

GND

TEST

IN

GND

TEST

00786-025

Figure 27. Inner Layer Power Plane

Figure 28. Component Side Silk Screen

Figure 29. AD633-EVALZ Assembly

Figure 30. Schematic of the AD633 Evaluation Board

Rev. I | Page 13 of 16

AD633 Data Sheet

COMPLIANT TO JEDEC STANDARDS MS-001

CONTROLLING DIMENSIONSARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES)ARE ROUNDE D- OFF INCH E QUIVALENTS FOR
REFERENCE O NLYAND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.

070606-A

0.022 (0.56)

0.018 (0.46)

0.014 (0.36)

SEATING
PLANE

0.015
(0.38)
MIN

0.210 (5.33)
MAX

0.150 (3.81)

0.130 (3.30)

0.115 (2.92)

0.070 (1.78)

0.060 (1.52)

0.045 (1.14)

8

1

4

5

0.280 (7.11)

0.250 (6.35)

0.240 (6.10)

0.100 (2.54)
BSC

0.400 (10.16)

0.365 (9.27)

0.355 (9.02)

0.060 (1.52)
MAX

0.430 (10.92)
MAX

0.014 (0.36)

0.010 (0.25)

0.008 (0.20)

0.325 (8.26)

0.310 (7.87)

0.300 (7.62)

0.195 (4.95)

0.130 (3.30)

0.115 (2.92)

0.015 (0.38)
GAUGE

PLANE

0.005 (0.13)
MIN

CONTROLLING DIMENSIONS

ARE IN MILLIMETERS; INCH DIMENSIONS

(IN PARENTHE

SES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR

R

EFERENCE ONLYAND ARE NOT APPROPRIATE FOR USE IN DES

IGN.

COMPLIANT TO JEDEC STANDARDS MS-012-AA

012407-A

0.25 (0.0098)

0.17 (0.0067)

1.27 (0.0500)

0.40 (0.0157)

0.50 (0.0196)

0.25 (0.0099)

45°

8°
0°

1.75 (0.0688)

1.35 (0.0532)

SEATING

PLANE

0.25 (0.0098)

0.10 (0.0040)

4

1

8 5

5.00(0.1968)

4.80(0.1890)

4.00 (0.1574)

3.80 (0.1497)

1.27 (0.0500)
BSC

6.20 (0.2441)

5.80 (0.2284)

0.51 (0.0201)

0.31 (0.0122)

COPLANARITY

0.10

OUTLINE DIMENSIONS

Figure 31. 8-Lead Plastic Dual-in-Line Package [PDIP]

(N-8)

Dimensions shown in inches and (millimeters)

Figure 32. 8-Lead Standard Small Outline Package [SOIC_N]

Narrow Body

(R-8)

Dimensions shown in millimeters and (inches)

Rev. I | Page 14 of 16

Data Sheet AD633

Model1

Temperature Range

Package Description

Package Option

AD633ARZ

−40°C to +85°C

8-Lead Standard Small Outline Package [SOIC_N]

R-8

AD633-EVALZ

Evaluation Board

ORDERING GUIDE

AD633ANZ −40°C to +85°C 8-Lead Plastic Dual-in-Line Package [PDIP] N-8

AD633ARZ-R7 −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N], 7" Tape and Reel R-8
AD633ARZ-RL −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N], 13" Tape and Reel R-8
AD633JN 0°C to 70°C 8-Lead Plastic Dual-in-Line Package [PDIP] N-8
AD633JNZ 0°C to 70°C 8-Lead Plastic Dual-in-Line Package [PDIP] N-8
AD633JR 0°C to 70°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
AD633JR-REEL 0°C to 70°C 8-Lead Standard Small Outline Package [SOIC_N], 13" Tape and Reel R-8
AD633JR-REEL7 0°C to 70°C 8-Lead Standard Small Outline Package [SOIC_N], 7" Tape and Reel R-8
AD633JRZ 0°C to 70°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
AD633JRZ-R7 0°C to 70°C 8-Lead Standard Small Outline Package [SOIC_N], 7" Tape and Reel R-8
AD633JRZ-RL 0°C to 70°C 8-Lead Standard Small Outline Package [SOIC_N], 13" Tape and Reel R-8

1

Z = RoHS Compliant Part.

Rev. I | Page 15 of 16

AD633 Data Sheet

NOTES

©2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00786-0-2/12(I)

Rev. I | Page 16 of 16