Datasheet AD632 Datasheet (Analog Devices)

Internally Trimmed

a

FEATURES

Pretrimmed to ±0.5% Max 4-Quadrant Error

All Inputs (X, Y and Z) Differential, High Impedance for

[(X
Scale-Factor Adjustable to Provide up to X10 Gain
Low Noise Design: 90 mV rms, 10 Hz–10 kHz
Low Cost, Monolithic Construction
Excellent Long-Term Stability

APPLICATIONS
High Quality Analog Signal Processing
Differential Ratio and Percentage Computations
Algebraic and Trigonometric Function Synthesis
Accurate Voltage Controlled Oscillators and Filters

PRODUCT DESCRIPTION

The AD632 is an internally-trimmed monolithic four-quadrant
multiplier/divider. The AD632B has a maximum multiplying

error of ±0.5% without external trims.

Excellent supply rejection, low temperature coefficients and
long term stability of the on-chip thin film resistors and buried
zener reference preserve accuracy even under adverse condi­tions. The simplicity and flexibility of use provide an attractive
alternative approach to the solution of complex control func­tions.

The AD632 is pin-for-pin compatible with the industry standard
AD532 with improved specifications and a fully differential high
impedance Z-input. The AD632 is capable of providing gains of
up to X10, frequently eliminating the need for separate instru­mentation amplifiers to precondition the inputs. The AD632
can be effectively employed as a variable gain differential input
amplifier with high common-mode rejection. The effectiveness
of the variable gain capability is enhanced by the inherent low

noise of the AD632: 90 µV rms.

)(Y1–Y2)/10] + Z2 Transfer Function

1–X2

Precision IC Multiplier

AD632

PIN CONFIGURATIONS

H-Package TO-100

D-Package TO-116

PRODUCT HIGHLIGHTS
Guaranteed Performance Over Temperature

The AD632A and AD632B are specified for maximum multi-

plying errors of ±1.0% and ±0.5% of full scale, respectively at
+25°C and are rated for operation from –25°C to +85°C.
Maximum multiplying errors of ±2.0% (AD632S) and ±1.0%

(AD632T) are guaranteed over the extended temperature range

of –55°C to +125°C.

High Reliability

The AD632S and AD632T series are also available with
MIL-STD-883 Level B screening and all devices are available in
either the hermetically-sealed TO-100 metal can or TO-116
ceramic DIP package.

REV. A

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
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Fax: [phone] © Analog Devices, Inc., 1997

AD632–SPECIFICATIONS

(@ +258C, V

= ±15 V, R ≥ 2 kV unless otherwise noted)

S

Model Min Typ Max Min Typ Max Min Typ Max Min Typ Max Units

AD632A AD632B AD632S AD632T

MULTIPLIER PERFORMANCE

( X

− X

)(Y

− Y

)

( X

− X

)(Y

− Y

)

( X

− X

)(Y

− Y

)

( X

− X

)(Y

− Y

1

2

1

2

Transfer Function

Total Error

= Min to Max 61.5 61.0 62.0 61.0 %

T

A

1

(–10 V ≤ X, Y ≤ +10 V) 61.0 60.5 61.0 60.5 %

10V

+ Z

1

2

1

2

2

10V

+ Z

1

2

1

2

2

10V

+ Z

1

2

10V

)

2

1

2

+ Z

2

Total Error vs. Temperature ±0.022 ±0.015 60.02 60.01 %/°C

Scale Factor Error

(SF = 10.000 V Nominal)

2

±0.25 ±0.1 ±0.25 ±0.1 %

Temperature-Coefficient of

Scaling-Voltage ±0.02 60.01 ±0.2 60.005 %/°C
Supply Rejection (±15 V ± 1 V) ±0.01 ±0.01 ±0.01 ±0.01 %
Nonlinearity, X (X = 20 V p-p, Y = 10 V) ±0.4 ±0.2 ±0.3 ±0.4 ±0.2 ±0.3 %
Nonlinearity, Y (Y = 20 V p-p, X = 10 V) ±0.2 ±0.1 ±0.1 ±0.2 ±0.1 ±0.1 %

Feedthrough

X = 20 V p-p 50 Hz) ±0.3 ±0.15 ±0.3 ±0.3 ±0.15 ±0.3 %

Feedthrough

3

, X (Y Nulled,

3

, Y (X Nulled,

Y = 20 V p-p 50 Hz) ±0.01 ±0.01 ±0.1 ±0.01 ±0.01 ±0.1 %
Output Offset Voltage ±5 630 ±2 ±15 ±5 630 ±2 ±15 mV
Output Offset Voltage Drift 200 100 500 300 µV/°C

DYNAMICS

Small Signal BW, (V
1% Amplitude Error (C
Slew Rate (V

OUT

Settling Time (to 1%, ∆V

= 0.1 rms) 1111MHz

OUT

= 1000 pF) 50 50 50 50 kHz

LOAD

20 p-p) 20 20 20 20 V/µs

= 20 V)2222µs

OUT

NOISE

Noise Spectral-Density SF = 10 V 0.8 0.8 0.8 0.8 µV/√Hz

SF = 3 V

4

0.4 0.4 0.4 0.4 µV/√Hz

Wideband Noise A = 10 Hz to 5 MHz 1.0 1 .0 1.0 1.0 mV rms

P = 10 Hz to 10 kHz 90 90 90 90 µV/rms

OUTPUT

Output Voltage Swing 611 611 611 611 V

Output Impedance (f ≤ 1 kHz) 0.1 0.1 0.1 0.1 Ω

Output Short Circuit Current

= 0, TA = Min to Max) 30 30 30 30 mA

(R

L

Amplifier Open Loop Gain (f = 50 Hz) 70 70 70 70 dB

INPUT AMPLIFIERS (X, Y and Z)

5

Signal Voltage Range (Diff. or CM ±10 ±10 ±10 ±10 V

Operating Diff.) ±12 ±12 ±12 ±12 V
Offset Voltage X, Y ±5 620 ±2 610 ±5 620 ±2 610 mV
Offset Voltage Drift X, Y 100 50 100 150 µV/°C
Offset Voltage Z ±5 630 ±2 615 ±5 630 ±2 615 mV
Offset Voltage Drift Z 200 100 500 300 µV/°C

CMRR 60 80 70 90 60 80 70 90 dB

Bias Current 0.8 2.0 0.8 2.0 0.8 2.0 0.8 2.0 µA
Offset Current 0.1 0. I 0.1 0.1 µA
Differential Resistance 10 10 1 0 10 MΩ

DIVIDER PERFORMANCE

Transfer Function (X1 > X2)
Total Error

1

10V

− Z

)

( Z

2

1

+Y

1

− X

)

( X

1

2

10V

− Z

)

( Z

2

1

+Y

1

− X

)

( X

1

2

10V

− Z

)

( Z

2

1

+Y

1

− X

)

( X

1

2

10V

− Z

)

( Z

2

1

+Y

1

− X

)

( X

1

2

(X = 10 V, –10 V ≤ Z ≤ +10 V) ±0.75 ±0.35 ±0.75 ±0.35 %

(X = 1 V, –1 V ≤ Z ≤ +1 V) ±2.0 ±1.0 ±2.0 ±1.0 %

(0.1 V ≤ X ≤ 10 V, –10 V ≤ Z ≤ 10 V) ±2.5 ±1.0 ±2.5 ±1.0 %

SQUARER PERFORMANCE

Transfer Function

Total Error (–10 V ≤ X ≤ 10 V) ±0.6 ±0.3 ±0.6 ±0.3 %

S

QUARE-ROOTER PERFORMANCE

Transfer Function, (Z
Total Error

1

(1 V ≤ Z ≤ 10 V) ±1.0 ±0.5 ±1.0 ±0.5 %

≤ Z

1

)

2

10V (Z

2

( X

− X

)

1

2

+ Z

− Z1) + X

2

2

10V (Z

2

10V

2

( X

− X

)

1

2

+ Z

− Z1) + X

2

2

10V (Z

2

10V

2

( X

− X

)

1

2

+ Z

− Z1) + X

2

2

10V (Z

2

10V

2

( X

− X

)

1

2

+ Z

− Z1) + X

2

2

2

10V

–2–

REV. A

AD632

AD632A AD632B AD632S AD632T

Model Min Typ Max Min Typ Max Min Typ Max Min Typ Max Units

POWER SUPPLY SPECIFICATIONS

Supply Voltage

Rated Performance ±15 ±15 ± 15 ±15 V

Operating ±8 618 ±8 618 ±8 622 ± 8 622 V

Supply Current

Quiescent 4 6 46 46 46 mA

NOTES

1

Figures given are percent of full-scale, ±l0 V (i.e., 0.01% = 1 mV).

2

May be reduced to 3 V using external resistor between –VS and SF.

3

Irreducible component due to nonlinearity: excludes effect of offsets.

4

Using external resistor adjusted to give SF = 3 V.

5

See functional block diagram for definition of sections.

All min and max specifications are guaranteed.

Specifications shown in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels.

Specifications subject to change without notice.

ORDERING GUIDE

Temperature Package Package

Model Range Description Option*

AD632AD –25°C to +85°C Side Brazed Ceramic DIP D-14
AD632BD –25°C to +85°C Side Brazed Ceramic DIP D-14
AD632AH –25°C to +85°C Header H-10A
AD632BH –25°C to +85°C Header H-10A
AD632SD –55°C to +125°C Side Brazed Ceramic DIP D-14
AD632SD/833B –55°C to +125°C Side Brazed Ceramic DIP D-14
AD632TD –55°C to +125°C Side Brazed Ceramic DIP D-14
AD632TD/883B –55°C to +125°C Side Brazed Ceramic DIP D-14
AD632SH –55°C to +125°C Header H-10A
AD632SH/883B –55°C to +125°C Header H-10A
AD632TH –55°C to +125°C Header H-10A
AD632TH/883B –55°C to +125°C Header H-10A

*For outline information see Package Information section.

CHIP DIMENSIONS AND PAD LAYOUT

Dimensions shown in inches and (mm).
(Contact factory for latest dimensions.)

For further information, consult factory.

Thermal Characteristics

Thermal Resistance θJC = 25°C/W for H-10A

θ

= 150°C/W for H-10A

JA

θ

= 25°C/W for D-14

JC

θJA = 95°C/W for D-14

–3–REV. A

AD632

Typical Performance Curves

(typical @ +258C with 6VS = 15 V)

Figure 1. AC Feedthrough vs. Frequency

Figure 4. AD632 Functional Block Diagram

OPERATION AS A MULTIPLIER

Figure 5 shows the basic connection for multiplication. Note
that the circuit will meet all specifications without trimming.

Figure 2. Frequency Response as a Multiplier

Figure 3. Frequency Response vs. Divider Denominator
Input Voltage

Figure 5. Basic Multiplier Connection

In some cases the user may wish to reduce ac feedthrough to a
minimum (as in a suppressed carrier modulator) by applying an

external trim voltage (±30 mV range required) to the X or Y

input. Curve 1 shows the typical ac feedthrough with this ad­justment mode. Note that the feedthrough of the Y input is a
factor of 10 lower than that of the X input and should be used
in applications where null suppression is critical.

The Z

terminal of the AD632 may be used to sum an addi-

2

tional signal into the output. In this mode the output amplifier
behaves as a voltage follower with a 1 MHz small signal band-

width and a 20 V/µs slew rate. This terminal should always be

referenced to the ground point of the driven system, particularly
if this is remote. Likewise the differential inputs should be refer­enced to their respective signal common potentials to realize the
full accuracy of the AD632.

A much lower scaling voltage can be achieved without any re­duction of input signal range using a feedback attenuator as
shown in Figure 6. In this example, the scale is such that
V

= XY, so that the circuit can exhibit a maximum gain of

OUT

10. This connection results in a reduction of bandwidth to
about 80 kHz without the peaking capacitor C
output offset voltage is increased by a factor of 10 making exter­nal adjustments necessary in some applications.

. In addition, the

F

–4–

REV. A

AD632

Feedback attenuation also retains the capability for adding a

signal to the output. Signals may be applied to the Z terminal,

where they are amplified by –10, or to the common ground

connection where they are amplified by –1. Input signals may

also be applied to the lower end of the 2.7 kΩ resistor, giving a

gain of +9.

Figure 6. Connections for Scale-Factor of Unity

OPERATION AS A DIVIDER

Figure 7 shows the connection required for division. Unlike

earlier products, the AD632 provides differential operation on

both numerator and denominator, allowing the ratio of two

floating variables to be generated. Further flexibility results from

access to a high impedance summing input to Y

. As with all

1

dividers based on the use of a multiplier in a feedback loop, the

bandwidth is proportional to the denominator magnitude, as

shown in Figure 3.

Without additional trimming, the accuracy of the AD632B is
sufficient to maintain a 1% error over a 10 V to 1 V denomina­tor range (The AD535 is functionally equivalent to the AD632
and has guaranteed performance in the divider and square-rooter
configurations and is recommended for such applications).

This range may be extended to 100:1 by simply reducing the X
offset with an externally generated trim voltage (range required

is ±3.5 mV max) applied to the unused X input. To trim, apply

a ramp of +100 mV to +V at 100 Hz to both X

and Z1 (if X2 is

1

used for offset adjustment, otherwise reverse the signal polarity)
and adjust the trim voltage to minimize the variation in the
output.*

Since the output will be near +10 V, it should be ac-coupled for
this adjustment. The increase in noise level and reduction in
bandwidth preclude operation much beyond a ratio of 100 to 1.

*See the AD535 data sheet for more details.

Figure 7. Basic Divider Connection

–5–REV. A

AD632

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

H-Package TO-100

C526a–1–6/97

D-Package TO-116

–6–

PRINTED IN U.S.A.

REV. A