Datasheet AD6311 Datasheet (AnaChip)

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1/8- to 1/16 Duty VFD Controller/Driver

Features



- 4-pin serial interface

- Key scanning (12x4 matrices)

- Programming display modes (16-digit & 12­ segment to 8-digit & 20-segment)

- Programming dimming step

- High-voltage output (V

- 5 channels LED ports

- 4-pin general-purpose input port

- Built-in oscillator

- No external resistor necessary for driver outputs

Pin Assignments



-35V max)

DD

9

10

/ Grid

6

Grid

/ Grid

20

19

EE

Grid8Grid7

V

Seg

Seg

AD6311

General Description



The AD6311 is a VFD (Vacuum Fluorescent
Display) controller/driver that is driven on a 1/8- to
1/16 duty factor (include key scan). It consists of 12
segment/key scan output lines, 8 grid output lines,
8 segment/grid output drive lines, a display memory,
a control circuit, and a key scan circuit. Serial data
is input to the AD6311 through a four-line serial
interface.

11

/ Grid

18

DD

Seg

V

Seg17 / Grid12

15

14

13

/ Grid

16

Seg

16

/ Grid

/ Grid

/ Grid

14

15

13

Seg

Seg

Seg

Grid

Grid

Grid

Grid

Grid

V

LED

LED

LED

LED

LED

VSS

OSC

5

4

3

2

1

DD

5

4

3

2

1

39

40

41

42

43

44

45

46

47

48

49

50

51

52

1

1

Sw

4

3

2

4Sw3

Sw

Sw2

5

OUT

D

7

6

IN

D

NC

10

9

8

1

CLK

STB

26

25

24

23

22

21

20

19

18

17

16

15

14

11

13

12

3

Key2Key

Key4Key

Seg12 / KS

Seg11 / KS

Seg10 / KS

Seg9 / KS

Seg8 / KS

Seg7 / KS

Seg

/ KS

6

Seg5 / KS

Seg4 / KS

Seg3 / KS

Seg2 / KS

Seg1 / KS

DD

V

12

11

10

9

8

7

6

5

4

3

2

1

27

28

29

30

31

32

33

34

35

36

37

38

Use all the power pins.

This datasheet contains new product information. Anachip Corp. reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of
this product. No rights under any patent accompany the sale of the product.

1/11

Rev. A5 Dec 29, 2003

1/8- to 1/16 Duty VFD Controller/Driver

Pin Descriptions



Symbol Name No. Description

DIN Data input 6

D

OUT

STB Strobe 9

CLK Clock input 8

OSC Oscillator pin 52

Seg1/KS1 to

Seg

/KS12

12

Grid1 to Grid8 High-voltage output (Grid) 37 to 44 Grid output pins

Seg13/Grid16 to

Seg

/Grid9

20

LED1 to LED5 LED output 46 to 50 CMOS output

KEY1 to KEY4 Key data input 10 to 13

VDD Logic power 14, 33, 45 Logic power supply

VSS Logic ground 51 Connect this pin to system GND.

VEE Pull-down level 34 Driver power supply

SW1 to SW

NC NC 7 No connection

High-voltage output (Segment/grid)

4

Data output

High-voltage output 15 to 26

27 to 32

35, 36

Switch input 1 to 4

Ordering Information



AD6311X X X

Input serial data at rising edge of shift clock,
starting from the low order bit.
Output serial data at the falling edge of the shift

5

clock, starting from low order bit. This is N-ch
open-drain output pin.
Initializes serial interface at the rising or falling
edge of the AD6311. It then waits for reception of a
command. Data input after STB falling is
processed as a command. While command data is
processed, current processing is stopped, and the
serial interface is initialized. While STB is high,
CLK is ignored.
Reads serial data at the rising edge, and outputs
data at the falling edge.
Connect resistor in between this pin and Vdd to set
up the oscillation frequency.
Multi-function pins, Segment output pins (Dual
function as key scan source)

These pins are selectable for segment or grid
driving.

Data input to these pins is latched at the end of the
display cycle.

These pins constitute a 4-bit general-purpose input
port.

AD6311

Package Lead

Blank: Normal
F: Lead Free

Packing

Blank : TrayQ: QFP-52L

Anachip Corp.
www.anachip.com.tw Rev. A5 Dec 29, 2003

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1/8- to 1/16 Duty VFD Controller/Driver

Block Diagram



Command

decoder

D

IN

D

CLK

STB

V

KEY

to

KEy

SW

to

SW

OUT

DD

1

4

1

4

R

4

Serial

I/F

OSC

4

4-bit

latch

Display memory

X

16Words

20 bit

Timing generator

key scan

Key data memory

X

2)

(4

5-bit latch

LED

1

LED

5

Dimming

circuit

20

20-bit

8

output latch

16-bit shift register

8

V

DD

(+5V)

12

Segment

8

Data selector

Segment/grid

816

EE

V

Vss

(-30V)

(0V)

AD6311

Seg

driver

Seg

Seg13/Grid

driver

Seg20/Grid

Grid

Grid driver

Grid

1

12

16

9

1

8

Anachip Corp.
www.anachip.com.tw Rev. A5 Dec 29, 2003

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1/8- to 1/16 Duty VFD Controller/Driver

AD6311

(T

Absolute Maximum Ratings



Parameter Symbol Rating Unit

Logic supply voltage VDD -0.5 to +7.0 V
Driver supply voltage VEE V
Logic input voltage VI1 -0.5 to VDD +0.5 V
VFD driver output voltage VO2 V
LED driver output current IO1 +15 mA
VFD driver output current IO2 -40(grid) –15 (segment) mA
Operating ambient temperature T

Storage temperature T

(T

Operating Conditions



=0 to +70℃,VSS=0V)

A

Parameter Symbol Conditions Min. Typ. Max. Unit

Logic supply voltage VDD 4.5 5 5.5 V
High-level input voltage VIH 0.7·VDD V
Low-level input voltage VIL 0 0.3xVDD V
Driver supply voltage VEE 0 VDD-35 V

DC Characteristics



=0 to 70℃, VDD=4.5 to 5.5V, VSS=0V, VEE=VDD-35V)

(T

a

Parameter Symbol Conditions Min. Typ. Max. Unit

High-level output voltage V
Low-level output voltage V
Low-level output voltage V
High-level output current I

High-level output current I

Driver leakage current I

LED1-LED5,I

OH1

LED1-LED5,I

OL1

D

OL2

VO=VDD-2V,Seg1 to Seg12 -3 mA

OH21

OH22

VO=VDD-35V, driver off -10

OLEAK

Output pull-down resistor RL Driver output 50 100 150
High-level input voltage VIH 0.7VDD V
Low-level input voltage VIL 0.3VDD V

(T

AC Characteristics



=0 to +70℃,VDD=4.5 to 5.5 V)

a

Parameter Symbol Conditions Min. Typ. Max. Unit

Oscillation frequency f
Maximum clock frequency f
Clock pulse width PW
Strobe pulse width PW
Data setup time t
Data hold time t
Clock-strobe time t
Wait time t

Note: Refer to page 8.

OSC

Duty=50% 1 MHZ

max.

500 ns

CLK

1 µs

STB

100 ns

SETUP

100 ns

HOLD

CLK-STB

WAIT

=25℃,VSS=0V )

A

-25 to +85

OPT

-50 to +125

STG

OH1

OL1

=2mA 0.4 V

OUT,IOL2

O=VDD

-2V,Grid

V

DD

EE

=-1mA 0.9VDD V

=12mA 1 V

to Grid

1

8,

Seg13/Grid16 to Seg20/Grid9

R=51 kΩ

CLK↑→STB
CLK↑→CLk↓(Note)

↑

+0.5 to VDD -40 V

-0.5 to VDD +0.5 V

℃
℃

V

DD

-15 mA

350 500 650 KHZ

1 µs
1 µs

μ

kΩ

A

Anachip Corp.
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1/8- to 1/16 Duty VFD Controller/Driver

AD6311

Function Description



1.0 Command

A command sets the display mode and status of the VFD driver. The first 1 byte input to the AD6311
through the Din pin after the STB pin has fallen is regarded as a command. If STB is made high while a
command/data is transmitted, serial communication is initialized, and the command/data being
transmitted is invalid (however, the command/data already transmitted remains valid).

1.1 Display mode setting command

This command initializes the AD6311 and selects the number of segments and number of grids (8 grid
& 20 segments to 16 grid & 12 segments). When this command is executed, display is forcibly turned
off, and key scanning is also stopped. To resume display, a display ON command must be executed. If
the same mode is selected, however, nothing is performed.

MSB

0 0 - - b3 b2 b1 b0

LSB

Don't care

Selects display mode
0xxx : 8 digits, 20 segments
1000: 9 digits, 19 segments
1001: 10 digits, 18 segments
1010: 11 digits, 17 segments
1011: 12 digits, 16 segments
1100: 13 digits, 15 segments
1101: 14 digits, 14 segments
1110: 15 digits, 13 segments
1111: 16 digits, 12 segments

On power application, the 16-digit, 12-segment mode is selected.

1.2 Data setting command

This command sets data write and data read modes. On power application, the normal operation mode
and address increment mode are set.

MSB LSB

0 1 - - b3 b2 b1 b0

Don't care

Sets data write and read modes.
00: Writes data to display memory.
01: Writes data to LED port.
10: Reads key data.
11: Reads SW data.

Sets address increment mode (display memory).
0: Incremenets address after data has been
written.
1: Fixes address.

Sets test mode
0: Normal operation
1: Test mode

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1/8- to 1/16 Duty VFD Controller/Driver

AD6311

1.3 Address setting command

This command sets an address of the display memory. If address 30H or higher is set, the data is

ignored, until a correct address is set. On power application, the address is set to 00H.

MSB LSB

1 1 b5 b3 b2 b1 b0

b4

Address (00H-2FH)

1.4 Display control command

MSB LSB

10- b3b2b1b0

-

Don't care

Sets dimming quantity.
000: Sets pulse width to 1/16.
001: Sets pulse width to 2/16.
010: Sets pulse width to 4/16.
011: Sets pulse width to 10/16.
100: Sets pulse width to 11/16.
101: Sets pulse width to 12/16.
110: Sets pulse width to 13/16.
111: Sets pulse width to 14/16.

Tums on/off display.
0: Display off (key scan continues )
1: Display on

On power application, the 1/16-pulse width is set, the display is turned off and key scanning is stopped.

2.0 Display RAM Address and Display Mode

The display RAM stores the data transmitted from an external device to the AD6311 through the serial
interface, and is assigned addresses as follows, in units of 8 bits:

Seg

b0 b3 b4 b7

Anachip Corp.
www.anachip.com.tw Rev. A5 Dec 29, 2003

Seg4 Seg8 Seg

1

00 H
03 H
06 H
09 H
0 CH
0 FH
12 H
15 H
18 H
1 BH
1 EH
21 H
24 H
27 H
2 AH
2 DH

XX H

00 H

L

L

L

L

L

L

L

L

L

L

L

L

L

L

L

L

L

03 H
06 H
09 H
0 CH
0 FH
12 H
15 H
18 H
1 BH
1 EH
21 H
24 H
27 H
2 AH
2 DH

XXHU

U

U

U

U

U

U

U

U

U

U

U

U

U

U

U

U

01 H
04 H
07 H
0 AH
0 DH
10 H
13 H
16 H
19 H
1 CH
1 FH
22 H
25 H
28 H
2 BH
2 EH

L

L

L

L

L

L

L

L

L

L

L

L

L

L

Seg

12

16

01 HU 02 HL GRID
04 HU 05 HL GRID
07 HU 08 HL GRID
0 AHU 0 BHL GRID
0 DHU 0 EHL GRID

L

10 HU 11 HL GRID
13 HU 14 HL GRID
16 HU 17 HL GRID
19 HU 1 AHL GRID
1 CHU 1 DHL GRID

L

1 FHU 20 HL GRID
22 HU 23 HL GRID
25 HU 26 HL GRID
28 HU 29 HL GRID
2 BHU 2 CHL GRID
2 EHU 2 FHL GRID

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Seg20

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

1/8- to 1/16 Duty VFD Controller/Driver

AD6311

Lower 4 bits Higher 4 bits

Only the lower 4 bits of the addresses assigned to Seg
are ignored.

3.0 LED Port

Data is written to the LED port by a write command, starting from the least significant bit of the port.
When a bit of this port is 0, the corresponding LED lights; when the bit is 1, the LED goes off . The data
of bits 6 through 8 is ignored.

MSB LSB

---b4b3b2b1b0

through Seg20 are valid, and the higher 4 bits

17

Don't care

LED2

LED3

LED4

LED1

LED5

On power application, all the LEDs remain dark.

4.0 Key Matrix and Key-Input data Storage RAM

The key matrix is of 12×4 configuration, as shown below.

1

KEY

2

KEY

3

KEY

4

KEY

1

2

3

4

5

6

7

8

9

10

11

/KS

1

Seg

/KS

2

Seg

/KS

3

Seg

/KS

4

Seg

/KS

5

Seg

/KS

6

Seg

/KS

7

Seg

/KS

8

Seg

/KS

9

Seg

/KS

10

Seg

/KS

11

Seg

12

KS

12/

Seg

The data of each key is stored as illustrated below, and is read by a read command, starting from the least
significant bit. When the most significant bit of data (Seg
next data (Seg

) is read.

1 b0

) has been read, the least significant bit of the

12 b7

KEY1

KEY4 KEY1

...

1

Seg1/KS

3

Seg3/KS

5

Seg5/KS

Seg7/KS

7

9

Seg9/KS

Seg11/KS

Anachip Corp.
www.anachip.com.tw Rev. A5 Dec 29, 2003

11

KEY4

...

Seg2/KS

Seg4/KS

Seg6/KS

Seg8/KS

Seg10/KS

Seg12/KS

b4--------b7b0--------b3

2

4

6

8

10

12

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Reading sequence

1/8- to 1/16 Duty VFD Controller/Driver

AD6311

5.0 SW Data

The SW data is read by a read command, starting from the least significant bit. Bits 5 through 8 of the
SW data are 0.

MSB LSB

0 0 0 0 b3 b2 b1 b0

SW1

SW2

SW3

SW4

Timing Diagram



(1) Serial Communication Format

Reception (command/write data)

If data continues

STB

D

IN

b7b6b2b1b0

87321CLK

Transmission (read data)

STB

b7b6b5b4b3b2b1b0

87654321

WAIT

t

(Note)

b0 b1 b2 b3 b4 b5

Data reading starts.Data reading command is set.

654321

CLK

D

D

OUT

IN

Because the D

pin is an N-ch, open-drain output pin, be sure to connect an external pull-up resistor to

OUT

this pin (1kΩ to 10 kΩ).

Note : When data is read, a wait time t
falling of the first clock that has read the data.

of 1 μs is necessary since the rising of the eighth clock that has set the command, until the

WAIT

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1/8- to 1/16 Duty VFD Controller/Driver

(2) Key Scanning and Display Timing

≅

T

500μs

DISP

AD6311

Key scan data

SEG Output

Grid1

Grid2

Gird3

Gridn

DIG1 DIG2 DIG3

1/16

T

DISP

1 frame = T

DISP

×

DIGn

(n+1)

One cycle of key scanning consists of two frames, and data of 12×4 matrices is stored in RAM.

AC characteristic waveform

fosc

OSC

50%

PW

STB

DIG1

STB

90%

10%

PW

t

HOLD

CLK

t

THZ

tPZL

t

CLK-STB

tPLZ

t

TZH

CLK

D

IN

D

OUT

Sn/Gn

PW

t

SETUP

CLK

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1/8- to 1/16 Duty VFD Controller/Driver

Applications

Updating display memory by incrementing address

STB

CLK

AD6311

IN

Command 4Data nCommand 3Command 2Command 1 Data 1D

Command 1: sets display mode
Command 2: sets data(write data to display memory)
Command 3: sets address
Data 1 to n: transfers display data (48 bytes max.)
Command 4: controls display

Updating specific display memory

STB

CLK

D

IN

DataCommand 2Command 2 DataCommand 1

Command 1: sets data
Command 2: sets address
Data: display data

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10/11

1/8- to 1/16 Duty VFD Controller/Driver

Package Information



52 pins QFP dimension Unit: mm

39 27

17.2

14.0

±

0.5

±

0.5

AD6311

2.7(MAX.)

40

52

Marking Information



Part Number

AC

AD6311 X

XX

26

14

131

1.6 TYP.

0.88 TYP.1.0 TYP.0.4 TYP.

Top view

XXX

XX

QFP52

14.0

17.2

±

±

0.5

0.5

Logo

Blank: Nomal
F: Lead Free Package

ID code: internal
Nth week: 01~52
Year:

"01" = 2001
"02" = 2002

0.15 TYP.

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