Datasheet AD629 Datasheet (ANALOG DEVICES)

High Common-Mode Voltage,

R

A

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FEATURES

Improved replacement for: INA117P and INA117KU
±270 V common-mode voltage range
Input protection to

±500 V common mode

±500 V differential mode
Wide power supply range (±2.5 V to ±18 V)
±10 V output swing on ±12 V supply
1 mA maximum power supply current

HIGH ACCURACY DC PERFORMANCE
3 ppm maximum gain nonlinearity (AD629B)
20 μV/°C maximum offset drift (AD629A)
10 μV/°C maximum offset drift (AD629B)
10 ppm/°C maximum gain drift

EXCELLENT AC SPECIFICATIONS
77 dB minimum CMRR @ 500 Hz (AD629A)
86 dB minimum CMRR @ 500 Hz (AD629B)
500 kHz bandwidth

APPLICATIONS

High voltage current sensing
Battery cell voltage monitors
Power supply current monitors
Motor controls
Isolation

100

95

90

TIO (dB)

85

80

75

70

65

60

COMMON-MO DE REJECTIO N

55

50

20 100 1k 10k 20k

Figure 2. Common-Mode Rejection Ratio vs. Frequency

FREQUENCY ( Hz)

Difference Amplifier

AD629

FUNCTIONAL BLOCK DIAGRAM

REF(–)

–V

–IN

+IN

2

3

4

S

380kΩ

380kΩ

AD629

NC = NO CONNECT

21.1kΩ

1

GENERAL DESCRIPTION

The AD629 is a difference amplifier with a very high input,
common-mode voltage range. It is a precision device that allows
the user to accurately measure differential signals in the
presence of high common-mode voltages up to ±270 V.

The AD629 can replace costly isolation amplifiers in

pplications that do not require galvanic isolation. The device

a
operates over a ±270 V common-mode voltage range and has
inputs that are protected from common-mode or differential
mode transients up to ±500 V.

The AD629 has low offset, low offset drift, low gain error drift,

w common-mode rejection drift, and excellent CMRR over a

lo
wide frequency range.

The AD629 is available in low cost, 8-lead PDIP and 8-lead
SO

IC packages. For all packages and grades, performance is
guaranteed over the industrial temperature range of −40°C to
+85°C.

2mV/DIV

OUTPUT ERROR (2mV/DIV)

00783-002

–240 240120–120 0

Figure 3. Error Voltage vs. Input Common-Mode Voltage

COMMON-MODE VOLTAGE (V)

380kΩ

20kΩ

Figure 1.

NC

8

7

+V

6

OUTPUT

5

REF(+)

60V/DIV

S

0783-001

00783-003

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©1999-2007 Analog Devices, Inc. All rights reserved.

AD629

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TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Absolute Maximum Ratings............................................................ 4

ESD Caution.................................................................................. 4

Typical Performance Characteristics ............................................. 5

Theory of Operation ........................................................................ 9

Applications..................................................................................... 10

REVISION HISTORY

3/07—Rev. A to Rev. B

Updated Format and Layout .............................................Universal

Changes to Ordering Guide.......................................................... 15

3/00—Rev. 0 to Rev. A

10/99—Revision 0: Initial Version

Basic Connections...................................................................... 10

Single-Supply Operation ........................................................... 10

System-Level Decoupling and Grounding.............................. 10

Using a Large Sense Resistor..................................................... 11

Output Filtering.......................................................................... 11

Output Current and Buffering.................................................. 12

A Gain of 19 Differential Amplifier......................................... 12

Error Budget Analysis Example 1 ............................................ 12

Error Budget Analysis Example 2 ............................................ 13

Outline Dimensions ....................................................................... 14

Ordering Guide............................................................................... 15

Rev. B | Page 2 of 16

AD629

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SPECIFICATIONS

TA = 25°C, VS = ±15 V, unless otherwise noted.

Table 1.

AD629A AD629B

Parameter Condition Min Typ Max Min Typ Max Unit

GAIN V

= ±10 V, RL = 2 kΩ

OUT

Nominal Gain 1 1 V/V
Gain Error 0.01 0.05 0.01 0.03 %
Gain Nonlinearity 4 10 4 10 ppm
R
Gain vs. Temperature TA = T

= 10 kΩ 1 1 3 ppm

L

to T

MIN

3 10 3 10 ppm/°C

MAX

OFFSET VOLTAGE

Offset Voltage 0.2 1 0.1 0.5 mV
V
vs. Temperature TA = T

= ±5 V 1 mV

S

to T

MIN

6 20 3 10 μV/°C

MAX

vs. Supply (PSRR) VS = ±5 V to ± 15 V 84 100 90 110 dB

INPUT

Common-Mode Rejection Ratio VCM = ±250 V dc 77 88 86 96 dB
T
V
V

= T

to T

A

MIN

= 500 V p-p, dc to 500 Hz 77 86 dB

CM

= 500 V p-p, dc to 1 kHz 88 90 dB

CM

73 82 dB

MAX

Operating Voltage Range Common mode ±270 ±270 V
Differential ±13 ±13 V

Input Operating Impedance Common mode 200 200 kΩ
Differential 800 800 kΩ
OUTPUT

Operating Voltage Range RL = 10 kΩ ±13 ±13 V

R

V

= 2 kΩ ±12.5 ±12.5 V

L

= ±12 V, RL = 2 kΩ ±10 ±10 V

S

Output Short-Circuit Current ±25 ±25 mA

Capacitive Load Stable operation 1000 1000 pF
DYNAMIC RESPONSE

Small Signal –3 dB Bandwidth 500 500 kHz

Slew Rate 1.7 2.1 1.7 2.1 V/μs

Full Power Bandwidth V

Settling Time 0.01%, V

0.1%, V

0.01%, VCM = 10 V step, V

= 20 V p-p 28 28 kHz

OUT

= 10 V step 15 15 μs

OUT

= 10 V step 12 12 μs

OUT

= 0 V 5 5 μs

DIFF

OUTPUT NOISE VOLTAGE

0.01 Hz to 10 Hz 15 15 μV p-p

Spectral Density, ≥100 Hz

1

550 550 nV/√Hz

POWER SUPPLY

Operating Voltage Range ±2.5 ±18 ±2.5 ±18 V

Quiescent Current V
T

= 0 V 0.9 1 0.9 1 mA

OUT

MIN

to T

MAX

1.2 1.2 mA

TEMPERATURE RANGE

For Specified Performance TA = T

1

See Figure 19.

MIN

to T

MAX

−40 +85 −40 +85 °C

Rev. B | Page 3 of 16

AD629

A

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ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

Supply Voltage, V
Internal Power Dissipation

8-Lead PDIP (N) See Figure 4

8-Lead SOIC (R) See Figure 4
Input Voltage Range, Continuous ±300 V
Common-Mode and Differential, 10 sec ±500 V
Output Short-Circuit Duration Indefinite
Pin 1 and Pin 5 –VS − 0.3 V to +VS + 0.3 V
Maximum Junction Temperature 150°C
Operating Temperature Range −55°C to +125°C
Storage Temperature Range −65°C to +150°C
Lead Temperature (Soldering 60 sec) 300°C

1

Specification is for device in free air:

8-Lead PDIP, θJA = 100°C/W;
8-Lead SOIC, θJA = 155°C/W.

S

1

±18 V

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

Figure 4. Maximum Power Dissipation vs. Temperature for SOIC and PDIP

2.0

8-LEAD PDIP

1.5

TION (W)

1.0

8-LEAD SOI C

0.5

MAXIMUM POWER DISSIP

0

–50 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90

AMBIENT TEMPERATURE (°C)

TJ = 150°C

00783-004

ESD CAUTION

Rev. B | Page 4 of 16

AD629

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A

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TYPICAL PERFORMANCE CHARACTERISTICS

TA = 25°C, VS = ±15 V, unless otherwise noted.

100

90

80

TIO (dB)

70

60

50

40

30

20

10

COMMON-M ODE REJECTI ON

0

100 1k 10k 100k 1M 10M

FREQUENCY ( Hz)

Figure 5. Common-Mode Rejection Ratio vs. Frequency

00783-006

400

360

320

280

240

200

160

120

80

COMMON-MODE VOLTAGE (±V)

40

0

02 6 104 8 12 14 1816 20

TA = +85°C

POWER SUPPLY VOLTAGE (±V)

TA = +25°C

TA = –40°C

Figure 8. Common-Mode Operating Range vs. Power Supply Voltage

00783-009

2mV/DIV

VS = ±18V

VS = ±15V

VS = ±12V

OUTPUT ERROR (2mV/DIV)

VS = ±10V

–20 –16 –8 –4 0 4 8 12 16–12 20

Figure 6. Typical Gain Error Normalized @ V

Operating Range vs. Supply Voltage, R

VS = ±18V

VS = ±15V

VS = ±12V

OUTPUT ERROR (2mV/DIV)

V

(V)

OUT

= 0 V and Output Voltage

OUT

= 10 kΩ (Curves Offset for Clarity)

L

RL = 10kΩ

4V/DIV

RL = 1kΩ

RL = 2kΩ

VS = ±18V

VS = ±15V

VS = ±12V

OUTPUT ERROR (2mV/DIV)

VS = ±10V

00783-007

–20 –16 –8 –4 0 4 8 12 16–12 20

Figure 9. Typical Gain Error Normalized @ V

Operating Range vs. Supply Voltage, R

VS = ±5V, RL = 10kΩ

VS = ±5V, RL = 2kΩ

VS = ±5V, RL = 1kΩ

OUTPUT ERROR (2mV/DIV)

V

(V)

OUT

= 0 V and Output Voltage

OUT

= 2 kΩ (Curves Offset for Clarity)

L

4V/DIV

00783-010

VS = ±10V

–20 –16 –8 –4 0 4 8 12 16–12 20

Figure 7. Typical Gain Error Normalized @ V

Operating Range vs. Supply Voltage, R

V

(V)

OUT

= 0 V and Output Voltage

OUT

= 1 kΩ (Curves Offset for Clarity)

L

4V/DIV

00783-008

Figure 10. Typical Gain Error Normalized @ V

VS = ±2.5V, RL = 1kΩ

–20 –16 –8 –4 0 4 8 12 16–12 20

Operating Range vs. Supply Voltage (Curves Offset for Clarity)

Rev. B | Page 5 of 16

1V/DIV

00783-011

V

(V)

OUT

= 0 V and Output Voltage

OUT

AD629

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20µV/DIV

ERROR (0.8ppm/DIV)

–10 –5 0 5 10

Figure 11. Gain Nonlinearity; V

V

(V)

OUT

= ±15 V, RL = 10 kΩ

S

VS = ±15V
R

= 10kΩ

L

2.5V/DIV

20µV/DIV

ERROR (1ppm/DIV)

–10 –2–4–6–8 0246810

Figure 12. Gain Nonlinearity; V

V

(V)

OUT

S

= ±12 V, RL =10 kΩ

VS = ±12V
R

= 10kΩ

L

2V/DIV

40µV/DIV

ERROR (6.67pp m/DIV)

–3.0 –0.6–1.2–1.8–2.4 0 0.6 1.2 1.8 2.4 3.0

Figure 13. Gain Nonlinearity; V

V

(V)

OUT

= ±5 V, RL = 1 kΩ

S

VS = ±5V
R

= 1kΩ

L

0.6V/DIV

40µV/DIV

ERROR (2ppm/DIV)

00783-012

–10 –2–4–6–8 0246810

Figure 14. Gain Nonlinearity; V

V

(V)

OUT

= ±15 V, RL = 2kΩ

S

VS = ±15V
R

= 2kΩ

L

2V/DIV

00783-015

14.0

13.0

–40°C

12.0

11.0

VS= ±15V

10.0

9.0

–11.5

–12.0

OUTPUT VOLTAGE (V)

–12.5

00783-013

–13.0

–13.5

02468101214161820

–40°C

OUTPUT CURRENT (mA)

Figure 15. Output Voltage Operating R

+85°C

+85°C

ange vs. Output Current; V

–40°C

+25°C

+25°C

= ±15 V

S

00783-016

11.5

10.5
–40°C

9.5

8.5

VS= ±12V

7.5

6.5

–9.0

–9.5

OUTPUT VOLTAGE (V)

–10.0

00783-014

–10.5

–11.0

–40°C

02468101214161820

Figure 16. Output Voltage Operating R

+85°C

+25°C

+85°C

OUTPUT CURRENT (mA)

ange vs. Output Current; V

+85°C

–40°C

+25°C

= ±12 V

S

00783-017

Rev. B | Page 6 of 16

AD629

A

T

T

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4.5

3.5

2.5

1.5

0.5

–40°C

VS= ±5V

+85°C

–40°C

+85°C

+25°C

G = +1

= 2kΩ

R

L

= 1000pF

C

L

–2.0

–2.5

OUTPUT VOLTAGE (V)

Figure 17. Output Voltage Operating R

–40°C

–3.0

–3.5

+25°C

–4.0

02468101214161820

+85°C

OUTPUT CURRENT (mA)

ange vs. Output Current; V

120

+V

S

110

–V

S

100

TIO (dB)

90

80

70

60

50

40

POWER SUPPLY REJECTION R

30

0.1 101.0 100 1k 10k

Figure 18. Power Supply Rejecti

FREQUENCY ( Hz)

on Ratio vs. Frequency

5.0

4.5

4.0

Y (µV/ Hz)

3.5

3.0

2.5

2.0

1.5

1.0

AGE NOISE SPECTRAL DENSI

0.5

VOL

0.01 1.00.1 10010 1k 100k10k
FREQUENCY ( Hz)

Figure 19. Voltage Noise Spectral Density vs. Frequency

+85°C

+25°C

= ±5 V

S

00783-018

25mV/DIV

4µs/DIV

00783-021

Figure 20. Small Signal Pulse Response

G = +1

= 2kΩ

R

L

= 1000pF

C

L

00783-019

25mV/DIV

4µs/DIV

00783-022

Figure 21. Small Signal Pulse Response

G = +1
R

= 2kΩ

L

C

= 1000pF

L

00783-020

5V/DIV

5µs/DIV

00783-023

Figure 22. Large Signal Pulse Response

Rev. B | Page 7 of 16

AD629

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5V/DIV

+10V

V

OUT

0V

OUTPUT
ERROR

1mV/DIV

1mV = 0.01%

10µs/DIV

Figure 23. Settling Time to 0.01%, for 0 V to 10 V Output Step; G = −1, R

350

N = 2180

300

n ≈ 200 PCS. FRO M
10 ASSEMBLY LOTS

250

200

150

NUMBER OF UNITS

100

50

00783-024

= 2 kΩ

L

5V/DIV

0V

V

OUT

–10V

OUTPUT
ERROR

1mV/DIV

1mV = 0.01%

10µs/DIV

Figure 26. Settling Time to 0.01% for 0 V to −10 V Output Step; G = −1, R

300

N = 2180
n ≈ 200 PCS. FRO M

250

10 ASSEMBLY LOTS

200

150

100

NUMBER OF UNIT S

50

00783-027

= 2kΩ

L

0
–150 –50–100 5001100

COMMON-MODE REJECTI ON RATIO (pp m)

00783-025

50

Figure 24. Typical Distribution of Common-Mode Rejection; Package Option N-8

400

N = 2180

350

n ≈ 200 PCS. FRO M
10 ASSEMBLY LOTS

300

250

200

150

NUMBER OF UNIT S

100

50

0
–600 –200–400 20006400

–1 GAIN ERROR (p pm)

00783-026

00

Figure 25. Typical Distribution of −1 Gain Error; Package Option N-8

0

–900 –300–600 30009600

OFFSET VOLTAGE (µV)

00783-028

00

Figure 27. Typical Distribution of Offset Voltage; Package Option N-8

400

N = 2180

350

n ≈ 200 PCS. FRO M
10 ASSEMBLY LOTS

300

250

200

150

NUMBER OF UNITS

100

50

0
–600 –200–400 2000 600400

+1 GAIN ERROR (ppm)

00783-029

Figure 28. Typical Distribution of +1 Gain Error; Package Option N-8

Rev. B | Page 8 of 16

AD629

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THEORY OF OPERATION

The AD629 is a unity gain, differential-to-single-ended
amplifier (diff amp) that can reject extremely high common­mode signals (in excess of 270 V with 15 V supplies). It consists
of an operational amplifier (op amp) and a resistor network.

To achieve high common-mode voltage range, an internal
r

esistor divider (Pin 3 or Pin 5) attenuates the noninverting
signal by a factor of 20. Other internal resistors (Pin 1, Pin 2,
and the feedback resistor) restore the gain to provide a differential
gain of unity. The complete transfer function equals

= V (+IN) − V (−IN)

V

OUT

Laser wafer trimming provides resistor matching so that
co

mmon-mode signals are rejected while differential input

signals are amplified.

To reduce output drift, the op amp uses super beta transistors

its input stage. The input offset current and its associated

in
temperature coefficient contribute no appreciable output
voltage offset or drift, which has the added benefit of reducing
voltage noise because the corner where 1/f noise becomes
dominant is below 5 Hz. To reduce the dependence of gain
accuracy on the op amp, the open-loop voltage gain of the op
amp exceeds 20 million, and the PSRR exceeds 140 dB.

REF(–)

380kΩ

2

–IN

380kΩ

3

+IN

4

–V

S

AD629

NC = NO CONNECT

Figure 29. Functional Block Diagram

21.1kΩ

1

380kΩ

20kΩ

NC

8

7

+V

6

OUTPUT

5

REF(+)

S

0783-001

Rev. B | Page 9 of 16

AD629

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APPLICATIONS

+V

BASIC CONNECTIONS

Figure 30 shows the basic connections for operating the AD629
with a dual supply. A supply voltage of between ±3 V and ±18 V
is applied between Pin 7 and Pin 4. Both supplies should be
decoupled close to the pins using 0.1 µF capacitors. Electrolytic
capacitors of 10 µF, also located close to the supply pins, may be
required if low frequency noise is present on the power supply.
While multiple amplifiers can be decoupled by a single set of
10 µF capacitors, each in amp should have its own set of 0.1 µF
capacitors so that the decoupling point can be located right at
the IC’s power pins.

+

S

+3V TO +18V

NC

8

7

+V

S

6

REF (+)

5

SHUNT

(SEE
TEXT)

× R

SHUNT

0.1µF

V

= I

OUT

I

SHUNT

(SEE
TEXT)

R

SHUNT

REF (–)

–IN

+IN

–V

S

0.1µF

–V

S

–3V TO –18V

AD629

21.1kΩ

1

380kΩ 380kΩ

2

380kΩ

3

4

NC = NO CONNECT

20kΩ

Figure 30. Basic Connections

The differential input signal, which typically results from a load
current flowing through a small shunt resistor, is applied to
Pin 2 and Pin 3 with the polarity shown to obtain a positive
gain. The common-mode range on the differential input signal
can range from −270 V to +270 V, and the maximum differential
range is ±13 V. When configured as shown in

vice operates as a simple gain-of-1, differential-to-single-

de

Figure 30, the

ended amplifier; the output voltage being the shunt resistance
times the shunt current. The output is measured with respect to
Pin 1 and Pin 5.

Pin 1 and Pin 5 (REF(–) and REF(+)) should be grounded for a

in of unity and should be connected to the same low impedance

ga
ground plane. Failure to do this results in degraded common­mode rejection. Pin 8 is a no connect pin and should be left open.

SINGLE-SUPPLY OPERATION

Figure 31 shows the connections for operating the AD629 with
a single supply. Because the output can swing to within only
about 2 V of either rail, it is necessary to apply an offset to the
output. This can be conveniently done by connecting REF(+)
and REF(–) to a low impedance reference voltage (some ADCs
provide this voltage as an output), which is capable of sinking
current. Therefore, for a single supply of 10 V, V
to 5 V for a bipolar input signal. This allows the output to swing
±3 V around the central 5 V reference voltage. Alternatively, for
unipolar input signals, V

can be set to about 2 V, allowing the

REF

output to swing from 2 V (for a 0 V input) to within 2 V of the
positive rail.

may be set

REF

AD629

21.1kΩ

1

380kΩ 380kΩ

2

3

4

V

380kΩ

NC = NO CONNECT

X

V

Y

20kΩ

8

7

6

5

I

SHUNT

R

SHUNT

REF (–)

–IN

+IN

–V

S

V

REF

Figure 31. Operation with a Single Supply

Applying a reference voltage to REF(+) and REF(–) and
operating on a single supply reduces the input common-mode
range of the AD629. The new input common-mode range
depends upon the voltage at the inverting and noninverting
inputs of the internal operational amplifier, labeled V
in Figure 31. These nodes can swing to within 1 V of either rail.
Ther

efore, for a (single) supply voltage of 10 V, V

range between 1 V and 9 V. If V

is set to 5 V, the permissible

REF

common-mode range is +85 V to –75 V. The common-mode

00783-030

voltage ranges can be calculated by

(±) = 20 VX/VY(±) − 19 V

V

CM

REF

SYSTEM-LEVEL DECOUPLING AND GROUNDING

The use of ground planes is recommended to minimize the
impedance of ground returns (and therefore the size of dc
errors). Figure 32 shows how to work with grounding in a
mixe

d-signal environment, that is, with digital and analog
signals present. To isolate low level analog signals from a noisy
digital environment, many data acquisition components have
separate analog and digital ground returns. All ground pins
from mixed-signal components, such as ADCs, should return
through a low impedance analog ground plane. Digital ground
lines of mixed-signal converters should also be connected to the
analog ground plane. Typically, analog and digital grounds
should be separated; however, it is also a requirement to
minimize the voltage difference between digital and analog
grounds on a converter, to keep them as small as possible
(typically <0.3 V). The increased noise, caused by the
converter’s digital return currents flowing through the analog
ground plane, is typically negligible. Maximum isolation
between analog and digital is achieved by connecting the ground
planes back at the supplies. Note that

ound system for the analog circuitry, with all ground lines

gr
being connected, in this case, to the ADC’s analog ground.
However, when ground planes are used, it is sufficient to
connect ground pins to the nearest point on the low impedance
ground plane.

Figure 32 suggests a “star”

NC

+V

S

REF (+)

S

0.1µF

OUTPUT = V

and VY can

X

OUT

and VY

X

– V

REF

00783-031

Rev. B | Page 10 of 16

AD629

–

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+IN

–IN

4

–V

S

3

AD629

2

REF(–) REF(+)

1 5

ANALOG P OWER

–5V

0.1µF0.1µF

7

+V

S

OUTPUT

SUPPLY

+5V GND

6 4

3

1

V

DD

V

IN1

V

IN2

0.1µF

6

AGND

AD7892-2

14

DGND

DIGITAL

POWER SUPPLY

0.1µF

GND

12

MICROPROCESSOR

+5VGND

V

DD

Figure 32. Optimal Grounding Practice for a Bipolar Supply Environment

wi

th Separate Analog and Digital Supplies

POWER SUPPLY

GND

+5V

0.1µF

47

+V

–V

S

+IN

–IN

3

AD629

2

REF(–) REF(+)

S

OUTPUT

1 5

Figure 33. Optimal Ground Pr

6

0.1µF

0.1µF

VDDAGND DGND

V

IN1

V

ADC

IN2

V

DD

MICROPROCESSOR

actice in a Single-Supply Environment

GND

If there is only a single power supply available, it must be shared
by both digital and analog circuitry. Figure 33 shows how to
mini

mize interference between the digital and analog circuitry.
In this example, the ADC’s reference is used to drive Pin REF(+)
and Pin REF(–). This means that the reference must be capable
of sourcing and sinking a current equal to V

/200 k. As in

CM

the previous case, separate analog and digital ground planes
should be used (reasonably thick traces can be used as an
alternative to a digital ground plane). These ground planes
should connect at the power supply’s ground pin. Separate
traces (or power planes) should run from the power supply to
the supply pins of the digital and analog circuits. Ideally, each
device should have its own power supply trace, but these can be
shared by a number of devices, as long as a single trace is not
used to route current to both digital and analog circuitry.

USING A LARGE SENSE RESISTOR

Insertion of a large value shunt resistance across the input pins,
Pin 2 and Pin 3, will imbalance the input resistor network,
introducing a common-mode error. The magnitude of the error
will depend on the common-mode voltage and the magnitude
of R

SHUNT

.

Tabl e 3 shows some sample error voltages generated by a

mmon-mode voltage of 200 V dc with shunt resistors from

co
20  to 2000 . Assuming that the shunt resistor is selected to
use the full ±10 V output swing of the AD629, the error voltage
becomes quite significant as R

Table 3. Error Resulting from

increases.

SHUNT

Large Values of R

SHUNT

(Uncompensated Circuit)

RS (Ω) Error V

(V) Error Indicated (mA)

OUT

20 0.01 0.5

00783-032

1000 0.498 0.498
2000 1 0.5

To measure low current or current near zero in a high common­mode environment, an external resistor equal to the shunt
resistor value can be added to the low impedance side of the
shunt resistor, as shown in Figure 34.

+V

REF (–)

1

R

COMP

–IN

2

I

00783-033

SHUNT

R

SHUNT

+IN

3

–V

S

4

0.1µF

–V

S

AD629

21.1kΩ

380kΩ 380kΩ

380kΩ

20kΩ

NC = NO CONNECT

8

7

6

5

NC

+V

S

V

REF (+)

OUT

S

0.1µF

00783-034

Figure 34. Compensating for Large Sense Resistors

OUTPUT FILTERING

A simple 2-pole, low-pass Butterworth filter can be implemented
using the OP177 after the AD629 to limit noise at the output, as
shown in Figure 35. Tabl e 4 gives recommended component
va

lues for various corner frequencies, along with the peak-to-

peak output noise for each case.

+V

AD629

21.1kΩ

1

380kΩ 380kΩ

2

380kΩ

3

4

NC = NO CON NECT

20kΩ

V

S

0.1µF

REF (–)

–IN

+IN

Figure 35. Filtering of Output Noise Using a 2-Pole Butterworth Filter

S

NC

8

0.1µF 0.1µF

7

+V

S

R1 R2

6

REF (+)

5

C1

+V

S

OP177

C2

0.1µF

–V

S

V

OUT

00783-035

Table 4. Recommended Values for 2-Pole Butterworth Filter

Corner Frequency R1 R2 C1 C2 Output Noise (p-p)

No Filter
50 kHz 2.94 kΩ ± 1% 1.58 kΩ ± 1% 2.2 nF ± 10% 1 nF ± 10% 1 mV
5 kHz 2.94 kΩ ± 1% 1.58 kΩ ± 1% 22 nF ± 10% 10 nF ± 10% 0.32 mV
500 Hz 2.94 kΩ ± 1% 1.58 kΩ ± 1% 220 nF ± 10% 0.1 μF ± 10% 100 μV
50 Hz 2.7 kΩ ± 10% 1.5 kΩ ± 10% 2.2 μF ± 20% 1 μF ± 20% 32 μV

Rev. B | Page 11 of 16

3.2 mV

AD629

–

T

T

www.BDTIC.com/ADI

OUTPUT CURRENT AND BUFFERING

The AD629 is designed to drive loads of 2 kΩ to within 2 V of
the rails but can deliver higher output currents at lower output
voltages (see Figure 15). If higher output current is required, the
o

utput of the AD629 should be buffered with a precision op amp,
such as the OP113, as shown in Figure 36. This op amp can swing
t

o within 1 V of either rail while driving a load as small as 600 Ω.

+V

OP113

–V

S

S

0.1µF

0.1µF

V

OU

00783-036

–IN

+IN

V

S

0.1µF

REF (–)

AD629

21.1kΩ

1

380kΩ 380kΩ

2

380kΩ

3

4

NC = NO CONNECT

20kΩ

8

7

6

5

NC

0.1µF

REF (+)

Figure 36. Output Buffering Application

A GAIN OF 19 DIFFERENTIAL AMPLIFIER

While low level signals can be connected directly to the –IN and
+IN inputs of the AD629, differential input signals can also be
connected, as shown in Figure 37, to give a precise gain of 19.
H

owever, large common-mode voltages are no longer permissible.
Cold junction compensation can be implemented using a
temperature sensor, such as the

REF (–)

THERMOCOUPLE

V

REF

–IN

+IN

AD590.

21.1kΩ

1

380kΩ 380kΩ

2

380kΩ

3

4

AD629

20kΩ

8

7

6

5

NC

+V

S

REF (+)

+V

S

0.1µF

V

OU

ERROR BUDGET ANALYSIS EXAMPLE 1

In the dc application that follows, the 10 A output current from
a device with a high common-mode voltage (such as a power
supply or current-mode amplifier) is sensed across a 1 Ω shunt
resistor (see

nd the resistor terminals are connected through a long pair of

a
lead wires located in a high noise environment, for example,
50 Hz/60 Hz, 440 V ac power lines. The calculations in

sume an induced noise level of 1 V at 60 Hz on the leads, in

as
addition to a full-scale dc differential voltage of 10 V. The error
budget table quantifies the contribution of each error source.
Note that the dominant error source in this example is due to
the dc common-mode voltage.

OUTPUT

CURRENT

1Ω

SHUNT

V

Figure 38). The common-mode voltage is 200 V,

10 AMPS

DC

200V

CM

TO GROUND

60Hz

POWER LI NE

REF (–)

–IN

+IN

–V

S

0.1µF

Figure 38. Error Budget Analysis Example 1: V

= 200 V DC, R

CM

= 1 Ω, 1 V p-p, 60 Hz Power-Line Interference

SHUNT

AD629

21.1kΩ

1

380kΩ 380kΩ

2

380kΩ

3

4

20kΩ

NC = NO CONNECT

= 10 V Full-Scale,

IN

8

7

6

5

NC

REF (+)

Tabl e 5

+V

0.1µF

V

OUT

S

00783-038

NC = NO CONNEC T

00783-037

Figure 37. A Gain of 19 Thermocouple Amplifier

Table 5. AD629 vs. INA117 Error Bud

get Analysis Example 1 (V

= 200 V dc)

CM

Error, ppm of FS

Error Source AD629 INA117 AD629 INA117

ACCURACY, TA = 25°C

Initial Gain Error (0.0005 × 10)/10 V × 10
Offset Voltage (0.001 V/10 V) × 10
DC CMR (Over Temperature) (224 × 10-6 × 200 V)/10 V × 10

6

6

(0.0005 × 10)/10 V × 10
(0.002 V/10 V) × 10

6

(500 × 10-6 × 200 V)/10 V × 10

Total Accurac y Error

6

6

500 500
100 200

6

4480 10,000
5080 10,700

TEMPERATURE DRIFT (85°C)

Gain 10 ppm/°C × 60°C 10 ppm/°C × 60°C 600 600
Offset Voltage (20 μV/°C × 60°C) × 106/10 V (40 μV/°C × 60°C) × 106/10 V 120 240

Total Drift Error

720 840

RESOLUTION

Noise, Typical, 0.01 Hz to 10 Hz, μV p-p 15 μV/10 V × 10
CMR, 60 Hz (141 × 10-6 × 1 V)/10 V × 10
Nonlinearity (10-5 × 10 V)/10 V × 10

6

6

6

25 μV/10 V × 10
(500 × 10-6 × 1 V)/10 V × 10
(10-5 × 10 V)/10 V × 10

Total Resolution Error
Total Erro r

Rev. B | Page 12 of 16

6

6

6

2 3
14 50
10 10
26 63
5826 11,603

AD629

www.BDTIC.com/ADI

ERROR BUDGET ANALYSIS EXAMPLE 2

This application is similar to the previous example except
that the sensed load current is from an amplifier with an ac
common-mode component of ±100 V (frequency = 500 Hz)
present on the shunt (see

e same as before. Note that the same kind of power-line

th
interference can happen as detailed in Example 1. However,
the ac common-mode component of 200 V p-p coming from
the shunt is much larger than the interference of 1 V p-p;
therefore, this interference component can be neglected.

Figure 39). All other conditions are

OUTPUT

CURRENT

10 AMPS
±100V AC CM
TO GROUND

1Ω

SHUNT

60Hz

POWER LI NE

Figure 39. Error Budget Analysis Example 2: V

V

CM

REF (–)

–IN

+IN

–V

S

0.1µF

= ±100 V at 500 Hz, R

AD629

21.1kΩ

1

380kΩ 380kΩ

2

380kΩ

3

SHUNT

20kΩ

IN

=1 Ω

4

NC = NO CONNECT

NC

8

7

0.1µF

6

REF (+)

5

= 10 V Full-Scale,

+V

V

OUT

S

00783-039

Table 6. AD629 vs. INA117 AC Error Budget Example 2 (V

= ±100 V @ 500 Hz)

CM

Error, ppm of FS

Error Source AD629 INA117 AD629 INA117

ACCURACY, TA = 25°C

Initial Gain Error (0.0005 × 10)/10 V × 10
Offset Voltage (0.001 V/10 V) × 10

6

6

(0.0005 × 10)/10 V × 10
(0.002 V/10 V) × 10

Total Accurac y Error

6

6

500 500
100 200
600 700

TEMPERATURE DRIFT (85°C)

Gain 10 ppm/°C × 60°C 10 ppm/°C × 60°C 600 600
Offset Voltage (20 μV/°C × 60°C) × 106/10 V (40 μV/°C × 60°C) × 106/10 V 120 240

Total Drift Error

720 840

RESOLUTION

Noise, Typical, 0.01 Hz to 10 Hz, μV p-p 15 μV/10 V × 10
CMR, 60 Hz (141 × 10-6 × 1 V)/10 V × 10
Nonlinearity (10-5 × 10 V)/10 V × 10
AC CMR @ 500 Hz (141 × 10-6 × 200 V)/10 V × 10

6

6

6

25 μV/10 V × 10
(500 × 10-6 × 1 V)/10 V × 10
(10-5 × 10 V)/10 V × 10

6

(500 × 10-6 × 200 V)/10 V × 10

Total Resolution Error
Total Erro r

6

6

6

2 3
14 50
10 10

6

2820 10,000
2846 10,063
4166 11,603

Rev. B | Page 13 of 16

AD629

www.BDTIC.com/ADI

OUTLINE DIMENSIONS

0.400 (10.16)

0.365 (9.27)

0.355 (9.02)

0.210 (5.33)

0.150 (3.81)

0.130 (3.30)

0.115 (2.92)

0.022 (0.56)

0.018 (0.46)

0.014 (0.36)

MAX

8

1

0.100 (2.54)

0.070 (1.78)

0.060 (1.52)

0.045 (1.14)

BSC

5

4

0.280 (7. 11)

0.250 (6.35)

0.240 (6.10)

0.015
(0.38)
MIN

SEATING
PLANE

0.005 (0.13)
MIN

0.060 (1.52)
MAX

0.015 (0.38)
GAUGE

PLANE

0.325 (8.26)

0.310 (7.87)

0.300 (7.62)

0.430 (10.92)
MAX

0.195 (4.95)

0.130 (3.30)

0.115 (2.92)

0.014 (0.36)

0.010 (0.25)

0.008 (0.20)

CONTROLLING DIMENSIONSARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ON LY AND ARE NOT APPRO PRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.

COMPLIANT TO JEDEC STANDARDS MS-001

070606-A

Figure 40. 8-Lead Plastic Dual In-Line Package [PDIP]

(N-8)

Dim

ensions shown in inches and (millimeters)

5.00 (0.1968)

4.80 (0.1890)

4.00 (0.1574)

3.80 (0.1497)

0.25 (0.0098)

0.10 (0.0040)

COPLANARITY

0.10

CONTROLL ING DIMENSI ONS ARE IN MILLIMETERS; INCH DI MENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRI ATE FOR USE IN DES IGN.

85

1

1.27 (0.0500)

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MS-012-A A

BSC

6.20 (0.2441)

5.80 (0.2284)

4

1.75 (0.0688)

1.35 (0.0532)

0.51 (0.0201)

0.31 (0.0122)

8°
0°

0.25 (0.0098)

0.17 (0.0067)

0.50 (0.0196)

0.25 (0.0099)

1.27 (0.0500)

0.40 (0.0157)

⋅ 45°

012407-A

Figure 41. 8-Lead Standard Small Outline Package [SOIC_N]

(R-8)

Dim

ensions shown in millimeters and (inches)

Rev. B | Page 14 of 16

AD629

www.BDTIC.com/ADI

ORDERING GUIDE

Model Temperature Range Package Description Package Option

AD629AN –40°C to +85°C 8-Lead PDIP N-8
AD629ANZ
AD629AR –40°C to +85°C 8-Lead SOIC_N R-8
AD629AR-REEL –40°C to +85°C 8-Lead SOIC_N R-8
AD629AR-REEL7 –40°C to +85°C 8-Lead SOIC_N R-8
AD629ARZ1 –40°C to +85°C 8-Lead SOIC_N R-8
AD629ARZ-RL1 –40°C to +85°C 8-Lead SOIC_N, 13-Inch Tape and Reel, 2,500 pieces R-8
AD629ARZ-R7
AD629BN –40°C to +85°C 8-Lead PDIP N-8
AD629BNZ
AD629BR –40°C to +85°C 8-Lead SOIC_N R-8
AD629BR-REEL –40°C to +85°C 8-Lead SOIC_N, 13-Inch Tape and Reel, 2,500 pieces R-8
AD629BR-REEL7 –40°C to +85°C 8-Lead SOIC_N, 7-Inch Tape and Reel, 1,000 pieces R-8
AD629BRZ
AD629BRZ-RL
AD629BRZ-R7
AD629-EVAL Evaluation Board

1

Z = RoHS compliant part.

1

1

1

1

1

1

–40°C to +85°C 8-Lead PDIP N-8

–40°C to +85°C 8-Lead SOIC_N, 7-Inch Tape and Reel, 1,000 pieces R-8

–40°C to +85°C 8-Lead PDIP N-8

–40°C to +85°C 8-Lead SOIC_N R-8
–40°C to +85°C 8-Lead SOIC_N, 13-Inch Tape and Reel, 2,500 pieces R-8
–40°C to +85°C 8-Lead SOIC_N, 7-Inch Tape and Reel, 1,000 pieces R-8

Rev. B | Page 15 of 16

AD629

www.BDTIC.com/ADI

NOTES

©1999-2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00783-0-2/07(B)

Rev. B | Page 16 of 16