Datasheet AD624ADZ Specification

Precision

a

FEATURES
Low Noise: 0.2 ␮V p-p 0.1 Hz to 10 Hz
Low Gain TC: 5 ppm max (G = 1)
Low Nonlinearity: 0.001% max (G = 1 to 200)
High CMRR: 130 dB min (G = 500 to 1000)
Low Input Offset Voltage: 25 ␮V, max
Low Input Offset Voltage Drift: 0.25 ␮V/ⴗC max
Gain Bandwidth Product: 25 MHz
Pin Programmable Gains of 1, 100, 200, 500, 1000
No External Components Required
Internally Compensated

PRODUCT DESCRIPTION

The AD624 is a high precision, low noise, instrumentation
amplifier designed primarily for use with low level transducers,
including load cells, strain gauges and pressure transducers. An
outstanding combination of low noise, high gain accuracy, low
gain temperature coefficient and high linearity make the AD624
ideal for use in high resolution data acquisition systems.

The AD624C has an input offset voltage drift of less than

0.25 µV/°C, output offset voltage drift of less than 10 µV/°C,
CMRR above 80 dB at unity gain (130 dB at G = 500) and a
maximum nonlinearity of 0.001% at G = 1. In addition to these
outstanding dc specifications, the AD624 exhibits superior ac
performance as well. A 25 MHz gain bandwidth product, 5 V/µs
slew rate and 15 µs settling time permit the use of the AD624 in
high speed data acquisition applications.

The AD624 does not need any external components for pre­trimmed gains of 1, 100, 200, 500 and 1000. Additional gains
such as 250 and 333 can be programmed within one percent
accuracy with external jumpers. A single external resistor can
also be used to set the 624’s gain to any value in the range of 1
to 10,000.

Instrumentation Amplifier

AD624

FUNCTIONAL BLOCK DIAGRAM

225.3⍀

124⍀

80.2⍀

50⍀

50⍀

4445.7⍀

V

B

20k⍀ 10k⍀

20k⍀ 10k⍀

AD624

10k⍀

10k⍀

SENSE

OUTPUT

REF

–INPUT

G = 100

G = 200

G = 500

RG

1

RG

2

+INPUT

PRODUCT HIGHLIGHTS

1. The AD624 offers outstanding noise performance. Input

noise is typically less than 4 nV/√Hz at 1 kHz.

2. The AD624 is a functionally complete instrumentation am­plifier. Pin programmable gains of 1, 100, 200, 500 and 1000
are provided on the chip. Other gains are achieved through
the use of a single external resistor.

3. The offset voltage, offset voltage drift, gain accuracy and gain
temperature coefficients are guaranteed for all pretrimmed
gains.

4. The AD624 provides totally independent input and output
offset nulling terminals for high precision applications.
This minimizes the effect of offset voltage in gain ranging
applications.

5. A sense terminal is provided to enable the user to minimize
the errors induced through long leads. A reference terminal is
also provided to permit level shifting at the output.

REV. C

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © Analog Devices, Inc., 1999

IMPORTANT LINKS for the AD624*

Last content update 05/09/2013 04:44 pm

PARAMETRIC SELECTION TABLES

Find Similar Products By Operating Parameters

DOCUMENTATION

AD624: Military Data Sheet

AN-244: A User's Guide to I.C. Instrumentation Amplifiers
AN-245: Instrumentation Amplifiers Solve Unusual Design Problems
AN-671: Reducing RFI Rectification Errors in In-Amp Circuits
AN-589: Ways to Optimize the Performance of a Difference Amplifier

A Designer's Guide to Instrumentation Amplifiers (3rd Edition)
Auto-Zero Amplifiers
High-performance Adder Uses Instrumentation Amplifiers
Input Filter Prevents Instrumentation-amp RF-Rectification Errors
The AD8221 - Setting a New Industry Standard for Instrumentation

Amplifiers
Applying Instrumentation Amplifiers Effectively: The Importance of an

Input Ground Return
Leading Inside Advertorials: Applying Instrumentation Amplifiers

Effectively–The Importance of an Input Ground Return

DESIGN TOOLS, MODELS, DRIVERS & SOFTWARE

In-Amp Error Calculator

These tools will help estimate error contributions in your
instrumentation amplifier circuit. It uses input parameters such as
temperature, gain, voltage input, and source impedance to determine
the errors that can contribute to your overall design.

AD624SPICE Macro-Model
AD624A SPICE Macro-Model
AD624B SPICE Macro-Model
AD624C SPICE Macro-Model
AD624S SPICE Macro-Model

DESIGN COLLABORATION COMMUNITY

Collaborate Online with the ADI support team and other designers

about select ADI products.

Follow us on Twitter: www.twitter.com/ADI_News
Like us on Facebook: www.facebook.com/AnalogDevicesInc

DESIGN SUPPORT

Submit your support request here:

Linear and Data Converters
Embedded Processing and DSP

Telephone our Customer Interaction Centers toll free:

Americas: 1-800-262-5643
Europe: 00800-266-822-82
China: 4006-100-006
India: 1800-419-0108
Russia: 8-800-555-45-90

Quality and Reliability
Lead(Pb)-Free Data

SAMPLE & BUY

AD624

View Price & Packaging
Request Evaluation Board
Request Samples Check Inventory & Purchase

Find Local Distributors

Powered by TCPDF (www.tcpdf.org)

EVALUATION KITS & SYMBOLS & FOOTPRINTS

Symbols and Footprints

Note: Dynamic changes to the content on this page (labeled 'Important Links') does not

constitute a change to the revision number of the product data sheet.

* This page was dynamically generated by Analog Devices, Inc. and inserted into this data sheet.

This content may be frequently modified.

AD624–SPECIFICATIONS

Model AD624A AD624B AD624C AD624S

GAIN

Gain Equation

(External Resistor Gain
Programming)

Gain Range (Pin Programmable) 1 to 1000 1 to 1000 1 to 1000 1 to 1000
Gain Error

G = 1
G = 100
G = 200, 500

Nonlinearity

G = 1 ±0.005 ±0.003 ±0.001 ±0.005 %
G = 100, 200 ±0.005 ±0.003 ±0.001 ±0.005 %
G = 500 ±0.005 ±0.005 ±0.005 ±0.005 %

Gain vs. Temperature

G = 1 5 5 5 5 ppm/°C
G = 100, 200 10 10 10 10 ppm/°C
G = 500 25 15 15 15 ppm/°C

VOLTAGE OFFSET (May be Nulled)

Input Offset Voltage 200 75 25 75 µV

vs. Temperature 2 0.5 0.25 2.0 µV/°C

Output Offset Voltage 5323mV

vs. Temperature 50 25 10 50 µV/°C

OUT

Offset Referred to the Input vs. Supply

G = 1 70 75 80 75 dB
G = 100, 200 95 105 110 105 dB
G = 500 100 110 115 110 dB

INPUT CURRENT

Input Bias Current

vs. Temperature ±50 ± 50 ±50 ± 50 pA/°C

Input Offset Current

vs. Temperature ±20 ± 20 ±20 ± 20 pA/°C

INPUT

Input Impedance

Differential Resistance 10
Differential Capacitance 10 10 10 10 pF
Common-Mode Resistance 10
Common-Mode Capacitance 10 10 10 10 pF

Input Voltage Range

Max Differ. Input Linear (VDL) ± 10 ±10 ± 10 ± 10 V

Max Common-Mode Linear (V

Common-Mode Rejection dc
to 60 Hz with 1 kΩ Source Imbalance

G = 1 70 75 80 70 dB
G = 100, 200 100 105 110 100 dB
G = 500 110 120 130 110 dB

OUTPUT RATING

V

, RL = 2 kΩ±10 ±10 ± 10 ±10 V

DYNAMIC RESPONSE

Small Signal –3 dB

G = 1 1111MHz
G = 100 150 150 150 150 kHz
G = 200 100 100 100 100 kHz
G = 500 50 50 50 50 kHz
G = 1000 25 25 25 25 kHz

Slew Rate 5.0 5.0 5.0 5.0 V/µs
Settling Time to 0.01%, 20 V Step

G = 1 to 200 15 15 15 15 µs
G = 500 35 35 35 35 µs
G = 1000 75 75 75 75 µs

NOISE

Voltage Noise, 1 kHz

R.T.I. 4 4 4 4 nV/√Hz
R.T.O. 75 75 75 75 nV/√Hz

R.T.I., 0.1 Hz to 10 Hz

G = 1 10101010µV p-p
G = 100 0.3 0.3 0.3 0.3 µV p-p
G = 200, 500, 1000 0.2 0.2 0.2 0.2 µV p-p

Current Noise

0.1 Hz to 10 Hz 60 60 60 60 pA p-p

SENSE INPUT

R

IN

I

IN

Voltage Range ±10 ±10 ± 10 ±10 V
Gain to Output 1 1 1 1 %

1

Min Typ Max Min Typ Max Min Typ Max Min Typ Max Units



40, 000



R

G



9

9

12 V −

)

CM

8 10 12 8 10 12 8 10 12 8 10 12 kΩ

30 30 30 30 µA

(@ VS = ⴞ15 V, RL = 2 k⍀ and TA = +25ⴗC, unless otherwise noted)



+ 1

± 20%




±

0.05

±

0.25

±

0.5

±

50

±

35

G








× V



D

2





40, 000




12 V −



+ 1

± 20%



R

G



±

0.03

±

0.15

±

0.35

±

25

±

15

9

10

9

10

G








× V



D

2





40, 000




12 V −



+ 1



R

G



9

10

9

10

G



× V



2



± 20%

±

0.02

±

0.1

±

0.25

±

15

±

10

D



40, 000






12 V −






+ 1

± 20%



R

G



±

0.05 %

±

0.25 %

±

0.5 %

±

50 nA

±

35 nA

9

10

9

10

G



× V



2



Ω

Ω




V

D



–2–

REV. C

AD624

–INPUT

+INPUT

RG

1

OUTPUT NULL

INPUT NULL

REF

–V

S

G = 200

G = 500

SENSE

RG

2

INPUT NULL

OUTPUT NULL

G = 100

+V

S

OUTPUT

1

2

5

6

7

3

4

8

16

15

12

11

10

14

13

9

TOP VIEW

(Not to Scale)

AD624

SHORT TO
RG

2

FOR
DESIRED
GAIN

FOR GAINS OF 1000 SHORT RG1 TO PIN 12
AND PINS 11 AND 13 TO RG

2

Model AD624A AD624B AD624C AD624S

REFERENCE INPUT

R

IN

I

IN

Voltage Range ± 10 ±10 ± 10 ±10 V
Gain to Output 1 1 1 1 %

Min Typ Max Min Typ Max Min Typ Max Min Typ Max Units

16 20 24 16 20 24 16 20 24 16 20 24 kΩ

30 30 30 30 µA

TEMPERATURE RANGE

Specified Performance –25 +85 –25 +85 –25 +85 –55 +125 °C
Storage –65 +150 –65 +150 –65 +150 –65 +150 °C

POWER SUPPLY

Power Supply Range

ⴞ

6

ⴞ

15

ⴞ

18

ⴞ

6

ⴞ

15

ⴞ

18

ⴞ

6

ⴞ

15

ⴞ

18

ⴞ

6

ⴞ

15

ⴞ

18 V

Quiescent Current 3.5 5 3.5 5 3.5 5 3.5 5 mA

NOTES

1

VDL is the maximum differential input voltage at G = 1 for specified nonlinearity, VDL at other gains = 10 V/G. VD = actual differential input voltage.

1

Example: G = 10, VD = 0.50. VCM = 12 V – (10/2 × 0.50 V) = 9.5 V.
Specifications subject to change without notice.
Specifications shown in boldface are tested on all production unit at final electrical test. Results from those tests are used to calculate outgoing quality levels. All min

and max specifications are guaranteed, although only those shown in boldface are tested on all production units.

ABSOLUTE MAXIMUM RATINGS*

CONNECTION DIAGRAM

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18 V

Internal Power Dissipation . . . . . . . . . . . . . . . . . . . . . 420 mW

Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± V

Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . ±V

S

S

Output Short Circuit Duration . . . . . . . . . . . . . . . . Indefinite

Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C

Operating Temperature Range

AD624A/B/C . . . . . . . . . . . . . . . . . . . . . . . –25°C to +85°C

AD624S . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C

Lead Temperature (Soldering, 60 secs) . . . . . . . . . . . . +300°C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

METALIZATION PHOTOGRAPH

ORDERING GUIDE

Contact factory for latest dimensions

Dimensions shown in inches and (mm).

Temperature Package Package

Model Range Description Option

AD624AD –25°C to +85°C 16-Lead Ceramic DIP D-16
AD624BD –25°C to +85°C 16-Lead Ceramic DIP D-16
AD624CD –25°C to +85°C 16-Lead Ceramic DIP D-16
AD624SD –55°C to +125°C 16-Lead Ceramic DIP D-16
AD624SD/883B* –55°C to +125°C 16-Lead Ceramic DIP D-16
AD624AChips –25°C to +85°CDie
AD624SChips –25°C to +85°CDie

*See Analog Devices’ military data sheet for 883B specifications.

REV. C –3–

AD624–Typical Characteristics

0

500

100

10

1

1

10 10M1M100k10k1k100

FREQUENCY – Hz

GAIN – V/V

20

15

+25ⴗC

10

5

INPUT VOLTAGE RANGE – ⴞV

0

0

5

SUPPLY VOLTAGE – ⴞV

10

15

20

Figure 1. Input Voltage Range vs.
Supply Voltage, G = 1

8.0

6.0

4.0

2.0

AMPLIFIER QUIESCENT CURRENT – mA

0

0

5

SUPPLY VOLTAGE – ⴞV

1510

20

Figure 4. Quiescent Current vs.
Supply Voltage

20

15

10

5

OUTPUT VOLTAGE SWING – ⴞV

0

0

SUPPLY VOLTAGE – ⴞV

10

5

15

20

Figure 2. Output Voltage Swing vs.
Supply Voltage

16

14

12

10

8

6

4

INPUT BIAS CURRENT – ⴞnA

2

0

SUPPLY VOLTAGE – ⴞV

10

50

15

20

Figure 5. Input Bias Current vs.
Supply Voltage

30

20

10

OUTPUT VOLTAGE SWING – V p-p

0

10

100 10k1k

LOAD RESISTANCE – ⍀

Figure 3. Output Voltage Swing vs.
Load Resistance

40

30

20

10

0

–10

–20

INPUT BIAS CURRENT – nA

–30

–40

–125

–75

TEMPERATURE – ⴗC

7525–25

125

Figure 6. Input Bias Current vs.
Temperature

16

14

12

10

8

6

4

INPUT BIAS CURRENT – ⴞnA

2

0

10

50

INPUT VOLTAGE – ⴞV

Figure 7. Input Bias Current vs. CMV

–1

0

1

2

3

4

5

⌬VOS FROM FINAL VALUE – ␮V

6

15

20

7

1.00
WARM-UP TIME – Minutes

8.0

7.06.05.04.03.02.0

Figure 8. Offset Voltage, RTI, Turn

Figure 9. Gain vs. Frequency

On Drift

–4–

REV. C

AD624

–140

G = 500

–120

G = 100

–100

G = 1

–80

–60

CMRR – dB

–40

–20

0

1

10 10M1M100k10k1k100

FREQUENCY – Hz

Figure 10. CMRR vs. Frequency RTI,
Zero to 1k Source Imbalance

160

–VS = –15V dc+
1V p-p SINEWAVE

G = 100

G = 1

FREQUENCY – Hz

10k1k100

100k

POWER SUPPLY REJECTION – dB

140

120

100

G = 500

80

60

40

20

0

10

Figure 13. Negative PSRR vs.
Frequency

30

20

G = 1, 100

G = 100

10

FULL-POWER RESPONSE – V p-p

0

G = 500

G = 1000

BANDWIDTH LIMITED

10k1k 100k 1M
FREQUENCY – Hz

Figure 11. Large Signal Frequency
Response

1000

100

10

VOLT NSD – nV/ Hz

1

0.1

G = 1

G = 10

G = 100, 1000

FREQUENCY – Hz

G = 1000

100k101 10k1k100

Figure 14. RTI Noise Spectral
Density vs. Gain

160

140

120

100

-

POWER SUPPLY REJECTION – dB

G = 500

80

60

40

20

0

10

FREQUENCY – Hz

–VS = –15V dc+
1V p-p SINEWAVE

G = 100

G = 1

10k1k100

100k

Figure 12. Positive PSRR vs.
Frequency

100k

10k

1000

100

10

CURRENT NOISE SPECTRAL DENSITY – fA/ Hz

FREQUENCY – Hz

100k10.1 10k10010

Figure 15. Input Current Noise

Figure 16. Low Frequency Voltage

G = 1 (System Gain = 1000)

Noise

,

REV. C

Figure 17. Low Frequency Voltage
Noise, G = 1000 (System Gain =
100,000)

–5–

–12 TO 12

–8 TO 8

–4 TO 4

OUTPUT
STEP –V

4 TO –4

8 TO –8

12 TO –12

0

1%

1%

SETTLING TIME – ␮s

0.1% 0.01%

0.1% 0.01%

15105

Figure 18. Settling Time, Gain = 1

20

AD624

Figure 19. Large Signal Pulse
Response and Settling Time, G = 1

–12 TO 12

–8 TO 8

–4 TO 4

OUTPUT
STEP –V

4 TO –4

8 TO –8

12 TO –12

0

0.1%

1%

1%

SETTLING TIME – ␮s

0.1%

0.01%

0.01%

15105

Figure 20. Settling Time Gain = 100

–12 TO 12

–8 TO 8

–4 TO 4

OUTPUT
STEP –V

4 TO –4

8 TO –8

12 TO –12

1%

1%

0.1%

0.1%

0.01%

0.01%

20

Figure 21. Large Signal Pulse
Response and Settling Time,
G = 100

Figure 22. Range Signal Pulse
Response and Settling Time,
G = 500

0

SETTLING TIME – ␮s

15105

Figure 23. Settling Time Gain = 1000

20

Figure 24. Large Signal Pulse
Response and Settling Time,
G = 1000

–6–

REV. C

INPUT

20V p-p

100k⍀

1%

1k⍀

0.1%

10k⍀

1%

RG

1

G = 100

500⍀

0.1%

200⍀

0.1%

G = 200

G = 500

RG

2

AD624

Figure 25. Settling Time Test Circuit

AD624

10k⍀

1k⍀

10T

+V

S

–V

S

1%

V

OUT

THEORY OF OPERATION

The AD624 is a monolithic instrumentation amplifier based on
a modification of the classic three-op-amp instrumentation
amplifier. Monolithic construction and laser-wafer-trimming
allow the tight matching and tracking of circuit components and
the high level of performance that this circuit architecture is ca­pable of.

A preamp section (Q1–Q4) develops the programmed gain by
the use of feedback concepts. Feedback from the outputs of A1
and A2 forces the collector currents of Q1–Q4 to be constant
thereby impressing the input voltage across R

The gain is set by choosing the value of R

.

G

from the equation,

G

40 k

Gain =

ance of the input preamp stage increasing it asymptotically to
the transconductance of the input transistors as R

+ 1. The value of RG also sets the transconduct-

R

G

is reduced

G

for larger gains. This has three important advantages. First, this
approach allows the circuit to achieve a very high open loop gain
of 3 × 10

8

at a programmed gain of 1000 thus reducing gain
related errors to a negligible 3 ppm. Second, the gain bandwidth
product which is determined by C3 or C4 and the input trans­conductance, reaches 25 MHz. Third, the input voltage noise
reduces to a value determined by the collector current of the
input transistors for an RTI noise of 4 nV/√Hz at G ≥ 500.

+V

S

+V

S

1/2

AD712

9.09k⍀

G1, 100, 200

100⍀

1k⍀

1␮F

AD712

1.62M⍀

1/2

–V

1␮F

S

1.82k⍀

16.2k⍀

RG

100

200

500

AD624

2

–V

S

16.2k⍀

1␮F

G500

Figure 26. Noise Test Circuit

The AD524 should be considered in applications that require
protection from severe input overload. If this is not possible,
external protection resistors can be put in series with the inputs
of the AD624 to augment the internal (50 Ω) protection resis­tors. This will most seriously degrade the noise performance.
For this reason the value of these resistors should be chosen to
be as low as possible and still provide 10 mA of current limiting
under maximum continuous overload conditions. In selecting
the value of these resistors, the internal gain setting resistor and
the 1.2 volt drop need to be considered. For example, to pro­tect the device from a continuous differential overload of 20 V
at a gain of 100, 1.9 kΩ of resistance is required. The internal
gain resistor is 404 Ω; the internal protect resistor is 100 Ω.
There is a 1.2 V drop across D1 or D2 and the base-emitter
junction of either Q1 and Q3 or Q2 and Q4 as shown in Figure
27, 1400 Ω of external resistance would be required (700 Ω in
series with each input). The RTI noise in this case would be

4 KTR

–IN

50⍀

+(4 nV / Hz )2= 6. 2 nV / Hz

ext

+V

S

50␮A

I1
50␮A

C3

Q1, Q3

13

4445⍀

A1

R57
20k⍀

80.2⍀

124⍀

225.3⍀

RG

VB

RG

1

2

500

200

100

–V

A2

C4

R56
20k⍀

50␮A

S

I2
50␮A

Q2,

Q4

I4

R53

10k⍀

R54

10k⍀

50⍀

R52

10k⍀

A3

R55

10k⍀

SENSE

V

O

REF

+IN

Figure 27. Simplified Circuit of Amplifier; Gain Is Defined
as (R56 + R57)/(R

) + 1. For a Gain of 1, RG Is an Open

G

Circuit.

INPUT CONSIDERATIONS

Under input overload conditions the user will see RG + 100 Ω
and two diode drops (~1.2 V) between the plus and minus
inputs, in either direction. If safe overload current under all
conditions is assumed to be 10 mA, the maximum overload
voltage is ~ ±2.5 V. While the AD624 can withstand this con­tinuously, momentary overloads of ±10 V will not harm the
device. On the other hand the inputs should never exceed the
supply voltage.

REV. C

INPUT OFFSET AND OUTPUT OFFSET

Voltage offset specifications are often considered a figure of
merit for instrumentation amplifiers. While initial offset may
be adjusted to zero, shifts in offset voltage due to temperature
variations will cause errors. Intelligent systems can often correct
for this factor with an autozero cycle, but there are many small­signal high-gain applications that don’t have this capability.

Voltage offset and offset drift each have two components; input
and output. Input offset is that component of offset that is

–7–

AD624

directly proportional to gain i.e., input offset as measured at
the output at G = 100 is 100 times greater than at G = 1.
Output offset is independent of gain. At low gains, output offset
drift is dominant, while at high gains input offset drift domi­nates. Therefore, the output offset voltage drift is normally
specified as drift at G = 1 (where input effects are insignificant),
while input offset voltage drift is given by drift specification at a
high gain (where output offset effects are negligible). All input­related numbers are referred to the input (RTI) which is to say
that the effect on the output is “G” times larger. Voltage offset
vs. power supply is also specified at one or more gain settings
and is also RTI.

By separating these errors, one can evaluate the total error inde­pendent of the gain setting used. In a given gain configura­tion both errors can be combined to give a total error referred to
the input (R.T.I.) or output (R.T.O.) by the following formula:

Total Error R.T.I. = input error + (output error/gain)
Total Error R.T.O. = (Gain × input error) + output error

As an illustration, a typical AD624 might have a +250 µV out­put offset and a –50 µV input offset. In a unity gain configura-
tion, the total output offset would be 200 µV or the sum of the
two. At a gain of 100, the output offset would be –4.75 mV
or: +250 µV + 100 (–50 µV) = –4.75 mV.

The AD624 provides for both input and output offset adjust­ment. This optimizes nulling in very high precision applications
and minimizes offset voltage effects in switched gain applica­tions. In such applications the input offset is adjusted first at the
highest programmed gain, then the output offset is adjusted at
G = 1.

GAIN

The AD624 includes high accuracy pretrimmed internal
gain resistors. These allow for single connection program­ming of gains of 1, 100, 200 and 500. Additionally, a variety
of gains including a pretrimmed gain of 1000 can be achieved
through series and parallel combinations of the internal resis­tors. Table I shows the available gains and the appropriate
pin connections and gain temperature coefficients.

The gain values achieved via the combination of internal
resistors are extremely useful. The temperature coefficient of the
gain is dependent primarily on the mismatch of the temperature
coefficients of the various internal resistors. Tracking of these
resistors is extremely tight resulting in the low gain TCs shown
in Table I.

If the desired value of gain is not attainable using the inter­nal resistors, a single external resistor can be used to achieve
any gain between 1 and 10,000. This resistor connected between

+V

–INPUT

+INPUT

G = 100

G = 200

G = 500

RG

RG

S

1

AD624

2

–V

10k⍀

S

INPUT
OFFSET
NULL

OUTPUT
SIGNAL
COMMON

V

OUT

Figure 28. Operating Connections for G = 200

Table I.

Temperature
Gain Coefficient Pin 3
(Nominal) (Nominal) to Pin Connect Pins

1 –0 ppm/°C ––
100 –1.5 ppm/°C13 –
125 –5 ppm/°C 13 11 to 16
137 –5.5 ppm/°C 13 11 to 12

186.5 –6.5 ppm/°C 13 11 to 12 to 16
200 –3.5 ppm/°C12 –
250 –5.5 ppm/°C 12 11 to 13
333 –15 ppm/°C 12 11 to 16
375 –0.5 ppm/°C 12 13 to 16
500 –10 ppm/°C11–
624 –5 ppm/°C 11 13 to 16
688 –1.5 ppm/°C 11 11 to 12; 13 to 16
831 +4 ppm/°C 11 16 to 12
1000 0 ppm/°C 11 16 to 12; 13 to 11

Pins 3 and 16 programs the gain according to the formula

40k

RG=

G −1

(see Figure 29). For best results RG should be a precision resis­tor with a low temperature coefficient. An external R

affects both

G

gain accuracy and gain drift due to the mismatch between it and
the internal thin-film resistors R56 and R57. Gain accuracy is
determined by the tolerance of the external R

and the absolute

G

accuracy of the internal resistors (±20%). Gain drift is determined
by the mismatch of the temperature coefficient of R

and the tem-

G

perature coefficient of the internal resistors (–15 ppm/°C typ),
and the temperature coefficient of the internal interconnections.

+V

S

AD624

G = + 1 = 20 ⴞ20%

–V

S

40.000

2.105

V

REFERENCE

OUT

1.5k⍀

1k⍀

–INPUT

OR

+INPUT

RG

2.105k⍀

RG

1

2

Figure 29. Operating Connections for G = 20

The AD624 may also be configured to provide gain in the out­put stage. Figure 30 shows an H pad attenuator connected to
the reference and sense lines of the AD624. The values of R1,
R2 and R3 should be selected to be as low as possible to mini­mize the gain variation and reduction of CMRR. Varying R2
will precisely set the gain without affecting CMRR. CMRR is
determined by the match of R1 and R3.

+V

–INPUT

+INPUT

G =

G = 100

G = 200

G = 500

RG

(R

2

RG

1

2

||20k⍀) + R1 + R3)

(R

||20k⍀)

2

AD624

–V

S

S

R1

6k⍀

R2
5k⍀

R3
6k⍀

(R1 + R2 + R3) || RL 2k⍀

V

R

L

OUT

Figure 30. Gain of 2500

–8–

REV. C

NOISE

AD624

–V

S

+V

S

LOAD

TO
POWER
SUPPLY
GROUND

AD624

RG

1

–V

S

REFERENCE

V

OUT

–INPUT

+INPUT

+V

S

–V

S

AD712

100⍀

100⍀

RG

2

The AD624 is designed to provide noise performance near the
theoretical noise floor. This is an extremely important design
criteria as the front end noise of an instrumentation amplifier is
the ultimate limitation on the resolution of the data acquisition
system it is being used in. There are two sources of noise in an
instrument amplifier, the input noise, predominantly generated
by the differential input stage, and the output noise, generated
by the output amplifier. Both of these components are present
at the input (and output) of the instrumentation amplifier. At
the input, the input noise will appear unaltered; the output
noise will be attenuated by the closed loop gain (at the output,
the output noise will be unaltered; the input noise will be ampli­fied by the closed loop gain). Those two noise sources must be
root sum squared to determine the total noise level expected at
the input (or output).

The low frequency (0.1 Hz to 10 Hz) voltage noise due to the
output stage is 10 µV p-p, the contribution of the input stage is

0.2 µV p-p. At a gain of 10, the RTI voltage noise would be

2





1 µV p-p,

10.2 µV p-p,

applications using either internal or external gain resistors.

10




G

102+ 0. 2 G




2

+ 0. 2

. The RTO voltage noise would be

()

2

. These calculations hold for

()

()

INPUT BIAS CURRENTS

Input bias currents are those currents necessary to bias the input
transistors of a dc amplifier. Bias currents are an additional
source of input error and must be considered in a total error
budget. The bias currents when multiplied by the source resis­tance imbalance appear as an additional offset voltage. (What is
of concern in calculating bias current errors is the change in bias
current with respect to signal voltage and temperature.) Input
offset current is the difference between the two input bias cur­rents. The effect of offset current is an input offset voltage whose
magnitude is the offset current times the source resistance.

+V

S

AD624

LOAD

–V

S

TO
POWER
SUPPLY
GROUND

a. Transformer Coupled

+V

S

AD624

c. AC-Coupled

Figure 31. Indirect Ground Returns for Bias Currents

Although instrumentation amplifiers have differential inputs,
there must be a return path for the bias currents. If this is not
provided, those currents will charge stray capacitances, causing
the output to drift uncontrollably or to saturate. Therefore,
when amplifying “floating” input sources such as transformers
and thermocouples, as well as ac-coupled sources, there must
still be a dc path from each input to ground, (see Figure 31).

COMMON-MODE REJECTION

Common-mode rejection is a measure of the change in output
voltage when both inputs are changed by equal amounts. These
specifications are usually given for a full-range input voltage
change and a specified source imbalance. “Common-Mode
Rejection Ratio” (CMRR) is a ratio expression while “Common­Mode Rejection” (CMR) is the logarithm of that ratio. For
example, a CMRR of 10,000 corresponds to a CMR of 80 dB.

In an instrumentation amplifier, ac common-mode rejection is
only as good as the differential phase shift. Degradation of ac
common-mode rejection is caused by unequal drops across
differing track resistances and a differential phase shift due to
varied stray capacitances or cable capacitances. In many appli­cations shielded cables are used to minimize noise. This tech­nique can create common-mode rejection errors unless the
shield is properly driven. Figures 32 and 33 shows active data
guards which are configured to improve ac common-mode
rejection by “bootstrapping” the capacitances of the input
cabling, thus minimizing differential phase shift.

+V

–INPUT

100⍀

AD711

G = 200

RG

+INPUT

2

Figure 32. Shield Driver, G ≥ 100

S

AD624

–V

S

V

REFERENCE

OUT

REV. C

b. Thermocouple

AD624

–V

S

LOAD

TO
POWER
SUPPLY
GROUND

Figure 33. Differential Shield Driver

–9–

AD624

GROUNDING

Many data-acquisition components have two or more ground
pins which are not connected together within the device. These
grounds must be tied together at one point, usually at the sys­tem power supply ground. Ideally, a single solid ground would
be desirable. However, since current flows through the ground
wires and etch stripes of the circuit cards, and since these paths
have resistance and inductance, hundreds of millivolts can be
generated between the system ground point and the data acqui­sition components. Separate ground returns should be provided
to minimize the current flow in the path from the most sensitive
points to the system ground point. In this way supply currents
and logic-gate return currents are not summed into the same
return path as analog signals where they would cause measure­ment errors (see Figure 34).

ANALOG P.S.

+15V C –15V

0.1

0.1

␮F

␮F

AD624

ANALOG

OUTPUT

REFERENCE

GROUND*

*IF INDEPENDENT, OTHERWISE RETURN AMPLIFIER REFERENCE
TO MECCA AT ANALOG P.S. COMMON

0.1

0.1

␮F

␮F

AD583

SAMPLE

AND HOLD

DIG
COM

SIGNAL
GROUND

DIGITAL P.S.

1␮F1␮F

AD574A

+5V

C

1␮F

+

DIGITAL
DATA
OUTPUT

Figure 34. Basic Grounding Practice

Since the output voltage is developed with respect to the poten­tial on the reference terminal an instrumentation amplifier can
solve many grounding problems.

SENSE TERMINAL

The sense terminal is the feedback point for the instrument
amplifier’s output amplifier. Normally it is connected to the
instrument amplifier output. If heavy load currents are to be
drawn through long leads, voltage drops due to current flowing
through lead resistance can cause errors. The sense terminal can
be wired to the instrument amplifier at the load thus putting the
IxR drops “inside the loop” and virtually eliminating this error
source.

VIN+

V

IN

V+

AD624

–

(SENSE)

OUTPUT
CURRENT
BOOSTER

X1

R

L

(REF)

V–

Figure 35. AD624 Instrumentation Amplifier with Output
Current Booster

Typically, IC instrumentation amplifiers are rated for a full
±10 volt output swing into 2 kΩ. In some applications, how­ever, the need exists to drive more current into heavier loads.
Figure 35 shows how a current booster may be connected

“inside the loop” of an instrumentation amplifier to provide the
required current without significantly degrading overall perfor­mance. The effects of nonlinearities, offset and gain inaccuracies
of the buffer are reduced by the loop gain of the IA output
amplifier. Offset drift of the buffer is similarly reduced.

REFERENCE TERMINAL

The reference terminal may be used to offset the output by up
to ±10 V. This is useful when the load is “floating” or does not
share a ground with the rest of the system. It also provides a
direct means of injecting a precise offset. It must be remem­bered that the total output swing is ±10 volts, from ground, to
be shared between signal and reference offset.

+V

S

VIN+

SENSE

AD624

V

–

IN

–V

REF

S

AD711

LOAD

V

OFFSET

Figure 36. Use of Reference Terminal to Provide Output
Offset

When the IA is of the three-amplifier configuration it is neces­sary that nearly zero impedance be presented to the reference
terminal. Any significant resistance, including those caused by
PC layouts or other connection techniques, which appears
between the reference pin and ground will increase the gain of
the noninverting signal path, thereby upsetting the common­mode rejection of the IA. Inadvertent thermocouple connections
created in the sense and reference lines should also be avoided
as they will directly affect the output offset voltage and output
offset voltage drift.

In the AD624 a reference source resistance will unbalance the
CMR trim by the ratio of 10 kΩ/R

. For example, if the refer-

REF

ence source impedance is 1 Ω, CMR will be reduced to 80 dB
(10 kΩ/1 Ω = 80 dB). An operational amplifier may be used to
provide that low impedance reference point as shown in Figure

36. The input offset voltage characteristics of that amplifier will
add directly to the output offset voltage performance of the
instrumentation amplifier.

An instrumentation amplifier can be turned into a voltage-to­current converter by taking advantage of the sense and reference
terminals as shown in Figure 37.

SENSE

+INPUT

–INPUT

V

X

IL = =

R

1

AD624

V

IN

1 +

R

1

REF

40.000
R

G

AD711

A2

R

+VX–

1

LOAD

I

L

Figure 37. Voltage-to-Current Converter

–10–

REV. C

AD624

–IN

+IN

–V

+V

ANALOG

COMMON

S

S

1␮F
35V

INPUT

OFFSET

TRIM

10k⍀

C1 C2

GAIN TABLE

A B GAIN
0 0 100

0 1 500
1 0 200
11 1

1

50⍀

2

3

4

20k⍀

5

R1

10k⍀

6

7

AD624

8

K1 – K3 =
THERMOSEN DM2C

4.5V COIL
D1 – D3 = IN4148

50⍀

10k⍀

80.2⍀

4445.7⍀

V

B

20k⍀

10k⍀

INPUTS

GAIN

RANGE

225.3⍀

10k⍀

A

B

+5V

124⍀

16

15

14

13

12

11

10

9

74LS138

DECODER

OUTPUT
OFFSET
TRIM

R2
10k⍀

OUT

SHIELDS

Figure 38. Gain Programmable Amplifier

RELAY

Y0

Y1

Y2

G = 100

NC

K1

K1

G = 200K2G = 500

D1 D2

K3

K2 K3

7407N

BUFFER

DRIVER

+5V

D3

10␮F

LOGIC
COMMON

By establishing a reference at the “low” side of a current setting
resistor, an output current may be defined as a function of input
voltage, gain and the value of that resistor. Since only a small
current is demanded at the input of the buffer amplifier A2, the
forced current I

will largely flow through the load. Offset and

L

drift specifications of A2 must be added to the output offset and
drift specifications of the IA.

PROGRAMMABLE GAIN

Figure 38 shows the AD624 being used as a software program­mable gain amplifier. Gain switching can be accomplished with
mechanical switches such as DIP switches or reed relays. It
should be noted that the “on” resistance of the switch in series
with the internal gain resistor becomes part of the gain equation
and will have an effect on gain accuracy.

A significant advantage in using the internal gain resistors in a
programmable gain configuration is the minimization of thermo­couple signals which are often present in multiplexed data
acquisition systems.

If the full performance of the AD624 is to be achieved, the user
must be extremely careful in designing and laying out his circuit
to minimize the remaining thermocouple signals.

The AD624 can also be connected for gain in the output stage.
Figure 39 shows an AD547 used as an active attenuator in the
output amplifier’s feedback loop. The active attenuation pre­sents a very low impedance to the feedback resistors therefore
minimizing the common-mode rejection ratio degradation.

Another method for developing the switching scheme is to use a
DAC. The AD7528 dual DAC which acts essentially as a pair of
switched resistive attenuators having high analog linearity and

symmetrical bipolar transmission is ideal in this application. The
multiplying DAC’s advantage is that it can handle inputs of
either polarity or zero without affecting the programmed gain.
The circuit shown uses an AD7528 to set the gain (DAC A) and
to perform a fine adjustment (DAC B).

10pF

+V

–V

50⍀

20k⍀

10k⍀

AD624

S

S

50⍀

10k⍀

16

OUTPUT
OFFSET
NULL

4445.7⍀

225.3⍀

124⍀

39.2k⍀

28.7k⍀

316k⍀

15

TO –V

10k⍀

14

13

12

11

10

9

1k⍀

1k⍀

1k⍀

V

OUT

80.2⍀

20k⍀

V

B

10k⍀

10k⍀

V

V

SS

GND

DD

AD7590

WRA4A3A2A1

–IN

+IN

–V

+V

(+INPUT)

(–INPUT)

OFFSET

S

S

1␮F

35V

INPUT

NULL

10k⍀

1

2

3

4

5

6

7

8

AD711

Figure 39. Programmable Output Gain

REV. C

–11–

AD624

225.3⍀

124⍀

80.2⍀

DATA

INPUTS

CS

WR

50⍀

4445.7⍀

50⍀

+V

DAC A

DB0

DB7

AD7528

DAC B

S

V

B

20k⍀ 10k⍀

20k⍀

10k⍀

AD712

AD624

10k⍀

10k⍀

256:1

1/2

1/2

AD712

V

OUT

+INPUT

(–INPUT)

G = 100

G = 200

G = 500

RG

RG

–INPUT

(+INPUT)

DAC A/DAC B

1

2

Figure 40. Programmable Output Gain Using a DAC

AUTOZERO CIRCUITS

In many applications it is necessary to provide very accurate
data in high gain configurations. At room temperature the offset
effects can be nulled by the use of offset trimpots. Over the
operating temperature range, however, offset nulling becomes a
problem. The circuit of Figure 41 shows a CMOS DAC operat­ing in the bipolar mode and connected to the reference terminal
to provide software controllable offset adjustments.

In many applications complex software algorithms for autozero
applications are not available. For these applications Figure 42
provides a hardware solution.

+V

S

15 16

14

13

RG

1

RG

2

V

DD

V

SS

GND

200␮s

ZERO PULSE

AD624

–V

S

A1 A2 A3 A4

0.1␮F LOW
LEAKAGE

AD542

1k⍀

12 11

910

CH

AD7510DIKD

V

OUT

Figure 42. Autozero Circuit

The microprocessor controlled data acquisition system shown in
Figure 43 includes includes both autozero and autogain capabil­ity. By dedicating two of the differential inputs, one to ground
and one to the A/D reference, the proper program calibration
cycles can eliminate both initial accuracy errors and accuracy
errors over temperature. The autozero cycle, in this application,
converts a number that appears to be ground and then writes
that same number (8 bit) to the AD624 which eliminates the
zero error since its output has an inverted scale. The autogain
cycle converts the A/D reference and compares it with full scale.
A multiplicative correction factor is then computed and applied
to subsequent readings.

–INPUT

RG

1

G = 100

G = 200

G = 500

RG

2

+INPUT

39k⍀ V

–V

S

AD589

MSB

DATA

LSB

INPUTS

CS

WR

AD7524

Figure 41. Software Controllable Offset

+V

+V

AD624

–V

S

GND

S

S

R

OUT1

OUT2

RG

2

1/2

20k⍀

AD583

–V

REF

AD7524

AGND

DECODE

V

OUT

REF

R3

FB

C1

+V

1/2

AD712

20k⍀

S

R4

10k⍀

5k⍀

R5

20k⍀

1/2

AD712

R6

–V

S

AD7507

A0

EN A1

LATCH

A2

RG

1

1/2

AD712

AD624

20k⍀

10k⍀

AD712

5k⍀

ADDRESS BUS

V

IN

CONTROL

V

AD574A

REF

MICRO-

PROCESSOR

Figure 43. Microprocessor Controlled Data Acquisition
System

–12–

REV. C

AD624

WEIGH SCALE

Figure 44 shows an example of how an AD624 can be used to
condition the differential output voltage from a load cell. The
10% reference voltage adjustment range is required to accom­modate the 10% transducer sensitivity tolerance. The high
linearity and low noise of the AD624 make it ideal for use in
applications of this type particularly where it is desirable to
measure small changes in weight as opposed to the absolute
value. The addition of an autogain/autotare cycle will enable the
system to remove offsets, gain errors, and drifts making possible
true 14-bit performance.

+15V

NOTE 2

+10V

+5V

AD584

3M⍀

R4
10k⍀
ZERO
ADJUST
(FINE)

NOTES

1. LOAD CELL TEDEA MODEL 1010 10kG. OUTPUT 2mV/Vⴞ10%.

2. R1, R2 AND R3 SELECTED FOR AD584. OUTPUT 10V ⴞ10%.

R5

+2.5V

VBG

R7
100k

⍀

R6
100k⍀
ZERO ADJUST
(COARSE)

10V ⴞ10%

R1
30k⍀

SCALE

R2

ERROR

20k⍀

ADJUST

R3
10k⍀

–INPUT

+INPUT

TRANSDUCER
SEE NOTE 1

G500

G200

G100

RG

AD707

AD624

2

GAIN = 500

+15V

100⍀

SENSE

OUT

REFERENCE

R3
10⍀

2N2219

+10V FULL

SCALE

OUTPUT

A/D

CONVERTER

Figure 44. AD624 Weigh Scale Application

AC BRIDGE

Bridge circuits which use dc excitation are often plagued by
errors caused by thermocouple effects, l/f noise, dc drifts in the
electronics, and line noise pickup. One way to get around these
problems is to excite the bridge with an ac waveform, amplify
the bridge output with an ac amplifier, and synchronously
demodulate the resulting signal. The ac phase and amplitude
information from the bridge is recovered as a dc signal at the
output of the synchronous demodulator. The low frequency
system noise, dc drifts, and demodulator noise all get mixed to
the carrier frequency and can be removed by means of a low­pass filter. Dynamic response of the bridge must be traded off
against the amount of attenuation required to adequately sup­press these residual carrier components in the selection of the
filter.

Figure 45 is an example of an ac bridge system with the AD630
used as a synchronous demodulator. The oscilloscope photo­graph shows the results of a 0.05% bridge imbalance caused by
the 1 Meg resistor in parallel with one leg of the bridge. The top
trace represents the bridge excitation, the upper middle trace is
the amplified bridge output, the lower-middle trace is the out­put of the synchronous demodulator and the bottom trace is the
filtered dc system output.

This system can easily resolve a 0.5 ppm change in bridge
impedance. Such a change will produce a 6.3 mV change in the
low-pass filtered dc output, well above the RTO drifts and noise.

The AC-CMRR of the AD624 decreases with the frequency of
the input signal. This is due mainly to the package-pin capaci­tance associated with the AD624’s internal gain resistors. If
AC-CMRR is not sufficient for a given application, it can be
trimmed by using a variable capacitor connected to the amplifier’s
RG

pin as shown in Figure 45.

2

+V

5k⍀

10k⍀

10k⍀

S

10k⍀

AD624C

–V

S

+V

MODULATION

INPUT

MODULATED

OUTPUT

SIGNAL

S

V

OUT

1kHz

BRIDGE

EXCITATION

1k⍀

PHASE

SHIFTER

CARRIER
INPUT

1k⍀

–V

RG

G = 1000

RG

4–49pF

BALANCE

–V

AD630

1

2

2.5k⍀

1k⍀

1k⍀

1M⍀

CERAMIC ac

CAPACITOR

2.5k⍀

A

B

B

S

COMP

Figure 45. AC Bridge

0V

0V

0V

0V

2V

BRIDGE EXCITATION
(20V/div) (A)

AMPLIFIED BRIDGE
OUTPUT (5V/div) (B)

DEMODULATED BRIDGE
OUTPUT (5V/div) (C)

FILTER OUTPUT
2V/div) (D)

REV. C

Figure 46. AC Bridge Waveforms

–13–

AD624

+V

ERROR BUDGET ANALYSIS

To illustrate how instrumentation amplifier specifications are

350⍀

350⍀

+10V

350⍀

350⍀

G = 100

RG

RG

1

2

applied, we will now examine a typical case where an AD624 is
required to amplify the output of an unbalanced transducer.
Figure 47 shows a differential transducer, unbalanced by ≈5 Ω,
supplying a 0 to 20 mV signal to an AD624C. The output of the
IA feeds a 14-bit A to D converter with a 0 to 2 volt input volt­age range. The operating temperature range is –25°C to +85°C.
Therefore, the largest change in temperature ∆T within the
operating range is from ambient to +85°C (85°C – 25°C =
60°C.)

In many applications, differential linearity and resolution are of
prime importance. This would be so in cases where the absolute

Figure 47. Typical Bridge Application

value of a variable is less important than changes in value. In
these applications, only the irreducible errors (20 ppm =

0.002%) are significant. Furthermore, if a system has an intelli­gent processor monitoring the A to D output, the addition of an
autogain/autozero cycle will remove all reducible errors and may
eliminate the requirement for initial calibration. This will also
reduce errors to 0.002%.

Table II. Error Budget Analysis of AD624CD in Bridge Application

Effect on Effect on
Absolute Absolute Effect

AD624C Accuracy Accuracy on

Error Source Specifications Calculation at TA = +25ⴗC at TA = +85ⴗC Resolution

Gain Error ± 0.1% ± 0.1% = 1000 ppm 1000 ppm 1000 ppm –
Gain Instability 10 ppm (10 ppm/°C) (60°C) = 600 ppm _ 600 ppm –
Gain Nonlinearity ±0.001% ± 0.001% = 10 ppm ––10 ppm
Input Offset Voltage ±25 µV, RTI ±25 µV/20 mV = ±1250 ppm 1250 ppm 1250 ppm –
Input Offset Voltage Drift ±0.25 µV/°C(± 0.25 µV/°C) (60°C)= 15 µV

Output Offset Voltage
Output Offset Voltage Drift

1

1

±2.0 mV ±2.0 mV/20 mV = 1000 ppm 1000 ppm 1000 ppm –
±10 µV/°C(±10 µV/°C) (60°C) = 600 µV

15 µV/20 mV = 750 ppm – 750 ppm –

600 µV/20 mV = 300 ppm – 300 ppm –

Bias Current–Source ± 15 nA (±15 nA)(5 Ω ) = 0.075 µV

Imbalance Error 0.075 µV/20mV = 3.75 ppm 3.75 ppm 3.75 ppm –

Offset Current–Source ± 10 nA (± 10 nA)(5 Ω) = 0.050 µV

Imbalance Error 0.050 µV/20 mV = 2.5 ppm 2.5 ppm 2.5 ppm –

Offset Current–Source ± 10 nA (10 nA) (175 Ω) = 1.75 µV

Resistance Error 1.75 µV/20 mV = 87.5 ppm 87.5 ppm 87.5 ppm –

Offset Current–Source ± 100 pA/°C (100 pA/°C) (175 Ω) (60°C) = 1 µV

Resistance–Drift 1 µV/20 mV = 50 ppm – 50 ppm –

Common-Mode Rejection 115 dB 115 dB = 1.8 ppm × 5V = 9µV

5V dc 9µV/20 mV = 444 ppm 450 ppm 450 ppm –

Noise, RTI

(0.1 Hz–10 Hz) 0.22 µV p-p 0.22 µV p-p/20 mV = 10 ppm _ – 10 ppm

Total Error 3793.75 ppm 5493.75 ppm 20 ppm

NOTE

1

Output offset voltage and output offset voltage drift are given as RTI figures.

S

10k⍀

AD624C

–V

S

14-BIT

ADC

0 TO 2V

F.S.

For a comprehensive study of instrumentation amplifier design
and applications, refer to the Instrumentation Amplifier Application
Guide, available free from Analog Devices.

–14–

REV. C

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

Side-Brazed Solder Lid Ceramic DIP

(D-16)

AD624

0.005 (0.13) MIN

0.200 (5.08)
MAX

0.200 (5.08)

0.125 (3.18)

16

1

0.840 (21.34) MAX

0.023 (0.58)

0.014 (0.36)

PIN 1

0.080 (2.03) MAX

0.100
(2.54)

BSC

9

0.310 (7.87)

0.220 (5.59)

8

0.070 (1.78)

0.030 (0.76)

0.060 (1.52)

0.015 (0.38)

0.150
(3.81)
MAX

SEATING
PLANE

0.320 (8.13)

0.290 (7.37)

0.015 (0.38)

0.008 (0.20)

REV. C

–15–

C805d–0–7/99

–16–

PRINTED IN U.S.A.