Page 1
Low Drift, Low Power
a
FEATURES
EASY TO USE
Pin-Strappable Gains of 10 & 100
All Errors Specified for Total System Performance
Higher Performance than Discrete In-Amp Designs
Available in 8-Pin DIP and SOIC
Low Power, 1.3 mA max Supply Current
Wide Power Supply Range (62.3 V to 618 V)
EXCELLENT DC PERFORMANCE
0.15% max, Total Gain Error
65 ppm/8C, Total Gain Drift
125 mV max, Total Offset Voltage
1.0 mV/8C max, Offset Voltage Drift
LOW NOISE
Hz, @ 1 kHz, Input Voltage Noise
9 nV/√
0.28 mV p-p Noise (0.1 Hz to 10 Hz}
EXCELLENT AC SPECIFICATIONS
800 kHz Bandwidth (G = 10}, 200 kHz (G = 100}
12 ms Settling Time to 0.01%
APPLICATIONS
Weigh Scales
Transducer Interface & Data Acquisition Systems
Industrial Process Controls
Battery Powered and Portable Equipment
PRODUCT DESCRIPTION
The AD621 is an easy to use, low cost, low power, high accuracy instrumentation amplifier which is ideally suited for a wide
range of applications. Its unique combination of high performance, small size and low power, outperforms discrete in amp
implementations. High functionality, low gain errors and low
gain drift errors are achieved by the use of internal gain setting
resistors. Fixed gains of 10 and 100 can be easily set via external
30,000
25,000
3 - OP AMP
20,000
15,000
10,000
5,000
TOTAL ERROR, ppm OF FULL SCALE
0
AD621A
5
SUPPLY CURRENT – mA
10
Three Op Amp IA Designs vs. AD621
IN-AMPS
(3 OP 07'S)
15 20
Instrumentation Amplifier
AD621
CONNECTION DIAGRAM
8-Pin Plastic Mini-DIP (N), Cerdip (Q)
and SOIC (R) Packages
8
G=10/100
1
AD621
2
–IN
3
+IN
–V
4
S
TOP VIEW
pin strapping. The AD621 is fully specified as a total system,
therefore, simplifying the design process.
For portable or remote applications, where power dissipation,
size and weight are critical, the AD621 features a very low supply current of 1.3 mA max and is packaged in a compact 8-pin
SOIC, 8-pin plastic DIP or 8-pin cerdip. The AD621 also
excels in applications requiring high total accuracy, such as precision data acquisition systems used in weigh scales and transducer interface circuits. Low maximum error specifications
including nonlinearity of 10 ppm, gain drift of 5 ppm/°C, 50 µV
offset voltage and 0.6 µV/°C offset drift (“B” grade), make pos-
sible total system performance at a lower cost than has been previously achieved with discrete designs or with other monolithic
instrumentation amplifiers.
When operating from high source impedances, as in ECG and
blood pressure monitors, the AD621 features the ideal combination of low noise and low input bias currents. Voltage noise is
specified as 9 nV/√
Hz at 1 kHz and 0.28 µV p-p from 0.1 Hz to
10 Hz. Input current noise is also extremely low at 0.1 pA/√
The AD621 outperforms FET input devices with an input bias
current specification of 1.5 nA max over the full industrial temperature range.
10,000
1,000
(0.1 – 10Hz)
TOTAL INPUT VOLTAGE NOISE, G = 100 – µVp-p
100
10
1
0.1
1k
TYPICAL STANDARD
BIPOLAR INPUT
IN-AMP
10k 100k
SOURCE RESISTANCE – Ω
G=10/100
7
+V
S
OUTPUT
6
REF
5
AD621 SUPERßETA
BIPOLAR INPUT
IN-AMP
1M
Hz.
10M 100M
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
Total Voltage Noise vs. Source Resistance
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700 Fax: 617/326-8703
Page 2
AD621–SPECIFICATIONS
Gain = 10
(typical @ +258C, VS = 615 V, and RL = 2 kV, unless otherwise noted)
AD621A AD621B AD620S
1
Model Conditions Min Typ Max Min Typ Max Min Typ Max Units
GAIN
Gain Error V
Nonlinearity,
= –10 V to +10 V RL = 2 kΩ 2 10 2 10 2 10 ppm of FS
V
OUT
Gain vs. Temperature –1.5 ±5 –1.5 ± 5–1±5 ppm/°C
= ±10 V 0.15 0.05 0.15 %
OUT
TOTAL VOLTAGE OFFSET
Offset (RTI) VS = ±15 V 75 250 50 125 75 250 µV
Over Temperature V
Average TC V
Offset Referred to the
= ±5 V to ±15 V 400 215 500 µV
S
= ±5 V to ±15 V 1.0 2.5 0.6 1.5 1.0 2.5 µV/°C
S
Input vs. Supply (PSR)2VS = ±2.3 V to ±18 V 95 120 100 120 95 120 dB
Total NOISE
Voltage Noise (RTI) 1 kHz 13 17 13 17 13 17 nV/√Hz
RTI 0.1 Hz to 10 Hz 0.55 0.55 0.8 0.55 0.8 µV p-p
Current Noise f = 1 kHz 100 100 100 fA/√
0.1 Hz–10 Hz 10 10 10 pA p-p
INPUT CURRENT V
Input Bias Current 0.5 2.0 0.5 1.0 0.5 2 nA
= ±15 V
S
Over Temperature 2.5 1.5 4 nA
Average TC 3.0 3.0 8.0 pA/°C
Input Offset Current 0.3 1.0 0.3 0.5 0.3 1.0 nA
Over Temperature 1.5 0.75 2.0 nA
Average TC 1.5 1.5 8.0 pA/°C
INPUT
Input Impedance
Differential 10i210i210i2GΩipF
Common-Mode 10i210i210i2GΩipF
Input Voltage Range
Over Temperature –V
Over Temperature –V
Common-Mode Rejection
3
VS = ±2.3 V to ±5 V –VS + 1.9 +VS – 1.2 –VS + 1.9 +VS – 1.2 –VS + 1.9 +VS – 1.2 V
= ±5 V to ±l8 V –VS + 1.9 +VS – 1.4 –VS + 1.9 +VS – 1.4 –VS + 1.9 +VS – 1.4 V
V
S
+ 2.1 +VS – 1.3 –VS + 2.1 +VS – 1.3 –VS + 2.1 +VS – 1.3 V
S
+ 2.1 +VS – 1.4 –VS + 2.1 +VS – 1.4 –VS + 2.3 +VS – 1.4 V
S
Ratio DC to 60 Hz with
1 kΩ Source Imbalance VCM = 0 V to ±10 V 93 110 100 110 93 110 dB
OUTPUT
Output Swing RL = 10 kΩ,
= ±2.3 V to ±5 V –VS + 1.1 +VS – 1.2 –VS + 1.1 +VS – 1.2 –VS + 1.1 +VS – 1.2 V
V
Over Temperature –V
Over Temperature –V
S
= ±5 V to ±18 V –VS + 1.2 +VS – 1.4 –VS + 1.2 +VS – 1.4 –VS + 1.2 +VS – 1.4 V
V
S
Short Current Circuit ±18 ±18 ±18 mA
+ 1.4 +VS – 1.3 –VS + 1.4 +VS – 1.3 –VS + 1.6 +VS – 1.3 V
S
+ 1.6 +VS – 1.5 –VS + 1.6 +VS – 1.5 –VS + 2.3 +VS – 1.5 V
S
DYNAMIC RESPONSE
Small Signal,
–3 dB Bandwidth 800 800 800 kHz
Slew Rate 0.75 1.2 0.75 1.2 0.75 1.2 V/µs
Settling Time to 0.01% 10 V Step 12 12 12 µs
REFERENCE INPUT
R
IN
I
IN
Voltage Range –V
VIN +, V
= 0 +50 +60 +50 +60 +50 +60 µA
REF
Gain to Output 1 ± 0.0001 1 ± 0.0001 1 ± 0.0001
20 20 20 kΩ
+ 1.6 +VS – 1.6 –VS + 1.6 +VS – 1.6 VS + 1.6 +VS – 1.6 V
S
POWER SUPPLY
Operating Range ± 2.3 ±18 ± 2.3 ±18 ±2.3 ±18 V
Quiescent Current V
Over Temperature 1.1 1.6 1.1 1.6 1.1 1.6 mA
= ± 2.3 V to ±18 V 0.9 1.3 0.9 1.3 0.9 1.3 mA
S
TEMPERATURE RANGE
For Specified Performance –40 to +85 –40 to +85 –55 to +125 °C
NOTES
1
See Analog Devices military data sheet for 883B tested specifications.
2
This is defined as the supply range over which PSRR is defined.
3
Input Voltage Range = CMV + (Gain × V
DIFF
).
Specifications subject to change without notice.
Hz
–2–
REV. A
Page 3
AD621
Gain = 100
(typical @ +258C, VS = 615 V, and RL = 2 kV, unless otherwise noted)
AD621A AD621B AD620S
1
Model Conditions Min Typ Max Min Typ Max Min Typ Max Units
GAIN
Gain Error V
Nonlinearity,
= –10 V to +10 V RL = 2 kΩ 2 10 2 10 2 10 ppm of FS
V
OUT
Gain vs. Temperature –1 ± 5–1±5–1±5 ppm/°C
= ±10 V 0.15 0.05 0.15 %
OUT
TOTAL VOLTAGE OFFSET
Offset (RTI) VS = ±15 V 35 125 25 50 35 125 µV
Over Temperature V
Average TC V
Offset Referred to the
= ±5 V to ±15 V 185 215 225 µV
S
= ±5 V to ±15 V 0.3 1.0 0.1 0.6 0.3 1.0 µV/°C
S
Input vs. Supply (PSR)2VS = ±2.3 V to ±18 V 110 140 120 140 110 140 dB
Total NOISE
Voltage Noise (RTI) 1 kHz 9 13 9 13 9 13 nV/√Hz
RTI 0.1 Hz to 10 Hz 0.28 0.28 0.4 0.28 0.4 µV p-p
Current Noise f = 1 kHz 100 100 100 fA/√
0.1 Hz–10 Hz 10 10 10 pA p-p
INPUT CURRENT V
Input Bias Current 0.5 2.0 0.5 1.0 0.5 2 nA
= ±15 V
S
Over Temperature 2.5 1.5 4 nA
Average TC 3.0 3.0 8.0 pA/°C
Input Offset Current 0.3 1.0 0.3 0.5 0.3 1.0 nA
Over Temperature 1.5 0.75 2.0 nA
Average TC 1.5 1.5 8.0 pA/°C
INPUT
Input Impedance
Differential 10i210i210i2GΩipF
Common-Mode 10i210i210i2GΩipF
Input Voltage Range
Over Temperature –V
Over Temperature –V
Common-Mode Rejection
3
VS = ±2.3 V to ± 5 V –VS + 1.9 +VS – 1.2 –VS + 1.9 +VS – 1.2 –VS + 1.9 +VS – 1.2 V
= ±5 V to ±l8 V –VS + 1.9 +VS – 1.4 –VS + 1.9 +VS – 1.4 –VS + 1.9 +VS – 1.4 V
V
S
+ 2.1 +VS – 1.3 –VS + 2.1 +VS – 1.3 –VS + 2.1 +VS – 1.3 V
S
+ 2.1 +VS – 1.4 –VS + 2.1 +VS – 1.4 –VS + 2.3 +VS – 1.4 V
S
Ratio DC to 60 Hz with
1 kΩ Source Imbalance VCM = 0 V to ±10 V 110 130 120 130 110 130 dB
OUTPUT
Output Swing RL = 10 kΩ,
= ±2.3 V to ± 5 V –VS + 1.1 +VS – 1.2 –VS + 1.1 +VS – 1.2 –VS + 1.1 +VS – 1.2 V
V
Over Temperature –V
Over Temperature –V
S
= ±5 V to ±18 V –VS + 1.2 +VS – 1.4 –VS + 1.2 +VS – 1.4 –VS + 1.2 +VS – 1.4 V
V
S
Short Current Circuit ±18 ±18 ±18 mA
+ 1.4 +VS – 1.3 –VS + 1.4 +VS – 1.3 –VS + 1.6 +VS – 1.3 V
S
+ 1.6 +VS – 1.5 –VS + 1.6 +VS – 1.5 –VS + 2.3 +VS – 1.5 V
S
DYNAMIC RESPONSE
Small Signal,
–3 dB Bandwidth 200 200 200 kHz
Slew Rate 0.75 1.2 0.75 1.2 0.75 1.2 V/µs
Settling Time to 0.01% 10 V Step 12 12 12 µs
REFERENCE INPUT
R
IN
I
IN
Voltage Range –V
VIN +, V
= 0 +50 +60 +50 +60 +50 +60 µA
REF
Gain to Output 1 ± 0.0001 1 ± 0.0001 1 ± 0.0001
20 20 20 kΩ
+ 1.6 +VS – 1.6 –VS + 1.6 +VS – 1.6 VS + 1.6 +VS – 1.6 V
S
POWER SUPPLY
Operating Range ± 2.3 ±18 ± 2.3 ±18 ±2.3 ±18 V
Quiescent Current V
Over Temperature 1.1 1.6 1.1 1.6 1.1 1.6 mA
= ± 2.3 V to ±18 V 0.9 1.3 0.9 1.3 0.9 1.3 mA
S
TEMPERATURE RANGE
For Specified Performance –40 to +85 –40 to +85 –55 to +125 °C
NOTES
1
See Analog Devices military data sheet for 883B tested specifications.
2
This is defined as the supply range over which PSEE is defined.
3
Input Voltage Range = CMV + (Gain × V
DIFF
).
Specifications subject to change without notice.
Hz
REV. A
–3–
Page 4
AD621
ABSOLUTE MAXIMUM RATINGS
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18 V
Internal Power Dissipation
2
. . . . . . . . . . . . . . . . . . . . .650 mW
Input Voltage (Common Mode) . . . . . . . . . . . . . . . . . . . . ±V
1
S
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . ±25 V
Output Short Circuit Duration . . . . . . . . . . . . . . . . . Indefinite
Storage Temperature Range (Q) . . . . . . . . . . –65°C to +150°C
Storage Temperature Range (N, R) . . . . . . . . –65°C to +125°C
Operating Temperature Range
AD621 (A, B) . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
AD621 (S) . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to +125°C
Lead Temperature Range
(Soldering 10 seconds) . . . . . . . . . . . . . . . . . . . . . . . +300°C
NOTES
1
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
Specification is for device in free air:
8-Pin Plastic Package: θJA = 95°C/Watt
8-Pin Cerdip Package: θJA = 110°C/Watt
8-Pin SOIC Package: θJA = 155°C/Watt
ESD SUSCEPTIBILITY
ESD (electrostatic discharge) sensitive device. Electrostatic
charges as high as 4000 volts, which readily accumulate on the
human body and on test equipment, can discharge without detection. Although the AD621 features proprietary ESD protection circuitry, permanent damage may still occur on these
devices if they are subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid any performance degradation or loss of functionality.
ORDERING GUIDE
Temperature Package Package
Model Range Description Option
1
AD621AN – 40°C to +85°C 8-Pin Plastic DIP N-8
AD621BN –40°C to +85°C 8-Pin Plastic DIP N-8
AD621AR –40°C to +85°C 8-Pin Plastic SOIC R-8
AD621BR –40°C to +85°C 8-Pin Plastic SOIC R-8
AD621SQ/883B
AD621ACHIPS –40°C to +85°C
NOTES
1
N = Plastic DIP; Q = Cerdip; R = SOIC.
2
See Analog Devices' military data sheet for 883B specifications.
2
–55°C to +125°C 8-Pin Cerdip Q-8
Die
METALIZATION PHOTOGRAPH
Dimensions shown in inches and (mm).
Contact factory for latest dimensions.
–4–
REV. A
Page 5
Typical Characteristics–AD621
50
SAMPLE SIZE = 90
40
30
20
PERCENTAGE OF UNITS
10
0
–200
INPUT OFFSET VOLTAGE – µV
Figure 1. Typical Distribution of V
50
SAMPLE SIZE = 90
40
30
20
Gain = 10
OS,
50
SAMPLE SIZE = 90
40
30
20
PERCENTAGE OF UNITS
10
0
+200+1000–100
–800
INPUT BIAS CURRENT – pA
+800+4000–400
Figure 4. Typical Distribution of Input Bias Current
2
1.5
1
PERCENTAGE OF UNITS
10
0
–80
INPUT OFFSET VOLTAGE – µV
+80+400–40
Figure 2. Typical Distribution of VOS, Gain = 100
50
SAMPLE SIZE = 90
40
30
20
PERCENTAGE OF UNITS
10
0
–400
INPUT OFFSET CURRENT – pA
+400+2000–200
0.5
CHANGE IN OFFSET VOLTAGE – µV
0
051
WARM-UP TIME – Minutes
432
Figure 5. Change in Input Offset Voltage vs. Warm-Up Time
1000
Hz
√
100
GAIN = 10
10
VOLTAGE NOISE – nV/
GAIN = 100
1
1
10
100 1k
FREQUENCY – Hz
10k
100k
Figure 3. Typical Distribution of Input Offset Current
REV. A
Figure 6. Voltage Noise Spectral Density
–5–
Page 6
AD621
10
90
100
0%
100mV
1s
100
1000
AD621A
FET INPUT
IN-AMP
SOURCE RESISTANCE – Ω
TOTAL DRIFT FROM 25°C TO 85°C, RTI – µV
100,000
10
1k 10M
10,000
10k 1M100k
1000
100
CURRENT NOISE – fA/ Hz
10
1 10 1000100
FREQUENCY – Hz
Figure 7. Current Noise Spectral Density vs. Frequency
RTI NOISE – 0.2 µV/div
TIME – 1 sec/div
Figure 8a. 0.1 Hz to 10 Hz RTI Voltage Noise, Gain = 10
Figure 9. 0.1 Hz to 10 Hz Current Noise, 5 pA per Vertical
Div, 1 Second per Horizontal Div
Figure 10. Total Drift vs. Source Resistance
+160
+140
GAIN = 100
+120
GAIN = 10
+100
RTI NOISE – 0.1 µV/div
TIME – 1 sec/div
Figure 8b. 0.1 Hz to 10 Hz RTI Voltage Noise, G = 100
+80
CMR – dB
+60
+40
+20
0
0.1
10 100 1k 10k 100k
1
FREQUENCY – Hz
Figure 11. CMR vs. Frequency, RTI, for a Zero to 1 k
Source Imbalance
–6–
1M
Ω
REV. A
Page 7
AD621
INPUT VOLTAGE LIMIT – Volts
(REFERRED TO SUPPLY VOLTAGES)
20
+1.0
+0.5
50
+1.5
–1.5
–1.0
–0.5
1510
SUPPLY VOLTAGE ± Volts
+V
s
–V
s
–0.0
+0.0
180
160
140
120
100
PSR – dB
80
60
40
20
0.1
1
G = 100
G = 10
FREQUENCY – Hz
Figure 12. Positive PSR vs. Frequency
180
160
140
120
100
PSR – dB
80
G = 100
G = 10
35
G = 10 & 100
30
25
20
15
10
OUTPUT VOLTAGE – Volts p-p
5
1M
100k10k1k10010
0
1k
10k
FREQUENCY – Hz
100k
1M
Figure 15. Large Signal Frequency Response
60
40
20
0.1
1
FREQUENCY – Hz
Figure 13. Negative PSR vs. Frequency
1000
100
10
1
CLOSED-LOOP GAIN – V/V
0.1
100 10M
1k
FREQUENCY – Hz
100k 1M10k
Figure 14. Closed-Loop Gain vs. Frequency
1M
100k10k1k10010
Figure 16. Input Voltage Range vs. Supply Voltage
–0.0
+V
s
–0.5
–1.0
–1.5
+1.5
+1.0
OUTPUT VOLTAGE SWING – Volts
(REFERRED TO SUPPLY VOLTAGES)
+0.5
–V
+0.0
s
0
5
SUPPLY VOLTAGE ± Volts
R = 2kΩ
L
R = 10kΩ
R = 2kΩ
L
L
R = 10kΩ
L
1510
20
Figure 17. Output Voltage Swing vs. Supply Voltage,
G = 10
REV. A
–7–
Page 8
AD621
10
90
100
0%
1mV
5V 10µs
10
30
V = ± 15V
S
G = 10
20
10
OUTPUT VOLTAGE SWING – Volts p-p
0
0
100 1k
LOAD RESISTANCE – Ω
10k
Figure 18. Output Voltage Swing vs. Resistive Load
5V 10µs
100
90
10
0%
1mV
Figure 19. Large Signal Pulse Response and Settling
Time Gain, G = 10 (0.5 mV = 0.01%), R
= 100 pF
C
L
20mV
100
90
= 1 k Ω,
L
10µs
Figure 21. Large Signal Pulse Response and Settling
Time, G = 100 (0.5 mV = 0.1%), R
100
90
10
0%
= 2 kΩ, CL = 100 pF
L
20mV
10µs
Figure 22. Small Signal Pulse Response, G = 100,
= 2 kΩ, CL = 100 pF
R
L
20
TO 0.01%
15
TO 0.1%
10
10
0%
Figure 20. Small Signal Pulse Response, G = 10,
= 1 k Ω, CL = 100 pF
R
L
–8–
SETTLING TIME – µs
5
0
020
5
OUTPUT STEP SIZE – Volts
10
15
Figure 23. Settling Time vs. Step Size, G = 10
REV. A
Page 9
AD621
AD621
V
OUT
10kΩ
1kΩ
10kΩ
G=10
3
8
1
2
4
6
7
+V
S
11kΩ 1kΩ
0.1%0.1%
100kΩ
0.1%
INPUT
20V p-p
–V
S
5
G=100
G=10
1%
10T
1%
G=100
20
TO 0.01%
15
TO 0.1%
10
SETTLING TIME – µs
5
0
020
5
OUTPUT STEP SIZE – Volts
10
Figure 24. Settling Time vs. Step Size, Gain = 100
15
Figure 27. Gain Nonlinearity, G = 10, RL = 10 kΩ, Vertical
Scale: 100
100
90
10
0%
µ
V/Div = 100 ppm/Div, Horizontal Scale:
2 Volts/Div
2.0
1.5
1.0
+I
B
2V100µV
0.5
–I
0
–0.5
INPUT CURRENT – nA
–1.0
–1.5
–2.0
–75
B
TEMPERATURE – °C
1257525–25–125
175
Figure 25. Input Bias Current vs. Temperature
0PW 0
100
90
10
0%
0 WFM
20 WFM AQR WARNING
2VVZR 0 100µV
Figure 28. Settling Time Test Circuit
Figure 26. Gain Nonlinearity, G = 100, RL = 10 kΩ,
= 0 pF. Vertical Scale: 100 µV/Div = 100 ppm/Div
C
L
Horizontal Scale: 2 Volts/Div
REV. A
–9–
Page 10
AD621
+V
S
7
I1
20µA
R3
400Ω
2
Q1 Q2
Figure 29. Simplified Schematic of AD621
THEORY OF OPERATION
The AD621 is a monolithic instrumentation amplifier based on
a modification of the classic three op amp circuit. Careful layout
of the chip, with particular attention to thermal symmetry builds
in tight matching and tracking of critical components, thus preserving the high level of performance inherent in this circuit, at a
low price.
On chip gain resistors are pretrimmed for gains of 10 and 100.
The AD621 is preset to a gain of 10. A single external jumper
(between Pins 1 and 8) is all that is needed to select a gain of
100. Special design techniques assure a low gain TC of 5 ppm/°C
max, even at a gain of 100.
Figure 29 is a simplified schematic of the AD621. The input
transistors Q1 and Q2 provide a single differential-pair bipolar
input for high precision, yet offer 10× lower Input Bias Current,
thanks to Superβeta processing. Feedback through the Q1-A1-R1
loop and the Q2-A2-R2 loop maintains constant collector current of the input devices Q1 and Q2, thereby impressing the
+10V
R = 350Ω
R = 350Ω R = 350Ω
V
A1 A2
C1
25k
R1 R2
R5
5555.6Ω
R6
555.6Ω
1
G=100
–V
R = 350Ω
B
8
G=100
4
S
20µA
C2
25k
I2
10kΩ
10kΩ
10kΩ
R4
400Ω
A3
3
10kΩ
+IN– IN
OUTPUT
6
REF
5
AD621A
REFERENCE
input voltage across the gain-setting resistor, RG, which equals
R5 at a gain of 10 or the parallel combination of R5 and R6 at a
gain of 100.
This creates a differential gain from the inputs to the A1/A2
outputs given by G = (R1 + R2) / RG + 1. The unity-gain subtracter A3 removes any common-mode signal, yielding a singleended output referred to the REF pin potential.
The value of RG also determines the transconductance of the
preamp stage. As RG is reduced for larger gains, the transconductance increases asymptotically to that of the input transistors. This has three important advantages: (a) Open-loop gain is
boosted for increasing programmed gain, thus reducing gain-related errors. (b) The gain-bandwidth product (determined by
C1, C2 and the preamp transconductance) increases with programmed gain, thus optimizing frequency response. (c) The input voltage noise is reduced to a value of 9 nV/√
Hz, determined
mainly by the collector current and base resistance of the input
devices.
Make vs. Buy: A Typical Bridge Application Error Budget
The AD621 offers improved performance over discrete three op
amp IA designs, along with smaller size, fewer components and
10 times lower supply current. In the typical application, shown
in Figure 30, a gain of 100 is required to amplify a bridge output of 20 mV full scale over the industrial temperature range
of –40°C to +85°C. The error budget table below shows how
to calculate the effect various error sources have on circuit
accuracy.
Regardless of the system it is being used in, the AD621 provides
greater accuracy, and at low power and price. In simple systems,
absolute accuracy and drift errors are by far the most significant
contributors to error. In more complex systems with an intelligent processor, an auto-gain/auto-zero cycle will remove all absolute accuracy and drift errors leaving only the resolution errors
of gain nonlinearity and noise, thus allowing full 14-bit accuracy.
Note that for the discrete circuit, the OP07 specifications for input voltage offset and noise have been multiplied by 2. This is
because a three op amp type in amp has two op amps at its inputs, both contributing to the overall input error.
10kΩ*
OP07D
10kΩ*
100Ω**
OP07D
OP07D
10kΩ*
10kΩ**
10kΩ**
10kΩ*
PRECISION BRIDGE TRANSDUCER
AD621A MONOLITHIC
INSTRUMENTATION
AMPLIFIER, G=100
SUPPLY CURRENT = 1.3mA MAX
Figure 30. Make vs. Buy
–10–
3 OP-AMP IN-AMP, G=100
*0.02% RESISTOR MATCH, 3PPM/°C TRACKING
**DISCRETE 1% RESISTOR, 100PPM/°C TRACKING
SUPPLY CURRENT = 15mA MAX
REV. A
Page 11
+5V
AD621
5
20kΩ
6
10kΩ
0.10mA
3kΩ
3kΩ
1.7mA
7
3kΩ
3kΩ
3
8
1
2
1.3mA
AD621B
4
MAX
Figure 31. A Pressure Monitor Circuit which Operates on a +5 V Power Supply
Pressure Measurement
Although useful in many bridge applications such as weighscales, the AD621 is especially suited for higher resistance pressure sensors powered at lower voltages where small size and low
power become more even significant.
Figure 31 shows a 3 kΩ pressure transducer bridge powered
from +5 V. In such a circuit, the bridge consumes only 1.7 mA.
Adding the AD621 and a buffered voltage divider allows the signal to be conditioned for only 3.8 mA of total supply current.
Small size and low cost make the AD621 especially attractive for
voltage output pressure transducers. Since it delivers low noise
and drift, it will also serve applications such as diagnostic
noninvasion blood pressure measurement.
Wide Dynamic Range Gain Block Suppresses Large CommonMode and Offset Signals
The AD621 is especially useful in wide dynamic range applications such as those requiring the amplification of signals in the
REF
20kΩ
AD705
0.6mA
MAX
IN
AGND
ADC
DIGITAL
DATA
OUTPUT
presence of large, unwanted common-mode signals or offsets.
Many monolithic in amps achieve low total input drift and noise
errors only at relatively high gains (~100). In contrast the
AD621’s low output errors allow such performance at a gain of
10, thus allowing larger input signals and therefore greater
dynamic range. The circuit of Figure 32 (± 15 V supply, G = 10)
has only 2.5 µV/°C max. V
drift and 0.55 µ/V p-p typical
OS
0.1 Hz to 10 Hz noise, yet will amplify a ±0.5 V differential signal while suppressing a ±10 V common-mode signal, or it will
amplify a ±1.25 V differential signal while suppressing a 1 V
offset by use of the DAC driving the reference pin of the
AD621. An added benefit, the offsetting DAC connected to the
reference pin allows removal of a dc signal without the associated time-constant of ac coupling. Note the representations of a
differential and common-mode signal shown in Figure 32 such
that a single-ended (or normal mode) signal of +1 V would be
composed of a +0.5 V common-mode component and a +1 V
differential component.
Table I. Make vs. Buy Error Budget
AD621 Circuit Discrete Circuit Error, ppm of Full Scale
Error Source Calculation Calculation AD621 Discrete
ABSOLUTE ACCURACY at T
= +25°C
A
Input Offset Voltage, µV 125 µV/20 mV (150 µV × 2/20 mV 16,250 15,000
Output Offset Voltage, µV N/A ((150 µV × 2)/100)/20 mV N/A 12,150
Input Offset Current, nA 2 nA × 350 Ω/20 mV (6 nA × 350 Ω)/20 mV 12,118 121,53
CMR, dB 110 dB→3.16 ppm, × 5 V/20 mV (0.02% Match × 5 V)/20 mV 12,791 14,988
Total Absolute Error 17,558 20,191
DRIFT TO +85°C
Gain Drift, ppm/°C 5 ppm × 60°C 100 ppm/°C Track × 60°C 13,300 12,600
Input Offset Voltage Drift, µV/°C1µV/°C × 60°C/20 mV (2.5 µV/°C × 2 × 60°C)/20 mV 13,000 15,000
Output Offset Voltage Drift, µV/°C N/A (2.5 µV/°C × 2 × 60°C)/100/20 mV N/A 12,150
Total Drift Error 13,690 15,750
RESOLUTION
Gain Nonlinearity, ppm of Full Scale 40 ppm 40 ppm 12,140 12,140
Typ 0.1 Hz–10 Hz Voltage Noise, µV p-p 0.28 µV p-p/20 mV (0.38 µV p-p × √2)120 mV 121,14 12,127
Total Resolution Error 121,54 121,67
Grand Total Error 11,472 36,008
G = 100, VS = ±15 V.
(All errors are min/max and referred to input.)
REV. A
–11–
Page 12
AD621
INPUT A:
±10V CM
V
COM
±10V–
INPUT B:
OFFSET
+
±1V
+
V
DIFF
±0.5V
–
+
V
+ V
DIFF
±(1.25V + 1V)
–
OFFSET
Optional
2
1
x10
AD621
8
3
0 TO ±10V
Use this in place of the DAC for zero suppression function.
5
TO
REF
6
DAC
V
G = 10
6
OUT1
C
AD548
10kΩ
2
1
8
10kΩ
3
R
2
3
x10
AD621
TO
V
OUT1
6
5
V
OUT2
TOTAL GAIN = 100
Figure 32. Suppressing a Large Common-Mode or Offset Voltage in Order to Measure a Small Differential Signal
= ±15 V)
(V
S
The AD621, as well as many other monolithic instrumentation
amplifiers, is based on the “three op amp” in amp circuit (Figure 33) amplifier. Since the input amplifiers (A1 and A2) have a
common-mode gain of unity and a differential gain equal to the
set gain of the overall in amp, the voltages V1 and V2 are defined by the equations
V
= VCM + G × V
1
= VCM – G × V
V
2
DIFF
DIFF
/2
/2
The common-mode voltage will drive the outputs of amplifiers
A1 and A2 to the differential-signal voltage, multiplied by the
gain, spreads them apart. For a +10 V common-mode +0.1 V
differential input, V1 would be at +10.5 V and V2 at +9.5 V.
INPUT AMPLIFIER
DIFFERENTIAL GAIN = 10
COMMON MODE GAIN = 1
A1
20kΩ
4.44kΩ
20kΩ
A2
OUTPUT AMPLIFIER
DIFFERENTIAL GAIN = 1
COMMON MODE GAIN = 1/1000
V1
10kΩ
V2
10kΩ
10kΩ
A3
10kΩ
The AD621’s input amplifiers can provide output voltage within
2.5 V of the supplies. To avoid saturation of the input amplifier
the input voltage must therefore obey the equations:
V
CM
V
CM
+ G × V
– G × V
/2 ≤ (Upper Supply – 2.5 V)
DIFF
/2 ≥ (Lower Supply + 2.5 V)
DIFF
Figure 34 shows the trade-off between common-mode and
differential-mode input for ±15 V supplies and G = 10.
By cascading with use of the optional AD621, the circuit of Figure 32 will provide ±1 V of zero suppression at gains of 10 and
100 (at V
OUT1
and V
respectively) with maximum TCs of
OUT2
±4 ppm/°C and ±8 ppm/°C, respectively. Therefore, depending
on the magnitude of the differential input signal, either V
V
may be used as the output.
OUT2
±1.2
±1.0
±0.8
– Volts
±0.6
DIFF
V
±0.4
±0.2
OUT1
or
Figure 33. Typical Three Op Amp Instrumentation
Amplifier, Differential Gain = 10
0
0
CM
Figure 34. Trade-Off Between VCM and V
±
15 V, G = 10), for Reference Pin at Ground
–12–
– VoltsV
DIFF
±12±10±6±4±2 ±8
Range (VS =
REV. A
Page 13
AD621
T
Precision V-I Converter
The AD621 along with another op amp and two resistors make
a precision current source (Figure 35). The op amp buffers the
reference terminal to maintain good CMR. The output voltage
V
of the AD621 appears across R1 which converts it to a cur-
X
rent. This current less only the input bias current of the op amp
then flows out to the load.
+V
S
V
IN+
V
IN–
I =
L
3
2
V
x
R1
AD621
=
7
5
4
–V
S
(V ) – (V ) G
IN+
IN–
R1
6
AD705
+ V –
x
R1
LOAD
I
L
Figure 35. Precision Voltage to Current Converter
(Operates on 1.8 mA,
±
3 V)
INPUT AND OUTPUT OFFSET VOLTAGE
The AD621 is fully specified for total input errors at gains of 10
and 100. That is, effects of all error sources within the AD621
are properly included in the guaranteed input error specs, eliminating the need for separate error calculation.
Total Error RTI = Input Error + (Output Error/G)
Total Error RTO = (Input Error × G) + Output Error
REFERENCE TERMINAL
Although usually grounded, the reference terminal may be used
to offset the output of the AD621. This is useful when the load
is “floating” or does not share a ground with the rest of the system. It also provides a direct means of injecting a precise offset.
Another benefit of having a reference terminal is that it can be
quite effective in eliminating ground loops and noise in a circuit
or system.
+V
S
R
V
OL
R
V
P
OL
GAIN = 10 OR 100
P
2
3
7
AD621
4
V
OU
6
5
INPUT OVERLOAD CONSIDERATIONS
Failure of a transducer, faults on input lines, or power supply
sequencing can subject the inputs of an instrumentation amplifier to voltages well beyond their linear range, or even the supply
voltage, so it is essential that the amplifier handle these overloads without being damaged.
The AD621 will safely withstand continuous input overloads of
±3.0 volts (±6.0 mA). This is true for gains of 10 and 100, with
power on or off.
The inputs of the AD621 are protected by high current capacity
dielectrically isolated 400 Ω thin-film resistors R3 and R4 (Figure 29) and by diodes which protect the input transistors Q1
and Q2 from reverse breakdown. If reverse breakdown occurred,
there would be a permanent increase in the amplifier’s input
current.
The input overload capability of the AD621 can be easily increased while only slightly degrading the noise, common-mode
rejection and offset drift of the device by adding external resistors in series with the amplifier’s inputs as shown in Figure 36.
Table II summarizes the overload voltages and total input noise
for a range of range of r values. Note that a 2 kΩ resistor in series with each input will protect the AD621 from a ± 15 volt
continuous overload, while only increasing input noise to
13 nV√
Hz—about the same level as would be expected from a
typical unprotected 3 op amp in amp.
Table II. Input Overload Protection vs. Value of Resistor R
P
Total Input Noise Maximum Continuous
Value of in nV√
Hz @ 1 kHz Overload Voltage, V
OL
Resistor RPG = 10 G = 100 In Volts
01493
499 Ω 14 10 6
1.00 kΩ 14 11 9
2.00 kΩ 15 13 15
3.01 kΩ*16 14 21
4.99 kΩ*17 16 33
*1/4 watt, 1% metal-film resistor. All others are 1/8 watt, 1% RN55
or equivalent.
REV. A
–V
S
Figure 36. Input Overload Protection
–13–
Page 14
AD621
7
4
6
5
3
2
AD621
+V
S
–V
S
INPUTS
–
+
10
7
9
4
3
AD526
+V
S
–V
S
0.1µF
0.1µF
G = 10
8
5
6
0.1µF
OUTPUT
2
20kΩ
OFFSET
NULL
(OPTIONAL)
0.1µF
REFERENCE
V
OUT
AD621
100Ω
100Ω
– INPUT
+ INPUT
AD648
1
2
3
7
8
5
6
4
+V
S
–V
S
100kΩ
100kΩ
–V
Gain Selection
The AD621 has accurate, low temperature coefficient (TC),
gains of 10 and 100 available. The gain of the AD621 is nominally set at 10; this is easily changed to a gain of 100 by simply
connecting a jumper between Pins 1 and 8.
2
555.5Ω
R
EXT
5,555.5Ω
3
Figure 37. Programming the AD621 for Gains Between
10 and 100
As shown in Figure 37, the device can be programmed for any
gain between 10 and 100 by connecting a single external resistor
between Pins 1 and 8. Note that adding the external resistor will
degrade both the gain accuracy and gain TC. Since the gain
equation of the AD621 yields:
G =1+
9(R
This can be solved for the nominal value of external resistor for
gains between 10 and 100:
(G – 1)555.555 – 55,000
RX=
Table III gives practical 1% resistor values for several common
gains.
...
AD621
...
5
+6 ,111.111)
X
+555.555)
(R
X
(10 – G)
6
Figure 38. A High Performance Programmable Gain
Amplifier
COMMON-MODE REJECTION
Instrumentation amplifiers like the AD621 offer high CMR
which is a measure of the change in output voltage when both
inputs arc changed by equal amounts. These specifications are
usually given for a full-range input voltage change and a specified source imbalance.
For optimal CMR the reference terminal should be tied to a low
impedance point, and differences in capacitance and resistance
should be kept to a minimum between the two inputs. In many
applications shielded cables are used to minimize noise, and for
best CMR over frequency the shield should he properly driven.
Figures 39 and 40 show active data guards which are configured
to improve ac common-mode rejections by “bootstrapping” the
capacitances of input cable shields, thus minimizing the capacitance mismatch between the inputs.
Table III. Practical 1% External Resistor
Values for Gains Between 10 and 100
Desired Recommended Gain Error Temperature
Gain 1% Resistor Value Coefficient (TC)
10 ∞ (Pins 1 and 8 Open) * *5 ppm/°C max
20 4.42 k ≈±10% ≈0.4 (50 ppm/°C
+ Resistor TC)
50 698 Ω≈±10% ≈0.4 (50 ppm/°C
+ Resistor TC)
100 0 (Pins 1 and 8 Shorted)* *5 ppm/°C max
A High Performance Programmable Gain Amplifier
The excellent performance of the AD621 at a gain of 10 make it
a good choice to team up with the AD526 programmable gain
amplifier (PGA) to yield a differential input PGA with gains of
10, 20, 40, 80, 160. As shown in Figure 38, the low offset of the
AD621 allows total circuit offset to be trimmed using the offset
null of the AD526, with only a negligible increase in total drift
error. The total gain TC will be 9 ppm/°C max, with 2 µV/°C
typical input offset drift. Bandwidth is 600 kHz to gains of 10 to
80, and 350 kHz at G = 160. Settling time is 13 µs to 0.01%
for a 10 V output step for all gains.
–14–
Figure 39. Differential Shield Driver, G = 10
+V
S
7
AD621
4
–V
S
6
5
REFERENCE
V
OUT
100Ω
– INPUT
AD548
+ INPUT
2
1
8
3
Figure 40. Common-Mode Shield Driver, G = 100
REV. A
Page 15
GROUNDING
V
OUT
7
+V
S
–V
S
AD621
– INPUT
+ INPUT
LOAD
TO POWER
SUPPLY
GROUND
REFERENCE
2
3
4
5
6
Since the AD621 output voltage is developed with respect to the
potential on the reference terminal, it can solve many grounding
problems by simply tying the REF pin to the appropriate “local
ground.”
In order to isolate low level analog signals from a noisy digital
environment, many data-acquisition components have separate
analog and digital ground pins (Figure 41). It would be convenient to use a single ground line; however, current through
ground wires and PC runs of the circuit card can cause hundreds of millivolts of error. Therefore, separate ground returns
should be provided to minimize the current flow from the sensitive points to the system ground. These ground returns must be
tied together at some point, usually best at the ADC package as
shown.
1µF1µF
7
DIGITAL P.S.
15
9
11
AD574A
ADC
C
+5V
1µF
+
1
DIGITAL
DATA
OUTPUT
2
3
0.1µF
7
AD621
4
5
ANALOG P.S.
+15VC–15V
11
6
6
0.1µF
AD585
S/H
4
Figure 41. Basic Grounding Practice
AD621
Figure 42b. Ground Returns for Bias Currents when Using
a Thermocouple Input
+V
7
AD621
4
–V
S
S
6
5
REFERENCE
LOAD
V
OUT
100kΩ
– INPUT
+ INPUT
100kΩ
2
3
GROUND RETURNS FOR INPUT BIAS CURRENTS
Input bias currents are those currents necessary to bias the input
transistors of an amplifier. There must be a direct return path
for these currents; therefore when amplifying “floating” input
sources such as transformers, or ac-coupled sources, there must
be a dc path from each input to ground as shown in Figures 42a
through 42c. Refer to the Instrumentation Amplifier Application
Guide (free from Analog Devices) for more information regarding in amp applications.
+V
7
AD621
4
–V
S
S
6
5
REFERENCE
V
OUT
LOAD
TO POWER
SUPPLY
GROUND
– INPUT
2
3
+ INPUT
Figure 42a. Ground Returns for Bias Currents when Using
Transformer Input Coupling
TO POWER
SUPPLY
GROUND
Figure 42c. Ground Returns for Bias Currents when Using
AC Input Coupling
REV. A
–15–
Page 16
AD621
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
Plastic DIP (N-8) Package
0.165 ± 0.01
(4.19 ± 0.25)
SEATING PLANE
0.125 (3.18)
0.200
(5.08)
MAX
0.200 (5.08)
0.125 (3.18)
MIN
0.018 ± 0.003
(0.46 ± 0.08)
8
1
0.39 (9.91)
0.033
(0.84)
NOM
MAX
0.10
(2.54)
TYP
5
4
Cerdip (Q-8) Package
0.005 (0.13) MIN 0.055 (1.4) MAX
58
0.310 (7.87)
0.220 (5.59)
41
0.405 (10.29) MAX
0.060 (1.52)
0.015 (0.38)
0.25
(6.35)
0.035 ± 0.01
(0.89 ± 0.25)
0.18 ± 0.03
(4.57 ± 0.76)
0.070 (1.78)
0.030 (0.76)
0.150
(3.81)
MIN
0.31
(7.87)
0 - 15
0.320 (8.13)
0.290 (7.37)
0.015 (0.38)
0.008 (0.20)
0.30 (7.62)
REF
0.011 ± 0.003
(4.57 ± 0.76)
C1673–24–6/92
0.050 (1.27)
0.010 (0.25)
0.004 (0.10)
0.023 (0.58)
0.014 (0.36)
0.198 (5.03)
0.188 (4.77)
8
1
TYP
0.100 (2.54)
BSC
0 - 15
SEATING PLANE
SOIC (R-8) Package
5
0.158 (4.00)
0.150 (3.80)
0.244 (6.200)
4
0.018 (0.46)
0.014 (0.36)
0.094(2.39)
0.100 (2.59)
0.228 (5.80)
0.015 (0.38)
0.007 (0.18)
0.205 (5.20)
0.181 (4.60)
PRINTED IN U.S.A.
0.045 (1.15)
0.020 (0.50)
–16–
REV. A
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