Datasheet AD608 Datasheet (Analog Devices)

Low Power Mixer/Limiter/RSSI

a

FEATURES
Mixer

–15 dBm 1 dB Compression Point
–5 dBm IP3
24 dB Conversion Gain
>500 MHz Input Bandwidth

Logarithmic/Limiting Amplifier

80 dB RSSI Range
638 Phase Stability over 80 dB Range

Low Power

21 mW at 3 V Power Consumption
CMOS-Compatible Power-Down to 300 mW typ
200 ns Enable/Disable Time

APPLICATIONS
PHS, GSM, TDMA, FM, or PM Receivers
Battery-Powered Instrumentation
Base Station RSSI Measurement

GENERAL DESCRIPTION

The AD608 provides both a low power, low distortion, low
noise mixer and a complete, monolithic logarithmic/limiting
amplifier using a “successive-detection” technique. It provides
both a high speed RSSI (Received Signal Strength Indicator)
output with 80 dB dynamic range and a hard-limited output.
The RSSI output is from a two-pole post-demodulation low­pass filter and provides a loadable output voltage of +0.2 V to
+1.8 V. The AD608 operates from a single 2.7 V to 5.5 V sup­ply at a typical power level of 21 mW at 3 V.

3 V Receiver IF Subsystem

AD608

The RF and LO bandwidths both exceed 500 MHz. In a typical
IF application, the AD608 will accept the output of a 240 MHz
SAW filter and downconvert it to a nominal 10.7 MHz IF with
a conversion gain of 24 dB (Z
rithmic/limiting amplifier section handles any IF from LF to as
high as 30 MHz.

The mixer is a doubly-balanced “Gilbert-Cell” type and oper­ates linearly for RF inputs spanning –95 dBm to –15 dBm. It
has a nominal –5 dBm third-order intercept. An onboard LO
preamplifier requires only –16 dBm of LO drive. The mixer’s
current output drives a reverse-terminated, industry-standard

10.7 MHz 330 Ω filter.
The nominal logarithmic scaling is such that the output is

+0.2 V for a sinusoidal input to the IF amplifier of –75 dBm
and +1.8 V at an input of +5 dBm; over this range the logarith­mic conformance is typically ±1 dB. The logarithmic slope is
proportional to the supply voltage. A feedback loop automati­cally nulls the input offset of the first stage down to the sub­microvolt level.

The AD608’s limiter output provides a hard-limited signal out­put at 400 mV p-p. The voltage gain of the limiting amplifier to
this output is more than 100 dB. Transition times are 11 ns and
the phase is stable to within ± 3° at 10.7 MHz for signals from
–75 dBm to +5 dBm.

The AD608 is enabled by a CMOS logic-level voltage input,
with a response time of 200 ns. When disabled, the standby
power is reduced to 300 µW within 400 ns.

The AD608 is specified for the industrial temperature range of
–25°C to +85°C for 2.7 V to 5.5 V supplies and –40°C to +85°C
for 4.5 V to 5.5 V supplies. It comes in a 16-pin plastic SOIC.

= 165 Ω). The AD608’s loga-

IF

FUNCTIONAL BLOCK DIAGRAM

RFHI

RF INPUT

–95 TO

–15dBm

RFLO

5

1

6

VPS1 COM1

+2.7V TO

5.5V

PREAMP

1

24dB MIXER GAIN

±6mA MAX OUTPUT
(±890mV INTO 165Ω)

MIXER

≈

LO

MID-SUPPLY

LOHI

COM2

2 4

3

LO INPUT
–16dBm

MXOP

BPF

DRIVER

VMID

IF BIAS

BIAS

PRUP

16

CMOS LOGIC

INPUT

7

8

3dB NOMINAL

INSERTION LOSS

10.7MHz

BANDPASS

FILTER

330Ω

100nF

IF INPUT

–75dBm TO

+15dBm

330Ω

100Ω

18nF

10nF

REV. B

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

110dB LIMITER GAIN

90dB RSSI

RSSI OUTPUT

7 FULL-WAVE

2

IFHI

9

10

IFLO

13

FDBK

RECTIFIER CELLS

5-STAGE IF AMPLIFIER

(16dB PER STAGE)

≈

2MHz
LPF

AD608

NOTES:

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] Fax: [phone]

1

–15dBm = ±56mV MAX FOR LINEAR OPERATION

2

39.76µV RMS TO 397.6mV RMS FOR ±1dB RSSI

ACCURACY

RSSI

20mV/dB

11

COM3

VPS2

LMOP

FINAL

LIMITER

±50µA

© Analog Devices, Inc., 1996

0.2V TO 1.8V

12

+2.7V TO 5.5V

14

15

LIMITER
OUTPUT
400mVp-p

AD608–SPECIFICA TIONS

(@ TA = + 258C, Supply = 3 V, dBm is referred to 50 V, unless otherwise noted)

Model AD608

Conditions Min Typ Max Units

MIXER PERFORMANCE

RF and LO Frequency Range 500 MHz
LO Power Input Terminated in 50 Ω –16 dBm
Conversion Gain Driving Doubly-Terminated 330 Ω IF Filter, Z
Noise Figure Matched Input, f

Matched Input, f

= 100 MHz 11 dB

RF

= 240 MHz 16 dB

RF

= 165 Ω 19 24 28 dB

IF

1 dB Compression Point Input Terminated in 50 Ω –15 dBm
Third-Order Intercept f
Input Resistance f

= 240 MHz and 240.02 MHz, fLO = 229.3 MHz –5 dBm

RF

= 100 MHz (See Table I) 1.9 kΩ

RF

Input Capacitance fRF = 100 MHz (See Table I) 3 pF

LIMITER PERFORMANCE

Gain Full Temperature and Supply Range 110 dB
Limiting Threshold 3° rms Phase Jitter at 10.7 MHz –75 dBm

280 kHz IF Bandwidth
Input Resistance 10 kΩ
Input Capacitance 3pF
Phase Variation –75 dBm to +5 dBm IF Input Signal at 10.7 MHz ±3 Degree
DC Level Center of Output Swing (VPOS-1) 2 V
Output Level Limiter Output Driving 5 kΩ Load 400 mV p-p
Rise and Fall Times Driving a 5 pF Load 11 ns
Output Impedance 200 Ω

RSSI PERFORMANCE At 10.7 MHz

Nominal Slope At VPOS = 3 V; Proportional to VPOS 17.27 20 23.27 mV/dB
Nominal Intercept –85 dBm
Minimum RSSI Voltage –75 dBm Input Signal 0.2 V
Maximum RSSI Voltage +5 dBm Input Signal 1.8 V
RSSI Voltage Intercept 0 dBm Input Signal 1.57 1.82 V
Logarithmic Linearity Error –75 dBm to +5 dBm Input Signal at IFHI ±1dB
RSSI Response Time 90% RF to 50% RSSI 200 ns
Output Impedance At Midscale 250 Ω

POWER-DOWN INTERFACE

Logical Threshold System Active on Logical High 1.5 V
Input Current For Logical High 75 µA
Power-Up Response Time Active Limiter Output 200 ns
Power-Down Response Time To 200 µA Supply Current 400 ns
Power-Down Current 100 µA

POWER SUPPLY

Operating Range –25°C to +85°C 2.7 5.5 V

–40°C to +85°C 4.5 5.5 V
Powered Up Current VPOS = 3 V 7.3 mA

OPERATING TEMPERATURE

T

to T

MIN

T

MIN

Specifications subject to change without notice.

to T

MAX
MAX

VPOS = 2.7 V to 5.5 V –25 +85 °C

VPOS = 4.5 V to 5.5 V –40 +85 °C

–2–

REV. B

AD608

WARNING!

ESD SENSITIVE DEVICE

VPS1

COM1

PRUP
LMOP

RFHI

RFLO

MXOP

COM3
RSSI
IFLO

LOHI

COM2

VPS2
FDBK

VMID IFHI

1
2

16
15

5
6
7

12
11
10

3
4

14
13

89

TOP VIEW

(Not to Scale)

AD608

ABSOLUTE MAXIMUM RATINGS

Supply Voltage VPS1, VPS2 . . . . . . . . . . . . . . . . . . . . . . +6 V

Internal Power Dissipation

2

. . . . . . . . . . . . . . . . . . . .600 mW

1

Temperature Range . . . . . . . . . . . . . . . . . . . . .–40°C to +85°C

Storage Temperature Range . . . . . . . . . . . . .–65°C to +150°C

Lead Temperature (Soldering 60 sec) . . . . . . . . . . . . . +300°C

NOTES

1

Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only, and functional
operation of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended rating conditions for extended periods
may affect device reliability.

2

Thermal Characteristics:
16-Pin SOIC Package: θJA = 110°C/W.

ORDERING GUIDE

Temperature Package

Model Range Option

AD608AR –25°C to +85°C, R-16A*

2.7 V to 5.5 V Supplies;
–40°C to +85°C,

4.5 V to 5.5 V Supplies

*R = Small Outline IC (SOIC).

PIN DESCRIPTIONS

Pin Mnemonic Description

1 VPS1 Positive Supply Input
2 COM1 Common
3 LOHI Local Oscillator Input Connection
4 COM2 Common
5 RFHI RF Input, Noninverting
6 RFLO RF Input, Inverting
7 MXOP Mixer Output
8 VMID Midpoint Supply Bias

Output
9 IFHI IF Input, Noninverting
10 IFLO IF Input, Inverting
11 RSSI Received Signal Strength Indicator

Output
12 COM3 Output Common
13 FDBK Offset-Null Feedback Loop Output
14 VPS2 Limiter Positive Supply Input
15 LMOP Limiter Output
16 PRUP Power-Up

TERMINAL DIAGRAM

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD608 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

REV. B

–3–

AD608

INPUT POWER AT IFHI – dBm

RSSI – V

3.0

0
–80 –70 10

–60 –50 –40 –20 –10 0–30

2.5

2.0

1.5

1.0

0.5

5V

3V

1
2
3
4
5
6
7
8

16
15
14
13
12
11
10

9

AD608

VPS1
COM1

RFHI
RFLO
MXOP

LOHI
COM2

VMID

PRUP

LMOP

COM3

RSSI
IFLO

VPS2

FDBK

IFHI

VPOS

LO IN

RF IN

IF OUT

NC

NC

0.1µF
1nF

51.1Ω

1nF

332Ω

301Ω

0.1µF

54.9Ω

51.1Ω

1nF

0.1µF

332Ω

10nF

100Ω

18nF

18nF

47kΩ

NC = NO CONNECT

PRUP IN

4.7k

1

0.1µF

332Ω

2
3
4
5

6

7

8

VPS1
COM1
LOHI
COM2
RFHI
RFLO
MXOP
VMID

VPOS

51.1Ω

0.1µF

51.1Ω

1nF

1nF

AD608

0.1µF

332Ω

U1 – 74HC00

Figure 1. IF Test Board Schematic

25.0

24.5

24.0

23.5

23.0

CONVERSION GAIN – dB

22.5

22.0
100 150 200 250 300 350 400 450

0 50 500

RF FREQUENCY – MHz

U1A

U1B

PRUP

LMOP

VPS2

FDBK

COM3

RSSI
IFLO

IFHI

16
15
14
13
12
11
10

9

IF INPUT

47kΩ

0.1µF

18nF

100Ω

10nF

301Ω

54.9Ω

TRIGGER

LMOP OUT

RSSI OUTPUT

0.1µF

0

–1

–2

–3

–4

–5

RESPONSE – dB

–6

–7

–8

010 80

20 30 40 50 60 70

IF FREQUENCY – MHz

Figure 2. Mixer Test Board Schematic

Figure 3. Mixer Conversion Gain vs.
Frequency

3.0

2.5

2.0

1.5

RSSI – V

1.0

0.5

Figure 6. IF RSSI Output vs.
Temperature (3 V Supply)

+85
+25
–25

0

–60 –50 –40 –20 –10 0–30

INPUT POWER – dBm

–80 –70 10

Figure 4. Mixer IF Port Bandwidth

FLUKE 6082A
SYNTHESIZER

10.7 MHz

Figure 7. Test Circuit for IF RSSI Out­put vs. Supply Voltage (Ambient Tem­perature) (Figure 5) and IF RSSI
Output vs. Temperature (3 V Supply)

IF TEST BOARD

IFHI

RSSI

VPOS

DCPS 3V

HP3366A

(Figure 6) and RSSI Error vs. Input
Power (Figure 8)

–4–

DMM

HP34401A

Figure 5. IF RSSI Output vs. Supply
Voltage (Ambient Temperature)

4.0

3.0

2.0

1.0

0

–1.0

RSSI ERROR – dB

–2.0

–3.0

–4.0

–80 –70 10–60 –50 –40 –20 –10 0–30

INPUT POWER – dBm

3V

5V

Figure 8. RSSI Error vs. Input Power

REV. B

AD608

IFHI

VPOS

LMOP

IF TEST BOARD

10.7 MHz

FLUKE 6082A
SYNTHESIZER

DCPS 3V

HP3366A

FET

PROBE

TEK P6201

HP54120A

0dBm

DIGITAL

OSCILLOSCOPE

PRUP

100ns/DIV

1V/DIV

220mV/DIV

100ns/DIV

LMOP

IFHI

VPOS

LMOP

IF TEST BOARD

10.7 MHz

FLUKE 6082A
SYNTHESIZER

3V

HP6633A

FET

PROBE

TEK P6201

PRUP TRIGGER

CH 1

CH 2

HP54120A

DIGITAL

OSCILLOSCOPE

0dBm

DCPS

800mV/DIV

RSSI

100ns/DIV

1V /DIV

PRUP

100ns/DIV

Figure 9. RSSI Power-Up Response

FLUKE 6082A
SYNTHESIZER

10.7 MHz
0dBm

IF TEST BOARD

IFHI

PRUP TRIGGER

RSSI

VPOS

DCPS 3V

HP3366A

TEK P6201

FET

PROBE

HP54120A

DIGITAL

OSCILLOSCOPE

CH 1

CH 2

Figure 10. Test Circuit for RSSI Power-Up Response
(Figure 9)

60mV/DIV

LMOP

20ns/DIV

Figure 13. Limiter Rise and Fall Times

Figure 14. Test Circuit for Limiter Rise and Fall Times
(Figure 13)

200mV/DIV

IFHI

RSSI

800mV/DIV

50ns/DIV

Figure 11. RSSI Pulse Response/RSSI Rise Time

FLUKE 6082A
SYNTHESIZER

10.7 MHz
0dBm

COUPLER

MCL

ZDC-20-1

IF TEST BOARD

IFHI

VPOS

DCPS 3V

HP3366A

RSSI

TEK P6201

FET

PROBE

CH 1

CH 2

HP54120A

DIGITAL

OSCILLOSCOPE

Figure 12. Test Circuit for RSSI Pulse Response/RSSI Rise
Time (Figure 11)

REV. B

Figure 15. Limiter Power-Up Response Time

Figure 16. Test Circuit for Limiter Power-Up Response
Time (Figure 15)

–5–

AD608

Figure 17. Limiter Phase Performance vs.
Input Power at IFHI

FLUKE 6082A
SYNTHESIZER

10.7 MHz

5
4
3
2
1

0
–1
–2

RELATIVE PHASE – Degrees

–3
–4

–5

MCL

ZDC-20-1

COUPLER

–60 –50 –40 –20 –10 0–30

–80 –70 10

INPUT POWER – dBm

IF TEST BOARD

HP8494A
HP8495A

TEK P6201

IFHI RSSI

DCPS

3V

HP3366A

280kHz BW

10.7MHz CF

TOKO SK107MK1-A0-10

PROBE

FET

BPF

HP8447A

HP54120A

DIGITAL

OSCILLOSCOPE

CH 1

TRIG

10

9
8
7
6
5
4

RMS JITTER – Degrees

3
2
1

0

–80 –70 10

–60 –50 –40 –20 –10 0–30

INPUT POWER AT IFHI – dBm

Figure 19. Limiter Jitter Performance vs.
Input Power at IFHI

Figure 18. Test Circuit for Limiter Phase Performance vs.
Input Power at IFHI (Figure 17) and Limiter Jitter Perfor­mance vs. Input Power at IFHI (Figure 19)

–6–

REV. B

AD608

THEORY OF OPERATION

The AD608 (Figure 20) consists of a mixer followed by a loga­rithmic IF strip with RSSI and hard limited outputs. Each sec­tion will be described below.

Mixer

The mixer is a doubly-balanced modified Gilbert cell mixer. Its
maximum input level for linear operation is ± 56.2 mV regard­less of the impedance across the mixer’s inputs, or –15 dBm for
a 50 Ω input termination. The input impedance of the mixer
can be modeled as a simple parallel RC network; the values ver­sus frequency are listed in Table I. The bandwidth from the RF
input to the IF output at MXOP pin is –1 dB at 30 MHz and
then falls off rapidly (Figure 4).

INSERTION LOSS

BANDPASS

7

330Ω

8

3dB NOMINAL

IF INPUT

–75dBm TO

+15dBm

10.7MHz
FILTER

100nF

100Ω

10nF

18nF

2.

IFHI

9

330Ω

10

IFLO

13

FDBK

5

RFHI

RF INPUT

–95 TO

1.

–15dBm

RFLO

6

VPS1 COM1

+2.7V TO 5.5V LO INPUT

24dB MIXER GAIN 110dB LIMITER GAIN

±6mA MAX OUTPUT
(±890mV INTO 165Ω)

MIXER

LO

PREAMP

LOIP

1 2 3 4 16

–16dBm

≈

DRIVER

MID-SUPPLY

IF BIAS

BIAS

COM2

CMOS LOGIC

INPUT

MXOP

BPF

VMID

PRUP

Mixer Gain

The mixer’s conversion gain is the product of its transcon­ductance and the impedance seen at pin MXOP. For a 330 Ω
parallel-terminated filter at 10.7 MHz, the load impedance is
165 Ω, the gain is 24 dB, and the output is 15.85 × 56.2 mV, or
±891 mV, centered on the midpoint of the supply voltage. For
other load impedances, the expression for the gain in dB is

GdB= 20 log100.0961 R

()

L

The mixer’s gain can be increased or decreased by changing RL,
the load impedance at pin MXOP. The limitations on the
mixer’s gain are the ±6 mA maximum output current at MXOP
and the maximum allowable voltage swing at pin MXOP, which
is ±1.0 V for a 3 V supply or 5 V supply.

90dB RSSI

RSSI OUTPUT

FINAL

LIMITER

RSSI

COM3

VPS2

LMOP

±50µA

11

20mV/dB

0.2V TO 1.8V

12

+2.7V TO 5.5V

14

LIMITER

15

OUTPUT
400mVp-p

RECTIFIER CELLS

5-STAGE IF AMPLIFIER

(16dB PER STAGE)

NOTES:

1. –15dBm = ±56mV MAX FOR LINEAR OPERATION

2. 39.76mV RMS TO 396.6mV RMS FOR ±1 dB
RSSI ACCURACY

7 FULL-WAVE

AD608

≈

Figure 20. Functional Block Diagram

Table I. Mixer Input Impedance vs. Frequency

Frequency Resistance Capacitance
(MHz) (Ohms) (pF)

45 2800 3.1
70 2600 3.1
100 1800 3.1
200 1200 3.1
300 760 3.2
400 520 3.4
500 330 3.6

REV. B

–7–

AD608

IF Filter Terminations

The AD608 was designed to drive a parallel-terminated 10.7 MHz
bandpass filter with a 330 Ω impedance. With a 330 Ω parallel­terminated filter, pin MXOP sees a 165 Ω termination and the
gain is nominally 24 dB. Other filter impedances and gains can
be accommodated by either accepting an increase or decrease in
gain in proportion to the filter impedance or by keeping the im­pedance seen by MXOP a nominal 165 Ω (by using resistive di­viders or matching networks). Figure 21 shows a simple resistive
voltage divider for matching an assortment of filter impedances,
and Table II lists component values.

The Logarithmic IF Amplifier

The logarithmic IF amplifier consists of five amplifier stages
of 16 dB gain each, plus a final limiter. The IF bandwidth is
30 MHz (–1 dB) and the limiting gain is 110 dB. The phase
skew is ±3° from –75 dBm to +5 dBm (approximately 111 µV
p-p to 1.1 V p-p). The limiter output impedance is 200 Ω
and the limiter’s output drive is ± 2 0 0 m V (400 mV p-p) into a

12dB NOMINAL

INSERTION LOSS

(ASSUMES 6dB IN FILTER)

BANDPASS

FILTER

R2

7

R1

8

R3

100nF

C5

10

R4

13

C1

RFHI

RFLO

+5V

24dB MIXER GAIN

5

6

VPS1 COM1

1 2 3 4 16

C1

1µF

PREAMP

MIXER

LOHI

LO INPUT
–16dBm

≈

MID-SUPPLY

IF BIAS

COM2

C2
100pF

MXOP

BPF

DRIVER

VMIDLO

BIAS

PRUP

CMOS
LOGIC
INPUT

47kΩ

5 kΩ load. In the absence of an input signal, the limiter’s output
will limit on noise fluctuations, which produces an output that
continues to swing 400 mV p-p but with random zero crossings.

Offset Feedback Loop

Because the logarithmic amplifier is dc coupled and has more
than 110 dB of gain from the input to the limiter output, a dc
offset at its input of even a few µV would cause the output to
saturate. Thus, the AD608 uses a low frequency feedback loop
to null out the input offset. Referring to Figure 21, the loop
consists of a current source driven by the limiter, which sends
50 µA current pulses to pin FDBK. The pulses are low pass
filtered by a π-network consisting of C1, R4, and C5. The
smoothed dc voltage that results is subtracted from the input to
the IF amplifier at pin IFLO. Because this is a high gain ampli­fier with a feedback loop, care should be taken in layout and
component values to prevent oscillation. Recommended values
for the common IFs of 450 kHz, 455 kHz, 6.5 MHz, and

10.7 MHz are listed in Table II.

110dB LIMITER GAIN

90dB RSSI

9

IFHI

IFLO

FDBK

7 FULL-WAVE

RECTIFIER CELLS

5-STAGE IF AMPLIFIER

(16dB PER STAGE)

AD608

≈

2MHz

LPF

FINAL

LIMITER

±50µA

11

RSSI

12

COM3

14

VPS2

15

LMOP

Figure 21. Applications Diagram for Common IFs and Filter Impedances

Table II. AD608 Filter Termination and Offset-Null Feedback Loop Resistor and Capacitor Values for Common IFs

Filter Filter Termination Resistor Offset Null

IF Impedance Values1 for 24 dB of Mixer Gain Feedback Loop Values

R1 R2 R3 R4 C1 C5

450 kHz

2

1500 Ω 174 Ω 1330 Ω 1500 Ω 1000 Ω 200 nF 100 nF

455 kHz 1500 Ω 174 Ω 1330 Ω 1500 Ω 1000 Ω 200 nF 100 nF

6.5 MHz 1000 Ω 178 Ω 825 Ω 1000 Ω 100 Ω 18 nF 10 nF

10.7 MHz 330 Ω 330 Ω 0 Ω 330 Ω 100 Ω 18 nF 10 nF

NOTES

1

Resistor values were calculated so that R1 + R2 = Z

2

Operation at IFs of 450 kHz and 455 kHz requires an external low pass filter with at least one pole at a cutoff frequency of 90 kHz (a decade below the ripple

at 900 kHz).

and R1i(R2+Z

FILTER

FILTER

) = 165 Ω.

–8–

REV. B

AD608

RSSI Output

The logarithmic amplifier uses a successive detection architec­ture. Each of the five stages has a full-wave detector; two addi­tional high level detectors are driven through attenuators at the
input to the limiting amplifiers, for a total of seven detector
stages. Because each detector is a full-wave rectifier, the ripple
component in the resulting dc is at twice the IF. The AD608’s
low-pass filter has a 2 MHz cutoff frequency, which is one
decade below the 21.4 MHz ripple that results from a 10.7 MHz
IF.

For operation at lower IFs such as 450 kHz or 455 kHz, the
AD608 requires an external low-pass filter with a single pole lo­cated at 90 kHz, a decade below the 900 kHz ripple frequency
for these IFs. The RSSI range is from the noise level at approxi­mately –80 dBm to overload at +15 dBm and is specified for
±1 dB accuracy from –75 dBm to +5 dBm. The +15 dBm
maximum IF input is provided to accommodate bandpass filters
of lower insertion loss than the nominal 4 dB for 10.7 MHz
ceramic filters.

Digitizing the RSSI

In typical cellular radio applications, the RSSI output of the
AD608 will be digitized by an A/D converter. The AD608’s
RSSI output is proportional to the power-supply voltage, which
not only allows the A/D converter to use the supply as a refer­ence but also causes the RSSI output and the A/D converter’s
output to track over power supply variations, reducing system
errors and component costs.

Power Consumption

The total power-supply current of the AD608 is a nominal

7.3 mA. The power is signal-dependent, partly as the RSSI
output increases (the current is increased by 200 µA at an RSSI
output of +1.8 V) but mostly due to the IF BPF consumption
when being driven to ±891 mV assuming a 4 dB loss in this
filter and a peak input of +5 dBm to the log-IF amp, and tem­perature dependent, as the biasing system used in the AD608 is
proportional to absolute temperature (PTAT).

Troubleshooting

The most common causes of problems with the AD608 are
incorrect component values for the offset feedback loop, poor
board layout, and pickup of RFI, which all cause the AD608 to
“lose” the low end (typically below –65 dBm) of its RSSI output
and cause the limiter to swing randomly. Both poor board lay­out and incorrect component values in the offset feedback loop
can cause low level oscillations. Pickup of RFI can be caused by
improper layout and shielding of the circuit.

REV. B

–9–

AD608

Applications

Figure 22 shows the AD608 configured for operation in a digital
system at a 10.7 MHz IF. The filter’s input and output imped­ance are parallel terminated using 330 Ω resistors and the con­version gain is 24 dB. The RF port is terminated in 50 Ω; in a
typical application the input would be matched to a SAW filter
using the impedance data shown previously in Table I.

C1

1µF

VPS1

1

LO INPUT

–16dBm

RF INPUT

–95dBm

TO

–15dBm

BIAS POINT

100pF

R5

51.1Ω

100pF

R6

51.1Ω

AT VPOS/2

BPF REVERSE

TERMINATION

C2

C3

C4

100pF

COM1

2

LOHI

3

COM2

4

RFHI

5

RFLO

6

MXOP

7

VMID

8

AD608

10.7MHz BPF Z = 330Ω

R1
330Ω

IF BIAS POINT

DECOUPLING

Figure 23 shows the AD608 configured for narrowband FM op­eration at a 450 kHz or 455 kHz with an external discriminator.
The IF filter has 1500 Ω input and output impedances— the
input is matched via a resistive divider and the output is termi­nated in 1500 Ω. The discriminator requires 1 V p-p drive from
a 1 kΩ source impedance, here provided by a gain-of-2.5 Class
A amplifier.

VPOS

SUPPLY

PRUP

LMOP

VPS2

FDBK

COM3

RSSI

IFLO

IFHI

C5

0.1µF

16
15
14

13
12

11

10

9

330Ω

R2

C7
18nF

C6

10nF

TERMINATION

2.7V TO 5.5V

R4

POWER-UP

47kΩ

3V CMOS

LIMO

LIMITER
OUTPUT
VPOS –1V
±200mV

R3
100Ω

RSSI OUTPUT
+0.2V TO +1.8V
(20mV/dB)

OFFSET-CONTROL

LOOP FILTER

BPF

PRUP

+5V

GND

LOHI

RFHI

51.1Ω

51.1Ω

Figure 22. Application at 10.7 MHz. The Bandpass Filter
Can Be a Toko Type SK107 or Murata Type SFE10.7

JUMPER

R16

1

VPS1

C1 0.1µF

R1

C2

1nF

C3

R2

1nF

C4

1nF

374Ω

R7

1130Ω

2
3
4
5
6
7

R3

8

COM1
LOHI
COM2

RFHI
RFLO
MXOP
VMID

PRUP

LMOP

VPS2

FDBK

COM3

RSSI
IFLO

IFHI

AD608

F1

47kΩ

16
15
14
13
12
11
10

9

1kΩ

R6

1.5kΩ

0.2µF

R4

C9

C5 0.1µF

C8 0.1µF

C6 0.1µF

R5 200Ω

C7

0.1µF

R13

R14

402

8.66k

R15

R12

24.9k

1k

RSSI

F1: TOKO HCFM2–455B
F2: MURATA CFY455S
CR1, CR2: 1N60
Q1: 2N3906

Q1

C11

0.1µF

F2

CR1

CR2

R10

3.3kΩ

R8

1k

C10

R9

0.01µF

1k

R11

3.3k

AUDIO

Figure 23. Narrowband FM Application at 450 kHz or 455 kHz

–10–

REV. B

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

16-Lead SOIC

(R-16A)

AD608

16 9

PIN 1

1

0.3937 (10.00)

0.3859 (9.80)

0.0098 (0.25)

0.0040 (0.10)

0.0500
(1.27)

BSC

0.0192 (0.49)

0.0138 (0.35)

0.1574 (4.00)

0.1497 (3.80)

8

0.0688 (1.75)

0.0532 (1.35)

0.2440 (6.20)

0.2284 (5.80)

0.0099 (0.25)

0.0075 (0.19)

8°
0°

0.0196 (0.50)

0.0099 (0.25)

0.0500 (1.27)

0.0160 (0.41)

x 45°

REV. B

–11–

AD608

C1990b–2–7/96

–12–

PRINTED IN U.S.A.

REV. B