Datasheet AD604ARS, AD604AN Datasheet (Analog Devices)

Page 1
Dual, Ultralow Noise
a
FEATURES Ultralow Input Noise at Maximum Gain:
0.80 nV/Hz, 3.0 pA/Hz
Two Independent Linear-in-dB Channels Absolute Gain Range per Channel Programmable:
0 dB to +48 dB (Preamp Gain = +14 dB), through +6 dB to +54 dB (Preamp Gain = +20 dB)
61.0 dB Gain Accuracy Bandwidth: 40 MHz (–3 dB) 300 kV Input Resistance Variable Gain Scaling: 20 dB/V through 40 dB/V Stable Gain with Temperature and Supply Variations Single-Ended Unipolar Gain Control Power Shutdown at Lower End of Gain Control Can Drive A/D Converters Directly
APPLICATIONS Ultrasound and Sonar Time-Gain Control High Performance AGC Systems Signal Measurement
PAI
PROGRAMMABLE
ULTRALOW NOISE
PREAMPLIFIER
G = 14–20dB
AD604

FUNCTIONAL BLOCK DIAGRAM

PAO
–DSX
LADDER NETWORK
PRECISION PASSIVE INPUT ATTENUATOR
+DSX
DIFFERENTIAL
ATTENUATOR
R-1.5R
0 TO –48.4dB
VGN
GAIN CONTROL
AND SCALING
AFA
FIXED GAIN
AMPLIFIER
+34.4dB
VREF
OUT
VOCM

PRODUCT DESCRIPTION

The AD604 is an ultralow noise, very accurate, dual channel, linear-in-dB variable gain amplifier (VGA) optimized for time­based variable gain control in ultrasound applications; however it will support any application requiring low noise, wide bandwidth variable gain control. Each channel of the AD604 provides a 300 k input resistance and unipolar gain control for ease of use. User determined gain ranges, gain scaling (dB/V) and dc level shifting of output further optimize application performance.
Each channel of the AD604 utilizes a high performance pre­amplifier that provides an input referred noise voltage of
0.8 nV/
Hz. The very accurate linear-in-dB response of the AD604 is achieved with the differential input exponential amplifier (DSX-AMP) architecture. Each of the DSX-AMPs comprise a variable attenuator of 0 dB to 48.36 dB followed by a high speed fixed gain amplifier. The attenuator is based on a seven stage R-1.5R ladder network. The attenuation between tap points is 6.908 dB and 48.36 dB for the ladder network.
Each independent channel of the AD604 provides a gain range of 48 dB which can be optimized for the application by program­ming the preamplifier with a single external resistor in the preamp feedback path. The linear-in-dB gain response of the AD604 can be described by the equation: G (dB) = (Gain Scaling (dB/V) × VGN (V)) + (Preamp Gain (dB) – 19 dB). Preamplifier gains between 5 and 10 (+14 dB and +20 dB)
provide overall gain ranges per channel of 0 dB through +48 dB and +6 dB through +54 dB. The two channels of the AD604 can be cascaded to provide greater levels of gain range by bypass­ing the 2nd channel’s preamplifier. However, in multiple channel systems, cascading the AD604 with other devices in the AD60x VGA family, which do not include a preamplifier may provide a more efficient solution. The AD604 provides access to the output of the preamplifier allowing for external filtering be­tween the preamplifier and the differential attenuator stage.
The gain control interface provides an input resistance of approximately 2 M and scale factors from 20 dB/V to 30 dB/V for a V
input voltage of 2.5 V to 1.67 V respect-
REF
ively. Note that scale factors up to 40 dB/V are achievable with reduced accuracy for scales above 30 dB/V. The gain scales linear-in-dB with control voltages of 0.4 V to 2.4 V with the 20 dB/V scale. Below and above this gain control range, the gain begins to deviate from the ideal linear-in-dB control law. The gain control region below 0.1 V is not used for gain control. In fact when the gain control voltage is <50 mV the amplifier channel is powered down to 1.9 mA.
The AD604 is available in a 24-pin plastic SSOP, SOIC and DIP, and is guaranteed for operation over the –40°C to +85°C temperature range.
REV. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 World Wide Web Site: http://www.analog.com Fax: 617/326-8703 © Analog Devices, Inc., 1996
Page 2
AD604–SPECIFICATIONS
(Each Amplifier Channel at TA = +258C, VS = 65 V, RS = 50 V, RL = 500 V, CL = 5 pF, V range (preamplifier gain = +14 dB), VOCM = 2.5 V, C1 and C2 = 0.1 mF (see Figure 35) unless otherwise noted)
Parameter Conditions Min Typ Max Unit
INPUT CHARACTERISTICS
Preamplifier
Input Resistance 300 k Input Capacitance 8.5 pF Input Bias Current –27 µA Peak Input Voltage Preamp Gain = +14 dB ±400 mV
Preamp Gain = +20 dB ±200 mV
Input Voltage Noise VGN
= 2.9 V, R
= 0
S
Preamp Gain = +14 dB 0.8 nV/ Preamp Gain = +20 dB 0.73 nV/
Input Current Noise Independent of Gain 3.0 pA/ Noise Figure R
= 50 , f = 1 MHz, VGN = 2.9 V 2.3 dB
S
R
= 200 , f =1 MHz, VGN
S
= 2.9 V 1.1 dB
DSX
Input Resistance 175 Input Capacitance 3.0 pF Peak Input Voltage 2.5 ± 2V Input Voltage Noise VGN Input Current Noise VGN Noise Figure R
= 2.9 V 1.8 nV/Hz = 2.9 V 2.7 pA/Hz
= 50 , f = 1 MHz, VGN = 2.9 V 8.4 dB
S
R
= 200 , f =1 MHz, VGN
S
= 2.9 V 12 dB
Common-Mode Rejection Ratio f = 1 MHz, VGN = 2.65 V –20 dB
= 2.50 V (Scaling = 20 dB/V), 0 dB to +48 dB gain
REF
Hz Hz Hz
OUTPUT CHARACTERISTICS
–3 dB Bandwidth Constant with Gain 40 MHz Slew Rate VGN = 1.5 V, Output = 1 V Step 170 V/µs Output Signal Range R
500 2.5 ± 1.5 V
L
Output Impedance f = 10 MHz 2 Output Short-Circuit Current ±40 mA Harmonic Distortion VGN
= 1 V, V
OUT
= 1 V p-p HD2 f = 1 MHz –54 dBc HD3 f = 1 MHz –67 dBc HD2 f = 10 MHz –43 dBc HD3 f = 10 MHz –48 dBc
Two-Tone Intermodulation VGN = 2.9 V, V
= 1 V p-p
OUT
Distortion (IMD) f = 1 MHz –74 dBc
f = 10 MHz –71 dBc
3rd Order Intercept f = 10 MHz, VGN
V
= 1 V p-p, Input Referred
OUT
1 dB Compression Point f = 1 MHz, VGN Channel-to-Channel Crosstalk V
= 1 V p-p, f = 1 MHz
OUT
= 2.65 V, –12.5 dBm
= 2.9 V, Output Referred +15 dBm
Ch #1: VGN = 2.65 V, Inputs Shorted –30 dB Ch #2: VGN = 1.5 V (Mid Gain) dB
Group Delay Variation 1 MHz < f < 10 MHz, Full Gain Range ±2ns V
Input Resistance 45 k
OCM
ACCURACY
Absolute Gain Error
0 dB to +3 dB 0.25 V < VGN < 0.400 V –1.2 +0.75 +3 dB +3 dB to +43 dB 0.400 V < VGN < 2.400 V –1.0 ±0.3 +1.0 dB +43 dB to +48 dB 2.400 V < VGN < 2.65 V –3.5 –1.25 +1.2 dB
Gain Scaling Error 0.400 V < VGN < 2.400 V ±0.25 dB/V Output Offset Voltage V Output Offset Variation V
= 2.500 V, V
REF
= 2.500 V, V
REF
= 2.500 V –50 ±30 +50 mV
OCM
= 2.500 V 30 50 mV
OCM
–2–
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Page 3
AD604
WARNING!
ESD SENSITIVE DEVICE
Parameter Conditions Min Typ Max Unit
GAIN CONTROL INTERFACE
Gain Scaling Factor V
Gain Range Preamp Gain = +14 dB 0 to +48 dB
Input Voltage (VGN) Range 20 dB/V, V Input Bias Current –0.4 µA Input Resistance 2M Response Time 48 dB Gain Change 0.2 µs V
Input Resistance 10 k
REF
POWER SUPPLY
Specified Operating Range One Complete Channel ±5V
Power Dissipation One Complete Channel 220 mW
Quiescent Supply Current VPOS, One Complete Channel 32 36 mA
Powered Down VPOS, VGN < 50 mV, One Channel 1.9 3.0 mA
Power-Up Response Time 48 dB Gain Change, V Power-Down Response Time 0.4 µs
= 2.5 V, 0.4 V < VGN < 2.4 V 19 20 21 dB/V
REF
= 1.67 V 30 dB/V
V
REF
Preamp Gain = +20 dB +6 to +54 dB
= 2.5 V 0.1 to 2.9 V
REF
One DSX Only +5 V
One DSX Only 95 mW
VPOS, One DSX Only 19 23 mA VNEG, One Preamplifier Only –15 –12 mA
VNEG, VGN < 50 mV, One Channel –150 µA
= 2 V p-p 0.6 µs
OUT

ABSOLUTE MAXIMUM RATINGS

Supply Voltage ±V
S
Pins 17, 18, 19, 20 (with Pins 16, 22 = 0 V) . . . . . . ±6.5 V
Input Voltages
Pins 1, 2, 11, 12 . . . . . . . . . . . . . VPOS/2 ±2 V Continuous
Pins 4, 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±2 V
Pins 5, 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . VPOS, VNEG
Pins 6, 7, 13, 14, 23, 24 . . . . . . . . . . . . . . . . . . . . VPOS, 0
Internal Power Dissipation
Plastic (N) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 W
Model Range u
AD604AN –40°C to +85°C57°C/W N-24 AD604AR –40°C to +85°C70°C/W R-24 AD604ARS –40°C to +85°C 112°C/W R-24
*N = Plastic DIP, R = Small Outline IC (SOIC), RS = Shrink Small Outline
Package (SSOP).

ORDERING GUIDE

Temperature Package
Small Outline (R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.7 W
Shrink Small Outline (RS) . . . . . . . . . . . . . . . . . . . . . 1.1 W
Operating Temperature Range . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature, Soldering 60 seconds . . . . . . . . . +300°C
NOTES
1
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional opera­tion of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maxi­mum rating conditions for extended periods may affect device reliability.
2
Pins 1, 2, 11, 12, 13, 14, 23, 24 are part of a single-supply circuit and the part will most likely be damaged if any of these pins are accidentally connected to VN.
3
When driven from an external low impedance source.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD604 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
JA
Option*
REV. 0
–3–
Page 4
AD604

PIN DESCRIPTIONS

Pin No. Mnemonic Description
Pin 1 –DSX1 CH1 Negative Signal Input to DSX1. Pin 2 +DSX1 CH1 Positive Signal Input to DSX1. Pin 3 PAO1 CH1 Preamplifier Output. Pin 4 FBK1 CH1 Preamplifier Feedback Pin. Pin 5 PAI1 CH1 Preamplifier Positive Input. Pin 6 COM1 CH1 Signal Ground; when connected to positive supply, Preamplifier1 will shut down. Pin 7 COM2 CH2 Signal Ground; when connected to positive supply, Preamplifier2 will shut down. Pin 8 PAI2 CH2 Preamplifier Positive Input. Pin 9 FBK2 CH2 Preamplifier Feedback Pin. Pin 10 PAO2 CH2 Preamplifier Output. Pin 11 +DSX2 CH2 Positive Signal Input to DSX2. Pin 12 –DSX2 CH2 Negative Signal Input to DSX2. Pin 13 VGN2 CH2 Gain-Control Input and Power-Down Pin. If grounded, device is off,
otherwise positive voltage increases gain. Pin 14 VOCM Input to this pin defines common-mode of output at OUT1 and OUT2. Pin 15 OUT2 CH2 Signal Output. Pin 16 GND2 Ground. Pin 17 VPOS Positive Supply. Pin 18 VNEG Negative Supply. Pin 19 VNEG Negative Supply. Pin 20 VPOS Positive Supply. Pin 21 GND1 Ground. Pin 22 OUT1 CH1 Signal Output. Pin 23 VREF Input to this pin sets gain-scaling for both channels +2.5 V = 20 dB/V, +1.67 V = 30 dB/V. Pin 24 VGN1 CH1 Gain-Control Input and Power-Down Pin. If grounded, device is off;
otherwise positive voltage increases gain.
PIN CONFIGURATION
1
–DSX1 +DSX1
PAO1
FBK1
PAI1 COM1 COM2
PAI2
FBK2
PAO2 +DSX2 –DSX2
2 3 4 5
AD604
6
TOP VIEW
(Not to Scale)
7
8
9 10 11 12
24
VGN1 VREF
23
OUT1
22
GND1
21 20
VPOS
19
VNEG
18
VNEG
17
VPOS GND2
16 15
OUT2
14
VOCM
13
VGN2
–4–
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Page 5
Typical Performance Characteristics (per Channel)–AD604
VGN – Volts
50
20
–10
0.1 2.9
40
30
10
0
0.5 0.9 1.3 1.7 2.1 2.5
ACTUAL
ACTUAL
30dB/V
VREF = 1.67V
20dB/V VREF
= 2.50V
GAIN – dB
VGN – Volts
GAIN ERROR – dB
2.0
0.2
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
0.7 1.2 1.7 2.2 2.7
FREQ = 5MHz
FREQ = 10MHz
FREQ = 1MHz
DELTA GAIN – dB
PERCENTAGE
25
–1.0
20
15
10
5
0
–0.8
–0.6 –0.4 –0.2
0.1 0.3 0.5
0.7
0.9
G(dB) = G(CH1) – G(CH2)
VGN1 = 2.50V VGN2 = 2.50V
N = 50
(Unless otherwise noted G (preamp) = +14 dB, V
50
40
3 CURVES
– Volts
–40°C, +25°C, +85°C
30
20
GAIN – dB
10
0
–10
0.1 2.9
0.5 0.9 1.3 1.7 2.1 2.5 VGN – Volts
Figure 1. Gain vs. VGN
40
37.5
35
32.5
30
27.5
GAIN SCALING – dB/V
25
22.5
20
1.25
THEORETICAL
ACTUAL
1.5 1.75 2 2.25 2.5 V
REF
= 2.5 V (20 dB/V Scaling), f = 1 MHz, RL = 500 V, CL = 5 pF, TA = +258C, VSS = 65V)
REF
60
50
40
30
20
GAIN – dB
10
0
–10
–20
0.1
Figure 2. Gain vs. VGN for Different Preamp Gains
2.0
1.5
1.0
0.5
0
–0.5
GAIN ERROR – dB
–1.0
–1.5
–2.0
0.2
G (PREAMP) = +14dB (0dB – +48dB)
G (PREAMP) = +20dB (+6dB – +54dB)
DSX ONLY
(–14dB – +34dB)
0.5 0.9 1.3 1.7 2.1 2.5 2.9 VGN – Volts
–40°C
+25°C
+85°C
0.7 1.2 1.7 2.2 2.7 VGN – Volts
Figure 3. Gain vs. VGN for Different Gain Scalings
Figure 4. Gain Scaling vs. V
2.0
1.5
1.0
0.5
0
–0.5
GAIN ERROR – dB
–1.0
–1.5
–2.0
0.2
Figure 7. Gain Error vs. VGN for Different Gain Scalings
REV. 0
VREF = 1.67V
0.7 1.2 1.7 2.2 2.7
30dB/V
VGN – Volts
REF
20dB/V
VREF = 2.50V
Figure 5. Gain Error vs. VGN at Different Temperatures
25
20
15
10
PERCENTAGE
5
0
–0.6
–1.0
–0.8
–0.4 –0.2 0.1 0.3 0.5 0.7 0.9
DELTA GAIN – dB
N = 50 VGN1 = 1.0V VGN2 = 1.0V G(dB) = G(CH1) – G(CH2)
Figure 8. Gain Match; VGN1 = VGN2 =
1.0 V
–5–
Figure 6. Gain Error vs. VGN at Different Frequencies
Figure 9. Gain Match: VGN1 = VGN2 =
2.50 V
Page 6
AD604–Typical Performance Characteristics (per Channel)
VGN – Volts
210
0.1
190
170
150
130
110
90
0.5 0.9 1.3 1.7 2.1 2.5 2.9
+85°C
+25°C
–40°C
NOISE – n V / Hz
NOISE – p V / Hz
FREQUENCY – Hz
770
745
740
760
765
750
755
100k 1M 10M
VGN = 2.9V
VGN – Volts
dB
40
20
0
0
1.2
35
30
25
15
10
5
0.4 0.8 1.6 2.0 2.4 2.8
RS = 240
(Unless otherwise noted G (preamp) = +14 dB, V
= 2.5 V (20 dB/V Scaling), f = 1 MHz, RL = 500 V, CL = 5 pF, TA = +258C, VSS = 65V)
REF
50
VGN = 2.5V
40 30 20
10
0
GAIN – dB
–10 –20 –30
–40 –50
100k
VGN = 1.5V
VGN = 0.5V
VGN = 0.1V
VGN = 0.0V
VGN = 2.9V
1M 10M 100M FREQUENCY – Hz
Figure 10. AC Response
1000
100
10
NOISE – n V / Hz
1
2.55
2.54
2.53
2.52
2.51
2.50
– Volts
OUT
2.49
V
2.48
2.47
2.46
2.45
VOCM = 2.50V
+85°C
0.2
0.7 1.2 1.7 2.2 2.7
–40°C
+25°C
VGN – Volts
Figure 11. Output Offset vs. VN
900
VGN = 2.9V
850
800
750
700
NOISE – p V / Hz
650
Figure 12. Output Referred Noise vs. VGN
0.1
0.1 2.9
0.5 0.9 1.3 1.7 2.1 2.5 VGN – Volts
Figure 13. Input Referred Noise vs. VGN
10
VGN = 2.9V
1
NOISE – n V / Hz
0.1 1101k100
Figure 16. Input Referred Noise vs. R
SOURCE
R
R
SOURCE
SOURCE
ALONE
600
–40 –20 20 40 60
080
TEMPERATURE – °C
Figure 14. Input Referred Noise vs. Temperature
16 15 14 13 12 11 10
9
dB
8 7 6 5
4
3 2 1
110
Figure 17. Noise Figure vs. R
VGN = 2.9V
100 RIN
1k
10k
SOURCE
90
Figure 15. Input Referred Noise vs. Frequency
Figure 18. Noise Figure vs. VGN
REV. 0–6–
Page 7
AD604
R
SOURCE
–20
–50
–80
0
HARMONIC DISTORTION – dBc
200 250
–30
–40
–70
–60
50 150100
HD3(10MHz)
HD2(10MHz)
HD3(1MHz)
HD2(1MHz)
R
S
DUT
50
500
VO = 1V p-p VGN = 1.0V
VGN – Volts
IP3 – dBm
25
20
–15
0.4 0.9 2.9
1.4 1.9 2.4
5
0
–5
–10
15
10
VO = 1V p-p
f = 1MHz
f = 10MHz
10 0%
100
90
500mV
200ns
500mV
2.9V
0V
VGN – Volts
–40
VO = 1V p-p VGN = +1.0V
–45
–50
–55
–60
–65
HARMONIC DISTORTION – dBc
–70
100k
HD2
HD3
1M FREQUENCY – Hz
10M 100M
Figure 19. Harmonic Distortion vs. Frequency
–20 –30 –40 –50 –60 –70
– dBm
–80
OUT
P
–90 –100 –110 –120
9.98 10 10.02 10.04
9.96 FREQUENCY – MHz
VO = 1V p-p VGN = 1.0V
–30
VO = 1V p-p
–35 –40
–45 –50 –55 –60 –65 –70
HD2(1MHz)
HARMONIC DISTORTION – dBc
–75 –80
0.9 1.3 1.7 2.5
0.5 VGN – Volts
HD3(10MHz)
HD2(10MHz)
HD3(1MHz)
2.1
2.9
Figure 20. Harmonic Distortion vs. VGN
5
0
INPUT
–5
SIGNAL LIMIT 800mV p-p
–10
–15
– dBm
IN
P
–20
–25
–30
–35
0.5 0.9 1.7 2.1
0.1
1.3
VGN – Volts
10MHz
1MHz
2.5 2.9
Figure 21. Harmonic Distortion vs. R
SOURCE
Figure 22. Intermodulation Distortion
2V
400mV / DIV
–2V
253ns
Figure 25. Large Signal Pulse Response
REV. 0
100ns / DIV
VO = 2V p-p VGN = 1.5V
1.253µs
Figure 23. 1 dB Compression vs. VGN
200
VO = 200mV p-p VGN = 1.5V
40mV / DIV
TRIG'D
–200
253ns
100ns / DIV
1.253µs
Figure 26. Small Signal Pulse Response
–7–
Figure 24. 3rd Order Intercept vs. VGN
Figure 27. Power-Up/Down Response
Page 8
AD604
TEMPERATURE – °C
SUPPLY CURRENT – mA
40
20
0
35
30
25
15
10
5
–40 40 90
–20 0 20 60 80
AD604 (+IS)
DSX (+IS)
PRE-AMP (±IS)
+IS (VGN = 0)
– IS (AD604) = –IS (PA)
+IS (AD604) = +IS (PA) + +IS (DSX)
500mV
2.9V
100
90
VGN – Volts
10
0%
0.1V
500mV
Figure 28. Gain Response
1M
100k
10k
1k
100
INPUT IMPEDANCE –
10
1
10k 100k
1k 1M 100M
FREQUENCY – Hz
100ns
10M
0
VGN1 = 1V
= 1V p-p
V
–10
OUT1
= GND
V
IN2
–20
VGN2 = 2.9V
–30
VGN2 = 2.0V
–40
–50
CROSSTALK – dB
–60
–70
100k 1M 100M
VGN2 = 1.5V
FREQUENCY – Hz
10M
VGN2 = 0.1V
Figure 29. Crosstalk (CH1 to CH2) vs. Frequency
27.6
27.4
27.2
27.0
26.8
26.6
26.4
26.2
INPUT BIAS CURRENT – µA
26.0
25.8 –20 0 60 80
–40
20 90
TEMPERATURE – °C
40
0
–10
–20
–30
CMRR – dB
–40
–50
–60
100k 1M 100M
VGN = 2.9V
VGN = 2.5V
VGN = 2.0V
VGN = 0.1V
FREQUENCY – Hz
10M
Figure 30. DSX Common-Mode Rejection vs. Frequency
Figure 31. Input Impedance vs. Frequency
Figure 32. Input Bias Current vs. Temperature
20
18
16
14
12
DELAY – ns
10
8
6 100k 1M 100M
VGN = 0.1V
VGN = 2.9V
FREQUENCY – Hz
10M
Figure 34. Group Delay vs. Frequency
–8–
Figure 33. Supply Current (One Channel) vs. Temperature
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Page 9
AD604

THEORY OF OPERATION

The AD604 is a dual channel, variable gain amplifier with an ultralow noise preamplifier. Figure 35 shows the simplified block diagram of one channel. Each channel consists of:
(1) a preamplifier with gain setting resistors R5, R6 and R7 (2) a single-supply X-AMP (hereafter called, DSX, Differential
Single-supply X-AMP) made up of: (a) a precision passive attenuator (differential ladder) (b) a gain control block (c) a VOCM buffer with supply splitting resistors R3 and R4 (d) an Active Feedback Amplifier
1
(AFA) with gain setting
resistors R1 and R2
The preamplifier is powered by a ± 5 V supply, while the DSX uses a single +5 V supply. The linear-in-dB gain response of the AD604 can generally be described by Equation 1:
G (dB) = (Gain Scaling (dB/V)) × (Gain Control (V )) + ((Preamp Gain (dB)) – 19 dB) (1)
Each channel provides between 0 dB to +48.4 dB through +6 dB to +54.4 dB of gain depending on the user determined pream­plifier gain. The center 40 dB of gain is exactly linear-in-dB while the gain error increases at the top and bottom of the range. The gain of the preamplifier is typically either +14 dB or +20 dB, but can be set to intermediate values by a single exter­nal resistor (see PREAMPLIFIER section for details). The gain of the DSX can vary from –14 dB to +34.4 dB which is deter­mined by the gain control voltage (VGN). The VREF input establishes the gain scaling – the useful gain scaling range is between 20 dB/V and 40 dB/V for a VREF voltage of 2.5 V and
1.25 V respectively. For example, if the preamp gain was set to +14 dB and VREF was set to 2.50 V (to establish a gain scaling of 20 dB/V), the gain equation would simplify to:
G (dB) = (20 (dB/V)) × (VGN (V )) – 5 dB
The desired gain can then be achieved by setting the unipolar gain control (VGN) to a voltage within its nominal operating range of 0.25 V to 2.65 V (for 20 dB/V gain scaling). The gain is monotonic for a complete gain control voltage range of 0.1 V to
2.9 V. Maximum gain can be achieved at a VGN of 2.9 V.
Since the two channels are identical, only Channel 1 will be used to describe their operation. VREF and VOCM are the only inputs that are shared by the two channels, and since they are normally ac grounds, crosstalk between the two channels is minimized. For highest gain scaling accuracy, VREF should have an external low impedance voltage source. For low accu­racy 20 dB/V applications, the VREF input can be decoupled with a capacitor to ground. In this mode the gain scaling will be determined by the midpoint between +V
and GND, so care
CC
should be taken to control the supply voltage to +5 V. The in­put resistance looking into the VREF pin is 10 k ± 20%.
The DSX portion of the AD604 is a single-supply circuit and the VOCM pin is used to establish the dc level of the midpoint of this portion of the circuit. VOCM needs only an external decoupling capacitor to ground to center the midpoint between the supply voltages (+5 V, GND); however, if the dc level of the output is important to the user (see APPLICATIONS section for AD9050 example), then VOCM can be specifically set. The input resistance looking into the VOCM pin is 45 k ± 20%.
Preamplifier
The input capability of the following single-supply DSX (2.5 ± 2 V for a +5 V supply) limits the maximum input voltage of the preamplifier to ±400 mV for the 14 dB gain configuration or ±200 mV for the 20 dB gain configuration.
The preamplifier’s gain can be programmed to +14 dB or +20 dB; by either shorting the FBK1 node to PAO1 (+14 dB), or leaving node FBK1 open (+20 dB). These two gain settings are very accurate since they are set by the ratio of on-chip resis­tors. Any intermediate gain can be achieved by connecting the appropriate resistor value between PAO1 and FBK1 according to Equations 2 and 3:
G =
R
V
V
EXT
(R7iR
OUT
=
IN
[R6 ×G (R5+ R6)]×R7
=
R7(R6×G)+(R5+ R6)
) + R5 +R6
EXT
R6
(2)
(3)
VREF
VGN
PAI
VOCM
EXT.
R7
40
FBK
R5
32
R6
VPOS
8
R3
COM
200k
C3
R4 200k
C1
PAO +DSX
EXT.
C2
–DSX
Figure 35. Simplified Block Diagram of a Single Channel of the AD604
1
To understand the active-feedback amplifier topology, refer to the AD830 data
sheet. The AD830 is a practical implementation of the idea.
REV. 0
175
175
–9–
GAIN
CONTROL
DIFFERENTIAL
ATTENUATOR
R2
20
DISTRIBUTED G
G1
G2
R1
820
M
Ao
OUT
Page 10
AD604
Since the internal resistors have an absolute tolerance of ±20%, the gain can be in error by as much as 0.33 dB when R 30 , where it was assumed that R
is exact.
EXT
EXT
is
Figure 36 shows how the preamplifier is set to gains of +14, +17.5 and +20 dB. The gain range of a single channel of the AD604 is 0 dB to +48 dB when the preamplifier is set to +14 dB (Figure 36a), 3.5 dB to +51.5 dB for a preamp gain of +17.5 dB (Figure 36b), and 6 dB to 54 dB for the highest preamp gain of +20 dB (Figure 36c).
PAI1
COM1
R6 8
R5
32
R7 40
PAO1
FBK1
a. Preamp Gain = 14 dB
R7 40
PAO1
FBK1
R10 40
PAI1
COM1
R6 8
R5
32
b. Preamp Gain = 17.5 dB
PAI1
COM1
R6 8
R5
32
R7 40
PAO1
FBK1
c. Preamp Gain = 20 dB
Figure 36. Preamplifier Gain Programmability
For a preamplifier gain of +14 dB, the preamplifier’s –3 dB small-signal bandwidth is 130 MHz; when the gain is at the high end (+20 dB), the bandwidth will be reduced by a factor of two to 65 MHz. Figure 37 shows the ac responses for the three preamp gains discussed above; note that the gain for an R
EXT
of 40
should be 17.5 dB, but the mismatch between the internal resis­tors and the external resistor has caused the actual gain for this particular preamplifier to be 17.7 dB. The –3 dB small-signal bandwidth of one complete channel of the AD604 (preamplifier and DSX) is 40 MHz and is independent of gain.
20
19
18
17
16
– dB
15
GAIN
14
13
V
IN
12
11 10
100k 1M
50
8
IN
40
32
R
EXT
OPEN
40
SHORT
150
R
EXT
10M 100M
To achieve its optimum specifications, power and ground man­agement are critical to the AD604. Large dynamic currents result because of the low resistances needed for the desired noise performance. Most of the difficulty is with the very low gain setting resistors of the preamplifier that allow for a total input referred noise, including the DSX, as low as 0.8 nV/
Hz. The consequently large dynamic currents have to be carefully handled to maintain performance even at large signal levels.
To accommodate these large dynamic currents as well as a ground referenced input, the preamplifier is operated from a dual ±5 V supply. This causes the preamplifiers output to also be ground referenced, which requires a common-mode level shift into the single-supply DSX. The two external coupling ca­pacitors (C1, C2 in Figure 35) connected to nodes PAO1 and +DSX, and –DSX and ground, respectively, perform this func­tion (see AC Coupling Section). In addition, they eliminate any offset that would otherwise be introduced by the preamplifier. It should be noted that an offset of 1 mV at the input of the DSX will get amplified by +34.4 dB (× 52.5) when the gain-control voltage is at its maximum, this equates to 52.5 mV at the out­put. AC coupling is consequently required to keep the offset from degrading the output signal range.
The internal feedback resistors setting the gain of the preampli­fier are so small (nominally 8 and 32 ) that even an addi­tional 1 in the “ground” connection at pin COM1, which serves as the input common-mode reference, will seriously degrade gain accuracy and noise performance. This node is very sensitive and careful attention is necessary to minimize the ground impedance. All connections to node COM1 should be as short as possible.
The preamplifier including the gain setting resistors has a noise performance of 0.71 nV/
Hz and 3 pA/Hz. Note that a signifi-
cant portion of the total input referred voltage noise is due to the feedback resistors. The equivalent noise resistance presented by R5 and R6 in parallel is nominally 6.4 , which contributes
0.33 nV/
Hz to the total input referred voltage noise. The larger
portion of the input referred voltage noise is coming from the amplifier with 0.63 nV/
Hz. The current noise is independent of
gain and depends only on the bias current in the input stage of the preamplifier—it is 3 pA/
Hz.
The preamplifier can drive 40 (the nominal feedback resis­tors) and the following 175 ladder load of the DSX with low distortion. For example, at 10 MHz and ± 1 V at the output, the preamplifier has less than –45 dB of second and third harmonic distortion when driven from a low (25 ) source resistance.
In some cases one may need more than 48 dB of gain range, in which case two AD604 channels could be cascaded. Since the preamplifier has limited input signal range, consumes over half (120 mW) of the total power (220 mW), and its ultralow noise is not necessary after the first AD604 channel, a shutdown mechanism that disables only the preamplifier is built in. All that is required to shut down the preamplifier is to tie the COM1 and/or COM2 pin to the positive supply. The DSX will be unaffected and can be used as before (see APPLICATIONS section for further details).
Figure 37. AC Responses for Preamplifier Gains Shown in Figure 36.
–10–
REV. 0
Page 11
AD604
1
–DSX1
2
+DSX1
3
PAO1
4
FBK1
5
PAI1
6
COM1
AD604
COM2
7 8
PAI2
9
FBK2
10
PAO2
11
+DSX2
12
–DSX2
VGN1 VREF
OUT1 GND1 VPOS
VNEG VNEG
VPOS
GND2
OUT2
VOCM
VGN2
24 23 22 21 20 19 18 17 16 15 14 13
Figure 38. Shutdown of Preamplifiers Only
Differential Ladder (Attenuator)
The attenuator before the fixed gain amplifier of the DSX is realized by a differential seven-stage R-1.5R resistive ladder net­work with an untrimmed input resistance of 175 single-ended or 350 differentially. The signal applied at the input of the ladder network (Figure 39) is attenuated by 6.908 dB per tap; thus, the attenuation at the first tap is 0 dB, at the second,
13.816 dB, and so on, all the way to the last tap where the attenuation is 48.356 dB. A unique circuit technique is used to interpolate continuously between the tap points, thereby provid­ing continuous attenuation from 0 to –48.36 dB. You can think of the ladder network together with the interpolation mechanism as a voltage-controlled potentiometer.
Since the DSX is a single-supply circuit, some means of biasing its inputs must be provided. Node MID together with the VOCM buffer performs this function. Without internal biasing, the user would have had to dc bias the inputs externally. If not done carefully, the biasing network can introduce additional noise and offsets. By providing internal biasing, the user is relieved of this task and only needs to ac couple the signal into the DSX. It should be made clear again that the input to the DSX is still fully differential if driven differentially, i.e., pins +DSX and –DSX see the same signal but with opposite polarity (see Differential Input VGA Application). What changes is the load as seen by the driver; it is 175 Ω when each input is driven single ended, but 350 when driven differentially. This can be easily explained when thinking of the ladder network as just two 175 resistors connected back-to-back with the middle node, MID, being biased by the VOCM buffer. A differential signal
applied between nodes +DSX and –DSX will result in zero cur­rent into node MID, but a single-ended signal applied to either input +DSX or –DSX while the other input is ac grounded, will cause the current delivered by the source to flow into the VOCM buffer via node MID.
The ladder resistor value of 175 was chosen to provide the optimum balance between the load driving capability of the preamplifier and the noise contribution of the resistors. One fea­ture of the X-AMP architecture is that the output referred noise is constant versus gain over most of the gain range. This can be easily explained by looking at Figure 39 and observing that the tap resistance is equal for all taps after only a few taps away from the inputs. The resistance seen looking into each tap is
54.4 which makes 0.95 nV/
Hz of Johnson noise spectral
density. Since there are two attenuators, the overall noise con­tribution of the ladder network is
1.34 nV/
Hz, a large fraction of the total DSX noise. The rest
of the DSX circuit components contribute another 1.20 nV/ which together with the attenuator produces 1.8 nV/
2 times 0.95 nV/Hz or
Hz
Hz of
total DSX input referred noise.
AC Coupling
As already mentioned, the DSX portion of the AD604 is a single-supply circuit and therefore its inputs need to be ac coupled to accommodate ground-based signals. External capacitors C1 and C2 in Figure 35 level shift the ground refer­enced preamplifier output from ground to the dc value estab­lished by VOCM (nominal 2.5 V). C1 and C2, together with the 175 looking into each of DSX inputs (+DSX and –DSX), will act as high pass filters with corner frequencies depending on the values chosen for C1 and C2. For example, if C1 and C2 are 0.1 µF, then together with the 175 input resistance seen into each side of the differential ladder of the DSX, a –3 dB high pass corner at 9.1 kHz is formed.
If the AD604 output needs to be ground referenced, then an­other ac coupling capacitor will be required for level shifting. This capacitor will also eliminate any dc offsets contributed by the DSX. With a nominal load of 500 and a 0.1 µF coupling capacitor, this adds a high pass filter with –3 dB corner fre­quency at about 3.2 kHz.
The choice for all three of these coupling capacitors depends on the application. They should allow the signals of interest to pass unattenuated, while at the same time they can be used to limit the low frequency noise in the system.
REV. 0
+DSX
MID
–DSX
NOTE: R = 96
1.5R = 144
R
R
–6.908dB
1.5R
1.5R
R
R
–13.82dB
1.5R
1.5R
R
R
–20.72dB
1.5R
1.5R
R
R
–27.63dB
1.5R
1.5R
Figure 39. R–1.5R Dual Ladder Network.
–11–
R
R
–34.54dB
1.5R
1.5R
R
R
–41.45dB
1.5R
1.5R
R
R
–48.36dB
1.5R
1.5R
175
175
Page 12
AD604
Gain Control Interface
The gain-control interface provides an input resistance of ap­proximately 2 M at Pin VGN1 and gain scaling factors from 20 dB/V to 40 dB/V for VREF input voltages of 2.5 V to 1.25 V respectively. The gain scales linearly-in-dB for the center 40 dB of gain range, that is for VGN equal to 0.4 V to 2.4 V for the 20 dB/V scale, and 0.2 V to 1.2 V for the 40 dB/V scale. Figure 40 shows the ideal gain curves for a nominal preamplifier gain of 14 dB which are described by the following equations:
G (20 dB/V) = 20 × VGN – 5, V G (30 dB/V) = 30 × VGN – 5, V G (40 dB/V) = 40 × VGN – 5, V
50 45 40 35 30 25
GAIN – dB
20 15 10
5 0
–5
40dB/V
1.0 2.51.5 2.0 3.0
0.5 GAIN CONTROL VOLTAGE – VGN
Figure 40. Ideal Gain Curves vs. V
= 2.500 V (4)
REF
= 1.666 V (5)
REF
= 1.250 V (6)
REF
30dB/V
20dB/V
LINEAR-IN-dB RANGE
OF AD604 WITH PREAMPLIFIER
SET TO 14dB
REF
.
From these equations you can see that all gain curves intercept at the same –5 dB point; this intercept will be 6 dB higher (+1 dB) if the preamplifier gain is set to +20 dB or 14 dB, lower (–19 dB) if the preamplifier is not used at all. Outside of the central linear range, the gain starts to deviate from the ideal control law but still provides another 8.4 dB of range. For a given gain scaling you can calculate V
V
2.500 V × 20 dB /V
=
REF
Gain Scale
as shown in Equation 7:
REF
(7)
Usable gain control voltage ranges are 0.1 V to 2.9 V for 20 dB/V scale and 0.1 V to 1.45 V for the 40 dB/V scale. VGN voltages of less than 0.1 V are not used for gain control since below 50 mV the channel (preamp and DSX) is powered down. This can be used to conserve power and at the same time gate­off the signal. The supply current for a powered-down channel is 1.9 mA, the response time to power the device on-or-off, is less than 1 µs.
Active Feedback Amplifier (Fixed Gain Amp)
To achieve single supply operation and a fully differential input to the DSX, an active-feedback amplifier (AFA) is utilized. The AFA is basically an op amp with two g
stages; one of the active
m
stages is used in the feedback path (therefore the name), while the other is used as a differential input. Note that the differential input is an open-loop gm stage that requires that it be highly linear over the expected input signal range. In this design, the g
stage that senses the voltages on the attenuator is a distrib-
m
uted one; for example, there are as many g
stages as there are
m
taps on the ladder network. Only a few of them are on at any one time, depending on the gain-control voltage.
The AFA makes a differential input structure possible since one of its inputs (G1) is fully differential; this input is made up of a distributed g
stage. The second input (G2) is used for feed-
m
back. The output of G1 will be some function of the voltages sensed on the attenuator taps which is applied to a high gain amplifier (A0). Because of negative feedback, the differential input to the high gain amplifier has to be zero; this in turn implies that the differential input voltage to G2 times g
m2
(the transconductance of G2) has to be equal to the differential input voltage to G1 times g
(the transconductance of G1). There-
m1
fore the overall gain function of the AFA is:
V
OUT
V
ATTEN
where V
is the output voltage, V
OUT
sensed on the attenuator, (R1+R2)/R2 = 42, and g
g
R1+ R2
m1
=
×
g
m2
R2
is the effective voltage
ATTEN
m1/gm2
(8)
=
1.25; the overall gain is thus 52.5 (34.4 dB). The AFA has additional features: (1) inverting the signal by
switching the positive and negative input to the ladder network, (2) the possibility of using the DSX1 input as a second signal input, (3) fully differential high impedance inputs when both preamplifiers are used with one DSX (the other DSX could still be used alone), and (4) independent control of the DSX common­mode voltage. Under normal operating conditions it is best to connect a decoupling capacitor to pin VOCM in which case the common-mode voltage of the DSX is half the supply voltage; this allows for maximum signal swing. Nevertheless, the common-mode voltage can be shifted up or down by directly applying a voltage to VOCM. It can also be used as another signal input, the only limitation being the rather low slew-rate of the VOCM buffer.
If the dc level of the output signal is not critical, another coupling capacitor is normally used at the output of the DSX; again this is done for level shifting and to eliminate any dc off­sets contributed by the DSX (see AC Coupling section).
–12–
REV. 0
Page 13
AD604
APPLICATIONS
The most basic circuit in Figure 41 shows the connections for one channel of the AD604. The signal is applied at Pin 5. RGN is normally zero, in which case the preamplifier is set to a gain­of-five (14 dB). When Pin FBK1 is left open, the preamplifier is set to a gain-of-ten (20 dB) and the gain range shifts up by 6 dB. The ac coupling capacitors before pins –DSX1 and +DSX1 should be selected according to the required lower cut­off frequency. In this example the 0.1 µF capacitors together with the 175 seen looking into each of the DSX input pins, provides a –3 dB high pass corner of about 9.1 kHz. The upper cutoff frequency is determined by the bandwidth of the channel which is 40 MHz. Note, the signal can be simply inverted by connecting the output of the preamplifier to pin –DSX1 instead of +DSX1, this is due to the fully differential input of the DSX.
0.1µF
0.1µF
RGN
V
–DSX1
1
+DSX1
2
PAO1
3
FBK1
4
AD604
PAI1
5
IN
COM1
6
COM2
7
PAI2
8
FBK2
9
PAO2
10
+DSX2
11
–DSX2
12
VGN1 VREF
OUT1 GND1 VPOS VNEG VNEG VPOS GND2 OUT2
VOCM
VGN2
24
VGN
0.1µF
0.1µF
R
500
2.500V OUT
L
+5V
–5V
23 22 21 20 19 18 17 16 15 14
13
Figure 41. Basic Connections for a Single Channel
As shown here, the output is ac coupled for optimum perfor­mance. In the case of connecting to the AD9050, ac coupling can be eliminated as long as pin VOCM is biased by the same
3.3 V common-mode voltage as the AD9050 (see Figure 50).
C1
VIN
(MAX
800mV p-p)
C12
0.1µF
0.1µF
0.1µF
0.1µF
C2
R1
49.9
C3
0.1µF
–DSX1
1
+DSX1
2
AD604
PAO1
3
FBK1
4
PAI1
5
COM1
6
COM2
7
PAI2
8
FBK2
9
PAO2
10
+DSX2
11
–DSX2
12
C4
FB FB
C13
0.1µF
ALL SUPPLY PINS ARE DECOUPLED AS SHOWN.
VGN1
VREF
OUT1
GND1
VPOS
VNEG
VNEG
VPOS
GND2
OUT2
VOCM
VGN2
+5V
–5V
24
23
22
21
+5V
20
–5V
19
–5V
18
17
+5V
16
15
C7
0.1µF
14
13
RF OUT
VREF
V1 = VIN * G
C7
0.33µF
C6
0.56µF
R2 453
0.33µF
R3 1k
C8
0.33µF
C9
Pin V
requires a voltage of 1.25 V to 2.5 V, with between
REF
40 dB/V and 20 dB/V gain scaling respectively. Voltage VGN controls the gain; its nominal operating range is from 0.25 V to
2.65 V for 20 dB/V gain scaling, and 0.125 V to 1.325 V for 40 dB/V scaling. When this pin is taken to ground, the chan­nel will power down and disable its output.
Pin COM1 is the main signal ground for the preamplifier and needs to be connected with as short a connection as possible to the input ground. Since the internal feedback resistors of the preamplifier are very small for noise reasons (8 and 32 nominally), it is of utmost importance to keep the resistance in this connection to a minimum! Furthermore, excessive induc­tance in this connection may lead to oscillations.
As a consequence of the AD604’s ultralow noise and wide band­width, large dynamic currents will be flowing to and from the power supply. To insure the stability of the part, extreme atten­tion to supply decoupling is required. A large storage capacitor in parallel with a smaller high frequency capacitor connected right at the supply pins, together with a ferrite bead coming from the supply should be used to insure high frequency stability.
To provide for additional flexibility, Pin COM1 can be used to depower the preamplifier. When COM1 is connected to VP, the preamplifier will be off, yet the DSX portion can be used independently. This may be of value when one desires to cas­cade the two DSX stages in the AD604. In this case the first DSX output signal with respect to noise will be large and using the second preamplifier at this point would be a waste of power (see AGC Amplifier Application).
An Ultralow Noise AGC Amplifier with 82 to 96 dB Gain Range
Figure 42 shows an implementation of an AGC amplifier with 82 dB of gain range using a single AD604. First, the connec­tions for the two channels of the AD604 will be discussed, and second, how the detector circuitry that closes the loop works.
VSET (<0V)
R4 2k
8765
X1 X2 VP W
1V
+5V
2
– (V1)
AD835
Y1 Y2 VN Z
1234
–5V
R5 2k
R6 2k
LOW
PASS
FILTER
R7 1k
C10 1µF
–5V
– (A)
R8 2k
2
1
2
3
4
2
C11 1µF
OFFS
NC
NULL
+VS
AD711
OUT
OFFS
–VS
NULL
IF V1 = A*cos (wt)
8
+5V
7
6
5
VG
REV. 0
Figure 42. AGC Amplifier with 82 dB of Gain Range
–13–
Page 14
AD604
The signal is applied to connector VIN, and since the signal source was 50 , a terminating resistor (R1) of 50 was added. The signal is then amplified by 14 dB (Pin FBK1 shorted to PAO1) through the Channel 1 preamplifier, and is further pro­cessed by the Channel 1 DSX. Next the signal is applied directly to the Channel 2 DSX. The second preamplifier is powered down by connecting its COM2 pin to the positive supply as explained in the preamplifier section earlier. Capacitors C1 and C2 level shift the signal from the preamplifier into the first DSX and at the same time eliminate any offset contribution of the preamp. C3 and C4 have the same offset cancellation purpose for the second DSX. Each set of capacitors together with the 175 input resistance of the corresponding DSX provides a high pass filter with –3 dB corner frequency of about 9.1 kHz. Pin VOCM is decoupled to ground by a 0.1 µF capacitor, while VREF can be externally provided; in this application the gain scale is set to 20 dB/V by applying 2.500 V. Since each of the DSX amplifiers operates from a single +5 V supply, the output is ac coupled via C6 and C7. The output signal can be moni­tored at the connector labeled RF OUT.
Figures 43 and 44 show the gain range and gain error for the AD604 connected as shown. The gain range is –14 dB to +82 dB; the useful range is 0 dB to +82 dB if the RF output amplitude is controlled to ±400 mV (+2 dBm). The main limitation on the lower end of the signal range is the input capability of the
90 80
f = 1MHz
70 60 50 40 30
GAIN – dB
20 10
0 –10 –20 –30
1.70.1 0.5 0.9 1.3 2.1 2.5
VGN – Volts
2.9
Figure 43. AD604 Cascaded Gain vs. VGN
4
3
2
1
0
–1
GAIN ERROR – dB
–2
–3
–4
0.2 0.7 1.2 1.7 VGN – Volts
f = 1MHz
2.2
2.7
Figure 44. AD604 Cascaded Gain Error vs. VGN
preamplifier. This can be overcome by adding an attenuator in front of the preamplifier, but that would defeat the advantage of the ultralow noise preamplifier. It should be noted that the sec­ond preamplifier is not used since its ultralow noise and the associated high power consumption are overkill after the first DSX stage. It is disabled in this application by connecting the COM2 pin to the positive supply. Nevertheless, the second preamplifier can be used if so desired and the useful gain range will shift up by 14 dB, to encompass 0 dB to +96 dB of gain. For the same +2 dBm output this would allow signals as small as –94 dBm to be measured.
To achieve the highest gains, the input signal has to ultimately be bandlimited to reduce the noise; this is especially true if the second preamplifier is used. If the maximum signal at Pin OUT2 of the AD604 is limited to be ±400 mV (+2 dBm), then the in­put signal level at the AGC threshold is 25 µV rms (–79 dBm). The circuit as shown has about 40 MHz of noise bandwidth; the
0.8 nV/
Hz of input referred voltage noise spectral density of
the AD604 results in an rms noise of 5.05 µV in the 40 MHz bandwidth. The 50 termination resistor, together with the 50 Ω source resistance of the signal generator, combine to an effective resistance as seen by the input of the preamplifier of 25 which makes 4.07 µV of rms noise in 40 MHz. The noise floor of this channel is consequently the rms sum of these two main noise sources, 6.5 µV rms. This means that the minimum dectectable signal (MDS) for this circuit is 6.5 µV rms (–90.7 dBm). As a general rule of thumb the measured signal should be about a factor-of-three larger than the noise floor, in this case 19.5 µV rms. As we can see the 25 µV rms signal that this AGC circuit can correct for is just slightly above the MDS. Of course, the sensitivity of the input can be improved by bandlimiting the signal; if the noise bandwidth is reduced by a factor-of-four to 10 MHz, the noise floor of the AGC circuit with 50 termination resistor will drop to 3.25 µV rms (–96.7 dBm). Further noise improvement can be achieved by an input matching network or by transformer coupling of the input signal.
Next we will describe the functioning of the detector circuitry comprised of a squarer, a low-pass filter, and an integrator. At this point it is necessary to make some assumptions about the input signal. The following explanation of the detector circuitry presumes an amplitude modulated RF carrier where the modu­lating signal is at a much lower frequency than the RF signal. The AD835 multiplier functions as the detector by squaring the output signal presented to it by the AD604. A low-pass filter fol­lowing the squaring operation removes the RF signal component at twice the incoming signal frequency, while passing the low frequency AM information. The following integrator with a time constant of 2 ms set by R8 and C11 integrates the error signal presented by the low-pass filter and changes VG until the error signal is equal to V
SET
.
For example, if the signal presented to the detector is V1 = A*cos(ωt) as indicated in Figure 42, then the output of the squarer is –(V1)
2
/1 V. The reason for all the minus signs in the detection circuitry comes from the necessity of providing nega­tive feedback in the control loop; actually if V
becomes
SET
greater-than 0 V, the control loop provides positive feedback. Squaring A*cos(ωt) results in two terms, one at dc and one at 2ω; the following low-pass filter passes only the –(A)
2
/2 dc term.
–14–
REV. 0
Page 15
AD604
PIN – dBm
4.5
4.0
0
–100 0–40
3.5
3.0
1.0
2.5
2.0
1.5
–90 –80 –70 –60 –50 –30 –20 –10
10
CONTROL VOLTAGE – Volts
1MHz
0.5
This dc voltage will now be forced equal to the voltage, V
SET
, by the control loop. The squarer together with the low-pass filter functions as a mean-square detector. As should be evident, by controlling the value of V voltage V1 at the input of the AD835; if V
, we can set the amplitude of the
SET
equals minus
SET
80 mV, the AGC output signal amplitude will be ±400 mV. Figure 45 shows the control voltage, VGN, versus the input
power at frequencies of 1 MHz (solid line) and 10 MHz (dashed line) at an output regulated level of +2 dBm (800 mV p-p). The AGC threshold is evident at a P
of about –79 dBm; the high-
IN
est input power that could still be accommodated was about +3 dBm. At this level the output starts being distorted because of clipping in the preamplifier.
4.5
4.0
3.5
3.0
2.5
2.0
1.5
CONTROL VOLTAGE – Volts
1.0
1MHz
10MHz
VGN1 VREF OUT1
GND1 VPOS VNEG VNEG VPOS GND2
OUT2
VOCM
VGN2
24 23 22
21 20 19 18
17 16 15 14 13
0.1µF
C5
R2
499
FB
FAIR-RITE
#2643000301
560pF
0.1µF
1
–DSX1
2
+DSX1
3
PAO1
4
FBK1
5
PAI1
AD604
6
COM1
7
C6
C3
COM2
8
PAI2
9
FBK2
10
PAO2
11
+DSX2
12
–DSX2
Figure 46. Modifications of AGC Amplifier to Get 96 dB of Gain Range
0.5 –80 –70 –60 –50 –30 –20 –10
Figure 45. Control Voltage vs. Input Power of Circuit in Figure 42
As mentioned already, the second preamplifier can be used to extend the range of the AGC circuit in Figure 42. Figure 46 shows the modifications that need to be made to Figure 44 to achieve 96 dB of gain and dynamic range. Because of the ex­tremely high gain, the bandwidth needs to be limited to reject some of the noise; furthermore, limiting the bandwidth will help suppress high frequency oscillations. The added components act as a low-pass filter and dc block (C5 level shifts the output of the first DSX from 2.5 V to ground); the ferrite bead has an im­pedance of about 5 at 1 MHz, 30 at 10 MHz, and 70 at 100 MHz. Together with R2 and C6, the bead makes a low-pass filter which attenuates higher frequencies; at 1 MHz the attenu­ation is about –0.2 dB, while at 10 MHz it increases to –6 dB, on to –28 dB at 100 MHz. Signals now have to be less than about 1 MHz to not be significantly affected by the added circuitry. In Figure 47 we see the control voltage vs. input power at 1 MHz to the circuit in Figure 46; note that the AGC threshold is at –95 dBm. The output signal level was set to 800 mV p-p by applying –80 mV to the V
REV. 0
PIN – dBm
connector.
SET
0–40
10
Figure 47. Control Voltage vs. Input Power of Circuit in Figure 46
–15–
Page 16
AD604
Ultralow Noise, Differential Input-Differential Output VGA
Figure 48 shows how to use both preamplifiers and DSXs to create a high impedance, differential input-differential output variable gain amplifier. This application takes advantage of the differential inputs to the DSXs. It should be pointed out that the input is not truly differential, in the sense that the common­mode voltage needs to be at ground to achieve maximum input signal swing. This has mainly to do with the limited output swing capability of the output drivers of the preamplifiers; they clip around ±2.2 V due to having to drive an effective load of about 30 . If a different input common-mode voltage needs to be accommodated, ac coupling (as was done in Figure 46) is recommended. The differential gain range of this circuit runs from +6 dB to +54 dB. This is 6 dB higher than each individual channel of the AD604 because the DSX inputs now see twice the signal amplitude compared to when they are driven single ended.
VGN1 VREF
OUT1 GND1 VPOS VNEG VNEG VPOS GND2
OUT2
VOCM
VGN2
+5V
–5V
24
23 22 21
20 19 18 17 16 15 14 13
+5V –5V –5V +5V
C5
0.1µF
C7
0.1µF
C6
0.1µF
R1
453
R2
453
VREF
VOUT+
VOUT–
VG
VIN+
VIN–
0.1µF
0.1µF
–DSX1
C1
C2
0.1µF
C4
C3
0.1µF
C12
0.1µF
1
+DSX1
2
PAO1
3
FBK1
4
PAI1
5
AD604
COM1
6
COM2
7 8
PAI2
9
FBK2
10
PAO2
11
+DSX2
12
–DSX2
FB FB
C13
0.1µF
ALL SUPPLY PINS ARE DECOUPLED AS SHOWN.
Figure 48. Ultralow Noise, Differential Input–Differential Output VGA
Figure 49 displays the output signals VOUT+ and VOUT– after a –20 dB attenuator formed between the 453 resistors shown in Figure 48 and the 50 loads presented by the oscilloscope
plug-in. R1 and R2 were inserted to insure a nominal load of 500 at each output. The differential gain of the circuit was set to +20 dB by applying a control voltage, VGN, of 1 V; the gain scaling was 20 dB/V for a VREF of 2.500 V; the input frequency was 10 MHz and the differential input amplitude 100 mV p-p. The resulting differential output amplitude was 1 V p-p as can be seen on the scope photo when reading the vertical scale as 200 mV/div.
20mV
100
90
10
0%
20mV
NOTE 1. OUTPUT AFTER 10x ATTENUATER FORMED BY 453 TOGETHER WITH 50 OF 7A24 PLUG-IN.
20ns
ACTUAL V
OUT
+500mV
–500mV
Figure 49. Output of VGA in Figure 48 for VG = 1 V
Medical Ultrasound TGC Driving the AD9050, a 10-Bit, 40 MSPS A/D
The AD604 is an ideal candidate for the TGC (Time Gain Control) amplifier that is required in medical ultrasound sys­tems to limit the dynamic range of the signal that is presented to the A/D converter. Figure 50 shows a schematic of an AD604 driving an AD9050 in a typical medical ultrasound application.
The gain is controlled by means of a digital byte that is input to an AD7226 D/A converter that outputs the analog gain control signal. The output common-mode voltage of the AD604 is set to VPOS/2 by means of an internal voltage divider. The VOCM pin is bypassed with a 0.1 µF to ground.
The DSX output is optionally filtered and then buffered by an AD9631 op amp, a low distortion, low noise amplifier. The op amp output is ac coupled into the self-biasing input of an AD9050 A/D converter which is capable of outputting 10 bits at a 40 MSPS sampling rate.
–16–
REV. 0
Page 17
ANALOG
INPUT
AD604
15
AD9050
VREF VREF COMP
REF
BP
AINB AIN ENCODE OR
(MSB) D9
OUT IN
(LSB) D0
+5V +5V
16
D8
17
D7
18
D6
19
D5 D4 D3 D2 D1
A/D OUTPUT
24 25 26 27 28 20 22
CLK
0.1µF
1k
0.1µF
FILTER
1k
2
3
–IN
+IN
OPTIONAL
1k
AD9631
OUT
6
0.1µF
0.1µF
0.1µF
3 4 5 6
9 10 13
14
0.1µF
0.1µF 1
–DSX1
2
0.1µF
J2
50
50
0.1µF
0.1µF
+DSX1 PAO1
3
FBK1
4
PAI1
5
COM1
6
COM2
7 8
PAI2 FBK2
9
PAO2
10
+DSX2
11
–DSX2
12
AD604
100
VGN1 VREF OUT1 GND1
VPOS VNEG VNEG VPOS GND2
OUT2
VOCM
VGN2
24 23 22 21 20 19 18 17 16 15 14 13
V
OUT
V
OUT
(LSB)
V
WR
DB0
DB1 DB2 DB3
20
C
19
D
18
DD
A0
17
A1
16 15 14
13 12 11
+15V
VREF
1
V
B
OUT
2
A
V
OUT
3
V
SS
AD7226
V
4
REF
5
AGND
6
DGND
DB7
7
(MSB)
8
DB6
9
DB5
10
DB4
DIGITAL GAIN CONTROL
Figure 50. TGC Circuit for Medical Ultrasound Application
C3
0.1µF 1
–DSX1
2
C1
NOTE 2
0.1µF
RGN
RGN
0.1µF
R2
R3
C6
0.1µF
PAO1
IN1
IN2
PAO2
NOTES:
1. PAO1 AND PAO2 ARE USED TO MEASURE PREAMPS.
2. RGN = 0 NOMINALLY; PREAMP GAIN = 5, RGN = OPEN; PREAMP GAIN = 10
3. WHEN MEASURING BW WITH 50 SPECTRUM ANALYZER, USE 450 IN SERIES.
+DSX1
3
PAO1
4
FBK1
AD604
5
PAI1
6
COM1
COM2
7
8
PAI2
9
FBK2
10
PAO2
11
+DSX2
12
–DSX2
C5
VGN1
VREF
OUT1
GND1
VPOS
VNEG
VNEG
VPOS
GND2
OUT2
VOCM
VGN2
24
23
C4
0.1µF
22
21
C12
0.1µF
20
C11
0.1µF
19
18
C10
0.1µF
17
C9
0.1µF
16
15
C7
0.1µF
14
13
C2 5pF
C8 5pF
R1 500
NOTE 3
NOTE 3
R4 500
OPTIONAL
+5V
–5V
VG1
VREF
OUT1
OUT2
VOCM
VG2
HP3577B
HP11636B
POWER
SPLITTER
49.9
OUT
PAI
AD604
DUT
A
R
50
0.1µF
450
Figure 52. Setup for Gain Measurements
REV. 0
Figure 51. Basic Test Board
–17–
Page 18
AD604
24
112
13
1.275 (32.30)
1.125 (28.60)
0.280 (7.11)
0.240 (6.10)
PIN 1
SEATING PLANE
0.022 (0.558)
0.014 (0.356)
0.060 (1.52)
0.015 (0.38)
0.150 (3.81) MIN
0.070 (1.77)
0.045 (1.15)
0.200 (5.05)
0.125 (3.18)
0.210
(5.33)
MAX
0.100 (2.54)
BSC
0.325 (8.25)
0.300 (7.62)
0.015 (0.381)
0.008 (0.204)
0.195 (4.95)
0.115 (2.93)
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
0.6141 (15.60)
0.5985 (15.20)
24 13
PIN 1
0.0118 (0.30)
0.0040 (0.10)
0.0500 (1.27)
BSC
Small Outline IC Package
(R-24)
0.2992 (7.60)
0.2914 (7.40)
0.4193 (10.65)
0.3937 (10.00)
0.0125 (0.32)
0.0091 (0.23)
24
0.0192 (0.49)
0.0138 (0.35)
121
0.1043 (2.65)
0.0926 (2.35)
SEATING PLANE
0.0291 (0.74)
0.0098 (0.25)
8° 0°
x 45°
0.0500 (1.27)
0.0157 (0.40)
Shrink Small Outline Package
(RS-24)
0.328 (8.33)
0.318 (8.08)
13
Plastic DIP Package
(N-24)
0.311 (7.9)
0.301 (7.64)
1
0.078 (1.98)
0.068 (1.73)
0.008 (0.203)
0.002 (0.050)
PIN 1
0.0256 (0.65)
BSC
0.015 (0.38)
0.010 (0.25)
12
0.07 (1.78)
0.066 (1.67)
SEATING
PLANE
–18–
0.212 (5.38)
0.205 (5.207)
0.009 (0.229)
0.005 (0.127)
8° 0°
0.037 (0.94)
0.022 (0.559)
REV. 0
Page 19
–19–
Page 20
C2190–9–10/96
–20–
PRINTED IN U.S.A.
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