Datasheet AD5930 Datasheet (ANALOG DEVICES)

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Programmable Frequency Sweep and

FEATURES

Programmable frequency profile
No external components necessary
Output frequency up to 25 MHz
Burst and listen capability
Preprogrammable frequency profile minimizes number of

DSP/µcontroller writes
Sinusoidal/triangular/square wave outputs
Automatic or single pin control of frequency stepping
Waveform starts at known phase
Increments at 0° phase or phase continuously
Power-down mode: 20 µA
Power supply: 2.3 V to 5.5 V
Automotive temperature range: −40°C to +125°C
20-lead pb-free TSSOP

APPLICATIONS

Frequency sweeping/radar
Network/impedance measurements
Incremental frequency stimulus
Sensory applications

Proximity and motion
BFSK
Frequency bursting/pulse trains

Output Burst Waveform Generator

AD5930

GENERAL DESCRIPTION

The AD59301 is a waveform generator with programmable
frequency sweep and output burst capability. Utilizing
embedded digital processing that allows enhanced frequency
control, the device generates synthesized analog or digital
frequency-stepped waveforms. Because frequency profiles
are preprogrammed, continuous write cycles are eliminated
and thereby free up valuable DSP/µcontroller resources.
Waveforms start from a known phase and are incremented
phase continuously, which allows phase shifts to be easily
determined. Consuming only 8 mA, the AD5930 provides a
convenient low power solution to waveform generation.

The AD5930 can be operated in a variety of modes. In
continuous output mode, the device outputs the required
frequency for a defined length of time and then steps to the
next frequency. The length of time the device outputs a
particular frequency is either preprogrammed and the device
increments the frequency automatically, or, alternatively, is
incremented externally via the CTRL pin. In burst mode, the
device outputs its frequency for a length of time and then
returns to midscale for a further predefined length of time
before stepping to the next frequency. When the MSBOUT pin
is enabled, a digital output is generated.

(continued on Page 3)

FUNCTIONAL BLOCK DIAGRAM

INTERRUPT

MCLK

CTRL

1

Protected by US Patent Number 6747583, other patents pending.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice.
No license is granted by implication or otherwise under any patent or patent rights of Analog
Devices. Trademarks and registered trademarks are the property of their respective owners.

STANDBY DVDD CAP/2.5V DGND AGND AVDD

AD5930

OUTPUT BURST

CONTRO LLER

DATA

INCREMENT

CONTROLL ER

DATA

FREQUENCY

CONTRO LLER

DATA

SERIAL INTERFACE

FSYNC SCLK SDATA

REGULATOR

SYNC

INCR

AND CONTROL

CONTRO L
REGISTER

24

PIPELINED
DDS CORE

24-BIT

Figure 1.

VCC

SYNC

2.5V

ON-BOARD

REFERENCE

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]
Fax: [phone] © 2005 Analog Devices, Inc. All rights reserved.

BUFFER

BUFFER

10-BIT

DAC

FULL-SCALE

CONTROL

REF FSADJUST

SYNCOUT

DGND O/P

MSBOUT

IOUTB

IOUT

COMP

05333-001

www.analog.com

AD5930

TABLE OF CONTENTS

Features .............................................................................................. 1

Powering up the AD5930 .......................................................... 17

Applications....................................................................................... 1

General Description......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 4

Timing Characteristics..................................................................... 6

Absolute Maximum Ratings............................................................ 8

ESD Caution.................................................................................. 8

Pin Configuration and Function Descriptions............................. 9

Typical Performance Characteristics ........................................... 11

Te r mi n ol o g y .................................................................................... 15

Theory of Operation ...................................................................... 16

The Frequency Profile................................................................ 16

Output Modes............................................................................. 16

Serial Interface............................................................................ 17

Programming the AD5930........................................................ 17

Setting up the Frequency Sweep............................................... 19

Activating and Controlling the Sweep..................................... 20

Outputs from the AD5930........................................................ 21

Applications..................................................................................... 22

Grounding and Layout .............................................................. 22

AD5930 to ADSP-21xx Interface ............................................. 22

AD5930 to 68HC11/68L11 Interface....................................... 23

AD5930 to 80C51/80L51 Interface.......................................... 23

AD5930 to DSP56002 Interface ............................................... 23

Evaluation Board ........................................................................ 24

Schematic..................................................................................... 25

Outline Dimensions ....................................................................... 27

Ordering Guide .......................................................................... 27

REVISION HISTORY

11/05—Revision 0: Initial Version

Rev. 0 | Page 2 of 28

AD5930

GENERAL DESCRIPTION

(continued from Page 1)

To program the device, the user enters the start frequency, the
increment step size, the number of increments to be made, and
the time interval that the part outputs each frequency. The
frequency sweep profile is initiated, started, and executed by
toggling the CTRL pin.

A number of different sweep profiles are offered. Frequencies can
be stepped in triangular-sweep mode, which continuously sweeps
up and down through the frequency range. Alternatively, in saw­sweep mode, the frequency is swept up through the frequency
range, but returns to the initial frequency before executing the

sweep again. In addition, a single frequency or burst can be
generated without any sweep.

The AD5930 is written to via a 3-wire serial interface, which
operates at clock rates up to 40 MHz. The device operates with
a power supply from 2.3 V to 5.5 V. Note that AV
are independent of each other and can be operated from
different voltages. The AD5930 also has a standby function,
which allows sections of the device that are not being used
to be powered down.

The AD5930 is available in a 20-lead pb-free TSSOP package.

and DVDD

DD

Rev. 0 | Page 3 of 28

AD5930

SPECIFICATIONS

AVDD = DVDD = 2.3 V to 5.5 V, AGND = DGND = 0 V, TA = T
unless otherwise noted.

Table 1.

Y Grade

1

Parameter Min Typ Max Unit Test Conditions/Comments

SIGNAL DAC SPECIFICATIONS

Resolution 10 Bits

Update Rate 50 MSPS

I

Full-Scale

OUT

V

Peak-to-Peak 0.56 V

OUT

V

Offset 45 mV From 0 V to the trough of the waveform

OUT

V

MIDSCALE

2

3 4.0 mA

0.325 V Voltage at midscale output
Output Compliance 0.8 V AV
DC Accuracy

Integral Nonlinearity (INL) ±1.5 LSB
Differential Nonlinearity (DNL) ±0.75 LSB

DDS SPECIFICATIONS

Dynamic Specifications

Signal-to-Noise Ratio 53 60 dB f

Total Harmonic Distortion −60 −53 dBc f

Spurious-Free Dynamic Range
(SFDR)

Wideband (0 to Nyquist) −62 −52 dBc f
Narrowband (±200 kHz) −76 −73 dBc f

Clock Feedthrough −50 dBc Up to 16 MHz out

Wake-Up Time 1.7 ms From standby

OUTPUT BUFFER

V

Peak-to-Peak 0 DVDDV Typically, square wave on MSBOUT and SYNCOUT

OUT

Output Rise/Fall Time

2

12 ns

VOLTAGE REFERENCE

Internal Reference 1.15 1.18 1.26 V
External Reference Range 1.3 V
REFOUT Input Impedance 1 kΩ VIN @ REF pin < Internal V
25 kΩ VIN @ REF pin > Internal V
Reference TC

2

90 ppm/°C

LOGIC INPUTS

Input Current 0.1 ±1 µA
V

, Input High Voltage 1.7 V DVDD = 2.3 V to 2.7 V

INH

2.0 V DVDD = 2.7 V to 3.6 V

2.8 V DVDD = 4.5 V to 5.5 V
V

, Input Low Voltage 0.6 V DVDD = 2.3 V to 2.7 V

INL

0.7 V DVDD = 2.7 V to 3.6 V

0.8 V DVDD = 4.5 V to 5.5 V
CIN, Input Capacitance

LOGIC OUTPUTS

2

2

3 pF

VOH, Output High Voltage DVDD − 0.4 V V I
VOL, Output Low Voltage 0.4 V I
Floating-State O/P Capacitance 5 pF

MIN

to T

MAX

, R

= 6.8 kΩ, R

SET

= 2.3 V, internal reference used

DD

= 50 MHz, f

MCLK

= 50 MHz, f

MCLK

= 50 MHz, f

MCLK

= 50 MHz, f

MCLK

= 1 mA

SINK

= 1 mA

SINK

= 200 Ω for IOUT and IOUTB,

LOAD

OUT

OUT

OUT

OUT

= f
= f

= f
= f

MCLK

MCLK

MCLK

MCLK

3

/4096
/4096

/50
/50

REF

REF

Rev. 0 | Page 4 of 28

AD5930

F

Y Grade

1

Parameter Min Typ Max Unit Test Conditions/Comments

POWER REQUIREMENTS f

AVDD/DV
I

AA

I

DD

IAA + I

DD

DD

2.3 5.5 V

3.8 4 mA

2.4 2.7 mA

6.2 6.7 mA

= 50 MHz, f

MCLK

OUT

= f

MCLK

/7

Low Power Sleep Mode Device is reset before putting into standby
20 85 µA All outputs powered down, MCLK = 0 V, serial interface active
140 240 µA All outputs powered down, MCLK active, serial interface active

1

Operating temperature range is as follows: Y Version: −40°C to +125°C; typical specifications are at 25°C.

2

Guaranteed by design.

3

Minimum R

= 3.9 kΩ.

SET

R

SET

FSADJUST

CONTROL

6.8V

COMP

AVD D

10nF

100n

10nF

CAP/2.5V

REGULATOR

REFOUT

ON-BOARD

REFERENCE

FULL-SCALE

AD5930

12

SIN

ROM

10-BIT

DAC

IOUT

R

LOAD

200V

20pF

05333-002

Figure 2. Test Circuit Used to Test the Specifications

Rev. 0 | Page 5 of 28

AD5930

C

TIMING CHARACTERISTICS

All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
See Figure 4 to Figure 7. DV

1

Table 2.

Parameter Limit at T

t

1

t

2

t

3

t

4

t

5

t

6

t

7

t

8

t

9

t

10

t

11

t

12

t

13

8 x t
t

14

t

15

t

16

t

17

1

Guaranteed by design, not production tested.

20 ns min MCLK period
8 ns min MCLK high duration
8 ns min MCLK low duration
25 ns min SCLK period
10 ns min SCLK high time
10 ns min SCLK low time
5 ns min FSYNC to SCLK falling edge setup time
10 ns min FSYNC to SCLK hold time
5 ns min Data setup time
3 ns min Data hold time
2 x t

1

0 ns min CTRL rising edge to MCLK falling edge setup time
10 x t

1

1

2 x t

1

2 x t

1

2 x t

1

20 ns max MCLK falling edge after 16th clock edge to MSB out

= 2.3 V to 5.5 V, AGND = DGND = 0 V, all specifications T

DD

, T

MIN

MAX

Unit Conditions/Comments

ns min Minimum CTRL pulse width

ns typ CTRL rising edge to IOUT/IOUTB delay (initial pulse, includes initialization)
ns typ CTRL rising edge to IOUT/IOUTB delay (initial pulse, includes initialization)
ns typ Frequency change to SYNC output, saw sweep, each frequency increment
ns typ Frequency change to SYNC output, saw sweep, end of sweep
ns typ Frequency change to SYNC output, triangle sweep, end of sweep

t

MCLK

Figure 3. Master Clock

1

t

2

t

3

05333-003

MIN

to T

, unless otherwise noted.

MAX

SCLK

FSYN

SDATA

t

5

t

7

D15 D14 D2 D1 D0 D15 D14

t

6

Figure 4. Serial Timing

t

4

t

8

t

10

t

9

05333-004

Rev. 0 | Page 6 of 28

AD5930

y

y

t

MCLK

12

CTRL

IOUT/IOUTB

t

11

t

13

05333-005

Figure 5. CTRL Timing

CTRL

t

13

IOUT

SYNC O/P

(Each Frequenc

Increment )

SYNC O/P

(End of Sweep)

t

14

t

15

05333-006

Figure 6. CTRL Timing, Saw-Sweep Mode

CTRL

IOUT

SYNC O/P

(Each Frequenc

Increment )

SYNC O/P

(End of Sweep)

t

13

t

14

t

16

Figure 7. CTRL Timing, Triangular-Sweep Mode

05333-007

Rev. 0 | Page 7 of 28

AD5930

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 3.

Parameter Rating
AVD D to AGND −0.3 V to +6.0 V
DVDD to DGND −0.3 V to +6.0 V
AGND to DGND −0.3 V to +0.3 V
CAP/2.5V to DGND −0.3 V to 2.75 V
Digital I/O Voltage to DGND −0.3 V to DVDD + 0.3 V
Analog I/O Voltage to AGND −0.3 V to AVDD + 0.3 V
Operating Temperature Range

Automotive (Y Version) −40°C to +125°C

Storage Temperature Range −65°C to +150°C
Maximum Junction Temperature +150°C
TSSOP Package (4-Layer Board)

θJA Thermal Impedance 112°C/W
θJC Thermal Impedance 27.6°C/W

Reflow Soldering (Pb-Free) 300°C

Peak Temperature 260(+0/−5)°C
Time at Peak Temperature 10 sec to 40 sec

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. 0 | Page 8 of 28

AD5930

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

FSADJUST

REF

COMP

AVD D

DVDD

CAP/2.5V

DGND

MCLK

SYNCOUT

MSBOUT

1

2

3

4

(Not to S cale)

5

6

7

8

9

10

AD5930

TOP VIEW

20

IOUTB

19

IOUT

18

AGND

17

STANDBY

16

FSYNC

15

SCLK

14

SDATA

13

CTRL

12

INTERRUPT

11

DGND O/P

05333-008

Figure 8. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description

1 FSADJUST

Full-Scale Adjust Control. A resistor (RSET) must be connected externally between this pin and AGND.
This determines the magnitude of the full-scale DAC current. The relationship between R
full-scale current is:

2 REF

IOUT

where V
Voltage Reference. This pin can be an input or an output. The AD5930 has an internal 1.18 V reference, which

= 18 × V

FULL-SCALE

= 1.20 V nominal and R

REFOUT

REFOUT/RSET

= 6.8 kΩ typical.

SET

is made available at this pin. Alternatively, this reference can be overdriven by an external reference, with a
voltage range as given in the Specifications section. A 10 nF decoupling capacitor should be connected

between REF and AGND.
3 COMP DAC Bias Pin. This pin is used for decoupling the DAC bias voltage to AVDD.
4 AVDD

Positive Power Supply for the Analog Section. AVDD can have a value from +2.3 V to +5.5 V. A 0.1 µF decoupling

capacitor should be connected between AVDD and AGND.
5 DVDD

Positive Power Supply for the Digital Section. DVDD can have a value from +2.3 V to +5.5 V. A 0.1 µF decoupling

capacitor should be connected between DVDD and DGND.
6 CAP/2.5V

Digital Circuitry. Operates from a 2.5 V power supply. This 2.5 V is generated from DVDD using an on-board

regulator. The regulator requires a decoupling capacitor of typically 100 nF, which is connected from CAP/2.5V

to DGND. If DVDD is equal to or less than 2.7 V, CAP/2.5V can be shorted to DVDD.
7 DGND Ground for all Digital Circuitry. This excludes digital output buffers.
8 MCLK

Digital Clock Input. DDS output frequencies are expressed as a binary fraction of the frequency of MCLK.

The output frequency accuracy and phase noise are determined by this clock.
9 SYNCOUT

Digital Output for Sweep Status Information. User selectable for end of sweep (EOS) or frequency increments

through the control register (SYNCOP bit). This pin must be enabled by setting Control Register Bit SYNCOPEN to 1.
10 MSBOUT

Digital Output. The inverted MSB of the DAC data is available at this pin. This output pin must be enabled by

setting bit MSBOUTEN in the control register to 1.
11 DGND O/P Separate DGND Connection for Digital Output Buffers. Connect to DGND.
12 INTERRUPT

Digital Input. This pins acts as an interrupt during a frequency sweep. A low to high transition is sampled by the

internal MCLK, which resets internal state machines. This results in the DAC output going to midscale.
13 CTRL

Digital Input. Triple function pin for initialization, start, and external frequency increments. A low-to-high transition,

sampled by the internal MCLK, is used to initialize and start internal state machines, which then execute the pre-

programmed frequency sweep sequence. When in auto-increment mode, a single pulse executes the entire sweep

sequence. When in external increment mode, each frequency increment is triggered by low-to-high transitions.
14 SDATA

Serial Data Input. The 16-bit serial data-word is applied to this input with the register address first followed by the

MSB to LSB of the data.
15 SCLK Serial Clock Input. Data is clocked into the AD5930 on each falling SCLK edge.
16 FSYNC

Active Low Control Input. This is the frame synchronization signal for the serial data. When FSYNC is taken low,

the internal logic is informed that a new word is being loaded into the device.
17 STANDBY

Active High Digital Input. When this pin is high, the internal MCLK is disabled, and the reference DAC and regulator

are powered down. For optimum power saving, it is recommended to reset the AD5930 before putting it into

standby, as this results in a shutdown current of typically 20 µA.

Rev. 0 | Page 9 of 28

and the

SET

AD5930

Pin No. Mnemonic Description

18 AGND Ground for all Analog Circuitry.
19 IOUT

20 IOUTB

Current Output. This is a high impedance current source output. A load resistor of nominally 200 Ω should be
connected between IOUT and AGND. A 20 pF capacitor to AGND is also recommended to act as a low-pass filter
and to reduce clock feedthrough. In conjunction with IOUTB, a differential signal is available.

Current Output. IOUTB is the compliment of IOUT. This pin should preferably be tied through an external load
resistor of 200 Ω to AGND, but can be tied directly to AGND. A 20 pF capacitor to AGND is also recommended as a
low-pass filter to reduce clock feedthrough. In conjunction with IOUT, a differential signal is available.

Rev. 0 | Page 10 of 28

AD5930

–

–

–

TYPICAL PERFORMANCE CHARACTERISTICS

9

TA = 25°C
AVD D = 5V

8

MSBOUT, SYNCOUT ENABLED

7

6

5

(mA)

DD

4

I

3

2

1

0

050

MCLK FREQUENCY (MHz)

DVDD = 5V

DVDD = 5V, F

DVDD = 3V, F

= MCLK/7

OUT

OUT

DVDD = 3V

= MCLK/7

05333-027

45403530252015105

SFDR (dBc)

40

AVDD = DVDD = 3V/5V
MCLK = 50MHz

–45

C

= 0111 1111 1111

REG

T

= 25°C

–50

A

–55

–60

–65

–70

–75

–80

–85

–90

05045403530252015105

F

= MCLK/7

OUT

F

= MCLK/50

OUT

F

= MCLK/3

OUT

MCLK FREQUENCY (MHz)

05333-030

Figure 9. Current Consumption (I

7

TA = 25°C
MCLK = 50MHz

6

5

4

(mA)

DD

3

I

2

1

0

1kHz

500kHz

Figure 10. I

3.5

3.0

2.5

2.0

(mA)

DD

I

1.5

1.0

0.5

DD

LEGEND

1. SINEWAVE OUT PUT, INTERNAL LY CO NTROLLED SWEE P

2. TRIA NGULAR OUT PUT, INT ERNALLY CONTRO LLED SWEE P

3. SINEWAVE OUT PUT, EXTERNAL LY CO NTROLLED SWEEP

4. TRIA NGULAR OUT PUT, EXTERNAL LY CONTROLLED SWEE P

0

Figure 11. I

MSBOUT OFF,
SYNCOUT ON

100kHz

10kHz

vs. F

OUT

CONTROL O PTION (See Legend )

vs. Output Waveform Type and Control

DD

1MHz

500kHz

2MHz

F

(Hz)

OUT

for Various Digital Output Conditions

AIDD

DIDD

) vs. MCLK Frequency

DD

MSBOUT ON,

SYNCOUT ON

MSBOUT ON,

SYNCOUT OF F

MSBOUT OFF,

SYNCOUT OF F

15MHz

5MHz

10MHz

3421

20MHz

25MHz

Figure 12. Wideband SFDR vs. MCLK Frequency

60

AVDD = DVDD = 3V/5V
MCLK = 50MHz
C

= 0111 1111 1111

REG

–65

T

= 25°C

A

F

–70

F

= MCLK/3

–75

SFDR (dBc)

–80

–85

05333-028

–90

0545403530252015105

OUT

MCLK FREQUENCY (MHz)

OUT

F

OUT

= MCLK/50

= MCLK/7

05333-031

0

Figure 13. Narrowband SFDR vs. MCLK Frequency

30

AVDD = DVDD = 3V/5V
C

= 0111 1111 1111

REG

T

= 25°C

A

–40

–50

–60

SFDR (dBc)

–70

–80

05333-029

–90

Figure 14. Wideband SFDR vs. F

MCLK = 10MHz

MCLK = 1MHz

0.001 1001010.10.01

F

(MHz)

OUT

for Various MCLK Frequencies

OUT

MCLK = 50MHz

MCLK = 30MHz

05333-032

Rev. 0 | Page 11 of 28

AD5930

70

65

60

55

SNR (dB)

50

45

40

1.25

1.23

1.21

(V)

REF

V

1.19

1.17

TA = 25°C
AVDD = DVDD = 5V

f

= FMCLK/4096

OUT

MCLK FREQUENCY (MHz)

Figure 15. SNR vs. MCLK Frequency

AVDD = DVDD = 5V

05333-034

50M40M30M20M10M0

NUMBER OF DEVICES

NUMBER OF DEVICES

12

10

8

6

4

2

0

552 572568 570566564562560558556554

Figure 18. Histogram of V

12

10

8

6

4

2

V

PEAK-TO-PEAK (mV)

OUT

Peak-to-Peak

OUT

05333-025

1.15

TEMPERATURE (° C)

Figure 16. V

vs. Temperature

REF

2.0

1.9

1.8

1.7

1.6

1.5

WAKE-UP TIME (ms)

1.4

1.3

1.2

AVDD = DVDD = 2.3V

AVDD = DVDD = 5V

TEMPERATURE (° C)

Figure 17. Wake-up Time vs. Temperature

05333-035

120100806040200–40 –20

0

44.4 46.245.8 46.045.645.445.245.044.844.6

V

OFFSET (mV)

OUT

Figure 19. Histogram of V

OUT

Offset

0

TA = 25°C
100mV p-p RIPPLE

–10

NO DECOUP LING ON SUPPLIES
AVDD = DVDD = 5V

–20

–30

–40

–50

ATTENUATION (dB)

–60

–70

05333-036

120100806040200–40 –20

–80

10 1M100k10k1k100

DVDD (on CAP/2.5V)

AVDD (on IOUT)

MODULATING FREQUENCY (Hz)

Figure 20. PSSR

05333-026

05333-033

Rev. 0 | Page 12 of 28

AD5930

0
–10
–20
–30
–40

–50
–60
–70
–80
–90

–100

PHASE NOISE

–110
–120
–130
–140

–150
–160
–170

f

(Hz)

05333-037

100k10k1k100

Figure 21. Output Phase Noise

0

–10

–20

–30

–40

–50

(dB)

–60

–70

–80

–90

–100

05

Figure 24. f

= 10 MHz; f

MCLK

VWB 300RWB 1K ST 50 SEC

FREQUENCY (Hz)

= 3.33 MHz = f

OUT

MCLK

/3,

05333-016

M

Frequency Word = 5555555

0

–10

–20

–30

–40

–50

(dB)

–60

–70

–80

–90

–100

0 100k

Figure 22. f

f

= 2.4 kHz, Frequency Word = 000FBA9

OUT

0

–10

–20

–30

–40

–50

(dB)

–60

–70

–80

–90

–100

05M

Figure 23. f

f

= 1.43 MHz = f

OUT

VWB 30RWB 100 ST 100 SEC

FREQUENCY (Hz)

= 10 MHz;

MCLK

VWB 300RWB 1K ST 50 SEC

FREQUENCY (Hz)

= 10 MHz;

MCLK

/7, Frequency Word = 2492492

MCLK

05333-014

05333-015

0

–10

–20

–30

–40

–50

(dB)

–60

–70

–80

–90

–100

0 160k

Figure 25. f

f

= 12 kHz, Frequency Word = 000FBA9

OUT

0

–10

–20

–30

–40

–50

(dB)

–60

–70

–80

–90

–100

01.6M

Figure 26. f

f

= 120 kHz, Frequency Word = 009D496

OUT

VWB 30RWB 100 ST 200 SEC

FREQUENCY (Hz)

= 50 MHz;

MCLK

VWB 300RWB 100 ST 200 SEC

FREQUENCY (Hz)

= 50 MHz;

MCLK

05333-017

05333-018

Rev. 0 | Page 13 of 28

AD5930

0

–10

–20

–30

–40

–50

(dB)

–60

–70

–80

–90

–100

0 25M

Figure 27. f

f

= 1.2 MHz, Frequency Word = 0624DD3

OUT

0

–10

–20

–30

–40

–50

(dB)

–60

–70

–80

–90

–100

0 25M

Figure 28. f

f

= 4.8 MHz, Frequency Word = 189374C

OUT

VWB 300RWB 1K ST 200 SEC

FREQUENCY (Hz)

= 50 MHz;

MCLK

VWB 300RWB 1K ST 200 SEC

FREQUENCY (Hz)

= 50 MHz;

MCLK

05333-019

05333-020

0

–10

–20

–30

–40

–50

(dB)

–60

–70

–80

–90

–100

0 25M

Figure 29. f

MCLK

= 50 MHz; f

VWB 300RWB 1K ST 200 SEC

FREQUENCY (Hz)

= 7.143 MHz = f

OUT

Frequency Word = 2492492

0

–10

–20

–30

–40

–50

(dB)

–60

–70

–80

–90

–100

0 25M

Figure 30. f

= 50 MHz; f

MCLK

VWB 300RWB 1K ST 200 SEC

FREQUENCY (Hz)

= 16.667 MHz = f

OUT

Frequency Word = 5555555

MCLK

MCLK

05333-021

/7,

05333-022

/3,

Rev. 0 | Page 14 of 28

AD5930

TERMINOLOGY

Integral Nonlinearity (INL)
This is the maximum deviation of any code from a straight line
passing through the endpoints of the transfer function. The
endpoints of the transfer function are zero scale and full scale.
The error is expressed in LSBs.

Differential Nonlinearity (DNL)
This is the difference between the measured and ideal 1 LSB
change between two adjacent codes in the DAC. A specified
differential nonlinearity of ±1 LSB maximum ensures
monotonicity.

Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of harmonics to the rms value
of the fundamental. For the AD5930, THD is defined as

22222

++++

VVVVV

54

THD

log20)dB(

=

32

V

1

6

where:

V

is the rms amplitude of the fundamental.

1

V

, V3, V4, V5, and V6 are the rms amplitudes of the second

2

through the sixth harmonic.

Output Compliance
The output compliance refers to the maximum voltage that can
be generated at the output of the DAC to meet the specifica­tions. When voltages greater than that specified for the output
compliance are generated, the AD5930 may not meet the
specifications listed in the data sheet.

Spurious-Free Dynamic Range (SFDR)
Along with the frequency of interest, harmonics of the
fundamental frequency and images of these frequencies are
present at the output of a DDS device. The SFDR refers to the
largest spur or harmonic that is present in the band of interest.
The wide band SFDR gives the magnitude of the largest
harmonic or spur relative to the magnitude of the fundamental
frequency in the 0 to Nyquist bandwidth. The narrow band
SFDR gives the attenuation of the largest spur or harmonic in a
bandwidth of ±200 kHz about the fundamental frequency.

Signal-to-Noise Ratio (SNR)

SNR is the ratio of the rms value of the measured output signal
to the rms sum of all other spectral components below the
Nyquist frequency. The value for SNR is expressed in decibels.

Clock Feedthrough

There is feedthrough from the MCLK input to the analog
output. Clock feedthrough refers to the magnitude of the
MCLK signal relative to the fundamental frequency in the
AD5930’s output spectrum.

Rev. 0 | Page 15 of 28

AD5930

THEORY OF OPERATION

The AD5930 is a general-purpose synthesized waveform
generator capable of providing digitally programmable
waveform sequences in both the frequency and time domain.
The device contains embedded digital processing to provide a
repetitive sweep of a user programmable frequency profile
allowing enhanced frequency control. Because the device is pre­programmable, it eliminates continuous write cycles from a
DSP/μcontroller in generating a particular waveform.

THE FREQUENCY PROFILE

The frequency profile is defined by the start frequency (F
the frequency increment (Δf) and the number of increments
per sweep (N
increments, t

). The increment interval between frequency

INCR

, is either user programmable with the interval

INT

automatically determined by the device (auto-increment mode),
or externally controlled via a hardware pin (external increment
mode). For automatic update, the interval profile can either be
for a fixed number of clock periods or for a fixed number of
output waveform cycles.

In the auto-increment mode, a single pulse at the CTRL pin starts
and executes the frequency sweep. In the external increment
mode, the CTRL pin also starts the sweep, but the frequency
increment interval is determined by the time interval between
sequential 0/1 transitions on the CTRL pin. Furthermore, the
CTRL pin can be used to directly control the burst profile, where
during the input high time, the output waveform is present, and
during the input low time, the output is reset to midscale.

The frequency profile can be swept in two different modes: saw
sweep or triangular (up/down) sweep.

START

),

Triangular-Sweep Mode

In the case of a triangular sweep, the AD5930 repeatedly
sweeps between sweep start to sweep end, that is, from F

START

incrementally to

F

+ N

START

and then returns to F

INCR

× Δf

in a decremented manner (see Figure 32).

START

The triangular-sweep cycle time is given by

(1 + (2 × N

F

START

MIDSCALE

)) × t

F

INCR

START

INT

F

+ N

START

F

+ ∆FF

START

INCR

Figure 32. Triangular-Sweep Profile

× ∆F

START

+ ∆F

F

START

OUTPUT MODES

The AD5930 offers two possible output modes: continuous
output mode and burst output mode. Both of these modes are
illustrated in Figure 33.

t

INT

CONTI NUOUS

MODE

T

BURST

BURST

MODE

05333-010

Saw-Sweep Mode

In the case of a saw sweep, the AD5930 repeatedly
sweeps between sweep start to sweep end, that is, from

incrementally to

F

START

F

+ N

START

and then returns directly to F

INCR

× Δf

to begin again (see Figure 31).

START

This gives a saw-sweep cycle time of

(N

+ 1) × t

F

START

MIDSCALE

INCR

INT

F

START

F

START

+ ∆FF

Figure 31. Saw-Sweep Profile

START

+ N

INCR

× ∆F

Continuous Output Mode

In this mode, each frequency of the sweep is available for the
length of time programmed into the time interval (t
This means the frequency swept output signal is continuously
available, and is therefore phase continuous at all frequency
increments.

To set up the AD5930 in continuous mode, the CW/BURST bit
(D7) in the control register must be set to 0. See the Activating
and Controlling the Sweep section for more details.

Burst Output Mode

In this mode, the AD5930 provides a programmable burst
of the waveform output for a fixed length of time (T
within the programmed increment interval (t
the remainder of the t

05333-009

Rev. 0 | Page 16 of 28

scale and remains there until the next frequency increment.

Figure 33.

12

NUMBER STEP CHANGES

Continuous Mode and Burst Mode of the AD5930

) register.

INT

BURST

). Then for

INT

interval, the output is reset to mid-

INT

05333-011

)

AD5930

This is beneficial for applications where the user needs to burst
a frequency for a set period, and then “listen” for a response
before increasing to the next frequency. Note also that the
beginning of each frequency increment is at midscale (Phase 0
Rad). Therefore, the phase of the signal is always known.

To set up the AD5930 in burst mode, the CW/BURST bit (D7)
in the control register must be set to 1. See the Activating and
Controlling the Sweep section for more details about the burst
output mode.

SERIAL INTERFACE

The AD5930 has a standard 3-wire serial interface, which is
compatible with SPI®, QSPI™, MICROWIRE™, and DSP
interface standards.

Data is loaded into the device as a 16-bit word under the
control of a serial clock input, SCLK. The timing diagram for
this operation is given in Figure 4.

The FSYNC input is a level-triggered input that acts as a frame
synchronization and chip enable. Data can only be transferred
into the device when FSYNC is low. To start the serial data
transfer, FSYNC should be taken low, observing the minimum
FSYNC to SCLK falling edge setup time, t

. After FSYNC goes

7

low, serial data is shifted into the device's input shift register on
the falling edges of SCLK for 16 clock pulses. FSYNC can be
taken high after the 16
minimum SCLK falling edge to FSYNC rising edge time, t

th

falling edge of SCLK, observing the

8.

Alternatively, FSYNC can be kept low for a multiple of 16 SCLK
pulses, and then brought high at the end of the data transfer. In
this way, a continuous stream of 16-bit words can be loaded while
FSYNC is held low. FSYNC should only go high after the 16th
SCLK falling edge of the last word is loaded.

The SCLK can be continuous, or, alternatively, the SCLK can
idle high or low between write operations.

POWERING UP THE AD5930

When the AD5930 is powered up, the part is in an undefined
state, and therefore, must be reset before use. The eight registers
(control and frequency) contain invalid data and need to be set
to a known value by the user. The control register should be the
first register to be programmed, as this sets up the part. Note
that a write to the control register automatically resets the
internal state machines and provides an analog output of
midscale as it provides the same function as the INTERRUPT
pin. Typically, this is followed by a serial loading of all the
required sweep parameters. The DAC output remains at
midscale until a sweep is started using the CTRL pin.

PROGRAMMING THE AD5930

The AD5930 is designed to provide automatic frequency sweeps
when the CTRL pin is triggered. The automatic sweep is
controlled by a set of registers, the addresses of which are given
in Table 5. The function of each register is described in more
detail in the following section.

Table 5. Register Addresses

Register Address

D15 D14 D13 D12 Mnemonic Name

0 0 0 0 C
0 0 0 1 N

0 0 1 0

0 0 1 1

0 1 t
1 0 T
1 1 0 0 F

1 1 0 1 F

1 1 1 0 Reserved
1 1 1 1 Reserved

REG

INCR

∆f

∆f

INT

BURST

START

START

The Control Register

The AD5930 contains a 12-bit control register (see Table 6) that
sets up the operating modes of the AD5930. The different
functions and the various output options from the AD5930 are
controlled by this register.

Table 7 describes the individual bits of the control register.

To address the control register, D15 to D12 of the 16-bit serial
word must be set to 0.

Table 6. Control Register

D15 D14 D13 D12 D11 to D0

0 0 0 0 Control Bits

Control bits
Number of

increments
Lower 12 bits of delta

frequency
Higher 12 bits of

delta frequency
Increment interval
Burst interval
Lower 12 bits of start

frequency
Higher 12 bits of start

frequency

Rev. 0 | Page 17 of 28

AD5930

Table 7. Description of Bits in the Control Register

Bit Name Function

D15
to
D12

D11 B24 Two write operations are required to load a complete word into the F

D10 DAC ENABLE When DAC ENABLE = 1, the DAC is enabled.

D9 SINE/TRI

D8 MSBOUTEN When MSBOUTEN = 1, the MSBOUT pin is enabled.

D7 CW/BURST

D6

D5

D4 MODE The function of this bit is to control what type of frequency sweep is carried out.

D3 SYNCSEL

D2 SYNCOUTEN When SYNCOUTEN= 1, the SYNC output is available at the SYNCOP pin.

D1 Reserved This bit must always be set to 1.
D0 Reserved This bit must always be set to 1.

ADDR Register address bits.

When B24 = 1, a complete word is loaded into a frequency register in two consecutive writes. The first write
contains the 12 LSBs of the frequency word and the next write contains the 12 MSBs. Refer to Table 5 for the
appropriate addresses. The write to the destination register occurs after both words have been loaded, so the
register never holds an intermediate value.

When B24 = 0, the 24-bit F
other containing the 12 LSBs. This means that the 12 MSBs of the frequency word can be altered independent of
the 12 LSBs and vice versa. This is useful if the complete 24-bit update is not required. To alter the 12 MSBs or the
12 LSBs, a single write is made to the appropriate register address. Refer to Table 5 for the appropriate addresses.

When DAC ENABLE = 0, the DAC is powered down. This saves power and is beneficial when only using the MSB of
the DAC input data (available at the MSBOUT pin).

The function of this bit is to control what is available at the IOUT/IOUTB pins.
When SINE/TRI = 1, the SIN ROM is used to convert the phase information into amplitude information resulting in a

sinusoidal signal at the output.
When SINE/TRI = 0, the SIN ROM is bypassed, resulting in a triangular (up-down) output from the DAC.

When MSBOUTEN = 0, the MSBOUT is disabled (tri-state).
When CW/BURST = 1, the AD5930 outputs each frequency continuously for the length of time or number of output

waveform cycles specified in the appropriate register, T
When CW/BURST = 0, the AD5930 bursts each frequency for the length of time/number of cycles specified in the

burst register, T

. For the remainder of the time within each increment window (T

BURST

outputs a DC value of midscale. In external increment mode, it is defined by the pulse widths on the CTRL pin.

INT/EXT
BURST

This bit is active when D7 = 0 and is also used in conjunction with D5. When the user is incrementing the frequency
externally (D5 = 1), D6 dictates whether the user is controlling the burst internally or externally.

When INT/EXT BURST = 1, the output burst is controlled externally through the CTRL pin. This is useful if the user is
using an external source to both trigger the frequency increments and determine the burst interval.

When INT/EXT BURST = 0, the output burst is controlled internally. The burst is pre-programmed by the user into
the T

register (the burst interval can either be clock-based or for a specified number of output cycles).

BURST

When D5 = 0, this bit is ignored.

INT/EXT
INCR

When INT/EXT INCR = 1, the frequency increments are triggered externally through the CTRL pin.
When INT/EXT INCR = 0, the frequency increments are triggered automatically.

When MODE = 1, the frequency profile is a saw sweep.
When MODE = 0, the frequency profile is a triangular (up-down) sweep.
This bit is active when D2 = 1. It is user-selectable to pulse at the end of sweep (EOS) or at each frequency

increment.
When SYNCSEL = 1, the SYNCOP pin outputs a high level at the end of the sweep and returns to zero at the start of

the subsequent sweep.
When SYNCSEL= 0, the SYNCOP outputs a pulse of 4 × T

When SYNCOUTEN= 0, the SYNCOP pin is disabled (tri-state).

register and the ∆f register.

START

/∆f register operates as two 12-bit registers, one containing the 12 MSBs and the

START

.

BURST

only at each frequency increment.

CLOCK

BURST

− t

), the AD5930

INT

Rev. 0 | Page 18 of 28

AD5930

SETTING UP THE FREQUENCY SWEEP

As stated previously in The Frequency Profile section, the
AD5930 requires certain registers to be programmed to enable a
frequency sweep. The following sections discuss these registers
in more detail.

Start Frequency (F

To start a frequency sweep, the user needs to tell the AD5930
what frequency to start sweeping from. This frequency is stored
in a 24-bit register called F
entire contents of the F
must be preformed, one to the LSBs and the other to the MSBs.
Note that for an entire write to this register, the Control Bit B24
(D11) should be set to 1 with the LSBs programmed first.

In some applications, the user does not need to alter all 24 bits
of the F

register. By setting the Control Bit B24 (D11) to 0,

START

the 24-bit register operates as two 12-bit registers, one
containing the 12 MSBs and the other containing the 12 LSBs.
This means that the 12 MSBs of the F
independently of the 12 LSBs, and vice versa. The addresses of
both the LSBs and the MSBs of this register is given in Table 8.

Table 8. F

Register Bits

START

D15 D14 D13 D12 D11 to D0

1 1 0 0 12 LSBs of F
1 1 0 1 12 MSBs of F

Frequency Increments (∆f)

The value in the Δf register sets the increment frequency for the
sweep and is added incrementally to the current output frequency.
Note that the increment frequency can be positive or negative,
thereby giving an increasing or decreasing frequency sweep.

At the start of a sweep, the frequency contained in the F
register is output. Next, the frequency (F
This is followed by (F
Δf value by the number of increments (N
the start frequency (F
sweep. Mathematically this final frequency/stop frequency is
represented by

+ (N

F

START

INCR

The Δf register is a 23-bit register, and requires two 16-bit
writes to be programmed. Table 9 gives the addresses associated
with both the MSB and LSB registers of the Δf word.

Table 9. ∆f Register Bits

D15 D14 D13 D12 D11 D10 to D0

0 0 1 0

0 0 1 1 0

0 0 1 1 1

)

START

. If the user wishes to alter the

START

register, two consecutive writes

START

word can be altered

START

START

START

+ Δf ) is output.

START

+ Δf + Δf) and so on. Multiplying the

START

), and adding it to

INCR

), gives the final frequency in the

START

× Δf).

12 LSBs of ∆f
<11…0>

11 MSBs of
Δf <22…12>

11 MSBs of
Δf <22…12>

<11…0>

<23…12>

START

Sweep
Direction

N/A

Positive Δf

+ Δf)

(F

START

Negative ∆f
(F

− Δf)

START

Number of Increments (N

An end frequency, or a maximum/minimum frequency before
the sweep changes direction is not required on the AD5930.
Instead, this end frequency is calculated by multiplying the
frequency increment value (Δf) by the number of frequency
steps (N
frequency (F

), and adding it to/subtracting it from the start

INCR

), that is, F

START

is a 12-bit register, with the address shown in Table 10.

Table 10. N

Register Bits

INCR

D15 D14 D13 D12 D11 to D0

0 0 0 1 12 bits of N

The number of increments is programmed in binary fashion,
with 000000000010 representing the minimum number of
frequency increments (2 increments), and 111111111111
representing the maximum number of increments (4095).

Table 11. N

Data Bits

INCR

D11 D0 Number of Increments

0000 0000 0010

2 frequency increments. This is the
minimum number of frequency

increments.
0000 0000 0011 3 frequency increments.
0000 0000 0100 4 frequency increments.
… … … …
1111 1111 1110 4094 frequency increments.
1111 1111 1111 4095 frequency increments.

Increment Interval (t

INT

The increment interval dictates the duration of the DAC output
signal for each individual frequency of the frequency sweep.
The AD5930 offers the user two choices:

• The duration is a multiple of cycles of the output frequency.

• The duration is a multiple of MCLK periods.

This is selected by Bit D13 in the t

Table 12. t

Register Bits

INT

D15 D14 D13 D12 D11 D10 to D0

0 1 0 x x

0 1 1 x x

Programming of this register is in binary form with the
minimum number being decimal 2. Note in Table 12 that 11
bits, Bit D10 to Bit D0, of the register are available to program
the time interval. As an example, if MCLK = 50 MHz, then each
clock period/base interval is (1/50 MHz) = 20 ns. If each
frequency needs to be output for 100 ns, then <00000000101>
or decimal 5 needs to be programmed to this register. Note that
the AD5930 can output each frequency for a maximum
duration of 211 −1 (or 2047) times the increment interval.

)

)

INCR

+ N

START

× Δ f. The N

INCR

INCR

register as shown in Table 12.

INT

11 bits <10…0>
Fixed number of output
waveform cycles.

11 bits <10…0>
Fixed number of clock
periods.

register

INCR

<11…0>

Rev. 0 | Page 19 of 28

AD5930

Therefore, in this example, a time interval of 20 ns × 2047 = 40 µs
is the maximum, with the minimum being 40 ns. For some
applications, this maximum time of 40 µs may be insufficient.
Therefore, to cater for sweeps that need a longer increment
interval, time-base multipliers are provided. Bit D12 and Bit D11
are dedicated to the time-base multipliers (see Table 12). A more
detailed table of the multiplier options is given in Table 13.

Table 13. Time-Base Multiplier Values

D12 D11 Multiplier Value

0 0 Multiply (1/MCLK) by 1
0 1 Multiply (1/MCLK) by 5
1 0 Multiply (1/MCLK) by 100
1 1 Multiply (1/MCLK) by 500

If MCLK is 50 MHz and a multiplier of 500 is used, then the
base interval (T
a multiplier of 500, the maximum increment interval is 10 µs ×

11 − 1

2

= 20.5 ms. Therefore, the option of time-base multipliers
gives the user enhanced flexibility when programming the
length of the frequency window, because any frequency can be
output for a minimum of 40 ns up to a maximum of 20.5 ms.

Length of Sweep Time

The length of time to complete a user-programmed frequency
sweep is given by the following equation:

= (1 + N

T

SWEEP

Burst Time Resister (T

As previously described in the Burst Output Mode section, the
AD5930 offers the user the ability to output each frequency in
the sweep for a length of time within the increment interval
(t

), and then return to midscale for the remainder of the time

INT

– T

(t

INT

BURST

option must be enabled. This is done by setting Bit D7 in the
control register to 0.

) is now (1/(50 MHz) x 500)) = 10 µs. Using

BASE

) × T

INCR

BURST

BASE

)

) before stepping to the next frequency. The burst

Table 14. T

Register Bits

BURST

D15 D14 D13 D12 D11 D10 to D0

1 0 0 x x

11 bits of <0…10>
Fixed number of output
waveform cycles.

1 0 1 x x

11 bits of <0…10>
Fixed number of clock
periods.

However, note that when using both the increment interval

) and burst time register (T

(t

INT

), the settings for Bit D13

BURST

should be the same. In instances where they differ, the AD5930
defaults to the value programmed into the t

register.

INT

Similarly, Bit 12 and Bit 11, the time-base multiplier bits, always
default to the value programmed into the t

register.

INT

ACTIVATING AND CONTROLLING THE SWEEP

After the registers have been programmed, a 0 ≥ 1 transition on
the CTRL pin starts the sweep. The sweep always starts from
the frequency programmed into the F
the value in the ∆F register and increases by the number of
steps in the N

register. However, both the time interval and

INCR

burst duration of each frequency can be internally controlled
using the t

INT

and T

registers, or externally using the CTRL

BURST

pin. The options available are:

1. auto-increment, auto-burst control

2. external increment, auto-burst control

3. external increment, external burst control

1. Auto-Increment, Auto-Burst Control

The values in the t

INT

and T

registers are used to control the

BURST

sweep. The AD5930 bursts each frequency for the length of
time programmed in the T

register, and outputs midscale

BURST

for the remainder of the interval time (t

register. It changes by

START

INT

– T

BURST

).

Similar to the time interval register, the burst register can have
its duration as:

• A multiple of cycles of the output frequency

• A multiple of MCLK periods

The address for this register is given in Table 14.

Rev. 0 | Page 20 of 28

To set up the AD5930 to this mode, CW/BURST (Bit D7) in the
control register must be set to 0, INT/EXT BURST (Bit D6)
must be set to 0, and INT/EXT INCR (Bit D5) must be set to 0.
Note that if the part is only operating in continuous mode, then
(Bit D7) in the control register should be set to 1.

2. External Increment, Auto-Burst Control

The time interval, t

, is set by the pulse rate on the CTRL pin.

INT

The first 0 ≥1 transition on the pin starts the sweep. Each
subsequent 0 ≥1 transition on the CTRL pin increments the
output frequency by the value programmed into the ∆F register.
For each increment interval, the AD5930 outputs each
frequency for the length of time programmed into the T

BURST

register, and outputs midscale until the CTRL pin is pulsed
again. Note that for this mode, the values programmed into Bit
D13, Bit D12, and bit D11 of the T

register are used.

BURST

AD5930

V

V

To setup the AD5930 to this mode, CW/BURST (Bit D7) in the
control register must be set to 0, INT/EXT BURST (Bit D6)
must be set to 0, and INT/EXT INCR (Bit D5) must be set to 1.
Note that if the part is only operating in continuous mode, then
Bit D7 in the control register should be set to 1.

3. External Increment, External Burst Control:

Both the increment interval (t

) and the burst interval (T

INT

BURST

are controlled by the CTRL pin. A 0 ≥ 1 transition on the CTRL
pin starts the sweep. The duration of CTRL high then dictates
the length of time the AD5930 bursts that frequency. The low
time of CTRL is the “listen” time, that is, how long the part
remains at midscale. Bringing the CTRL pin high again initiates a
frequency increment, and the pattern continues. For this mode,
the settings for Bit D13, Bit D12, and Bit D11 are ignored.

To setup the AD5930 to this mode, CW/BURST (Bit D7) in the
control register must be set to 0, INT/EXT BURST (Bit D6)
must be set to 1, and INT/EXT INCR (Bit D5) must be set to 1.
Note that if the part is only operating in continuous mode, then
Bit D7 in the control register should be set to 1.

Interrupt Pin

This function is used as an interrupt during a frequency sweep.
A low-to-high transition on this pin is sampled by the internal
MCLK, thereby resetting internal state machines, which results
in the output going to midscale.

Standby Pin

Sections of the AD5930 that are not in use can be powered
down to minimize power consumption. This is done by using
the STANDBY pin. For the optimum power savings, it is
recommended to reset the AD5930 before entering standby,
because doing so reduces the power-down current to 20 µA.

When this pin is high, the internal MCLK is disabled, and the
reference, DAC, and regulator are powered down. When in this
state, the DAC output of the AD5930 remains at its present
value as the NCO is no longer accumulating. When the device
is taken back out of standby mode, the MCLK is re-activated
and the sweep continues. To ensure correct operation for new
data, it is recommended that the device be internally reset using
a control register write or using the INTERRUPT pin, and then
restarted.

)

OUTPUTS FROM THE AD5930

The AD5930 offers a variety of outputs from the chip. The analog
outputs are available from the IOUT/IOUTB pins, and include a
sine wave and a triangle output. The digital outputs are available
from the MSBOUT pin and the SYNCOUT pin.

Analog Outputs

Sinusoidal Output

The SIN ROM is used to convert the phase information from
the frequency register into amplitude information, which results
in a sinusoidal signal at the output. To have a sinusoidal output
from the IOUT/IOUTB pins, set Bit SINE/TRI (Bit D9) to 1.

Triang l e Output

The SIN ROM can be bypassed so that the truncated digital
output from the NCO is sent to the DAC. In this case, the
output is no longer sinusoidal. The DAC produces a 10-bit
linear triangular function. To have a triangle output from the
IOUT/IOUTB pins, set Bit SINE/TRI (D9) to 0. Note that the
DAC ENABLE bit (D10) must be 1 (that is, the DAC is enabled)
when using these pins.

OUT MAX

OUT MIN

Digital Outputs

Square Wave Output from MSBOUT

The inverse of the MSB from the NCO can be output from the
AD5930. By setting the MSBOUTEN (D8) control bit to 1, the
inverted MSB of the DAC data is available at the MSBOUT pin.
This is useful as a digital clock source.

DVDD

DGND

SYNCOUT Pin

The SYNCOUT pin can be used to give the status of the sweep.
It is user selectable for the end of the sweep, or to output a 4 ×

pulse at frequency increments. The timing information

T

CLOCK

for both of these modes is shown in Figure 6 and Figure 7.

The SYNCOUT pin must be enabled before use. This is done
using Bit D2 in the control register. The output available from
this pin is then controlled by Bit D3 in the control register. See
Table 5 for more information.

p/2 5p/2 9p/2

3p/2 7p/2

Figure 34. Triangle Output

Figure 35. MSB Output

11p/ 2

05333-013

05333-012

Rev. 0 | Page 21 of 28

AD5930

APPLICATIONS

GROUNDING AND LAYOUT

The printed circuit board that houses the AD5930 should be
designed so that the analog and digital sections are separated
and confined to certain areas of the board. This facilitates the
use of ground planes that can be easily separated. A minimum
etch technique is generally best for ground planes because it
gives the best shielding. Digital and analog ground planes
should only be joined in one place. If the AD5930 is the only
device requiring an AGND to DGND connection, then the
ground planes should be connected at the AGND and DGND
pins of the AD5930. If the AD5930 is in a system where
multiple devices require AGND to DGND connections, the
connection should be made at one point only, a star ground
point that should be established as close as possible to the
AD5930.

Avoid running digital lines under the device as these couple
noise onto the die. The analog ground plane should be allowed
to run under the AD5930 to avoid noise coupling. The power
supply lines to the AD5930 should use as large a track as
possible to provide low impedance paths and reduce the effects
of glitches on the power supply line. Fast switching signals, such
as clocks, should be shielded with digital ground to avoid
radiating noise to other sections of the board. Avoid crossover
of digital and analog signals. Traces on opposite sides of the
board should run at right angles to each other. This reduces the
effects of feedthrough through the board. A microstrip
technique is by far the best, but is not always possible with a
double-sided board. In this technique, the component side of
the board is dedicated to ground planes, while signals are placed
on the other side.

Proper operation of the comparator requires good layout
strategy. The strategy must minimize the parasitic capacitance
between V

and the SIGN BIT OUT pin by adding isolation

IN

using a ground plane. For example, in a multilayered board, the

signal could be connected to the top layer and the SIGN

V

IN

BIT OUT connected to the bottom layer, so that isolation is
provided between the power and ground planes.

Interfacing to Microprocessors

The AD5930 has a standard serial interface that allows the part
to interface directly with several microprocessors. The device
uses an external serial clock to write the data/control
information into the device. The serial clock can have a
frequency of 40 MHz maximum. The serial clock can be
continuous, or it can idle high or low between write operations.
When data/control information is being written to the AD5930,
FSYNC is taken low and is held low while the 16 bits of data are
being written into the AD5930. The FSYNC signal frames the
16 bits of information being loaded into the AD5930.

AD5930 TO ADSP-21xx INTERFACE

Figure 36 shows the serial interface between the AD5930 and
the ADSP-21xx. The ADSP-21xx should be set up to operate in
the SPORT transmit alternate framing mode (TFSW = 1). The
ADSP-21xx are programmed through the SPORT control
register and should be configured as follows:

1. Internal clock operation (ISCLK = 1)

2. Active low framing (INVTFS = 1)

3. 16-bit word length (SLEN = 15)

Good decoupling is important. The analog and digital supplies
to the AD5930 are independent and separately pinned out to
minimize coupling between analog and digital sections of the
device. All analog and digital supplies should be decoupled to
AGND and DGND, respectively, with 0.1 µF ceramic capacitors
in parallel with 10 µF tantalum capacitors. To achieve the best
from the decoupling capacitors, they should be placed as close
as possible to the device, ideally right up against the device. In
systems where a common supply is used to drive both the
AVDD and DVDD of the AD5930, it is recommended that the
system’s AVDD supply be used. This supply should have the
recommended analog supply decoupling between the AVDD
pins of the AD5930 and AGND, and the recommended digital
supply decoupling capacitors between the DVDD pins and
DGND.

Rev. 0 | Page 22 of 28

4. Internal frame sync signal (ITFS = 1)

5. Generate a frame sync for each write (TFSR = 1)

Transmission is initiated by writing a word to the Tx register
after the SPORT has been enabled. The data is clocked out on
each rising edge of the serial clock and clocked into the AD5930
on the SCLK falling edge.

1

ADSP-2101/

ADSP-2103

1

ADDITIONAL PI NS OMIT TED FOR CLARITY.

Figure 36. ADSP-2101/ADSP-2103 to AD5930 Interface

1

TFS

DT

SCLK

AD5930

FSYNC

SDATA

SCLK

05333-038

AD5930

AD5930 TO 68HC11/68L11 INTERFACE

Figure 37 shows the serial interface between the AD5930 and
the 68HC11/68L11 µcontroller. The µcontroller is configured as
the master by setting bit MSTR in the SPCR to 1, which
provides a serial clock on SCK while the MOSI output drives
the serial data line SDATA. Since the µcontroller does not have
a dedicated frame sync pin, the FSYNC signal is derived from a
port line (PC7). The setup conditions for correct operation of
the interface are as follows:

1. SCK idles high between write operations (CPOL = 0)

2. Data is valid on the SCK falling edge (CPHA = 1)

a second write operation is initiated to transmit the second byte
of data. P3.3 is taken high following the completion of the
second write operation. SCLK should idle high between the two
write operations. The 80C51/80L51 outputs the serial data in an
LSB first format. The AD5930 accepts the MSB first (the 4
MSBs being the control information, the next 4 bits being the
address while the 8 LSBs contain the data when writing to a
destination register). Therefore, the transmit routine of the
80C51/80L51 must take this into account and rearrange the bits
so that the MSB is output first.

80C51/80L51

1

AD5930

1

When data is being transmitted to the AD5930, the FSYNC line
is taken low (PC7). Serial data from the 68HC11/68L11 is
transmitted in 8-bit bytes with only eight falling clock edges
occurring in the transmit cycle. Data is transmitted MSB first.
In order to load data into the AD5930, PC7 is held low after the
first 8 bits are transferred and a second serial write operation is
performed to the AD5930. Only after the second 8 bits have
been transferred should FSYNC be taken high again.

AD5930

1

05333-039

PC7

MOSI

SCK

1

FSYNC

SDATA

SCLK

68HC11/68L11

1

ADDITIONAL PI NS OMIT TED FOR CL ARITY.

Figure 37. 68HC11/68L11 to AD5930 Interface

AD5930 TO 80C51/80L51 INTERFACE

Figure 38 shows the serial interface between the AD5930 and
the 80C51/80L51 µcontroller. The µcontroller is operated in
mode 0 so that TXD of the 80C51/80L51 drives SCLK of the
AD5930, while RXD drives the serial data line SDATA. The
FSYNC signal is again derived from a bit programmable pin on
the port (P3.3 being used in the diagram). When data is to be
transmitted to the AD5930, P3.3 is taken low. The 80C51/80L51
transmits data in 8-bit bytes, thus, only eight falling SCLK edges
occur in each cycle. To load the remaining 8 bits to the AD5930,
P3.3 is held low after the first 8 bits have been transmitted, and

P3.3

RXD

TXD

1

ADDITIONAL PI NS OMIT TED FOR CLARITY.

Figure 38. 80C51/80L51 to AD5930 Interface

FSYNC

SDATA

SCLK

05333-040

AD5930 TO DSP56002 INTERFACE

Figure 39 shows the interface between the AD5930 and the
DSP56002. The DSP56002 is configured for normal mode,
asynchronous operation with a gated internal clock (SYN = 0,
GCK = 1, SCKD = 1). The frame sync pin is generated internally
(SC2 = 1), the transfers are 16 bits wide (WL1 = 1, WL0 = 0), and
the frame sync signal frames the 16 bits (FSL = 0). The frame
sync signal is available on Pin SC2, but needs to be inverted
before being applied to the AD5930. The interface to the
DSP56000/DSP56001 is similar to that of the DSP56002.

DSP56002

1

ADDITIONAL PI NS OMIT TED FOR CLARITY.

1

SC2

STD

SCK

Figure 39. DSP56002 to AD5930 Interface

FSYNC

SDATA

SCLK

AD5930

1

05333-041

Rev. 0 | Page 23 of 28

AD5930

EVALUATION BOARD

The AD5930 evaluation board allows designers to evaluate the high
performance AD5930 DDS modulator with minimum effort.

The evaluation board interfaces to the USB port of a PC. It is
possible to power the entire board off the USB port. All that is
needed to complete the evaluation of the chip is either a
spectrum analyzer or a scope.

The DDS evaluation kit includes a populated and tested
AD5930 printed circuit board. The EVAL-AD5930EB kit is
shipped with a CD-ROM that includes self-installing software.
The PC is connected to the evaluation board using the supplied
cable. The software is compatible with Microsoft® Windows®
2000 and Windows XP.

A schematic of the evaluation board is shown in Figure 40 and
Figure 41.

Using the AD5930 Evaluation Board

The AD5930 evaluation kit is a test system designed to simplify
the evaluation of the AD5930. An application note is also
available with the evaluation board and gives full information
on operating the evaluation board.

Prototyping Area

An area is available on the evaluation board for the user to add
additional circuits to the evaluation test set. Users may want to
build custom analog filters for the output or add buffers and
operational amplifiers to be used in the final application.

XO vs. External Clock

The AD5930 can operate with master clocks up to 50 MHz. A
50 MHz oscillator is included on the evaluation board.
However, this oscillator can be removed and, if required, an
external CMOS clock can be connected to the part.

Rev. 0 | Page 24 of 28

AD5930

SCHEMATIC

R1

2.2kΩ

3.3V

R0603

R2

2.2kΩ

R0603

3.3V

181920212223242545464748495051522930311615

PB0/FD0

PB1/FD1

PB2/FD2

VCC

55

3.3V

R170ΩR0603

3.3V

C12

0.1µF

C0603

3.3V

K

LED

A

02

R3

1kΩ

R0603

+

3.3V

3.3V

VCC

IN1

C7

R17

100kΩ

R0603

R4

100kΩ

R0603

C5

0.1µF

3

U3

NR

WP

SCL

4

GND

IN2

SD

C8

0.1µF

C0603

C9

10µF

RTAJ_A

+

C10

2.2µF
RTAJ_A

126

ADP3303-3.3

875

VCC

43

VCC

32

VCC

27

VCC

17

VCC

11

VCC

7

AVC C

3

0.1µF

C0603

C4

0.1µF

C0603

C3

0.1µF

C0603

C0603

C11

PB3/FD3

RESET

42

44

+

10µF

RTAJ_A

PB4/FD4

PB5/FD5

PB6/FD6

PB7/FD7

PD0/FD8

PD1/FD9

U4

*WAKEUP

CLKOUT

D–

9

54

C6

22pF

C0603

3.3V

PD3/FD11

PD2/FD10

PD4/FD12

CY7C68013-CS P

D+

8

876

5

WP

SCL

SDA

VCC

A0A1A2

PD6/FD14

PA0 /IN T0

123

PD7/FD15

PA1 /IN T1

STANDBY

VSS

4

CTL0/*F LAGA

PA2 /*S LO E

PA3 /*W U2

PA4/FIFOADR0

CTRL

INTERRUPT

24LC01

PD5/FD13

33343536373839

SCLSD A

Y1

4

5

SCL

SDA

CTL1/*FLAGB

CTL2/*FLAGC

PA5/FIFOADR1

PA6 /*P KTE ND

PA7 /*F LD/ SL CS

RDY0/*SLRD

1

40

SCLK

SDATA

FSYNC

XTALIN

XTALOUT

RDY1/*SLWR

IFCLK

RSVD

2

13

14

C36

0.1µF

C35

0.1µF

C34

0.1µF

C33

0.1µF

C32

0.1µF

C2

22pF

C0603

24MHz

C1

22pF

C0603

GND

56

GND

53

GND

41

GND

28

GND

26

GND

12

GND

10

AGND

6

3.3V

T6 T7

1

234

5

IO

D–

D+

GND

VBUS

J1

1GL2 2

GROUND LINK

USB-MINI-B

SHIELD

C30

0.1µF

C28

0.1µF

3.3V

T3 T4 T5

05333-023

Figure 40. Page 1 of EVAL-AD5930EB Schematic

Rev. 0 | Page 25 of 28

AD5930

J9

SYNCOUT

C18

C0603

SYNCOUT

THROUGH HO LE AREA

10

9

MSBOUT

STANDBY

8

SURFACE MOUNT ARE A

18

SYNCOUT

MCLK

GL1

7

GROUND LINK

11

DGND O/P DGND AGND

MCLK

IOUT

10µF

C0603

J11

IOUT

R7

200Ω

R0603

C24

C0603

FS_A

C20

+

0.1µF

RTAJ_A

T26

LK7

C17

0.1µF

C0603

IOUTB

R6

C21

C0603

J12

IOUTB

R8

200Ω

R0603

C25

C0603

6.8kΩ

R0603

C23

C0603

0.01µF

123

4

FSADJUST

5

6

CAP/2.5V DVDD AVDD

FSYNC

16

15

C0603

REF

SCLK

J10

MSBOUT

C26

C0603

MSBOUT

AVD D

19

20

IOUT

COMP

IOUTB

U1

AD5930

SDATA

CTRL

INTERRUPT

14

131217

J15

REF

C22

0.1µF

C0603

REF

T23 T24

J14–2

J14–1

AVD D

AGND

LK8L1

R16

1.5kΩ

3.3V

LK1

BA

21

BEAD

AB

AVD D

DVDD

C31

0.1µF

C0603

C29

10µF

RTAJ_A

C16

C13

10µF

RTAJ_A

C14

0.1µF
C0603

AVD D

DVDD

C19

+

C15

10µF

0.1µF

RTAJ_A

R0603

DVDD

C17

0.1µF

C0603

T25

14

7

VDD

GND

U7

50MHZ_XTAL

O/P

8

R15

R0603

LK6

AB

R9

49.9kΩ

R0603

J13

MCLK

05333-024

J2–1

DVDD

T21 T22

J2–2

DGND

479

12

S2A

SCLK

11

0.1µF

S3A

14

SDATA

C0603

ADG774

D4

8

GNDENIN

15

1

S4A

DVDD

LK2

AB

D1D2D3

S4B

13

J5

SDATA

J4

SCLK

J3

FSYNC

S3B

10

S2B

6

S1B

3

VDD

S1A

2

5

16

DVDD

FSYNC

C37

DVDD

FSYNC

SCLK

SDATA

CTRL

CTRL

LK4

AB

R10

CTRL

INT

INTERRUPT

LK5

AB

10kΩ

R0603

J6

R11

INTERRUP T

STANDBY

STANDBY

LK6

AB

10kΩ

R0603

J7

R12

10kΩ

J8

STANDBY

Figure 41. Page 2 of EVAL-AD5930EB Schematic

Rev. 0 | Page 26 of 28

AD5930

Y

OUTLINE DIMENSIONS

6.60

6.50

6.40

PIN 1

0.15

0.05

COPLANARIT

20

1

0.65

BSC

0.30

0.19

0.10

COMPLIANT TO JEDEC STANDARDS MO-153-AC

1.20 MAX

11

10

SEATING
PLANE

4.50

4.40

4.30

6.40 BSC

0.20

0.09
8°

0°

0.75

0.60

0.45

Figure 42. 20-Lead Thin Shrink Small Outline Package (TSSOP)

(RU-20)

Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Range Package Description Package Option

AD5930YRUZ
AD5930YRUZ-REEL7
EVAL-AD5930EB Evaluation Board

1

Z = Pb-free part.

1

−40°C to +105°C 20-Lead Thin Shrink Small Outline Package [TSSOP] RU-20

1

−40°C to +105°C 20-Lead Thin Shrink Small Outline Package [TSSOP] RU-20

Rev. 0 | Page 27 of 28

AD5930

NOTES

© 2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05333-0-11/05(0)

Rev. 0 | Page 28 of 28