Datasheet AD588 Datasheet (ANALOG DEVICES)

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High Precision Voltage Reference

FEATURES

Low drift: 1.5 ppm/°C
Low initial error: 1 mV
Pin programmable output
+10 V, +5 V, ±5 V tracking, −5 V

Flexible output force and sense terminals
High impedance ground sense
SOIC_W-16 and CERDIP-16 packages
MIL-STD-883-compliant versions available

GENERAL DESCRIPTION

The AD5881 represents a major advance in state-of-the-art
monolithic voltage references. Low initial error and low
temperature drift give the AD588 absolute accuracy performance
previously not available in monolithic form. The AD588 uses a
proprietary ion-implanted, buried Zener diode and laser-wafer
drift trimming of high stability thin film resistors to provide
outstanding performance.

The AD588 includes the basic reference cell and three

dditional amplifiers that provide pin programmable output

a
ranges. The amplifiers are laser trimmed for low offset and low
drift to maintain the accuracy of the reference. The amplifiers
are configured to allow Kelvin connections to the load and/or
boosters for driving long lines or high current loads, delivering
the full accuracy of the AD588 where it is required in the
application circuit.

The low initial error allows the AD588 to be used as a system
r

eference in precision measurement applications requiring
12-bit absolute accuracy. In such systems, the AD588 can provide
a known voltage for system calibration in software. The low
drift also allows compensation for the drift of other components
in a system. Manual system calibration and the cost of periodic
recalibration can, therefore, be eliminated. Furthermore, the
mechanical instability of a trimming potentiometer and the
potential for improper calibration can be eliminated by using
the AD588 in conjunction with auto calibration software.

The AD588 is available in 16-lead SOIC and CERDIP packages.
The AD588
CERDIP and are specified for 0°C to 70°C operation.

1

Protected by Patent Number 4,644,253.

JQ and AD588KQ grades are packaged in a 16-lead

, −10 V

Microcomputer

AD588

FUNCTIONAL BLOCK DIAGRAM

A3 IN

BAL
ADJ

A3 OUT

SENSE

3467

A3

A4

R6

AD588

13111281095

V

A4 IN

CT

1

14

15

2

16

A3 OUT
FORCE

A4 OUT
SENSE

A4 OUT
FORCE

+V

–V

GAIN

ADJ

R3

NOISE

REDUCTION

R

B

R2

A2

GND

SENSE

+IN

A1

R1

GND

SENSE

–IN

V

V

HIGH

R4

R5

LOW

Figure 1.

PRODUCT HIGHLIGHTS

1. The AD588 offers 12-bit absolute accuracy without any

user adjustments. Optional fine-trim connections are
provided for applications requiring higher precision. The
fine trimming does not alter the operating conditions of
the Zener or the buffer amplifiers, and so does not increase
the temperature drift.

2. O

utput noise of the AD588 is very low, typically 6 μV p-p.
A pin is provided for additional noise filtering using an
external capacitor.

3. A p

4. Pin st

recision ±5 V tracking mode with Kelvin output
connections is available with no external components.
Tracking error is less than 1 mV, and a fine trim is available
for applications requiring exact symmetry between the
+5 V and −5 V outputs.

rapping capability allows configuration of a wide
variety of outputs: ±5 V, +5 V, +10 V, −5 V, and −10 V dual
ou tp ut s or +5 V, − 5 V, +1 0 V, an d − 10 V si ng le ou tput s.

S

S

00531-001

Rev. G

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2006 Analog Devices, Inc. All rights reserved.

AD588

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TABLE OF CONTENTS

Features.............................................................................................. 1

Temperature Performance......................................................... 10

General Description......................................................................... 1

Functional Block Diagram ..............................................................1

Product Highlights........................................................................... 1

Revision History ...............................................................................2

Specifications..................................................................................... 3

Absolute Maximum Ratings............................................................ 4

ESD Caution.................................................................................. 4

Pin Configuration and Function Descriptions............................. 5

Theory of Operation ........................................................................ 6

Applications....................................................................................... 7

Calibration..................................................................................... 7

Noise Performance and Reduction ............................................9

Turn-On Time ............................................................................ 10

REVISION HISTORY

Kelvin Connections.................................................................... 11

Dynamic Performance............................................................... 13

Using the AD588 with Converters............................................... 15

AD7535 14-Bit Digital-to-Analog Converter......................... 15

AD569 16-Bit Digital-to-Analog Converter........................... 15

Substituting for Internal References ........................................ 16

AD574A 12-Bit Analog-to-Digital Converter........................ 16

Resistance Temperature Detector (RTD) Excitation............. 16

Boosted Precision Current Source........................................... 17

Bridge Driver Circuits ............................................................... 17

Outline Dimensions....................................................................... 19

Ordering Guide .......................................................................... 19

6/06—Rev. F to Rev. G

Changes to Table 5............................................................................ 7

Updated Outline Dimensions....................................................... 19

3/06—Rev. E to Rev. F

aced Figure 5 ............................................................................. 8

Repl

Updated Outline Dimensions....................................................... 19

11/05—Rev. D to Rev. E

pdated Format..................................................................Universal

U

Added SOIC Version..........................................................Universal

Changes to Pin 14 in Figures.............................................Universal

Changes to Pin 9 and Pin 10 in Figures...........................Universal

Changes to Specifications Section.................................................. 3

Added Table 3.................................................................................... 4

Added Pin Configuration and Function Descriptions Section.. 5

Added Table 4.................................................................................... 5

Changes to Grade in Reference and in Figure 12....................... 11

Updated Outline Dimensions....................................................... 19

Changes to Ordering Guide.......................................................... 19

2/03—Rev. C to Rev. D

A

dded KQ Model and Deleted SQ and TQ Models ......Universal

Changes to General Description .....................................................1

Change to Product Highlights.........................................................1

Changes to Specifications.................................................................2

Change to Ordering Guide...............................................................3

Updated Outline Dimensions....................................................... 15

10/02—Rev. B to Rev. C

hanges to General Description .....................................................1

C

Changes to Specifications.................................................................2

Changes to Ordering Guide.............................................................3

Changes to Table 1.............................................................................5

Deleted Figure 10c.............................................................................7

Outline Dimensions Updated....................................................... 15

Rev. G | Page 2 of 20

AD588

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SPECIFICATIONS

Typical @ 25°C, 10 V output, VS = ±15 V, unless otherwise noted.

Specifications shown in boldface are tested on all production units at final electrical test. Results from those tests are used to

calculate
outgoing quality levels. All minimum and maximum specifications are guaranteed, although only those shown in boldface are tested on
all production units.

Table 1.

AD588JQ/AQ AD588BQ/KQ AD588ARWZ

Parameter

OUTPUT VOLTAGE ERROR

+10 V, −10 V Outputs
+5 V, −5 V Outputs

±5 V TRACKING MODE

Symmetry Error

OUTPUT VOLTAGE DRIFT

0°C to 70°C (J, K, B) ±2

−25°C to +85°C (A, B)

GAIN ADJ AND BAL ADJ2

Trim Range ±4
Input Resistance 150

LINE REGULATION

T

LOAD REGULATION

T

SUPPLY CURRENT

T
Power Dissipation 180

1

3

to T

MIN

MAX

to T

MIN

MAX

+10 V Output, 0 mA < I

−10 V Output, −10 mA < I

to T

MIN

6

MAX

Min Typ Max Min Typ Max Min Typ Max Unit

< 10 mA

OUT

< 0 mA

OUT

±3 −1 +1 −5 +5

±3 −1 +1 −5 +5

±1.5 ±0.75

±3
±3

±200

±4
150

±1.5
±3

±200

±50 ±50
±50 ±50

10
300

6
180

10
300

±2

±4

±1.5

±3
±3

150 kΩ

6
180

±200

±50
±50

10
300

mV
mV

mV

ppm/°C
ppm/°C

mV

μV/V

μV/mA
μV/mA

mA
mW

OUTPUT NOISE (Any Output)

0.1 Hz to 10 Hz 6 6 6 μV p-p

Spectral Density, 100 Hz 100 100 100 nV/√Hz
LONG-TERM STABILITY (@ 25°C) 15 15 15 ppm/1000 hr
BUFFER AMPLIFIERS

Offset Voltage 100 10 100 μV

Offset Voltage Drift 1 1 1 μV/°C

Bias Current 20 20 20 nA

Open-Loop Gain 110 110 110 dB

Output Current (A3, A4) −10 +10 −10 +10 −10 +10 mA

Common-Mode Rejection (A3, A4)

VCM = 1 V p-p 100 100 100 dB

Short Circuit Current 50 50 50 mA
TEMPERATURE RANGE

Specified Performance

J, K Grades 0 70 0 70 °C
A, B Grades −25 +85 −25 +85 −25 +85 °C

1

Specifications tested using ±5 V configuration, unless otherwise indicated. See Figure 4 through Figure 6 for output configurations at +10 V, −10 V, +5 V, −5 V

and ±5 V.

2

Gain and balance adjustments guaranteed capable of trimming output voltage error and symmetry error to zero.

3

For ±10 V output, ±VS can be as low as ±12 V. See Table 3 for test conditions at various voltages.

Rev. G | Page 3 of 20

AD588

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ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

+VS to −VS 36 V
Power Dissipation (25°C) 600 mW
Storage Temperature Range −65°C to +150°C
Lead Temperature (Soldering 10 sec) 300°C
Package Thermal Resistance (θ
Output Protection

Table 3. Test Conditions

Voltage Conditions

+10 V Output −VS = –15 V, +13.5 V ≤ +VS ≤ +18 V

−18 V ≤ –VS ≤ –13.5 V, +VS = +15 V −10 V Output
±5 V Output +VS = +18 V, –VS = –18 V
+V

= +10.8 V, −VS = −10.8 V

S

) 90°C/25°C/W

JA/θJC

All outputs safe if
shor

ted to ground

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

Rev. G | Page 4 of 20

AD588

A

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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

3 OUT FORCE

+V

A3 OUT SENSE

A3 IN

GAIN ADJ

V

HIGH

NOISE

REDUCTION

V

LOW

1

2

S

3

4

5

6

7

8

AD588

TOP VIEW

(Not to Scale)

16

–V

S

15

A4 OUT F ORCE

14

A4 OUT SENSE

13

A4 IN

12

BAL ADJ

11

V

CT

10

GND SENSE –IN

9

GND SENSE +IN

00531-002

Figure 2. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description

1 A3 OUT FORCE Output from Buffering Amplifier 3 with Kelvin Force. Connect to Pin 3.
2 +VS Positive Power Supply.
3 A3 OUT SENSE
4 A3 IN
5 GAIN ADJ
6 V

Unbuffered Reference High Output.

HIGH

7 NOISE REDUCTION

Output from Buffering Amplifier 3 with Kelvin Sense. Connect to Pin 1.
+ Input to Amplifier 3. Connect to V

HIGH

, Pin 6.

Reference Gain Adjustment for Calibration. See the Calibration section.

Noise Filtering Pin. Connect external 1 μF capacitor to ground to reduce the output noise

(see the Noise Performance and Reduction section). Can be left open.
8 V
9 GND SENSE POSITIVE IN
10 GND SENSE NEGATIVE IN
11 V
12 BAL ADJ
13 A4 IN
14 A4 OUT SENSE
15 A4 OUT FORCE
16 −V

Unbuffered Reference Low Output.

LOW

+ Input to the Ground Sense Amplifier.

− Input to the Ground Sense Amplifier.

Center Tap Voltage used for Calibration. See the Calibration section.

CT

Reference Centering Adjustment for Calibration. See the Calibration section.

+ Input to Amplifier 4. Connect to V

LOW

, Pin 8.
Output of Buffering Amplifier 4 with Kelvin Sense. Connect to Pin 15.
Output of Buffering Amplifier 4 with Kelvin Force. Connect to Pin 14.

Negative Power Supply.

S

Rev. G | Page 5 of 20

AD588

A

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THEORY OF OPERATION

The AD588 consists of a buried Zener diode reference,

mplifiers used to provide pin programmable output ranges,

a
and associated thin-film resistors, as shown in Figure 3. The
t

emperature compensation circuitry provides the device with

a temperature coefficient of 1.5 ppm/°C or less.

Amplifier A1 performs several functions. A1 primarily acts to
a

mplify the Zener voltage from 6.5 V to the required 10 V
output. In addition, A1 provides for external adjustment of the
10 V output through Pin 5, GAIN ADJ. Using the bias
compensation resistor between the Zener output and the
noninverting input to A1, a capacitor can be added at the
NOISE REDUCTION pin (Pin 7) to form a low-pass filter and
reduce the noise contribution of the Zener to the circuit. Two
matched 10 kΩ nominal thin-film resistors (R4 and R5) divide
the 10 V output in half. Pin V

(Pin 11) provides access to the

CT

center of the voltage span and BAL ADJ (Pin 12) can be used
for fine adjustment of this division.

NOISE

REDUCTION

V

HIGH

Ground sensing for the circuit is provided by Amplifier A2. The
noninverting input (Pin 9) senses the system ground, which is
transferred to the point on the circuit where the inverting input
(Pin 10) is connected. This can be Pin 6, Pin 8, or Pin 11. The
output of A2 drives Pin 8 to the appropriate voltage. Thus, if
Pin 10 is connected to Pin 8, the V

pin is the same voltage as

LOW

the system ground. Alternatively, if Pin 10 is connected to the
V

pin, it is a ground; and Pin 6 and Pin 8 are +5 V and −5 V,

CT

respectively.

Amplifier A3 and Amplifier A4 are internally compensated and
a

re used to buffer the voltages at Pin 6, Pin 8, and Pin 11, as well
as to provide a full Kelvin output. Thus, the AD588 has a full
Kelvin capability by providing the means to sense a system
ground and provide forced and sensed outputs referenced to
that ground.

Note that both positive and negative supplies are required for
o

peration of the AD588.

3 OUT

A3 IN

SENSE

3467

1

14

15

2

16

A3 OUT
FORCE

A4 OUT
SENSE

A4 OUT
FORCE

+V

S

–V

S

00531-003

GAIN

ADJ

R

B

A1

R1

R2

R3

A2

GND

GND

SENSE

SENSE

+IN

–IN

Figure 3. AD588 Functional Block Diagram

R4

R5

R6

BAL
ADJ

V

CT

V

LOW

A3

A4

AD588

13111281095

A4 IN

Rev. G | Page 6 of 20

AD588

www.BDTIC.com/ADI

APPLICATIONS

The AD588 can be configured to provide +10 V and –10 V
reference outputs, as shown in Figure 4 and Figure 6, respectively.

t can also be used to provide +5 V, −5 V, or a 5 V tracking

I
reference, as shown in

in connections for each output range. In each case, Pin 9 is

p
connected to system ground, and power is applied to Pin 2
and Pin 16.

The architecture of the AD588 provides ground sense and

committed output buffer amplifiers that offer the user a great

un
deal of functional flexibility. The AD588 is specified and tested
in the configurations shown in Figure 6. The user can choose to
tak

e advantage of the many other configuration options available
with the AD588. However, performance in these configurations
is not guaranteed to meet the extremely stringent data sheet
specifications.

As indicated in Table 5, a +5 V buffered output can be provided
usin

g Amplifier A4 in the +10 V configuration (Figure 4).
A −5 V b
in the −10 V configuration (Figure 6). Specifications are not
gua
tions. Performance is similar to that specified for the +10 V or

−10 V outputs.

As indicated in Table 5, unbuffered outputs are available at
Pin 6, Pin 8,
impairs circuit performance.

uffered output can be provided using Amplifier A3

ranteed for the +5 V or −5 V outputs in these configura-

and Pin 11. Loading of these unbuffered outputs

Figure 5. Tabl e 5 details the appropriate

Amplifier A3 and Amplifier A4 can be used interchangeably.

owever, the AD588 is tested (and the specifications are

H
guaranteed) with the amplifiers connected, as indicated in
Figure 4 and Tabl e 5. When either A3 or A4 is unused, its

utput force and sense pins should be connected and the input

o
tied to ground.

Two outputs of the same voltage can be obtained by connecting
b

oth A3 and A4 to the appropriate unbuffered output on Pin 6,
Pin 8, or Pin 11. Performance in these dual-output configura­tions typically meets data sheet specifications.

CALIBRATION

Generally, the AD588 meets the requirements of a precision
system without additional adjustment. Initial output voltage
error of 1 mV and output noise specs of 10 μV p-p allow for
accuracies of 12 bits to 16 bits. However, in applications where
an even greater level of accuracy is required, additional calibra­tion may be called for. Provision for trimming has been made
through the use of the GAIN ADJ and BAL ADJ pins (Pin 5 and
Pin 12, respectively).

The AD588 provides a precision 10 V span with a center tap

) that is used with the buffer and ground sense amplifiers to

(V

CT

achieve the voltage output configurations in Tabl e 5. GAIN ADJ

nd BAL ADJ can be used in any of these configurations to trim

a
the magnitude of the span voltage and the position of the center
tap within the span. The gain adjust should be performed first.
Although the trims are not interactive within the device, the
gain trim moves the balance trim point as it changes the
magnitude of the span.

Table 5. Pin Connections

Connect Pin 10
to

Range

+10 V 8 8 11 6 11 to 13, 14 to 15, 15
6 to 4, and 3 to 1 1

−5 V or +5 V 11 8 11 6 8 to 13, 14 to 15, 15
6 to 4, and 3 to 1 1

−10 V 6 8 11 6 8 to 13, 14 to 15, 15
11 to 4, and 3 to 1 1
+5 V 11 6 6 to 4 and 3 to 1 1

−5 V 11 8 8 to 13 and 14 to 15 15

1

Unbuffered outputs should not be loaded.

Pin

Unbuffered

−10 V −5 V 0 V +5 V +10 V

1

Output on Pins

Rev. G | Page 7 of 20

Buffered Output
Connections

Buffered Output on Pins

−10 V −5 V 0 V +5 V +10 V

AD588

www.BDTIC.com/ADI

AD588

R6

AD588

R6

3467

39kΩ

+15V

A3

A4

+V

S

–V

S

A3

1

14

15

A4

+V

2

S

–V

16

S

13111281095

0.1µF

0.1µF

0.1µF

0.1µF

+5V

–5V

+15V

SYSTEM
GROUND

–15V

–5V

–10V

+15V

SYSTEM
GROUND

–15V

Figure 5 shows gain and balance trims in a +5 V and −5 V
tracking configuration. A 100 kΩ, 20-turn potentiometer
is used for each trim. The potentiometer for gain trim is
connected between Pin 6 (V

) and Pin 8 (V

HIGH

) with the

LOW

wiper connected to Pin 5 (GAIN ADJ). The potentiometer is
adjusted to produce exactly 10 V between Pin 1 and Pin 15, the
amplifier outputs. The balance potentiometer, also connected
between Pin 6 and Pin 8 with the wiper to Pin 12 (BAL ADJ), is
then adjusted to center the span from +5 V to −5 V.

Trimming in other configurations works in exactly the same
ma

nner. When producing +10 V and +5 V, GAIN ADJ is used
to trim +10 V and BAL ADJ is used to trim +5 V. In the −10 V
and −5 V configuration, GAIN ADJ is again used to trim the
magnitude of the span, −10 V, while BAL ADJ is used to trim
the center tap, −5 V.

Trimming the AD588 introduces no additional errors over
t

emperature, so precision potentiometers are not required. For
single-output voltage ranges, or in cases when balance adjust is
not required, Pin 12 should be connected to Pin 11. If gain
adjust is not required, Pin 5 should be left floating.

In single output configurations, GAIN ADJ is used to trim
outputs utilizing the full span (+10 V or −10 V), while BAL ADJ
is used to trim outputs using half the span (+5 V or −5 V).

Input impedance on both the GAIN ADJ and BAL ADJ pins is
approximately 150 kΩ. The GAIN ADJ trim network effectively
attenuates the 10 V across the trim potentiometer by a factor of
about 1500 to provide a trim range of −3.5 mV to +7.5 mV with
a resolution of approximately 550 V/turn (20-turn potentiometer).
The BAL ADJ trim network attenuates the trim voltage by a
factor of about 1400, providing a trim range of ±4.5 mV with
resolution of 450 μV/turn.

7

R

B

A1

R1

R2

R3

A2

R4

R5

346

0.1µF

0.1µF

+10V

+5V

+15V

SYSTEM
GROUND

–15V

A3

1

14

15

A4

+V

2

R6

13111281095

AD588

–V

S

16

S

R3

100kΩ

20T

GAIN ADJUST

0.1µF

0.1µF

R3

1µF

R

B

R2

SYSTEM

GROUND

R

B

SYSTEM

GROUND

NOISE
REDUCTIO N

A1

R1

A2

100kΩ

20T

BALANCE

ADJUST

R4

R5

Figure 5. +5 V and −5 V Outputs

NOISE
REDUCTION

A1

R1

R2

A2

R4

R5

Figure 6. –10 V Output

00531-005

00531-006

SYSTEM

GROUND

Figure 4. +10 V Output

00531-004

Rev. G | Page 8 of 20

AD588

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NOISE PERFORMANCE AND REDUCTION

The noise generated by the AD588 is typically less than
6 μV p-p over the 0.1 Hz to 10 Hz band. Noise in a 1 MHz
bandwidth is approximately 600 μV p-p. The dominant source
of this noise is the buried Zener, which contributes approx­imately 100 nV/√Hz. In comparison, the op amp’s contribution
is negligible.
typ

ical AD588.

Figure 7 shows the 0.1 Hz to 10 Hz noise of a

1µV

If further noise reduction is desired, an optional capacitor, C
can be added between the NOISE REDUCTION pin and
ground, as shown in Figure 5.

This forms a low-pass filter with the 4 kΩ R
the Zener cell. A 1 μF capacitor has a 3 dB point at 40 Hz and
reduces the high frequency noise (to 1 MHz) to about
200 μV p-p.
both with and without a 1 μF capacitor.

Note that a second capacitor is needed in order to implement

e noise reduction feature when using the AD588 in the −10 V

th
mode (Figure 6). The noise reduction capacitor is limited to

0.1 μF maxim

Figure 8 shows the 1 MHz noise of a typical AD588

um in this mode.

on the output of

B

,

N

00531-007

Figure 7. 0.1 Hz to 10 Hz Noise (0.1 Hz to 10 Hz BPF

CN = 1mF

NO C

N

Figure 8. Effect of 1 μF Noise Redu

wit

h Gain of 1000 Applied)

ction Capacitor on Broadband Noise

00531-008

Rev. G | Page 9 of 20

AD588

V

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TURN-ON TIME

Upon application of power (cold start), the time required for
the output voltage to reach its final value within a specified
error band is the turn-on settling time. Two components
normally associated with this are the time for active circuits to
settle and the time for thermal gradients on the chip to stabilize.

Figure 9 and Figure 10 show the turn-on characteristics of the
AD588. The s

ettling is about 600 μs. Note the absence of any
thermal tails when the horizontal scale is expanded to 2 ms/cm
in

Figure 10.

+V

S

V

OUT

Output turn-on time is modified when an external noise
reduction capacitor is used. When present, this capacitor
presents an additional load to the internal Zener diode current
source, resulting in a somewhat longer turn-on time. In the case
of a 1 μF capacitor, the initial turn-on time is approximately
60 ms (see

Figure 11).

Note that if the noise reduction feature is used in the ±5 V

nfiguration, a 39 kΩ resistor between Pin 6 and Pin 2 is

co
required for proper startup.

+V

S

–V

S

V

OUT

+V

OUT

Figure 9. Electrical Turn-On

S

Figure 10. Extended Time Scale Turn-On

0531-011

00531-009

Figure 11. Turn-On with CN = 1 μF

TEMPERATURE PERFORMANCE

The AD588 is designed for precision reference applications where
temperature performance is critical. Extensive temperature testing
ensures that the device’s high level of performance is maintained
over the operating temperature range.

Figure 12 shows typical output temperature drift for the
AD588B
Figure 12 is bounded on the sides by the operating temperature

00531-010

ext
minimum output voltages measured over the operating
temperature range. The slope of the diagonal drawn from the
lower left corner of the box determines the performance grade
of the device.

Q and illustrates the test methodology. The box in

remes and on top and bottom by the maximum and

Rev. G | Page 10 of 20

AD588

V

– V

V

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MAX

SLOPE = T.C. =

10.002

V

MAX

10.001

OUTPUT (Volts)

V

MIN

10.000

(T

MAX

10.0013V – 10.00025V

(85°C – –25°C) × 10 × 10

= 0.95ppm/°C

–35 –15 5 25 45 65 85

TEMPERATURE (°C)

V

MIN

– T

MIN

MIN

) × 10 × 1

–4

–4

V

00531-012

MAX

Figure 12. Typical AD588BQ Temperature Drift

Each AD588 A and B grade unit is tested at −25°C, 0°C, +25°C,
+50°C, +70°C, and +85°C. This

approach ensures that the
variations of output voltage that occur as the temperature
changes within the specified range is contained within a box
whose diagonal has a slope equal to the maximum specified
drift. The position of the box on the vertical scale changes from
device to device as initial error and the shape of the curve vary.
Maximum height of the box for the appropriate temperature
range is shown in

Figure 13. Duplication of these results
requires a combination of high accuracy and stable temperature
control in a test system. Evaluation of the AD588 produces a
curve similar to that in

Figure 12, but output readings may vary,

depending on the test methods and equipment utilized.

DEVICE
GRADE

AD588JQ

AD588JQ

AD588JQ

AD588JQ

AD588JQ

AD588JQ

MAXIMUM OUT PUT CHANGE (mV)

0°C TO +70° C

2.10

1.05

1.40 (TYP)

1.05

–25°C TO +85° C –55°C TO +125°C

3.30

3.30

10.80

7.20

Figure 13. Maximum Output Change—mV

00531-013

KELVIN CONNECTIONS

Force and sense connections, also referred to as Kelvin
connections, offer a convenient method of eliminating the
effects of voltage drops in circuit wires. As seen in Figure 14,
t

he load current and wire resistance produce an error

(V

= R × IL) at the load.

ERROR

The Kelvin connection of Figure 14 overcomes the problem by
in

cluding the wire resistance within the forcing loop of the
amplifier and sensing the load voltage. The amplifier corrects
for any errors in the load voltage. In the circuit shown, the
output of the amplifier would actually be at 10 V + V
the voltage at the load would be the desired 10 V.

The AD588 has three amplifiers that can be used to implement
Kelvin connections. Amplifier A2 is dedicated to the ground
force-sense function, while uncommitted Amplifier A3 and
Amplifier A4 are free for other force-sense chores.

R

I = 0

V = 10V – RI

R

+

10

–

R

LOAD

I

L

R

L

I = 0

V = 10V – RI

I

L

L

Figure 14. Advantage of Kelvin Connection

In some single-output applications, one amplifier can be
un

used. In such cases, the unused amplifier should be
connected as a unity-gain follower (force and sense pin tied
together), and the input should be connected to ground.

An unused amplifier section can be used for other circuit
functions, as well. Figure 15 through Figure 19 show the typical

erformance of A3 and A4.

p

100

80

GAIN

60

ERROR

V = 10V

R

LOAD

, and

0

–30

–60

00531-014

40

20

OPEN-LOOP GAIN (dB)

0

–20

10 10M100

PHASE

Figure 15. Open-Loop Frequency Resp

Rev. G | Page 11 of 20

1k 10k 100k 1M

FREQUENCY (Hz)

onse (A3, A4)

–90

–120

–150

–180

PHASE (Degrees)

00531-015

AD588

√

www.BDTIC.com/ADI

110

100

V

= ±15V WIT H

S

1V p-p SINE WAVE

+SUPPLY

80

110

100

VS = ±15V

= 1V p-p +25°C

V

CM

80

60

40

POWER SUPPLY REJECTIO N (dB)

20

10

10 10M100

Figure 16. Power Supply Rejection vs.

–SUPPLY

1k 10k 100k 1M

FREQUENCY (Hz)

Frequency (A3, A4)

Figure 17. Unity-Gain Follower Pulse Response (Large Signal)

60

CMRR (dB)

40

20

0

10 10M100

00531-016

1k 10k 100k 1M

FREQUENCY ( Hz)

00531-019

Figure 19. Common-Mode Rejection vs. Frequency (A3, A4)

100

90

Hz)

80

70

60

50

40

30

20

NOISE SPECT RAL DENSITY (n V/

10

00531-017

0

1 10k10

100 1k

FREQUENCY ( Hz)

00531-020

Figure 20. Input Noise Voltage Spectral Density

00531-018

Figure 18. Unity-Gain Follower Pulse Response (Small Signal)

Rev. G | Page 12 of 20

AD588

C

V

www.BDTIC.com/ADI

DYNAMIC PERFORMANCE

The output buffer amplifiers (A3 and A4) are designed to
provide the AD588 with static and dynamic load regulation
superior to less complete references. Many analog-to-digital and
digital-to-analog converters present transient current loads to
the reference, and poor reference response can degrade the
converter’s performance.
characteristics of the AD588 output amplifier driving a 0 mA
to 10 mA load.

V

OUT

Figure 21 and Figure 22 display the

A3 OR A4

V

1kΩ

10V
0V

OUT

00531-021

I

10V

L

V

L

Figure 21. Transient Load Test Circuit

In some applications, a varying load can be both resistive and
capacitive in nature or can be connected to the AD588 by a long
capacitive cable.

mplifier characteristics driving a 1000 pF, 0 mA to 10 mA load.

a

Figure 25. Capacitive Load Transient Response Test Circuit

CL = 0

= 1000pF

L

Figure 25 and Figure 26 display the output

A3 OR A4

V

C

L

10V

V

L

1000pF

V

L

Figure 26. Output Response with Capacitive Load

1kΩ

10V
0V

OUT

00531-025

00531-026

V

L

00531-022

Figure 22. Large-Scale Transient Response

Figure 23 and Figure 24 display the output amplifier
characteristics driving a 5 mA to 10 mA load, a common
situation found when the reference is shared among multiple
converters or is used to provide a bipolar offset current.

A3 OR A4

V

I

2kΩ

L

10V

V

L

0V

10V

+

–

Figure 23. Transient and Constant Load Test Circuit

V

OUT

1mV/CM

V

OUT

200mV/CM

V

L

Figure 24. Transient Response 5 mA to10 mA Load

2kΩ

OUT

0531-023

Figure 27 and Figure 28 display the crosstalk between output
amplifiers. The top trace shows the output of A4, dc-coupled
and offset by 10 V, while the output of A3 is subjected to a 0 mA
to 10 mA load current step. The transient at A4 settles in about
1 μs, and the load-induced offset is about 100 μV.

00531-024

Rev. G | Page 13 of 20

OUT

V

V

OUT

V

L

1kΩ

10V
0V

A3

+

10V

–

00531-027

+

10V
–

A4

Figure 27. Load Crosstalk Test Circuit

L

00531-028

Figure 28. Load Crosstalk

AD588

Ω

www.BDTIC.com/ADI

Attempts to drive a large capacitive load (in excess of 1000 pF)
can result in ringing or oscillation, as shown in the step response

Figure 29). This is due to the additional pole formed by

photo (
t

he load capacitance and the output impedance of the amplifier,

which consumes phase margin.

V

IN

V

OUT

00531-029

Figure 29. Output Amplif

10k

1µF

ier Step Response, C

= 1 μF

L

The recommended method of driving capacitive loads of this
ma

gnitude is shown in Figure 30. The 150 Ω resistor isolates the

pacitive load from the output stage, while the 10 kΩ resistor

ca
provides a dc feedback path and preserves the output accuracy.
The 1 μF capacitor provides a high frequency feedback loop.
The performance of this circuit is shown in

V

IN

V

OUT

Figure 31. Output Amplifier Step Response Using Figure 30 Compensation

Figure 31.

00531-031

150Ω

+

V

IN

–

Figure 30. Compensation for Capacitive Loads

C
1µF

V

OUT

L

00531-030

Rev. G | Page 14 of 20

AD588

V

V

www.BDTIC.com/ADI

USING THE AD588 WITH CONVERTERS

The AD588 is an ideal reference for a wide variety of analog-to­digital and digital-to-analog converters. Several representative
examples follow.

AD7535 14-BIT DIGITAL-TO-ANALOG CONVERTER

High resolution CMOS digital-to-analog converters require a
reference voltage of high precision to maintain rated accuracy.
The combination of the AD588 and AD7535 takes advantage of
the initial accuracy, drift, and full Kelvin output capability of the
AD588, as well as the resolution, monotonicity, and accuracy of the
AD7535 to produce a subsystem with outstanding characteristics
(see

Figure 32).

AD588

R6

A3 + IN

A3

A2

A4

346

A3

A4

131112

Figure 32. AD588/AD7535 Connections

A

3

OUT

A3 – IN

A

– IN

2

A

+ IN

2

– IN

A

4

OUT

A

4

3

1

+5V

3

2

12

V

CT

11

10

9

–5V

14

16

15

15

7

R

B

A1

R1

R2

R3

A2

1095

216 64

R4

R5

8

V

H

A1

10kΩ

10kΩ

AD588

14

15

16

+V

REF

FORCE

+V

REF

SENSE

–V

REF

SENSE

–V

REF

FORCE

1

2

AD569 16-BIT DIGITAL-TO-ANALOG CONVERTER

Another application that fully utilizes the capabilities of the AD588

upplying a reference for the AD569, as shown in Figure 33.

is s

plifier A2 senses system common and forces V

Am
value, producing +5 V and −5 V at Pin 6 and Pin 8, respectively.
Amplifier A3 and Amplifier A4 buffer these voltages out to the
appropriate reference force-sense pins of the AD569. The full
Kelvin scheme eliminates the effect of the circuit traces or wires and
the wire bonds of the AD588 and AD569 themselves, which would
otherwise degrade system performance.

LS

INPUT

REGISTER

AD569

DD

AD7535

DGNDDB0DB13

17

V

V

OUT

–5V TO
+5V

SS

V

REFS

+10V

+V

–V

AGNDS

AGNDF

S

S

N.C.

28 26

1

14-BIT DAC

V

REF

2

5

6

REGIS TER

+V

S

1

S

S

E

E

L

G

E

M

C

E

T

N

O

T

R

14

DAC REGISTER

MS

INPUT

821727

+12
–12V

–V

S

28

S
E

L

T

E

A

C

P

T
O
R

to assume this

CT

3

R

FS

4

I

OUT

23

LDAC

24

CSLSB

22

CSMSB

25

WR

00531-032

V

L

813

A

+ IN

4

18

GND

13 14 12 9 7 4 19 22 24 27 8 23

CS

8 MSBs 8 LSBs

LDAC

DB15

LATCHES

HBE LBE

DB0

Figure 33. High Accuracy ±5 V Tracking Reference for AD569

Rev. G | Page 15 of 20

00531-033

AD588

www.BDTIC.com/ADI

SUBSTITUTING FOR INTERNAL REFERENCES

Many converters include built-in references. Unfortunately,
such references are the major source of drift in these converters.
By using a more stable external reference like the AD588, drift
performance can be improved dramatically.

AD574A 12-BIT ANALOG-TO-DIGITAL CONVERTER

The AD574A is specified for gain drift from 10 ppm/°C to
50 ppm/°C (depending on grade), using its on-chip reference.
The reference contributes typically 75% of this drift. Using an
AD588 as a reference source can improve the total drift by a
factor of 3 to 4.

Using this combination can result in apparent increases in
full-scale error due to the difference between the on-board
reference, by which the device is laser-trimmed, and the
external reference, with which the device is actually applied.
The on-board reference is specified to be 10 V ± 100 mV, while
the external reference is specified to be 10 V ± 1 mV. This may
result in up to 101 mV of apparent full-scale error beyond the
±25 mV specified AD574 gain error. External Resistor R2 and
Resistor R3 allow this error to be nulled. Their contribution to
full-scale drift is negligible.

The high output drive capability allows the AD588 to drive up

o six converters in a multiconverter system. All converters have

t
gain errors that track to better than ±5 ppm/°C.

RESISTANCE TEMPERATURE DETECTOR (RTD) EXCITATION

The RTD is a circuit element whose resistance is characterized

y a positive temperature coefficient. A measurement of

b
resistance indicates the measured temperature. Unfortunately,
the resistance of the wires leading to the RTD often adds error
to this measurement. The 4-wire ohms measurement overcomes
this problem. This method uses two wires to bring an excitation
current to the RTD and two additional wires to tap off the resulting
RTD voltage. If these additional two wires go to a high input
impedance measurement circuit, the effect of their resistance is
negligible. They therefore transmit the true RTD voltage.

R

I

EXC

R

RTD

Figure 34. 4-Wire Ohms Measurement

I = 0

R

R

I = 0

+

α R

V

OUT

RTD

–

00531-034

HIGH

BITS

MIDDLE

BITS

LOW
BITS

+5V

+15V

–15V

DIG

COM

28

27

24

23

20

19

16

1

7

11

15

00531-035

2

12√8STS

3

CS

4

AO

5

R1

50Ω

R/C

6

CE

10

REF IN

8

REF OUT

12

BIPP OFF

13

10V

14

20V

9

ANA COM

AD574A

IN

IN

7643

R

B

A1

R1

R2

R3

A2

AD588

R4

R5

R6

A3

A4

13111281095

1

14

15

2

16

+V

–V

20 TURN

V

10V

S

S

R3

500Ω

IN

R2

61.9Ω

Figure 35. AD588/AD574A Connections

Rev. E | Page 16 of 20

AD588

www.BDTIC.com/ADI

A practical consideration when using the 4-wire ohms
technique with an RTD is the self-heating effect that the
excitation current has on the temperature of the RTD. The
designer must choose the smallest practical excitation current
that still gives the desired resolution. RTD manufacturers
usually specify the self-heating effect of each of their models or
types of RTDs.

Figure 36 shows an AD588 providing the precision excitation

urrent for a 100 Ω RTD. The small excitation current of 1 mA

c
dissipates a mere 0.1 mW of power in the RTD.

BOOSTED PRECISION CURRENT SOURCE

In the RTD current-source application, the load current is limited
to ±10 mA by the output drive capability of Amplifier A3. In the
event that more drive current is needed, a series-pass transistor
can be inserted inside the feedback loop to provide higher
current. Accuracy and drift performance are unaffected by the
pass transistor.

BRIDGE DRIVER CIRCUITS

The Wheatstone bridge is a common transducer. In its simplest

rm, a bridge consists of four two-terminal elements connected

fo
to form a quadrilateral, a source of excitation connected along
one of the diagonals and a detector comprising the other
diagonal.

Figure 38 shows a simple bridge driven from a unipolar

xcitation supply. EO, a differential voltage, is proportional to

e
the deviation of the element from the initial bridge values.
Unfortunately, this bridge output voltage is riding on a
common-mode voltage equal to approximately V
processing of this signal may necessarily be limited to high
common-mode rejection techniques, such as instrumentation
or isolation amplifiers.

Figure 39 shows the same bridge transducer, this time driven
f

rom a pair of bipolar supplies. This configuration ideally
eliminates the common-mode voltage and relaxes the
restrictions on any processing elements that follow.

/2. Further

IN

R4

12

AD588

R6

11

3467

A3

A4

13

7643

R

B

A1

R4

R1

R2

R3

A2

59108

R5

12

AD588

R6

11 13

1

A3

14

15

A4

+V

2

16

–V

RTD = Ω K4515

0.24°C/mW SELF- HEATING

R
VISHAY S102C

OR SIMILAR

RC = 10kΩ

100Ω

S

S

GROUND

C

–15V

1.0mA

0.01%

OR

R

B

A1

R1

+

V

OUT

–

00531-036

R2

R3

A2

R5

81095

Figure 36. Precision Current Source for RTD Figure 37. Boosted Precision Current Source

R4

+

V

IN

–

R1

R3

+–

E

O

R2

00531-038

+

V

V

R4

1

–

+

2

–

+–

E

O

R1

Figure 38. Bridge Transducer Excitation—Unipolar Drive Figure 39. Bridge Transducer Excitation—Bipolar Drive

V

CC

220Ω

1

Q

1

14

15

10V

IL =

+V

2

16

–V

R3

R2

00531-039

S

S

LIMITED BY
Q
POWER
DISSIPATION

LOAD

AND R

1

R

C

C

00531-037

Rev. G | Page 17 of 20

AD588

V

www.BDTIC.com/ADI

As shown in Figure 40, the AD588 is an excellent choice for the
control element in a bipolar bridge driver scheme. Transistor Q1
and Transistor Q2 serve as series-pass elements to boost the
current drive capability to the 28 mA required by a typical
350 Ω bridge. A differential gain stage can still be required if the
bridge balance is not perfect. Such gain stages can be expensive.

Additional common-mode voltage reduction is realized by

g the circuit illustrated in Figure 41. A1, the ground sense

usin

mplifier, serves the supplies on the bridge to maintain a virtual

a
ground at one center tap. The voltage that appears on the opposite
center tap is now single-ended (referenced to ground) and can
be amplified by a less expensive circuit.

+15V

220Ω

46

AD588

R4

12

3

A3

1

14

220Ω

15

A4

+V

R6

13

11

2

S

–V

16

S

7

R

B

A1

R1

R2

R3

A2

5

R5

8109

E

–15V

Q1 =
2N3904

+–

O

Q

2

2N3904

=

00531-040

Figure 40. Bipolar Bridge Drive

+15

220Ω

Q1 =
2N3904

6

7

R

B

A1

R1

R2

R3

A2

5

4

3

A3

AD588

R4

R5

R6

12

8109

11

A4

13

1

14

220Ω

15

2

+V

S

16

–V

S

Q
2N3904

–15V

AD OP-07

+
V

OUT

–

R1

=

2

R2

00531-041

Figure 41. Floating Bipolar Bridge Drive with Minimum CMV

Rev. G | Page 18 of 20

AD588

0

www.BDTIC.com/ADI

OUTLINE DIMENSIONS

10.50 (0.4134)

10.10 (0.3976)

16

1

1.27 (0.0500)
BSC

0.30 (0.0118)

0.10 (0.0039)

COPLANARITY

0.10

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

0.51 (0.0201)

0.31 (0.0122)

COMPLIANT TO JEDEC STANDARDS MS-013-AA

9

7.60 (0.2992)

7.40 (0.2913)

8

2.65 (0.1043)

2.35 (0.0925)

SEATING
PLANE

10.65 (0.4193)

10.00 (0.3937)

0.33 (0.0130)

0.20 (0.0079)

Figure 42. 16-Lead Standard Small Outline Package [SOIC_W]

Wide Body

(R

W-16)

Dimensions shown in millimeters and (inches)

0.005 (0.13) MIN

PIN 1

.200 (5.08)

MAX

0.200 (5.08)

0.125 (3.18)

16

1

0.100 (2.54) BSC

0.840 (21.34) MAX

0.023 (0.58)

0.014 (0.36)

0.098 (2.49) MAX

9

0.310 (7.87)

0.220 (5.59)

8

0.070 (1.78)

0.030 (0.76)

SEATING
PLANE

0.060 (1.52)

0.015 (0.38)

0.150
(3.81)
MIN

0.75 (0.0295)

0.25 (0.0098)

8°
0°

0.320 (8.13)

0.290 (7.37)

15°

0°

× 45°

1.27 (0.0500)

0.40 (0.0157)

0.015 (0.38)

0.008 (0.20)

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

Figure 43. 16-Lead Ceramic Dual In-Line Package [CERDIP]

(Q-16)

Dim

ensions shown in inches and (millimeters)

ORDERING GUIDE

1 2

AD588ARWZ 5 3 ppm/°C −25 to +85 16-Lead Standard Small Outline Package [SOIC-W] RW-16

Initial Error
(mV

3

)

Temperature
CoefficientModel Package Description Package Option

AD588AQ 3 3 ppm/°C −25 to +85 16-Lead Ceramic Dual In-Line Package [CERDIP] Q-16
AD588BQ 1 1.5 ppm/°C −25 to +85 16-Lead C
AD588JQ 3 3 ppm/°C 0 to 70 16-Lead Ceramic Dual In-Line Package [CERDIP]
AD588KQ 1 1.5 ppm/°C 0 to 70 16-Lead Ceramic Dual In-Line Package [CERDIP] Q-16

1

For details on grade and package offerings screened in accordance with MIL-STD-883, refer to the Analog Devices Military Products Databook or current AD588/883B

data sheet.

2

Temperature coefficient specified from 0°C to 70°C.

3

Z = Pb-free part.

Temperature
Range (°C)

eramic Dual In-Line Package [CERDIP] Q-16

Q-16

Rev. G | Page 19 of 20

AD588

www.BDTIC.com/ADI

NOTES

©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C00531-0-6/06(G)

Rev. G | Page 20 of 20