Datasheet AD5755-1 Datasheet (ANALOG DEVICES)

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Page 1

Quad Channel, 16-Bit, Serial Input,

4 mA to 20 mA and Voltage Output DAC,

Dynamic Power Control, HART Connectivity

Data Sheet

FEATURES

16-bit resolution and monotonicity Dynamic power control for thermal management Current and voltage output pins connectable to a single

terminal

Current output ranges: 0 mA to 20 mA, 4 mA to 20 mA,

or 0 mA to 24 mA ±0.05% total unadjusted error (TUE) maximum

Voltage output ranges (with 20% overrange): 0 V to 5 V, 0 V

to 10 V, ±5 V, and ±10 V

±0.04% total unadjusted error (TUE) maximum User programmable offset and gain On-chip diagnostics On-chip reference (±10 ppm/°C maximum)

−40°C to +105°C temperature range

APPLICATIONS

Process control Actuator control PLCs HART network connectivity

GENERAL DESCRIPTION

The AD5755-1 is a quad, voltage and current output DAC that operates with a power supply range from −26.4 V to +33 V. On-chip dynamic power control minimizes package power

AD5755-1

dissipation in current mode. This is achieved by regulating the voltage on the output driver from 7.4 V to 29.5 V using a dc-to-dc boost converter optimized for minimum on-chip power dissipation. Each channel has a corresponding CHART pin so that HART signals can be coupled onto the current output of the AD5755-1.

The part uses a versatile 3-wire serial interface that operates at clock rates of up to 30 MHz and is compatible with standard SPI, QSPI™, MICROWIRE™, DSP, and microcontroller interface standards. The interface also features optional CRC-8 packet error checking, as well as a watchdog timer that monitors activity on the interface.

PRODUCT HIGHLIGHTS

1. Dynamic power control for thermal management.

2. 16-bit performance.

3. Multichannel.

4. HART compliant.

COMPANION PRODUCTS

Product Family: AD5755, AD5757 External References: ADR445, ADR02 Digital Isolators: ADuM1410, ADuM1411 Power: ADP2302, ADP2303

Additional companion products on the AD5755-1 product page

FUNCTIONAL BLOCK DIAGRAM

–15V/0V

DGND

LDAC SCLK

SDIN

SYNC

SDO

CLEAR

FAULT

ALERT

AD1 AD0

REFOUT

REFIN

DIGITAL

INTERFACE

REFERENCE

AD5755-1

NOTES

1. x = A, B, C, AND D.

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

AGND

+15V

GAIN REG A OFFSET REG A

DAC CHANNEL A

DAC CHANNEL B DAC CHANNEL C DAC CHANNEL D

5.0V

DC-TO-DC

CONVERTER

DAC A

CURRENT AND

OUTPUT RANGE

BOOST_x

7.4V TO 29.5V

VOLTAGE SCALING

OUT_x

SET_x

CHARTx

SENSE_x

OUT _x

Figure 1.

09226-101

Page 2

AD5755-1 Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

General Description ......................................................................... 1

Product Highlights ........................................................................... 1

Companion Products ....................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 3

Detailed Functional Block Diagram .............................................. 4

Specifications ..................................................................................... 5

AC Performance Characteristics ................................................ 8

Timing Characteristics ................................................................ 9

Absolute Maximum Ratings .......................................................... 12

ESD Caution ................................................................................ 12

Pin Configuration and Function Descriptions ........................... 13

Typ i cal Performance Characteristics ........................................... 16

Voltage Outputs .......................................................................... 16

Current Outputs ......................................................................... 20

DC-to-DC Block ......................................................................... 24

Reference ..................................................................................... 25

General ......................................................................................... 26

Terminology .................................................................................... 27

Theory of Operation ...................................................................... 29

DAC Architecture ....................................................................... 29

Power-On State of the AD5755-1 ............................................. 29

Serial Interface ............................................................................ 30

Transfer Function ....................................................................... 30

Registers ........................................................................................... 31

Programming Sequence to Write/Enable the Output

Correctly ...................................................................................... 32

Changing and Reprogramming the Range ............................. 32

Data Registers ............................................................................. 33

Control Registers ........................................................................ 35

Readback Operation .................................................................. 38

Device Features ............................................................................... 40

Output Fault ................................................................................ 40

Voltage Output Short-Circuit Protection ................................ 40

Digital Offset and Gain Control ............................................... 40

Status Readback During a Write .............................................. 40

Asynchronous Clear ................................................................... 41

Packet Error Checking ............................................................... 41

Watchdog Timer ......................................................................... 41

Output Alert ................................................................................ 41

Internal Reference ...................................................................... 41

External Current Setting Resistor ............................................ 41

HART ........................................................................................... 42

Digital Slew Rate Control .......................................................... 42

Power Dissipation control ......................................................... 43

DC-to-DC Converters ............................................................... 43

AICC Supply Requirements—Static .......................................... 44

AICC Supply Requirements—Slewing ...................................... 44

Applications Information .............................................................. 46

Voltage and Current Output Ranges on the Same Terminal 46

Current Output Mode with Internal R

Precision Voltage Reference Selection ..................................... 46

Driving Inductive Loads ............................................................ 47

Transient Voltage Protection .................................................... 47

Microprocessor Interfacing ....................................................... 47

Layout Guidelines....................................................................... 47

Galvanically Isolated Interface ................................................. 48

Outline Dimensions ....................................................................... 49

Ordering Guide .......................................................................... 49

................................ 46

SET

Rev. B | Page 2 of 52

Page 3

Data Sheet AD5755-1

REVISION HISTORY

11/11—Rev. A to Rev. B

Removed Voltage Output Test Conditions/Comments, Table 1 .... 5

Changed Headroom and Footroom Test Conditions/Comments,

Table 1 .............................................................................................................. 5

Changes to Figure 4......................................................................... 10

Changes to Figure 5......................................................................... 11

Changes to SCLK Description, Table 5 ........................................ 13

Changes to Figure 12 ...................................................................... 16

Changes to Figure 21 ...................................................................... 18

Changes to Figure 37 ...................................................................... 20

Changes to Figure 44 ...................................................................... 22

Changes to Figure 71 ...................................................................... 29

Changes to Power-On State of the AD5755-1 Section ............... 30

Changes to Table 17 ........................................................................ 35

Changes to Readback Operation section and Table 26 .............. 38

Changes to Voltage Output Short-Circuit Protection Section .. 40

Changes to Figure 78 ...................................................................... 41

Changes to Figure 82 ...................................................................... 44

Changes to Figure 83, Figure 84, and Figure 85 .................................. 45

Changes to Transient Voltage Protection Section and Figure 86 ... 47

Changes to Galvanically Isolated Interface Section .................... 48

5/11—Rev. 0 to Rev. A

Removed Endnote 6 (Table 1) ......................................................... 6

Ch a n ged AV Changed AI Ch a n ged AV

Minimum Value from 10.8 V to 9 V ................... 6

Minimum Value from −1.4 mA to −1.7 mA......... 7

Voltage in Pin 19 Description ............................ 13

Changes to Ordering Guide ........................................................... 48

4/11—Revision 0: Initial Version

Rev. B | Page 3 of 52

Page 4

AD5755-1 Data Sheet

DETAILED FUNCTIONAL BLOCK DIAGRAM

5.0V

–15V/0V

AGND

+15V

BOOST_A

DGND

LDAC

CLEAR

SCLK

SDIN

SYNC

SDO

FAULT

ALERT

REFOUT

REFIN

AD1

AD0

POWER-ON

RESET

INPUT SHIFT

AND

CONTROL

STATUS

WATCHDOG

TIMER

(SPI ACTIVITY)

VREF

REFERENCE

BUFFERS

AD5755-1

INPUT REG A

GAIN REG A OFFSET REG A

DAC CHANNEL A

DAC CHANNEL B DAC CHANNEL C DAC CHANNEL D

DC-TO-DC

CONVERTER

REG

SEN1VSEN2

OUT_A

SET_A

POWER

CONTROL

DAC

REG A

DAC A

7.4V TO 29.5V

R2 R3

CHARTA

SENSE_A

OUT_A

, I

SET_B

SENSE_B

OUT_B

OUT_C

, R

SET_C

, +V

OUT_C

, I

OUT_D

, R

SENSE_

SET_D

OUT_D

, +V

OUT_B

R CHARTB, CHARTC, CHARTD

+V V

SENSE_

09226-001

RANGE

SCALING

SWB, SWC, SW

VOUT

BOOST_B,VBOOST_C,VBOOST_D

Figure 2.

Rev. B | Page 4 of 52

Page 5

Data Sheet AD5755-1

Full-Scale TC2

±2 ppm FSR/°C

Differential Nonlinearity (DNL)

−1 +1

LSB

Guaranteed monotonic

DC PSRR

50 µV/V

SPECIFICATIONS

AVDD = V GNDSW otherwise noted.

Table 1.

Parameter1 Min Typ Max Unit Test Conditions/Comments

VOLTAGE OUTPUT

Output Voltage Ranges 0 5 V

0 10 V

−5 +5 V

−10 +10 V 0 6 V 0 12 V

−6 +6 V

−12 +12 V

ACCURACY BIPOLAR SUPPLY AVSS = −15 V, loaded and unloaded

Resolution 16 Bits

Total Unadjusted Error (TUE) −0.04 +0.04 % FSR

−0.03 ±0.0032 +0.03 % FSR TA = 25°C

TUE Long-Term Stability 35 ppm FSR Drift after 1000 hours, TJ = 150°C

Relative Accuracy (INL) −0.006 ±0.0012 +0.006 % FSR 0 V to 5 V, 0 V to 10 V, ±5 V, ±10 V ranges

−0.008 ±0.0012 +0.008 % FSR On overranges

Differential Nonlinearity (DNL) −1 +1 LSB Guaranteed monotonic

Zero-Scale Error −0.03 ±0.002 +0.03 % FSR

Zero-Scale TC2 ±2 ppm FSR/°C

Bipolar Zero Error −0.03 ±0.002 +0.03 % FSR

Bipolar Zero TC

Offset Error −0.03 ±0.002 +0.03 % FSR

Offset TC2 ±2 ppm FSR/°C

Gain Error −0.03 ±0.004 +0.03 % FSR

Gain TC2 ±3 ppm FSR/°C

Full-Scale Error −0.03 ±0.002 +0.03 % FSR

= 15 V; AVSS = −15 V/0 V; DVDD = 2.7 V to 5.5 V; AVCC = 4.5 V to 5.5 V; dc-to-dc converter disabled; AGND = DGND =

BOOST_x

= 0 V; REFIN = 5 V; voltage outputs: RL = 1 kΩ, CL = 220 pF; current outputs: RL = 300 Ω; all specifications T

±1 ppm FSR/°C

MIN

to T

MAX

, unless

ACCURACY UNIPOLAR SUPPLY2 AVSS = 0 V

Total Unadjusted Error (TUE) −0.06 ±0.025 +0.06 % FSR

Relative Accuracy (INL)3 −0.009 +0.009 % FSR

Zero-Scale Error +0.22 % FSR

Offset Error −0.07 ±0.025 +0.07 % FSR

Gain Error −0.07 ±0.015 +0.07 % FSR

Full-Scale Error −0.06 ±0.015 +0.06 % FSR

OUTPUT CHARACTERISTICS2

Headroom 1 2.2 V

Footroom 0.7 1.4 V

Output Voltage Drift vs. Time 20 ppm FSR Drift after 1000 hours, ¾ scale output, TJ = 150°C,

Short-Circuit Current 12/6 16/8 mA Programmable by user, defaults to 16 mA typical

Load 1 kΩ For specified performance

Capacitive Load Stability 10 nF

2 µF External compensation capacitor of 220 pF connected

DC Output Impedance 0.06 Ω

DC Crosstalk 24 µV

Rev. B | Page 5 of 52

With respect to V

BOOST

supply

With respect to the AVSS supply, bipolar output

ranges

= −15 V

level

Page 6

AD5755-1 Data Sheet

Gain Error

−0.05

±0.004

+0.05

% FSR

Offset Error Drift2

±6 ppm FSR/°C

Gain TC2

±9 ppm FSR/°C

Parameter1 Min Typ Max Unit Test Conditions/Comments

CURRENT OUTPUT

Output Current Ranges 0 24 mA

0 20 mA 4 20 mA

Resolution 16 Bits

ACCURACY (EXTERNAL R

)

SET

Total Unadjusted Error (TUE) −0.05 ±0.009 +0.05 % FSR TUE Long-Term Stability 100 ppm FSR Drift after 1000 hours, TJ = 150°C Relative Accuracy (INL) −0.006 +0.006 % FSR Differential Nonlinearity (DNL) −1 +1 LSB Guaranteed monotonic Offset Error −0.05 ±0.005 +0.05 % FSR Offset Error Drift2 ±4 ppm FSR/°C

Gain TC2 ±3 ppm FSR/°C Full-Scale Error −0.05 ±0.008 +0.05 % FSR Full-Scale TC2 ±5 ppm FSR/°C DC Crosstalk 0.0005 % FSR External R

ACCURACY (INTERNAL R

Total Unadjusted Error (TUE)

)

SET

4, 5

−0.14 +0.14 % FSR

−0.11 ±0.009 +0.11 % FSR TA = 25°C TUE Long-Term Stability 180 ppm FSR Drift after 1000 hours, TJ = 150°C Relative Accuracy (INL) −0.006 +0.006 % FSR Relative Accuracy (INL) −0.004 +0.004 % FSR TA = 25°C Differential Nonlinearity (DNL) −1 +1 LSB Guaranteed monotonic Offset Error

4, 5

−0.05 +0.05 % FSR

−0.04 ±0.007 +0.04 % FSR TA = 25°C

Assumes ideal resistor, see the External Current Setting Resistor section for more information

SET

Gain Error −0.12 +0.12 % FSR

−0.06 ±0.002 +0.06 % FSR TA = 25°C

Full-Scale Error

4, 5

−0.14 +0.14 % FSR

−0.1 ±0.007 +0.1 % FSR TA = 25°C Full-Scale TC2 ±14 ppm FSR/°C DC Crosstalk5 −0.011 % FSR Internal R

SET

OUTPUT CHARACTERISTICS2

Current Loop Compliance Voltage V

BOOST_x

2.4

−

BOOST_x

2.7

−

Output Current Drift vs. Time Drift after 1000 hours, ¾ scale output, TJ = 150°C 90 ppm FSR External R 140 ppm FSR Internal R

SET

Resistive Load 1000 Ω The dc-to-dc converter has been characterized with

a maximum load of 1 kΩ, chosen such that compliance is not exceeded; see MaxV bits in

Tab le 25

Figure 53 and DC-DC

Output Impedance 100 MΩ DC PSRR 0.02 1 µA/V

Rev. B | Page 6 of 52

Page 7

Data Sheet AD5755-1

Output Noise (0.1 Hz to 10 Hz)2

µV p-p

VOL, Output Low Voltage

0.6 V

At 2.5 mA

Parameter1 Min Typ Max Unit Test Conditions/Comments

REFERENCE INPUT/OUTPUT

Reference Input2

Reference Input Voltage 4.95 5 5.05 V For specified performance DC Input Impedance 45 150 MΩ

Reference Output

Output Voltage 4.995 5 5.005 V TA = 25°C Reference TC2 −10 ±5 +10 ppm/°C

Noise Spectral Density2 100 nV/√Hz At 10 kHz

Output Voltage Drift vs. Time2 180 ppm Drift after 1000 hours, TJ = 150°C Capacitive Load2 1000 nF Load Current 9 mA Short-Circuit Current 10 mA Line Regulation2 3 ppm/V Load Regulation2 95 ppm/mA Thermal Hysteresis2 160 ppm First temperature cycle 5 ppm Second temperature cycle

DC-TO-DC

Switch

Switch On Resistance 0.425 Ω Switch Leakage Current 10 nA Peak Current Limit 0.8 A

Oscillator

Oscillator Frequency 11.5 13 14.5 MHz This oscillator is divided down to give the dc-to-dc

Maximum Duty Cycle 89.6 % At 410 kHz dc-to-dc switching frequency

DIGITAL INPUTS2 JEDEC compliant

VIH, Input High Voltage 2 V VIL, Input Low Voltage 0.8 V Input Current −1 +1 µA Per pin Pin Capacitance 2.6 pF Per pin

DIGITAL OUTPUTS2

SDO, ALERT

VOL, Output Low Voltage 0.4 V Sinking 200 µA VOH, Output High Voltage DVDD − 0.5 V Sourcing 200 µA High Impedance Leakage

Current

High Impedance Output

Capacitance

FAULT

VOL, Output Low Voltage 0.4 V 10 kΩ pull-up resistor to DVDD

−1 +1 µA

2.5 pF

See

Figure 64

See

Figure 65

See

Figure 64

converter switching frequency

VOH, Output High Voltage 3.6 V 10 kΩ pull-up resistor to DVDD

POWER REQUIREMENTS

AVDD 9 33 V AVSS −26.4 −10.8/0 V DVDD 2.7 5.5 V AVCC 4.5 5.5 V

Rev. B | Page 7 of 52

Page 8

AD5755-1 Data Sheet

Power Dissipation

173 mW

AVDD = +15 V, AVSS = −15 V, dc-to-dc converter

Digital Feedthrough

nV-sec

AC PSRR

83 dB

200 mV 50 Hz/60 Hz sine wave superimposed on power

Output Noise Spectral Density

0.5 nA/√Hz

Measured at 10 kHz, midscale output, 0 mA to 24 mA

Parameter1 Min Typ Max Unit Test Conditions/Comments

AIDD 8.6 10.5 mA Voltage output mode on all channels, output

7 7.5 mA Current output mode on all channels AISS −11 −8.8 mA Voltage output mode on all channels, output

−1.7 mA Current output mode on all channels DICC 9.2 11 mA VIH = DVDD, VIL = DGND, internal oscillator running,

AICC 1 mA Output unloaded, over supplies I

2.7 mA Per channel, voltage output mode, output

BOOST

1 mA Per channel, current output mode, 0 mA output

BOOST

Temperature range: −40°C to +105°C; typical at +25°C.

Guaranteed by design and characterization; not production tested.

For voltage output ranges in unipolar supply mode, the INL and TUE are measured beginning from Code 4096.

For current outputs with internal R

loaded with the same code.

See the Current Output Mode with Internal R

Efficiency plots in Figure 55, Figure 56, Figure 57, and Figure 58 include the I

, the offset, full-scale, and TUE measurements exclude dc crosstalk. The measurements are made with all four channels enabled

SET

section for more explanation of the dc crosstalk.

SET

quiescent current

BOOST

AC PERFORMANCE CHARACTERISTICS

AVDD = V GNDSW otherwise noted.

= 15 V; AVSS = −15 V; DVDD = 2.7 V to 5.5 V; AVCC = 4.5 V to 5.5 V; dc-to-dc converter disabled; AGND = DGND =

BOOST_x

= 0 V; REFIN = 5 V; voltage outputs: RL = 2 kΩ, CL = 220 pF; current outputs: RL = 300 Ω; all specifications T

unloaded, over supplies

over supplies

unloaded, over supplies

enable, current output mode, outputs disabled

MIN

to T

MAX

, unless

Table 2.

Parameter1 Min Typ Max Unit Test Conditions/Comments

DYNAMIC PERFORMANCE

Voltage Output

Output Voltage Settling Time 11 µs 5 V step to ±0.03% FSR, 0 V to 5 V range 18 µs 10 V step to ±0.03% FSR, 0 V to 10 V range 13 µs 100 mV step to 1 LSB (16-bit LSB), 0 V to 10 V range Slew Rate 1.9 V/µs 0 V to 10 V range Power-On Glitch Energy 150 nV-sec Digital-to-Analog Glitch Energy 6 nV-sec Glitch Impulse Peak Amplitude 25 mV

DAC to DAC Crosstalk 2 nV-sec 0 V to 10 V range Output Noise (0.1 Hz to 10 Hz

Bandwidth)

Output Noise Spectral Density 150 nV/√Hz Measured at 10 kHz, midscale output, 0 V to 10 V range

Current Output

Output Current Settling Time 15 µs To 0.1% FSR (0 mA to 24 mA) See test conditions/

Output Noise (0.1 Hz to 10 Hz

Bandwidth)

Guaranteed by design and characterization; not production tested.

0.15 LSB p-p 16-bit LSB, 0 V to 10 V range

supply voltage

See

Figure 49, Figure 50, and Figure 51

comments

0.15 LSB p-p 16-bit LSB, 0 mA to 24 mA range

range

Rev. B | Page 8 of 52

Page 9

Data Sheet AD5755-1

t17

500

ns min

falling edge to

rising edge

TIMING CHARACTERISTICS

AVDD = V GNDSW otherwise noted.

= 15 V; AVSS = −15 V; DVDD = 2.7 V to 5.5 V; AVCC = 4.5 V to 5.5 V; dc-to-dc converter disabled; AGND = DGND =

BOOST_x

= 0 V; REFIN = 5 V; voltage outputs: RL = 1 kΩ, CL = 220 pF; current outputs: RL = 300 Ω; all specifications T

MIN

to T

MAX

, unless

Table 3.

Parameter

1, 2, 3

Limit at T

, T

Unit Description

MIN

MAX

t1 33 ns min SCLK cycle time t2 13 ns min SCLK high time t3 13 ns min SCLK low time t4 13 ns min

falling edge to SCLK falling edge setup time

SYNC t5 13 ns min 24th/32nd SCLK falling edge to t6 198 ns min

SYNC

high time t7 5 ns min Data setup time t8 5 ns min Data hold time t9 20 µs min

rising edge to

SYNC

falling edge (all DACs updated or any channel has

LDAC

digital slew rate control enabled)

5 µs min t10 10 ns min t11 500 ns max t12 See the AC Performance

µs max DAC output settling time

rising edge to

SYNC

pulse width low

LDAC

falling edge to DAC output response time

LDAC

falling edge (single DAC updated)

LDAC

Characteristics section t13 10 ns min CLEAR high time t14 5 µs max CLEAR activation time t15 40 ns max SCLK rising edge to SDO valid t16 21 µs min

5 µs min

t18 800 ns min

20 µs min

5 µs min

rising edge to DAC output response time (

SYNC

rising edge to DAC output response time (

SYNC LDAC RESET

high to next

SYNC

high to next

SYNC

pulse width

SYNC

low (digital slew rate control enabled) (all DACs updated)

SYNC

low (digital slew rate control disabled) (single DAC

SYNC

updated)

Guaranteed by design and characterization; not production tested.

All input signals are specified with tR = tF = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.2 V.

See Figure 3, Figure 4, Figure 5, and Figure 6.

This specification applies if

LDAC

is held low during the write cycle; otherwise, see t9.

rising edge (see Figure 78)

SYNC

LDAC LDAC

= 0) (all DACs updated) = 0) (single DAC updated)

Rev. B | Page 9 of 52

Page 10

AD5755-1 Data Sheet

Timing Diagrams

SCLK

SYNC

SDIN

LDAC

OUT_x

LDAC = 0

OUT_x

CLEAR

OUT_x

12 24

MSB

LSB

SCLK

YNC

SDIN

SDO

RESET

Figure 3. Serial Interface Timing Diagram

1 1

MSB MSBLSB LSB

INPUT WORD SPECIFIES REGISTER TO BE READ

UNDEFINED SELECTED REGISTER DATA

24 24

NOP CONDITION

MSB LSB

CLOCKED OUT

Figure 4. Readback Timing Diagram

09226-002

9226-003

Rev. B | Page 10 of 52

Page 11

Data Sheet AD5755-1

SDO DISABL E D

R/W

SDIN

SCLK

SYNC

SDO

1 2 16

LSB MSB

DUT_

AD1

SDO_

ENAB

DUT_

AD0

X X X D15 D14 D1 D0

STATUSSTATUSSTATUSSTATUS

09226-004

200µA I

(MIN) OR

(MAX)

TO OUTPUT

50pF

09226-005

Figure 5. Status Readback During Write

Figure 6. Load Circuit for SDO Timing Diagram

Rev. B | Page 11 of 52

Page 12

AD5755-1 Data Sheet

AVSS to AGND, DGND

+0.3 V to −28 V

DVDD to DGND

−0.3 V to +7 V

(whichever is less)

REFIN, REFOUT to AGND

−0.3 V to AVDD + 0.3 V or +7 V Junction Temperature (TJ max)

125°C

Lead Temperature

JEDEC industry standard

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted. Transient currents of up to 100 mA do not cause SCR latch-up.

Table 4.

Parameter Rating

AVDD, V

AVDD to AVSS −0.3 V to +60 V AVCC to AGND −0.3 V to +7 V

to AGND, DGND −0.3 V to +33 V

BOOST_x

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

Digital Inputs to DGND −0.3 V to DVDD + 0.3 V or +7 V

(whichever is less)

Digital Outputs to DGND −0.3 V to DVDD + 0.3 V or +7 V

(whichever is less)

to AGND AVSS to V

OUT_x

or 33 V if using

BOOST_x

the dc-to-dc circuitry

to AGND AVSS to V

SENSE_x

or 33 V if using

BOOST_x

the dc-to-dc circuitry

to AGND AVSS to V

OUT_x

or 33 V if using

BOOST_x

the dc-to-dc circuitry SWx to AGND −0.3 to +33 V AGND, GNDSWx to DGND −0.3 V to +0.3 V Operating Temperature Range (TA)

Industrial1 −40°C to +105°C

Storage Temperature Range −65°C to +150°C

64-Lead LFCSP

θJA Thermal Impedance2 20°C/W

Power Dissipation (TJ max − TA)/θJA

Soldering J-STD-020

Power dissipated on chip must be derated to keep the junction temperature

below 125°C.

Based on a JEDEC 4-layer test board.

Rev. B | Page 12 of 52

Page 13

Data Sheet AD5755-1

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

LV_D

PIN 1

INDICATOR

DCDC_D

SET_CRSET_D

R 646362616059585756555453525150

SENSE_D

REFOUT

REFIN

COMP

CHARTD

COMP

BOOST_DVOUT_D

LV_C

SENSE_C

OUT_D

AVSSCOMP

OUT_C

CHARTC

V 49

SET_B

SET_A

REFGND REFGND

NOTES

1. THE EXPOSED PAD SHOULD BE CONNECTED TO THE POTENTIAL OF THE AV UNCONNECTED . IT I S RE C OMMENDED T H AT THE PAD BE THERMALL Y CONNECTED TO A COPPER PLANE FOR ENHANCED THERMAL PERFORM ANCE .

3 4

AD0

AD1

SYNC

SCLK

SDIN

SDO

DGND

LDAC

CLEAR

ALERT

FAULT

171819202122232425262728293031

POC

PIN, O R, ALTERNATIVELY, IT CAN BE LEFT E LECTRICA LLY

RESET

LV_A

COMP

AD5755-1

TOP VIEW

(Not to Scale)

DCDC_A

SENSE_A

BOOST_A

CHARTA

COMP

OUT_AIOUT_A

LV_B

CHARTB

COMP

SENSE_B

COMP

DCDC_C

OUT_C

BOOST_C

GNDSW GNDSW

AGND V

BOOST_B

OUT_B

C D

A B

09266-006

42 41 40 39 38 37 36 35 34 33

OUT_B

DCDC_B

COMP

Figure 7. Pin Configuration

Table 5. Pin Function Descriptions

Pin No. Mnemonic Description

1 R

SET_B

An external, precision, low drift 15 kΩ current setting resistor can be connected to this pin to improve the I temperature drift performance. See the Device Features section.

2 R

SET_A

An external, precision, low drift 15 kΩ current setting resistor can be connected to this pin to improve the I

temperature drift performance. See the Device Features section. 3, 4 REFGND Ground Reference Point for Internal Reference. 5 AD0 Address Decode for the Device Under Test (DUT) on the Board. 6 AD1 Address Decode for the DUT on the Board. 7

Active Low Input. This is the frame synchronization signal for the serial interface. While SYNC is low, data is

SYNC

transferred in on the falling edge of SCLK. 8 SCLK

Serial Clock Input. Data is clocked into the input shift register on the falling edge of SCLK. This operates at clock

speeds of up to 30 MHz. 9 SDIN Serial Data Input. Data must be valid on the falling edge of SCLK. 10 SDO Serial Data Output. Used to clock data from the serial register in readback mode. See Figure 4 and Figure 5. 11 DVDD Digital Supply. The voltage range is from 2.7 V to 5.5 V. 12 DGND Digital Ground. 13

Load DAC, Active Low Input. This is used to update the DAC register and consequently the DAC outputs. When

LDAC

tied permanently low, the addressed DAC data register is updated on the rising edge of SYNC

. If LDAC is held

high during the write cycle, the DAC input register is updated, but the DAC output update only takes place at

14 CLEAR

the falling edge of LDAC

LDAC

pin must not be left unconnected.

Active High, Edge Sensitive Input. Asserting this pin sets the output current and voltage to the preprogrammed

(see Figure 3). Using this mode, all analog outputs can be updated simultaneously. The

clear code bit setting. Only channels enabled to be cleared are cleared. See the Device Features section for more

information. When CLEAR is active, the DAC output register cannot be written to.

OUT_B

OUT_A

Rev. B | Page 13 of 52

Page 14

AD5755-1 Data Sheet

AVDD

Positive Analog Supply. The voltage range is from 9 V to 33 V.

SWB

Switching Output for Channel B DC-to-DC Circuitry. To use the dc-to-dc feature of the device, connect as shown in Figure 80.

Pin No. Mnemonic Description

15 ALERT Active High Output. This pin is asserted when there has been no SPI activity on the interface pins for a

predetermined time. See the Device Features section for more information.

FAULT

17 POC Power-On Condition. This pin determines the power-on condition and is read during power-on or, alternatively,

RESET

Active Low Output. This pin is asserted low when an open circuit in current mode is detected, a short circuit in voltage mode is detected, a PEC error is detected, or an overtemperature is detected (see the Device Features section). Open-drain output.

after a device reset. If POC = 0, the device is powered up with the voltage and current channels in tristate mode. If POC = 1, the device is powered up with a 30 kΩ pull-down resistor to ground on the voltage output channel, and the current channel is in tristate mode.

Hardware Reset, Active Low Input.

20 COMP

Optional Compensation Capacitor Connection for V

LV_ A

this pin and the V

pin allows the voltage output to drive up to 2 µF. Note that the addition of this capacitor

OUT_A

Output Buffer. Connecting a 220 pF capacitor between

OUT_A

reduces the bandwidth of the output amplifier, increasing the settling time. 21 CHARTA HART Input Connection for DAC Channel A. 22 +V 23 COMP

Sense Connection for the Positive Voltage Output Load Connection for V

SENSE_A

DC-to-DC Compensation Capacitor. Connect a 10 nF capacitor from this pin to ground. Used to regulate the

DCDC_A

OUT_A

feedback loop of the Channel A dc-to-dc converter. Alternatively, if using an external compensation resistor,

place a resistor in series with a capacitor to ground from this pin (see the DC-to-DC Converter Compensation

Capacitors and the AI

Supply Requirements—Slewing sections in the Device Features section for more

information). 24 V

Supply for Channel A Current Output Stage (see Figure 73). This is also the supply for the V

BOOST_A

regulated to 15 V by the dc-to-dc converter. To use the dc-to-dc feature of the device, connect as shown in

Figure 80. 25 V 26 I

Buffered Analog Output Voltage for DAC Channel A.

OUT_A

Current Output Pin for DAC Channel A.

OUT_A

27 AVSS Negative Analog Supply. Voltage range is from −10.8 V to −26.4 V. 28 COMP

Optional Compensation Capacitor Connection for V

LV_ B

this pin and the V

pin allows the voltage output to drive up to 2 µF. Note that the addition of this capacitor

OUT_B

Output Buffer. Connecting a 220 pF capacitor between

OUT_B

reduces the bandwidth of the output amplifier, increasing the settling time. 29 CHARTB HART Input Connection for DAC Channel B. 30 +V 31 V 32 COMP

Sense Connection for the Positive Voltage Output Load Connection for V

SENSE_B

Buffered Analog Output Voltage for DAC Channel B.

OUT_B

DC-to-DC Compensation Capacitor. Connect a 10 nF capacitor from this pin to ground. Used to regulate the

DCDC_B

OUT_B

feedback loop of the Channel B dc-to-dc converter. Alternatively, if using an external compensation resistor,

place a resistor in series with a capacitor to ground from this pin (see the DC-to-DC Converter Compensation

Capacitors and AI

Supply Requirements—Slewing sections in the Device Features section for more

information). 33 I 34 V

Current Output Pin for DAC Channel B.

OUT_B

Supply for Channel B Current Output Stage (see Figure 73). This is also the supply for the V

BOOST_B

regulated to 15 V by the dc-to-dc converter. To use the dc-to-dc feature of the device, connect as shown in

Figure 80. 35 AGND Ground Reference Point for Analog Circuitry. This must be connected to 0 V.

stage, which is

OUT_x

stage, which is

OUT_x

in Figure 80. 37 GNDSWB Ground Connection for DC-to-DC Switching Circuit. This pin should always be connected to ground. 38 GNDSWA Ground Connection for DC-to-DC Switching Circuit. This pin should always be connected to ground. 39 SWA Switching Output for Channel A DC-to-DC Circuitry. To use the dc-to-dc feature of the device, connect as shown

40 AVSS Negative Analog Supply Pin. The voltage range is from −10.8 V to −26.4 V. This pin can be connected to 0 V if

using the device in unipolar supply mode. 41 SWD Switching Output for Channel D DC-DC Circuitry. To use the dc-to-dc feature of the device, connect as shown in

Figure 80. 42 GNDSWD Ground Connections for DC-to-DC Switching Circuit. This pin should always be connected to ground. 43 GNDSWC Ground Connections for DC-to-DC Switching Circuit. This pin should always be connected to ground. 44 SWC Switching Output for Channel C DC-to-DC Circuitry. To use the dc-to-dc feature of the device, connect as shown

in Figure 80. 45 AVCC Supply for DC-to-DC Circuitry.

Rev. B | Page 14 of 52

Page 15

Data Sheet AD5755-1

COMP

DC-to-DC Compensation Capacitor. Connect a 10 nF capacitor from this pin to ground. Used to regulate the

REFOUT

Internal Reference Voltage Output. It is recommended to place a 0.1 µF capacitor between REFOUT and

Pin No. Mnemonic Description

46 V

47 I

49 V 50 +V 51 CHARTC HART Input Connection for DAC Channel C. 52 COMP

53 AVSS Negative Analog Supply Pin. 54 I 55 V 56 V

57 COMP

58 +V 59 CHARTD HART Input Connection for DAC Channel D 60 COMP

61 REFIN External Reference Voltage Input.

Supply for Channel C Current Output Stage (see Figure 73). This is also the supply for the V

BOOST_C

regulated to 15 V by the dc-to-dc converter. To use the dc-to-dc feature of the device, connect as shown in Figure 80.

Current Output Pin for DAC Channel C.

OUT_C

DCDC_C

feedback loop of the Channel C dc-to-dc converter. Alternatively, if using an external compensation resistor, place a resistor in series with a capacitor to ground from this pin (see the

DC-to-DC Converter Compensation Capacitors and AICC Supply Requirements—Slewing sections in the Device Features section for more information).

Buffered Analog Output Voltage for DAC Channel C.

OUT_C

Sense Connection for the Positive Voltage Output Load Connection for V

SENSE_C

Optional Compensation Capacitor Connection for V

LV_ C

this pin and the V

pin allows the voltage output to drive up to 2 µF. Note that the addition of this capacitor

OUT_C

Output Buffer. Connecting a 220 pF capacitor between

OUT_C

reduces the bandwidth of the output amplifier, increasing the settling time.

Current Output Pin for DAC Channel D.

OUT_D

Buffered Analog Output Voltage for DAC Channel D.

OUT_D

Supply for Channel D Current Output Stage (see Figure 73). This is also the supply for the V

BOOST_D

regulated to 15 V by the dc-to-dc converter. To use the dc-to-dc feature of the device, connect as shown in Figure 80.

DC-to-DC Compensation Capacitor. Connect a 10 nF capacitor from this pin to ground. Used to regulate the

DCDC_D

feedback loop of the Channel D dc-to-dc converter. Alternatively, if using an external compensation resistor, place a resistor in series with a capacitor to ground from this pin (see the DC-to-DC Converter Compensation Capacitors and AI

Supply Requirements—Slewing sections in the Device Features section for more

information).

Sense Connection for the Positive Voltage Output Load Connection for V

SENSE_D

Optional Compensation Capacitor Connection for V

LV_ D

this pin and the V

pin allows the voltage output to drive up to 2 µF. Note that the addition of this capacitor

OUT_D

Output Buffer. Connecting a 220 pF capacitor between

OUT_D

reduces the bandwidth of the output amplifier, increasing the settling time.

stage, which is

OUT_x

stage, which is

OUT_x

REFGND.

63 R

An external, precision, low drift 15 kΩ current setting resistor can be connected to this pin to improve the I

SET_D

temperature drift performance. See the Device Features section.

64 R

An external, precision, low drift 15 kΩ current setting resistor can be connected to this pin to improve the I

SET_C

temperature drift performance. See the Device Features section.

EPAD Exposed Pad. This exposed pad should be connected to the potential of the AVSS pin, or, alternatively, it can be

left electrically unconnected. It is recommended that the pad be thermally connected to a copper plane for enhanced thermal performance.

Rev. B | Page 15 of 52

OUT_D

OUT_C

Page 16

AD5755-1 Data Sheet

0.0015

0.0010

0.0005

–0.0005

–0.0010

0 10k 20k 30k 40k 50k 60k

INL ERROR ( %FSR)

CODE

09226-023

±10V RANGE ±5V RANGE +10V RANGE +5V RANGE +10V RANGE WITH DCDC

= +15V

= –15V

= 25°C

–1.0

–0.8

–0.6

–0.4

–0.2

0.2

0.4

0.6

0.8

1.0

0 10k 20k 30k 40k 50k 60k

DNL ERROR (LSB)

CODE

±10V RANGE ±5V RANGE +10V RANGE +5V RANGE +10V RANGE WI TH DCDC

= +15V

= –15V

= 25°C

09226-024

10k 20k 30k 40k 50k 60k

–0.010

–0.008

–0.006

–0.004

–0.002

0.002

0.004

0.006

TOTAL UNADJUSTED ERROR (%FSR)

CODE

±10V RANGE ±5V RANGE +10V RANGE +5V RANGE +10V RANGE WI TH DCDC

= +15V

= –15V

= 25°C

09226-025

–0.0015

–0.0010

–0.0005

0.0005

0.0010

0.0015

–40 –20 0 20 40 60 80 100

INL ERROR ( %FSR)

TEMPERATURE (°C)

+5V RANGE MAX I NL +10V RANGE MAX INL ±5V RANGE MAX I NL ±10V RANGE MAX INL +5V RANGE MIN INL +10V RANGE MI N INL ±5V RANGE MIN INL

±10V RANGE MIN INL

= +15V

= –15V

OUTPUT UNLOADED

09226-127

–1.0

–0.8

–0.6

–0.4

–0.2

0.2

0.4

0.6

0.8

1.0

–40 –20 0 20 40 60 80 100

DNL ERROR (L S B)

TEMPERATURE (°C)

AVDD = +15V AV

= –15V

ALL RANGES

DNL ERROR MAX DNL ERROR MI N

09226-128

–0.006

–0.004

–0.002

0.002

0.004

0.006

0.008

0.010

0.012

–40 –20 0 20 40 60 80 100

TOTAL UNADJUSTED ERROR ( %FSR)

TEMPERATURE (°C)

AVDD = +15V AV

= –15V

OUTPUT UNLOADED

+5V RANGE +10V RANGE ±5V RANGE ±10V RANGE

09226-129

TYPICAL PERFORMANCE CHARACTERISTICS

VOLTAGE OUTPUTS

Figure 8. Integral Nonlinearity Error vs. DAC Code

Figure 9. Differential Nonlinearity Error vs. DAC Code

Figure 11. Integral Nonlinearity Error vs. Temperature

Figure 12. Differential Nonlinearity Error vs. Temperature

Figure 10. Total Unadjusted Error vs. DAC Code

Figure 13. Total Unadjusted Error vs. Temperature

Rev. B | Page 16 of 52

Page 17

Data Sheet AD5755-1

–0.035

–0.030

–0.025

–0.020

–0.015

–0.010

–0.005

–40 –20 0 20 40 60 80 100

TOTAL UNADJUSTED ERROR (%FSR)

TEMPERATURE (°C)

= +15V

= 0V

OUTPUT UNLOADED

+5V RANGE +12V RANGE

09226-130

–0.006

–0.004

–0.002

0.002

0.004

0.006

0.008

0.010

0.012

–40 –20 0 20 40 60 80 100

FULL-S CALE ERROR (%FS R)

TEMPERATURE (°C)

AVDD = +15V AV

= –15V

OUTPUT UNLOADED

+5V RANGE +10V RANGE ±5V RANGE ±10V RANGE

09226-132

–0.0025

–0.0020

–0.0015

–0.0010

–0.0005

0.0005

0.0010

0.0015

–40 –20 0 20 40 60 80 100

OFFSET (%FSR)

TEMPERATURE (°C)

= +15V

= –15V

OUTPUT UNLOADED

+5V RANGE +10V RANGE

09226-133

–0.0020

–0.0015

–0.0010

–0.0005

0.0005

0.0010

0.0015

0.0020

0.0025

–40 –20 0 20 40 60 80 100

BIPOLAR ZERO ERROR (%FSR)

TEMPERATURE (°C)

AVDD = +15V AV

= –15V

OUTPUT UNLOADED

±5V RANGE ±10V RANGE

09226-134

–0.006

–0.004

–0.002

0.002

0.004

0.006

0.008

0.010

–40 –20 0 20 40 60 80 100

TEMPERATURE (°C)

AVDD = +15V AV

= –15V

OUTPUT UNLOADED

+5V RANGE +10V RANGE ±5V RANGE ±10V RANGE

GAIN ERROR ( %FSR)

09226-135

–0.0020

–0.0015

–0.0010

–0.0005

0.0005

0.0010

0.0015

ZERO-SCALE ERROR (%FS R)

AVDD = +15V AV

= –15V

OUTPUT UNLOADED

+5V RANGE +10V RANGE ±5V RANGE ±10V RANGE

09226-136

–40 –20 0 20 40 60 80 100

TEMPERATURE (°C)

Figure 14. Total Unadjusted Error vs. Temperature, Single Supply

Figure 15. Full-Scale Error vs. Temperature

Figure 17. Bipolar Zero Error vs. Temperature

Figure 18. Gain Error vs. Temperature

Figure 16. Offset Error vs. Temperature

Figure 19. Zero-Scale Error vs. Temperature

Rev. B | Page 17 of 52

Page 18

AD5755-1 Data Sheet

0.0020

–0.0020

10 15 20 25 30

INL EROR ( %FSR)

SUPPLY (V)

09226-034

–0.0015

–0.0010

–0.0005

0.0005

0.0010

0.0015

0V TO 10V RANG E M AX INL 0V TO 10V RANG E M IN INL T

= 25°C

= –26.4V FOR AVDD > +26.4V

–1.0

–0.8

–0.6

–0.4

–0.2

0.2

0.4

0.6

0.8

1.0

10 15 20 25 30

DNL ERROR (L S B)

SUPPLY (V)

AVSS = –26.4V FOR AVDD > +26.4V

= +15V

= –15V ALL RANGES T

= 25°C

DNL ERROR MAX DNL ERROR MI N

09226-138

0.008

0.006

0.004

0.002

–0.002

–0.004

10 15 20 25 30

TOTAL UNADJUS TED ERROR (%FS R)

SUPPLY (V)

09226-035

0V TO 10V RANG E M AX INL 0V TO 10V RANG E M IN INL T

= 25°C

= –26.4V FOR AVDD > +26.4V

0.0020

0.0015

0.0010

0.0005

–0.0005

–0.0010

–0.0015

–0.0020

–20 201612840–4–8–12–16

OUTPUT VOLTAGE DELTA (V)

OUTPUT CURRE NT (mA)

09226-036

8mA LIMIT, CODE = 0xFFFF 16mA LIMIT, CODE = 0xFFFF

= +15V

= –15V ±10V RANGE T

= 25°C

–4

–8

–12

–5 151050

OUTPUT VOLTAGE (V)

TIME (µs)

09226-037

= +15V

= –15V ±10V RANGE T

= 25°C

OUTPUT UNLOADED

–4

–8

–12

–5 151050

OUTPUT VOLTAGE (V)

TIME (µs)

09226-038

AVDD = +15V AV

= –15V ±10V RANGE T

= 25°C

OUTPUT UNLOADED

Figure 20. Integral Nonlinearity Error vs. AVDD/|AVSS|

Figure 21. Differential Nonlinearity Error vs. AVDD/|AVSS|

Figure 23. Source and Sink Capability of Output Amplifier

Figure 24. Full-Scale Positive Step

Figure 22. Total Unadjusted Error vs. AVDD/|AVSS|

Figure 25. Full-Scale Negative Step

Rev. B | Page 18 of 52

Page 19

Data Sheet AD5755-1

–5

–10

–15

–20

0 54321

OUTPUT VOLTAGE (mV)

TIME (µs)

09226-039

0x7FFF TO 0x8000 0x8000 TO 0x7FFF AV

= +15V

= –15V +10V RANGE T

= 25ºC

–5

–10

–15

0 7 8 9 105 61 2 3 4

OUTPUT VOLTAGE (µV)

TIME (s)

09226-040

= +15V

= –15V ±10V RANGE T

= 25°C

OUTPUT UNLOADED

300

200

100

–100

–200

–300

0 7 8 9 105 61 2 3 4

OUTPUT VOLTAGE (µV)

TIME (µs)

09226-041

= +15V

= –15V

±10V RANGE TA = 25°C

OUTPUT UNLOADED

25 20

–5

–10

–15

–20

–25

0 25 50 75 100 125

OUTPUT VOLTAGE (mV)

TIME (µs)

09226-043

= +15V

= –15V

= 25°C

60 40

–20

–40

–60

–80

–100

–120

–140

0 2 4 6 8 10

OUTPUT VOLTAGE (mV)

TIME (µs)

09226-044

POC = 1 POC = 0

AVDD = +15V AV

= –15V ±10V RANGE T

= 25°C

INT_ENABLE = 1

–120

–100

–80

–60

–40

–20

10 100 1k 10k 100k 1M 10M

OUT_x

PSRR (dB)

FREQUENCY ( Hz )

09226-045

AVDD = +15V V

BOOST

= +15V

= –15V

= 25°C

Figure 26. Digital-to-Analog Glitch

Figure 27. Peak-to-Peak Noise (0.1 Hz to 10 Hz Bandwidth)

Figure 29. V

Figure 30. V

vs. Time on Power-Up

OUT_x

vs. Time on Output Enable

OUT_x

Figure 28. Peak-to-Peak Noise (100 kHz Bandwidth)

Figure 31. V

PSRR vs. Frequency

OUT_x

Rev. B | Page 19 of 52

Page 20

AD5755-1 Data Sheet

–0.0025

–0.0015

–0.0005

0.0005

0.0015

0.0025

0 10000 20000 30000 40000 50000 60000

INL ERROR (%FSR)

CODE

AVDD = +15V AV

= –15V

= 25°C

4mA TO 2 0mA, EXTERNAL R

SET

4mA TO 2 0mA, EXTERNAL R

SET

, WITH DC-TO-DC CONVERTER

4mA TO 2 0mA, INTERNAL R

SET

4mA TO 2 0mA, INTERNAL R

SET

, WITH DC-TO-DC CONVERTER

09226-149

0 10000 20000 30000 40000 50000 60000

DNL ERROR (LSB)

CODE

AVDD = +15V AV

= –15V

= 25°C

09226-150

–1.0

–0.8

–0.6

–0.4

–0.2

0.2

0.4

0.6

0.8

1.0

4mA TO 2 0mA, EXTERNAL R

SET

4mA TO 2 0mA, EXTERNAL R

SET

, WITH DC-TO-DC CONVERTER

4mA TO 2 0mA, INTERNAL R

SET

4mA TO 2 0mA, INTERNAL R

SET

, WITH DC-TO-DC CONVERTER

0 10000 20000 30000 40000 50000 60000

TOTAL UNADJUS TED ERROR (%FS R)

CODE

09226-151

–0.015

–0.010

–0.005

0.005

0.010

0.015

0.020

0.025

0.030

0.035

AVDD = +15V AV

= –15V

= 25°C

ALL CHANNELS E NABLED

4mA TO 20 m A, EXTERNAL R

SET

4mA TO 20 m A, EXTERNAL R

SET

, WITH DC-TO-DC CONVERTER

4mA TO 20 m A, INTERNAL R

SET

4mA TO 20 m A, INTERNAL R

SET

, WITH DC-TO-DC CONVERTER

–0.0010

–0.0008

–0.0006

–0.0004

–0.0002

0.0002

0.0004

0.0006

0.0008

0.0010

INL ERROR (%FSR)

4mA TO 20mA RANGE M AX INL

0mA TO 20mA RANGE M AX INL

0mA TO 24mA RANGE M AX INL

4mA TO 20mA RANGE M AX INL 0mA TO 24mA RANGE M IN INL

0mA TO 20mA RANGE M IN INL

= +15V

= –15V/0V

–40 –20 0 20 40 60 80 100

TEMPERATURE (°C)

09226-152

–0.0020

–0.0015

–0.0010

–0.0005

0.0005

0.0010

0.0015

0.0020

INL ERROR (%FSR)

4mA TO 20mA RANGE M AX INL

0mA TO 20mA RANGE M AX INL

0mA TO 24mA RANGE M AX INL

4mA TO 20mA RANGE M IN INL 0mA TO 24mA RANGE M IN INL

0mA TO 20mA RANGE M IN INL

–40 –20 0 20 40 60 80 100

TEMPERATURE (°C)

= +15V

= –15V/0V

09226-153

–1.0

–0.8

–0.6

–0.4

–0.2

0.2

0.4

0.6

0.8

1.0

–40 –20 0 20 40 60 80 100

DNL ERROR (L S B)

TEMPERATURE (°C)

= +15V

= –15V/0V ALL RANGES INTERNAL AND E X TERNAL R

SET

DNL ERROR MAX DNL ERROR MI N

09226-154

CURRENT OUTPUTS

Figure 32. Integral Nonlinearity vs. Code

Figure 35. Integral Nonlinearity vs. Temperature, Internal R

SET

Figure 33. Differential Nonlinearity vs. Code

Figure 34. Total Unadjusted Error vs. Code

Figure 36. Integral Nonlinearity vs. Temperature, External R

SET

Figure 37. Differential Nonlinearity vs. Temperature

Rev. B | Page 20 of 52

Page 21

Data Sheet AD5755-1

–0.08

–0.07

–0.06

–0.05

–0.04

–0.03

–0.02

–0.01

0.01

0.02

0.03

TOTAL UNADJSUTED ERROR (%FSR)

–40 –20 0 20 40 60 80 100

TEMPERATURE (°C)

AVDD = +15V AV

= –15V/0V

4mA TO 20mA INT E RNAL R

SET

4mA TO 20mA EXT E RNAL R

SET

0mA TO 20mA INT E RNAL R

SET

0mA TO 20mA EXT E RNAL R

SET

0mA TO 24mA EXT E RNAL R

SET

0mA TO 24mA INT E RNAL R

SET

09226-155

–0.08

–0.07

–0.06

–0.05

–0.04

–0.03

–0.02

–0.01

0.01

0.02

0.03

FULL-S CALE ERROR (%FS R)

–40 –20 0 20 40 60 80 100

TEMPERATURE (°C)

= +15V

= –15V/0V

4mA TO 20mA INT E RNAL R

SET

4mA TO 20mA EXT E RNAL R

SET

0mA TO 20mA INT E RNAL R

SET

0mA TO 20mA EXT E RNAL R

SET

0mA TO 24mA EXT E RNAL R

SET

0mA TO 24mA INT E RNAL R

SET

09226-157

–0.020

–0.015

–0.010

–0.005

0.005

0.010

0.015

0.020

OFFSET ERROR (%FSR)

–40 –20 0 20 40 60 80 100

TEMPERATURE (°C)

4mA TO 20mA INT E RNAL R

SET

4mA TO 20mA EXT E RNAL R

SET

0mA TO 20mA INT E RNAL R

SET

0mA TO 20mA EXT E RNAL R

SET

0mA TO 24mA EXT E RNAL R

SET

0mA TO 24mA INT E RNAL R

SET

AVDD = +15V AV

= –15V/0V

09226-158

–0.06

–0.05

–0.04

–0.03

–0.02

–0.01

0.01

0.02

GAIN ERROR ( %FSR)

–40 –20 0 20 40 60 80 100

TEMPERATURE (°C)

4mA TO 20mA INT E RNAL R

SET

4mA TO 20mA EXT E RNAL R

SET

0mA TO 20mA INT E RNAL R

SET

0mA TO 20mA EXT E RNAL R

SET

0mA TO 24mA EXT E RNAL R

SET

0mA TO 24mA INT E RNAL R

SET

= +15V

= –15V/0V

09226-159

–0.0020

–0.0015

–0.0010

–0.0005

0.0005

0.0010

0.0015

0.0020

0.0025

10 15 20 25 30

INL ERROR (%FSR)

SUPPLY (V)

4mA TO 20mA RANGE M AX INL

4mA TO 20mA RANGE M IN INL

= 25°C

= –26.4V FOR AV

> +26.4V

09226-056

–0.0020

–0.0025

–0.0015

–0.0010

–0.0005

0.0005

0.0010

0.0015

15 20 25 30

INL ERROR (%FSR)

SUPPLY (V)

4mA TO 20mA RANGE M AX INL

4mA TO 20mA RANGE M IN INL

= 25°C

= –26.4V FOR AV

> +26.4V

09226-057

Figure 38. Total Unadjusted Error vs. Temperature

Figure 39. Full Scale Error vs. Temperature

Figure 41. Gain Error vs. Temperature

Figure 42. Integral Nonlinearity Error vs. AVDD/|AVSS|,

Over Supply, External R

SET

Figure 40. Offset Error vs. Temperature

Figure 43. Integral Nonlinearity Error vs. AVDD/|AVSS|,

Over Supply, Internal R

SET

Rev. B | Page 21 of 52

Page 22

AD5755-1 Data Sheet

–1.0

–0.8

–0.6

–0.4

–0.2

0.2

0.4

0.6

0.8

1.0

10 15 20 25 30

DNL ERROR (L S B)

SUPPLY (V)

DNL ERROR MAX DNL ERROR MI N

09226-162

AVSS = –26.4V FOR AVDD > +26.4V

ALL RANGES INTERNAL AND E X TERNAL R

SET

TA = 25°C

0.002

0.004

0.006

0.008

0.010

0.012

10 15 20 25 30

TOTAL UNADJUSTED ERROR ( %FSR)

SUPPLY (V)

4mA TO 20mA RANGE M AX TUE 4mA TO 20mA RANGE M IN TUE T

= 25°C

= –26.4V FOR AVDD > +26.4V

09226-060

10 15 20 25 30

TOTAL UNADJUSTED ERROR ( %FSR)

SUPPLY (V)

4mA TO 20mA RANGE M AX TUE 4mA TO 20mA RANGE M IN TUE T

= 25°C

= –26.4V FO R AV

> +26.4V

–0.020

–0.018

–0.016

–0.014

–0.012

–0.010

–0.008

–0.006

–0.004

–0.002

09226-061

0 2015105

CURRENT (µA)

TIME (µs)

09226-062

= +15V

= –15V

= 25°C

LOAD

= 300Ω

–10

–8

–6

–4

–2

0 1 2 3 4 5 6

CURRENT (µA)

TIME (µs)

09226-063

AVDD = +15V AV

= –15V

= 25°C

LOAD

= 300Ω

INT_EN = 1

OUTPUT CURRE NT (mA)

–0.50 –0.25 0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00

TIME (ms)

0mA TO 24mA RANGE

1kΩ LOAD

= 410kHz INDUCTOR = 10µ H ( X AL4040-103) AV

= 5V

= 25°C

09226-167

OUT

BOOST

Figure 44. Differential Nonlinearity Error vs. AVDD

Figure 45. Total Unadjusted Error vs. AVDD, External R

Figure 47. Output Current vs. Time on Power-Up

SET

Figure 48. Output Current vs. Time on Output Enable

Figure 46. Total Unadjusted Error vs. AVDD, Internal R

SET

Figure 49. Output Current and V

Settling Time with DC-to-DC

BOOST_x

Converter (See Figure 80)

Rev. B | Page 22 of 52

Page 23

Data Sheet AD5755-1

OUTPUT CURRE NT (mA)

–0.25 0 0.25 0.50 0.75 1.00 1.25 1.50 1.75

TIME (ms)

09226-168

OUT

, TA = –40°C

OUT

, T

= +25°C

OUT

, T

= +105°C

0mA TO 24mA RANGE

1kΩ LOAD

= 410kHz INDUCTOR = 10µ H ( X AL4040-103) AV

= 5V

OUTPUT CURRE NT (mA)

–0.25 0 0.25 0.50 0.75 1.00 1.25 1.50 1.75

TIME (ms)

09226-169

OUT

, AV

= 4.5V

OUT

, AV

= 5.0V

OUT

, AV

= 5.5V

0mA TO 24mA RANGE

1kΩ LOAD

= 410kHz INDUCTOR = 10µ H ( X AL4040-103) T

= 25°C

–10

–8

–6

–4

–2

0 2 4 6 8 10 12 14

CURRENT (AC COUPLED) (µA)

TIME (µs)

AVCC = 5V

= 410kHz

INDUCTOR = 10µH (XAL4040-103)

0mA TO 24 m A RANGE

1kΩ LOAD

EXTERNAL R

SET

TA = 25°C

20mA OUTPUT 10mA OUTPUT

09226-170

0 5 10 15 20

HEADROOM VOLTAGE (V)

CURRENT (mA)

09226-067

0mA TO 24mA RANGE

1kΩ LOAD

= 410kHz INDUCTOR = 10µ H ( X AL4040-103) T

= 25°C

–120

–100

–80

–60

–40

–20

10 100 1k 10k 100k 1M 10M

OUT_x

PSRR (dB)

FREQUENCY ( Hz )

09226-068

AVDD = +15V V

BOOST

= +15V

= –15V

= 25°C

Figure 50. Output Current Settling with DC-to-DC Converter vs. Time and

Temperature (See Figure 80)

Figure 51. Output Current Settling with DC-to-DC Converter vs. Time and

(See Figure 80)

Figure 53. DC-to-DC Converter Headroom vs. Output Current (See Figure 80)

Figure 54. I

PSRR vs. Frequency

OUT_x

Figure 52. Output Current vs. Time with DC-to-DC Converter (See Figure 80)

Rev. B | Page 23 of 52

Page 24

AD5755-1 Data Sheet

0 2420161284

BOOST_x

EFFICIENCY (%)

CURRENT (mA)

09226-016

0mA TO 24mA RANGE

1kΩ LOAD

EXTERNAL R

SET

= 410kHz INDUCTOR = 10µ H ( X AL4040-103) T

= 25°C

= 4.5V

= 5V

= 5.5V

–40 10040 60 80200–20

BOOST_x

EFFICIENCY (%)

TEMPERATURE (°C)

09226-01709226-017

0mA TO 24mA RANGE

1kΩ LOAD

EXTERNAL R

SET

AVCC = 5V

= 410kHz

INDUCTOR = 10µ H ( X AL4040-103)

20mA

0 2420161284

OUT_x

EFFICIENCY (%)

CURRENT (mA)

09226-018

0mA TO 24mA RANGE

1kΩ LOAD

EXTERNAL R

SET

= 410kHz INDUCTOR = 10µ H ( X AL4040-103) T

= 25°C

= 4.5V

= 5V

= 5.5V

–40 10040 60 80200–20

OUT_x

EFFICIENCY (%)

TEMPERATURE (°C)

09226-019

0mA TO 24mA RANGE

1kΩ LOAD

EXTERNAL R

SET

AVCC = 5V

= 410 kHz

INDUCTOR = 10µ H ( X AL4040-103)

20mA

0.1

0.2

0.3

0.4

0.5

0.6

–40 –20 0 20 40 60 80 100

SWITCH RE S ISTANCE (Ω)

TEMPERATURE (°C)

09226-123

DC-TO-DC BLOCK

Figure 55. Efficiency at V

Figure 56. Efficiency at V

vs. Output Current (See Figure 80)

BOOST_x

vs. Temperature (See Figure 80)

BOOST_x

Figure 58. Output Efficiency vs. Temperature (See Figure 80)

Figure 59. Switch Resistance vs. Temperature

Figure 57. Output Efficiency vs. Output Current (See Figure 80)

Rev. B | Page 24 of 52

Page 25

Data Sheet AD5755-1

–2

0 0.2 0.4 0.6 0.8 1.0 1.2

VOLTAGE (V)

TIME (ms)

09226-010

REF

OUT

TA = 25°C

–1

–2

–3

0 2 4 6 8 10

REFOUT (µV)

TIME (s)

09226-011

= 15V

= 25°C

150

100

–50

–100

–150

0 5 10 15 20

REFOUT (µV)

TIME (ms)

09226-012

= 15V

= 25°C

5.0000

5.0005

5.0010

5.0015

5.0020

5.0025

5.0030

5.0035

5.0040

5.0045

5.0050

–40 –20 0 20 40 60 80 100

REFOUT (V)

TEMPERATURE (°C)

30 DEVICES SHOWN AV

= 15V

09226-163

5.002

5.001

5.000

4.999

4.998

4.997

4.996

4.995 0 2 4 6 8 10

REFOUT (V)

LOAD CURRENT ( mA)

09226-014

= 15V

= 25°C

5.00000

4.99995

4.99990

4.99980

4.99985

4.99975

4.99970

4.99965

4.99960 10 15 20

25 30

REFOUT (V)

AVDD (V)

09226-015

TA = 25°C

REFERENCE

Figure 60. REFOUT Turn-On Transient

Figure 61. REFOUT Output Noise (0.1 Hz to 10 Hz Bandwidth)

Figure 63. REFOUT vs. Temperature (When the AD5755-1 is soldered onto a PCB, the reference shifts due to thermal shock on the package. The average output voltage shift is −4 mV. Measurement of these parts after seven days shows that the outputs typically shift back 2 mV toward their initial values.

This second shift is due to the relaxation of stress incurred during soldering.)

Figure 64. REFOUT vs. Load Current

Figure 62. REFOUT Output Noise (100 kHz Bandwidth)

Figure 65. REFOUT vs. Supply

Rev. B | Page 25 of 52

Page 26

AD5755-1 Data Sheet

450

400

350

300

250

200

150

100

0 1 2 3 4 5

(µA)

SDIN VOLTAGE (V)

09226-007

= 5V

= 25°C

8 6 4 2 0

–12

–10

–8

–6

–4

–2

10 15 20 25 30

CURRENT (mA)

VOLTAGE (V)

09226-008

= 25°C

OUT

= 0V

OUTPUT UNLOADED

CURRENT (mA)

VOLTAGE (V)

09226-009

TA = 25°C I

OUT

= 0mA

10 15 20 25 30

13.4

13.3

13.2

13.1

13.0

12.9

12.8

12.7

12.6 –40 –20 0 20 40 60 80 100

FREQUENCY (MHz)

TEMPERATURE (°C)

09226-020

DVCC = 5.5V

14.4

14.2

14.0

13.8

13.6

13.4

13.2

13.0

2.5 3.0 3.5 4.0 4.5 5.0 5.5

FREQUENCY (MHz)

VOLTAGE (V)

09226-021

= 5.5V

= 25°C

GENERAL

Figure 66. DICC vs. Logic Input Voltage

Figure 67. AIDD/AISS vs. AVDD/|AVSS|

Figure 69. Internal Oscillator Frequency vs. Temperature

Figure 70. Internal Oscillator Frequency vs. DVCC Supply Voltage

Figure 68. AIDD vs. AVDD

Rev. B | Page 26 of 52

Page 27

Data Sheet AD5755-1

TERMINOLOGY

Relative Accuracy or Integral Nonlinearity (INL)

For the DAC, relative accuracy, or integral nonlinearity, is a measure of the maximum deviation, in LSBs, from the best fit line through the DAC transfer function. A typical INL vs. code plot is shown in Figure 8.

Differential Nonlinearity (DNL)

Differential nonlinearity (DNL) is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ±1 LSB maximum ensures monotonicity. This DAC is guaranteed monotonic by design. A typical DNL vs. code plot is shown in Figure 9.

Monotonicity

A DAC is monotonic if the output either increases or remains constant for increasing digital input code. The AD5755-1 is monotonic over its full operating temperature range.

Negative Full-Scale Error/Zero-Scale Error

Negative full-scale error is the error in the DAC output voltage when 0x0000 (straight binary coding) is loaded to the DAC register.

Zero-Scale TC

This is a measure of the change in zero-scale error with a change in temperature. Zero-scale error TC is expressed in ppm FSR/°C.

Bipolar Zero Error

Bipolar zero error is the deviation of the analog output from the ideal half-scale output of 0 V when the DAC register is loaded with 0x8000 (straight binary coding).

Bipolar Zero TC

Bipolar zero TC is a measure of the change in the bipolar zero error with a change in temperature. It is expressed in ppm FSR/°C.

Offset Error

In voltage output mode, offset error is the deviation of the analog output from the ideal quarter-scale output when in bipolar output ranges and the DAC register is loaded with 0x4000 (straight binary coding).

In current output mode, offset error is the deviation of the analog output from the ideal zero-scale output when all DAC registers are loaded with 0x0000.

Gain Error

This is a measure of the span error of the DAC. It is the deviation in slope of the DAC transfer characteristic from the ideal, expressed in % FSR.

Gain TC

This is a measure of the change in gain error with changes in temperature. Gain TC is expressed in ppm FSR/°C.

Rev. B | Page 27 of 52

Full-Scale Error

Full-scale error is a measure of the output error when full-scale code is loaded to the DAC register. Ideally, the output should be full-scale − 1 LSB. Full-scale error is expressed in percent of full-scale range (% FSR).

Full-Scale TC

Full-scale TC is a measure of the change in full-scale error with changes in temperature and is expressed in ppm FSR/°C.

Total Unadjusted Error

Total unadjusted error (TUE) is a measure of the output error taking all the various errors into account, including INL error, offset error, gain error, temperature, and time. TUE is expressed in % FSR.

DC Crosstalk

This is the dc change in the output level of one DAC in response to a change in the output of another DAC. It is measured with a full-scale output change on one DAC while monitoring another DAC, which is at midscale.

Current Loop Compliance Voltage

The maximum voltage at the I current is equal to the programmed value.

Voltage Reference Thermal Hysteresis

Voltage reference thermal hysteresis is the difference in output voltage measured at +25°C compared to the output voltage measured at +25°C after cycling the temperature from +25°C to

−40°C to +105°C and back to +25°C. The hysteresis is specified for the first and second temperature cycles and is expressed in ppm.

Output Voltage Settling Time

Output voltage settling time is the amount of time it takes for the output to settle to a specified level for a full-scale input change. A plot of settling time is shown in Figure 24, Figure 50, and Figure 51.

Slew Rate

The slew rate of a device is a limitation in the rate of change of the output voltage. The output slewing speed of a voltageoutput digital-to-analog converter is usually limited by the slew rate of the amplifier used at its output. Slew rate is measured from 10% to 90% of the output signal and is given in V/µs.

Power-On Glitch Energy

Power-on glitch energy is the impulse injected into the analog output when the AD5755-1 is powered-on. It is specified as the area of the glitch in nV-sec. See Figure 29 and Figure 47.

Digital-to-Analog Glitch Impulse

Digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the DAC register changes state, but the output voltage remains constant. It is normally specified as the area of the glitch in nV-sec and is measured when the digital input code is changed by 1 LSB at the major carry transition (~0x7FFF to 0x8000). See Figure 26.

pin for which the output

OUT_x

Page 28

AD5755-1 Data Sheet

CCCC

LOAD

AIAV

OUT

CCCC

xBOOSTOUT

AIAVVI×

Glitch Impulse Peak Amplitude

Glitch impulse peak amplitude is the peak amplitude of the impulse injected into the analog output when the input code in the DAC register changes state. It is specified as the amplitude of the glitch in mV and is measured when the digital input code is changed by 1 LSB at the major carry transition (~0x7FFF to 0x8000). See Figure 26.

Digital Feedthrough

Digital feedthrough is a measure of the impulse injected into the analog output of the DAC from the digital inputs of the DAC but is measured when the DAC output is not updated. It is specified in nV-sec and measured with a full-scale code change on the data bus.

DAC-to-DAC Crosstalk

DAC-to-DAC crosstalk is the glitch impulse transferred to the output of one DAC due to a digital code change and a subsequent output change of another DAC. This includes both digital and analog crosstalk. It is measured by loading one of the DACs with a full-scale code change (all 0s to all 1s and vice versa) with LDAC

low and monitoring the output of another DAC. The

energy of the glitch is expressed in nV-sec.

Power Supply Rejection Ratio (PSRR)

PSRR indicates how the output of the DAC is affected by changes in the power supply voltage.

Reference TC

Reference TC is a measure of the change in the reference output voltage with a change in temperature. It is expressed in ppm/°C.

Line Regulation

Line regulation is the change in reference output voltage due to a specified change in supply voltage. It is expressed in ppm/V.

Load Regulation

Load regulation is the change in reference output voltage due to a specified change in load current. It is expressed in ppm/mA.

DC-to-DC Converter Headroom

This is the difference between the voltage required at the current output and the voltage supplied by the dc-to-dc converter. See Figure 53.

Output Efficiency

This is defined as the power delivered to a channel’s load vs. the power delivered to the channel’s dc-to-dc input.

Efficiency at V

BOOST_x

This is defined as the power delivered to a channel’s V

BOOS T_x

supply vs. the power delivered to the channel’s dc-to-dc input. The V

quiescent current is considered part of the dc-to-

BOOS T_x

dc converter’s losses.

Rev. B | Page 28 of 52

Page 29

Data Sheet AD5755-1

12-BIT R-2R L ADDE R FOUR MSBs DECODED INTO

15 EQUAL SEGMENTS

2R 2R

S0 S1 S7/S11 E1 E2 E15

OUT

2R 2R 2R 2R 2R

09226-069

09226-070

RANGE

SCALING

DAC

OUT_X

SHORT FAULT

SENSE_x

OUT_x

09226-071

16-BIT

DAC

BOOST_x

OUT_x

SET

THEORY OF OPERATION

The AD5755-1 is a quad, precision digital-to-current loop and voltage output converter designed to meet the requirements of industrial process control applications. It provides a high precision, fully integrated, low cost, single-chip solution for generating current loop and unipolar/bipolar voltage outputs. The current ranges available are 0 mA to 20 mA, 0 mA to 24 mA, and 4 mA to 20 mA. The voltage ranges available are 0 V to 5 V, ± 5 V, 0 V to 10 V, and ±10 V. The current and voltage outputs are available on separate pins, and only one is active at any one time. The desired output configuration is user selectable via the DAC control register.

On-chip dynamic power control minimizes package power dissipation in current mode.

DAC ARCHITECTURE

The DAC core architecture of the AD5755-1 consists of two matched DAC sections. A simplified circuit diagram is shown in Figure 71. The four MSBs of the 16-bit data-word are decoded to drive 15 switches, E1 to E15. Each of these switches connects one of 15 matched resistors to either ground or the reference buffer output. The remaining 12 bits of the data-word drive Switch S0 to Switch S11 of a 12-bit voltage mode R-2R ladder network.

Figure 71. DAC Ladder Structure

The voltage output from the DAC core is either converted to a current (see Figure 73), which is then mirrored to the supply rail so that the application simply sees a current source output, or it is buffered and scaled to output a software selectable unipolar or bipolar voltage range (see Figure 72). Both the voltage and current outputs are supplied by V output on separate pins and cannot be output simultaneously. A channel’s current and voltage output pins can be tied together.

Figure 72. Voltage Output

. The current and voltage are

BOOST_x

Figure 73. Voltage-to-Current Conversion Circuitry

Voltage Output Amplifier

The voltage output amplifier is capable of generating both unipolar and bipolar output voltages. It is capable of driving a load of 1 kΩ in parallel with 1 µF (with an external compensation capacitor) to AGND. The source and sink capabilities of the output amplifier are shown in Figure 23. The slew rate is

1.9 V/µs with a full-scale settling time of 16 µs (10 V step). If remote sensing of the load is not required, connect +V directly to V

OUT_x

. + V

must stay within ±3.0 V of V

SENSE_x

OUT_x

for correct operation.

Driving Large Capacitive Loads

The voltage output amplifier is capable of driving capacitive loads of up to 2 µF with the addition of a 220 pF nonpolarized compensation capacitor on each channel. Care should be taken to choose an appropriate value of compensation capacitor. This capacitor, while allowing the AD5755-1 to drive higher capacitive loads and reduce overshoot, increases the settling time of the part and, therefore, affects the bandwidth of the system. Without the compensation capacitor, up to 10 nF capacitive loads can be driven. See Table 5 for information on connecting compensation capacitors.

Reference Buffers

The AD5755-1 can operate with either an external or internal reference. The reference input requires a 5 V reference for specified performance. This input voltage is then buffered before it is applied to the DAC.

POWER-ON STATE OF THE AD5755-1

On initial power-up of the AD5755-1, the power-on reset circuit powers up in a state that is dependent on the power-on condition (POC) pin.

Rev. B | Page 29 of 52

If POC = 0, the voltage output and current output channels power up in tristate mode.

If POC = 1, the voltage output channel powers up with a 30 kΩ pull-down resistor to ground, and the current output channel powers up to tristate.

Even though the output ranges are not enabled, the default output range is 0 V to 5 V, and the clear code register is loaded

Page 30

AD5755-1 Data Sheet

OUT_x

DAC

INTERFACE

LOGIC

OUTPUT

I/V AMPLIFIER

LDAC

SDO

SDIN

16-BIT

DAC

REFIN

SYNC

DAC DATA

OFFSET

AND GAIN

CALIBRATION

DAC INPUT

SCLK

09226-072

0000

0001

−2 V

× (32,767/32,768)

with all zeros. This means that if the user clears the part after power-up, the output is actively driven to 0 V (if the channel has been enabled for clear).

After a device power on, or a device reset, it is recommended to wait 100 μs or more before writing to the device to allow time for internal calibrations to take place.

SERIAL INTERFACE

The AD5755-1 is controlled over a versatile 3-wire serial interface that operates at clock rates of up to 30 MHz and is compatible with SPI, QSPI, MICROWIRE, and DSP standards. Data coding is always straight binary.

Input Shift Register

The input shift register is 24 bits wide. Data is loaded into the device MSB first as a 24-bit word under the control of a serial clock input, SCLK. Data is clocked in on the falling edge of SCLK.

If packet error checking, or PEC (see the Device Features section), is enabled, an additional eight bits must be written to the AD5755-1, creating a 32-bit serial interface.

There are two ways in which the DAC outputs can be updated: individual updating or simultaneous updating of all DACs.

Individual DAC Updating

In this mode,

LDAC

is held low while data is being clocked into

the DAC data register. The addressed DAC output is updated on

SYNC

the rising edge of

. See Table 3 and Figure 3 for timing

information.

Simultaneous Updating of All DACs

In this mode,

LDAC

is held high while data is being clocked

into the DAC data register. Only the first write to each channel’s

LDAC

DAC data register is valid after

LDAC

quent writes while

is still held high are ignored, though

is brought high. Any subse-

they are loaded into the DAC data register. All the DAC outputs are updated by taking

LDAC

low after

SYNC

is taken high.

Figure 74. Simplified Serial Interface of Input Loading Circuitry

for One DAC Channel

TRANSFER FUNCTION

Table 6 shows the input code to ideal output voltage relationship for the AD5755-1 for straight binary data coding of the ±10 V output range.

Table 6. Ideal Output Voltage to Input Code Relationship

Digital Input

Straight Binary Data Coding Analog Output

MSB LSB V

1111 1111 1111 1111 +2 V 1111 1111 1111 1110 +2 V 1000 0000 0000 0000 0 V

0000 0000 0000 0000 −2 V

OUT

× (32,767/32,768)

REF

× (32,766/32,768)

REF

Rev. B | Page 30 of 52

Page 31

Data Sheet AD5755-1

REGISTERS

Table 7 shows an overview of the registers for the AD5755-1.

Table 7. Data, Control, and Readback Registers for the AD5755-1

Data

DAC Data Register (×4) Used to write a DAC code to each DAC channel. AD5755-1 data bits = D15 to D0. There are four DAC

data registers, one per DAC channel.

Gain Register (×4) Used to program gain trim, on a per channel basis. AD5755-1 data bits = D15 to D0. There are four

gain registers, one per DAC channel.

Offset Register (×4) Used to program offset trim, on a per channel basis. AD5755-1 data bits = D15 to D0. There are four

offset registers, one per DAC channel.

Clear Code Register (×4) Used to program clear code on a per channel basis. AD5755-1 data bits = D15 to D0. There are four

clear code registers, one per DAC channel.

Control

Main Control Register Used to configure the part for main operation. Sets functions such as status readback during write,

enables output on all channels simultaneously, powers on all dc-to-dc converter blocks simultaneously, and enables and sets conditions of the watchdog timer. See the Device Features section for more details.

Software Register Has three functions. Used to perform a reset, to toggle the user bit, and, as part of the watchdog timer

feature, to verify correct data communication operation.

Slew Rate Control Register (×4) Used to program the slew rate of the output. There are four slew rate control registers, one per

channel.

DAC Control Register (×4) These registers are used to control the following:

Set the output range, for example, 4 mA to 20 mA, 0 V to 10 V. Set whether an internal/external sense resistor is used. Enable/disable a channel for CLEAR. Enable/disable overrange. Enable/disable internal circuitry on a per channel basis. Enable/disable output on a per channel basis. Power on dc-to-dc converters on a per channel basis. There are four DAC control registers, one per DAC channel.

DC-to-DC Control Register Use to set the dc-to-dc control parameters. Can control dc-to-dc maximum voltage, phase, and

frequency.

Readback

Status Register This contains any fault information, as well as a user toggle bit.

Rev. B | Page 31 of 52

Page 32

AD5755-1 Data Sheet

PROGRAMMING SEQUENCE TO WRITE/ENABLE THE OUTPUT CORRECTLY

To correctly write to and set up the part from a power-on condition, use the following sequence:

1. Perform a hardware or software reset after initial power-on.

2. The dc-to-dc converter supply block must be configured.

Set the dc-to-dc switching frequency, maximum output voltage allowed, and the phase that the four dc-to-dc channels clock at.

3. Configure the DAC control register on a per channel basis.

The output range is selected, and the dc-to-dc converter block is enabled (DC_DC bit). Other control bits can be configured at this point. Set the INT_ENABLE bit; however, the output enable bit (OUTEN) should not be set.

4. Write the required code to the DAC data register. This

implements a full DAC calibration internally. Allow at least 200 μs before Step 5 for reduced output glitch.

5. Write to the DAC control register again to enable the

output (set the OUTEN bit).

A flowchart of this sequence is shown in Figure 75.

CHANGING AND REPROGRAMMING THE RANGE

When changing between ranges, the same sequence as described in the Programming Sequence to Write/Enable the Output Correctly section should be used. It is recommended to set the range to its zero point (can be midscale or zero scale) prior to disabling the output. Because the dc-to-dc switching frequency, maximum voltage, and phase have already been selected, there is no need to reprogram these. A flowchart of this sequence is shown in Figure 76.

CHANNEL’S O UTPUT IS ENABLED.

STEP 1: WRITE TO CHANNEL’S DAC DATA

STEP 2: WRITE TO DAC CO NTROL REGISTER.

DISABLE T HE O U T P UT (OUTEN = 0) , AND SET THE NE W O U T PU T RANGE. KEEP THE DC_DC BIT AND THE INT_E NAB L E BIT SET.

STEP 3: WRI T E VALUE TO T HE DAC DATA REGISTER.

POWER ON.

STEP 1: PERF ORM A SOFTWARE/HARDWARE RESET.

STEP 2: WRIT E TO DC-TO-DC CONTROL REG ISTER TO

SET DC-TO- DC CLOCK FREQUENCY, PHASE, AND MAXIMUM VO LTAGE.

STEP 3: WRIT E TO DAC CONTROL REGISTER. SEL E CT

THE DAC CHANNEL AND OUTPUT RANG E . SET THE DC_DC BIT AND OT HE R CONTROL BITS AS REQUIRED. SET T HE INT_ENABLE BI T BUT DO NOT SELECT THE OUTE N BIT.

STEP 4: WRI TE TO EACH/ ALL DAC DATA REGISTERS.

ALLOW AT LEAS T 200µs BETWEEN STEP 3 AND STEP 5 FOR REDUCED OUT P UT GLITCH.

STEP 5: WRIT E TO DAC CONTROL REGISTER. RELOAD

SEQUENCE AS IN STEP 3 ABOV E. THIS TIME SELECT THE OUTEN BIT TO ENABLE THE OUTPUT.

09226-073

Figure 75. Programming Sequence for Enabling the Output Correctly

STEP 4: WRITE TO DAC CO NTROL REGISTER.

RELOAD SEQUENCE AS IN STEP 2ABOVE. THIS TIME SELECT THE OUTEN BITTO ENABLE THE OUTPUT.

09226-074

Figure 76. Steps for Changing the Output Range

Rev. B | Page 32 of 52

Page 33

Data Sheet AD5755-1

a control register is written to. If a control register is selected, a further decode

DATA REGISTERS

The input register is 24 bits wide. When PEC is enabled, the input register is 32 bits wide, with the last eight bits corresponding to the PEC code (see the Packet Error Checking section for more information on PEC). When writing to a data register, the format in Table 8 must be used.

Table 8. Writing to a Data Register

MSB LSB D23 D22 D21 D20 D19 D18 D17 D16 D15 to D0

R/W DUT_AD1 DUT_AD0 DREG2 DREG1 DREG0 DAC_AD1 DAC_AD0 Data

Table 9. Input Register Decode

Bit Description

R/W Indicates a read from or a write to the addressed register. DUT_AD1, DUT_AD0 Used in association with the external pins, AD1 and AD0, to determine which AD5755-1 device is being

addressed by the system controller.

0 0 Addresses part with Pin AD1 = 0, Pin AD0 = 0 0 1 Addresses part with Pin AD1 = 0, Pin AD0 = 1 1 0 Addresses part with Pin AD1 = 1, Pin AD0 = 0 1 1 Addresses part with Pin AD1 = 1, Pin AD0 = 1 DREG2, DREG1, DREG0 Selects whether a data register or

DAC_AD1, DAC_AD0 These bits are used to decode the DAC channel.

0 0 DAC A 0 1 DAC B 1 0 DAC C 1 1 DAC D X X These are don’t cares if they are not relevant to the operation being performed.

DUT_AD1 DUT_AD0 Function

of CREG bits (see Table 17) is required to select the particular control register, as follows.

DREG2 DREG1 DREG0 Function

0 0 0 Write to DAC data register (individual channel write) 0 1 0 Write to gain register 0 1 1 Write to gain register (all DACs) 1 0 0 Write to offset register 1 0 1 Write to offset register (all DACs) 1 1 0 Write to clear code register 1 1 1 Write to a control register

DAC_AD1 DAC_AD0 DAC Channel/Register Address

DAC Data Register

When writing to the AD5755-1 DAC data registers, D15 to D0 are used for DAC data bits. Table 10 shows the register format and Table 9 describes the function of Bit D23 to Bit D16.

Table 10. Programming the DAC Data Registers

MSB LSB D23 D22 D21 D20 D19 D18 D17 D16 D15 to D0

R/W DUT_AD1 DUT_AD0 DREG2 DREG1 DREG0 DAC_AD1 DAC_AD0 DAC data

Rev. B | Page 33 of 52

Page 34

AD5755-1 Data Sheet

… … … … … … … … …

Gain Register

The 16-bit gain register, as shown in Table 11, allows the user to adjust the gain of each channel in steps of 1 LSB. This is done by setting the DREG[2:0] bits to 010. It is possible to write the same gain code to all four DAC channels at the same time by setting the DREG[2:0] bits to 011. The gain register coding is straight binary as shown in Table 12. The default code in the gain register is 0xFFFF. In theory, the gain can be tuned across the full range of the output. In practice, the maximum recommended gain trim is about 50% of programmed range to maintain accuracy. See the Digital Offset and Gain Control section for more information.

Offset Register

The 16-bit offset register, as shown in Tabl e 13, allows the user to adjust the offset of each channel by −32,768 LSBs to +32,767 LSBs

Table 11. Programming the Gain Register

R/W

0 Device address 0 1 0 DAC channel address Gain adjustment

DUT_AD1 DUT_AD0 DREG2 DREG1 DREG0 DAC_AD1 DAC_AD0 D15 to D0

in steps of 1 LSB. This is done by setting the DREG[2:0] bits to

100. It is possible to write the same offset code to all four DAC channels at the same time by setting the DREG[2:0] bits to 101. The offset register coding is straight binary as shown in Tabl e 14. The default code in the offset register is 0x8000, which results in zero offset programmed to the output. See the Digital Offset and Gain Control section for more information.

Clear Code Register

The 16-bit clear code register allows the user to set the clear value of each channel as shown in Table 15. It is possible, via software, to enable or disable on a per channel basis which channels are cleared when the CLEAR pin is activated. The default clear code is 0x0000. See the Asynchronous Clear section for more information.

Table 12. Gain Register

Gain Adjustment G15 G14 G13 G12 to G4 G3 G2 G1 G0

+65,535 LSBs 1 1 1 1 1 1 1 1 +65,534 LSBs 1 1 1 1 1 1 0 0

1 LSB 0 0 0 0 0 0 0 1 0 LSBs 0 0 0 0 0 0 0 0

Table 13. Programming the Offset Register

R/W

0 Device address 1 0 0 DAC channel address Offset adjustment

DUT_AD1 DUT_AD0 DREG2 DREG1 DREG0 DAC_AD1 DAC_AD0 D15 to D0

Table 14. Offset Register Options

Offset Adjustment OF15 OF14 OF13 OF12 to OF4 OF3 OF2 OF1 OF0

+32,767 LSBs 1 1 1 1 1 1 1 1 +32,766 LSBs 1 1 1 1 1 1 0 0 … … … … … … … … … No Adjustment (Default) 1 0 0 0 0 0 0 0 … … … … … … … … …

−32,767 LSBs 0 0 0 0 0 0 0 0

−32,768 LSBs 0 0 0 0 0 0 0 0

Table 15. Programming the Clear Code Register

R/W

0 Device address 1 1 0 DAC channel address Clear code

DUT_AD1 DUT_AD0 DREG2 DREG1 DREG0 DAC_AD1 DAC_AD0 D15 to D0

Rev. B | Page 34 of 52

Page 35

Data Sheet AD5755-1

0 0 1

POC

STATREAD

EWD

WD1

WD0

ShtCctLim

OUTEN_ALL

DCDC_ALL

CONTROL REGISTERS

When writing to a control register, the format shown in Table 16 must be used. See Tab l e 9 for information on the configuration of Bit D23 to Bit D16. The control registers are addressed by setting the DREG[2:0] bits to 111 and then setting the CREG[2:0] bits to the appropriate decode address for that register, according to Table 17. These CREG bits select among the various control registers.

Table 16. Writing to a Control Register

MSB LSB D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 to D0

R/W DUT_AD1 DUT_AD0 1 1 1 DAC_AD1 DAC_AD0 CREG2 CREG1 CREG0 Data

Table 17. Register Access Decode

CREG2 (D15) CREG1 (D14) CREG0 (D13) Function

0 0 0 Slew rate control register (one per channel) 0 0 1 Main control register 0 1 0 DAC control register (one per channel) 0 1 1 DC-to-dc control register 1 0 0 Software register

Main Control Register

The main control register options are shown in Ta b l e 18 and Table 19. See the Device Features section for more information on the features controlled by the main control register.

Table 18. Programming the Main Control Register

MSB LSB

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 to D0

X = don’t care.

Table 19. Main Control Register Functions

Bit Description

POC The POC bit determines the state of the voltage output channels during normal operation. Its default value is 0.

POC = 0. The output goes to the value set by the POC hardware pin when the voltage output is not enabled (default). POC = 1. The output goes to the opposite value of the POC hardware pin if the voltage output is not enabled.

STATREAD Enable status readback during a write. See the Device Features section.

STATREAD = 1, enable. STATREAD = 0, disable (default).

EWD Enable watchdog timer. See the Device Features section for more information.

EWD = 1, enable watchdog. EWD = 0, disable watchdog (default).

WD1, WD0 Timeout select bits. Used to select the timeout period for the watchdog timer.

0 0 5 0 1 10 1 0 100 1 1 200 ShtCctLim Programmable short-circuit limit on the V

OUTEN_ALL Enables the output on all four DACs simultaneously.

DCDC_ALL When set, powers up the dc-to-dc converter on all four channels simultaneously.

WD1 WD0 Timeout Period (ms)

pin in the event of a short-circuit condition.

OUT_x

0 = 16 mA (default). 1 = 8 mA.

Do not use the OUTEN_ALL bit when using the OUTEN bit in the DAC control register.

To power down the dc-to-dc converters, all channel outputs must first be disabled. Do not use the DCDC_ALL bit when using the DC_DC bit in the DAC control register.

Rev. B | Page 35 of 52

Page 36

AD5755-1 Data Sheet

INT_ENABLE

Powers up the dc-to-dc converter, DAC, and internal amplifiers for the selected channel. Does not enable the output. Can

OVRNG

Enables 20% overrange on voltage output channel only. No current output overrange available.

Output Range Selected

DAC Control Register

The DAC control register is used to configure each DAC channel. The DAC control register options are shown in Ta b l e 20 and Table 21.

Table 20. Programming DAC Control Register

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

0 1 0 X1 X1 X1 X1 INT_ENABLE CLR_EN OUTEN RSET DC_DC OVRNG R2 R1 R0

X = don’t care.

Table 21. DAC Control Register Functions

Bit Description

only be done on a per channel basis. It is recommended to set this bit and allow a >200 µs delay before enabling the output because this results in a reduced output enable glitch. See

CLR_EN Per channel clear enable bit. Selects if this channel clears when the CLEAR pin is activated.

CLR_EN = 1, channel clears when the part is cleared. CLR_EN = 0, channel does not clear when the part is cleared (default).

OUTEN Enables/disables the selected output channel.

OUTEN = 1, enables the channel. OUTEN = 0, disables the channel (default).

RSET Selects an internal or external current sense resistor for the selected DAC channel.

RSET = 0, selects the external resistor (default). RSET = 1, selects the internal resistor.

DC_DC Powers the dc-to-dc converter on the selected channel.

DC_DC = 1, power up the dc-to-dc converter. DC_DC = 0, power down the dc-to-dc converter (default). This allows per channel dc-to-dc converter power-up/power-down. To power down the dc-to-dc converter, the OUTEN and INT_ENABLE bits must also be set to 0. All dc-to-dc converters can also be powered up simultaneously using the DCDC_ALL bit in the main control register.

Figure 30 and Figure 48 for plots of this glitch.

OVRNG = 1, enabled. OVRNG = 0, disabled (default).

R2, R1, R0 Selects the output range to be enabled.

0 0 0 0 V to 5 V voltage range (default). 0 0 1 0 V to 10 V voltage range. 0 1 0 ±5 V voltage range. 0 1 1 ±10 V voltage range. 1 0 0 4 mA to 20 mA current range. 1 0 1 0 mA to 20 mA current range. 1 1 0 0 mA to 24 mA current range.

Rev. B | Page 36 of 52

Page 37

Data Sheet AD5755-1

Bit

Description

11 = Channel A, Channel B, Channel C, and Channel D clock 90° out of phase from each other.

Software Register

The software register has three functions. It allows the user to perform a software reset to the part. It can be used to set the user toggle bit, D11, in the status register. It is also used as part of the watchdog feature when it is enabled. This feature is useful to ensure that communication has not been lost between the MCU and the AD5755-1 and that the datapath lines are working properly (that is, SDIN, SCLK, and

SYNC

Table 22. Programming the Software Register

MSB LSB

D15 D14 D13 D12 D11 to D0

1 0 0 User program Reset code/SPI code

Table 23. Software Register Functions

Bit Description

User Program This bit is mapped to Bit D11 of the status register. When this bit is set to 1, Bit D11 of the status register is

set to 1. Likewise, when D12 is set to 0, Bit D11 of the status register is also set to zero. This feature can be used to ensure that the SPI pins are working correctly by writing a known bit value to this register and

reading back the corresponding bit from the status registe r. Reset Code/SPI Code Reset code Writing 0x555 to D[11:0] performs a reset of the AD5755-1. SPI code If the watchdog timer feature is enabled, 0x195 must be written to the software register

Option Description

(D11 to D0) within the programmed timeout period.

When the watchdog feature is enabled, the user must write 0x195 to the software register within the timeout period. If this command is not received within the timeout period, the ALERT pin signals a fault condition. This is only required when the watchdog timer function is enabled.

DC-to-DC Control Register

The dc-to-dc control register allows the user control over the dc-to-dc switching frequency and phase, as well as the maximum allowable dc-to-dc output voltage. The dc-to-dc control register options are shown in Table 24 and Table 25.

Table 24. Programming the DC-to-DC Control Register

MSB LSB

D15 D14 D13 D12 to D7 D6 D5 to D4 D3 to D2 D1 to D0

0 1 1 X1 DC-DC Comp DC-DC phase DC-DC Freq DC-DC MaxV

X = don’t care.

Table 25. DC-to-DC Control Register Options

DC-DC Comp Selects between an internal and external compensation resistor for the dc-to-dc converter. See the DC-to-DC Converter

Compensation Capacitors and AICC Supply Requirements—Slewing sections in the Device Features section for more information. 0 = selects the internal 150 kΩ compensation resistor (default). 1 = bypasses the internal compensation resistor for the dc-to-dc converter. In this mode, an external dc-to-dc compensation resistor must be used; this is placed at the COMP capacitor to ground. Typically, a ~50 kΩ resistor is recommended.

DC-DC Phase User programmable dc-to-dc converter phase (between channels).

00 = all dc-to-dc converters clock on the same edge (default). 01 = Channel A and Channel B clock on the same edge, Channel C and Channel D clock on opposite edges. 10 = Channel A and Channel C clock on the same edge, Channel B and Channel D clock on opposite edges.

DC-DC Freq DC-to-dc switching frequency; these are divided down from the internal 13 MHz oscillator (see Figure 69 and Figure 70).

00 = 250 ± 10% kHz. 01 = 410 ± 10% kHz (default). 10 = 650 ± 10% kHz.

DC-DC MaxV Maximum allowed V

00 = 23 V + 1 V/−1.5 V (default). 01 = 24.5 V ± 1 V. 10 = 27 V ± 1 V. 11 = 29.5 V ± 1V.

voltage supplied by the dc-to-dc converter.

BOOST_x

pin in series with the 10 nF dc-to-dc compensation

DCDC_x

Rev. B | Page 37 of 52

Page 38

AD5755-1 Data Sheet

0 0 0 1 1

Read DAC D data register

1 0 1 0 1

DAC B slew rate control register

Slew Rate Control Register

This register is used to program the slew rate control for the selected DAC channel. This feature is available on both the current and voltage outputs. The slew rate control is enabled/ disabled and programmed on a per channel basis. See Table 26 and the Digital Slew Rate Control section for more information.

READBACK OPERATION

Readback mode is invoked by setting the R/W bit = 1 in the

serial input register write. See Tab l e 27 for the bits associated with a readback operation. The DUT_AD1 and DUT_AD0 bits, in association with Bits RD[4:0], select the register to be read. The remaining data bits in the write sequence are don’t cares. During the next SPI transfer (see Figure 4), the data appearing on the SDO output contains the data from the previously addressed register. This second SPI transfer should either be a

Table 26. Programming the Slew Rate Control Register

D15 D14 D13 D12 D11 to D7 D6 to D3 D2 to D0

0 0 0 SREN X1 SR_CLOCK SR_STEP

X = don’t care.

request to read yet another register on a third data transfer or a no operation command. The no operation command for DUT Address 00 is 0x1CE000, for other DUT addresses, Bits D22 and D21 are set accordingly.

Readback Example

To read back the gain register of Device 1, Channel A on the AD5755-1, implement the following sequence:

1. Write 0xA80000 to the AD5755-1 input register. This

configures the AD5755-1 Device Address 1 for read mode with the gain register of Channel A selected. All the data bits, D15 to D0, are don’t cares.

2. Follow with another read command or a no operation

command (0x3CE000). During this command, the data from the Channel A gain register is clocked out on the SDO line.

Table 27. Input Shift Register Contents for a Read Operation

D23 D22 D21 D20 D19 D18 D17 D16 D15 to D0

R/W DUT_AD1 DUT_AD0 RD4 RD3 RD2 RD1 RD0 X1

X = don’t care.

Table 28. Read Address Decoding

RD4 RD3 RD2 RD1 RD0 Function

0 0 0 0 0 Read DAC A data register 0 0 0 0 1 Read DAC B data register 0 0 0 1 0 Read DAC C data register

0 0 1 0 0 Read DAC A control register 0 0 1 0 1 Read DAC B control register 0 0 1 1 0 Read DAC C control register 0 0 1 1 1 Read DAC D control register 0 1 0 0 0 Read DAC A gain register 0 1 0 0 1 Read DAC B gain register 0 1 0 1 0 Read DAC C gain register 0 1 0 1 1 Read DAC D gain register 0 1 1 0 0 Read DACA offset register 0 1 1 0 1 Read DAC B offset register 0 1 1 1 0 Read DAC C offset register 0 1 1 1 1 Read DAC D offset register 1 0 0 0 0 Clear DAC A code register 1 0 0 0 1 Clear DAC B code register 1 0 0 1 0 Clear DAC C code register 1 0 0 1 1 Clear DAC D code register 1 0 1 0 0 DAC A slew rate control register

1 0 1 1 0 DAC C slew rate control register 1 0 1 1 1 DAC D slew rate control register 1 1 0 0 0 Read status register 1 1 0 0 1 Read main control register 1 1 0 1 0 Read dc-to-dc control register

Rev. B | Page 38 of 52

Page 39

Data Sheet AD5755-1

MSB

LSB

Fault

This bit is set if a fault is detected on the I

pin.

Fault

This bit is set if a fault is detected on the I

pin.

Status Register

The status register is a read only register. This register contains any fault information as a well as a ramp active bit and a user toggle bit. When the STATREAD bit in the main control register is set, the status register contents can be read back on

Table 29. Decoding the Status Register

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

DC-

DCD

DCC

DCB

DCA

User toggle

PEC error

Ramp active

Over TEMP

Table 30. Status Register Options

Bit Description

DC-DCD In current output mode, this bit is set on Channel D if the dc-to-dc converter cannot maintain compliance (it may be

reaching its V

voltage). In this case, the I

MAX

fault bit is also set. See the DC-to-DC Converter V

OUT_D

for more information on this bit’s operation under this condition. In voltage output mode, this bit is set if, on Channel D, the dc-to-dc converter is unable to regulate to 15 V as expected.

FAULT

When this bit is set, it does not result in the

pin going high.

DC-DCC In current output mode, this bit is set on Channel C if the dc-to-dc converter cannot maintain compliance (it may be

reaching its V

voltage). In this case, the I

MAX

fault bit is also set. See the DC-to-DC Converter V

OUT_C

more information on this bit’s operation under this condition. In voltage output mode, this bit is set if, on Channel C, the dc-to-dc converter is unable to regulate to 15 V as expected.

FAULT

When this bit is set, it does not result in the

pin going high.

DC-DCB In current output mode, this bit is set on Channel B if the dc-to-dc converter cannot maintain compliance (it may be

reaching its V

voltage). In this case, the I

MAX

fault bit is also set. See the DC-to-DC Converter V

OUT_B

more information on this bit’s operation under this condition. In voltage output mode, this bit is set if, on Channel B, the dc-to-dc converter is unable to regulate to 15 V as expected.

When this bit is set, it does not result in the

FAULT

pin going high.

DC-DCA In current output mode, this bit is set on Channel A if the dc-to-dc converter cannot maintain compliance (it may be

reaching its V

voltage). In this case, the I

MAX

fault bit is also set. See the DC-to-DC Converter V

OUT_A

more information on this bit’s operation under this condition. In voltage output mode, this bit is set if, on Channel A, the dc-to-dc converter is unable to regulate to 15 V as expected.

FAULT

When this bit is set, it does not result in the

pin going high. User Toggl e User toggle bit. This bit is set or cleared via the software register. This can be used to verify data communications if needed. PEC Error Denotes a PEC error on the last data-word received over the SPI interface. Ramp Active This bit is set while any one of the output channels is slewing (slew rate control is enabled on at least one channel). Over TEMP This bit is set if the AD5755-1 core temperature exceeds approximately 150°C. V

Fault This bit is set if a fault is detected on the V

OUT_D

Fault This bit is set if a fault is detected on the V

OUT_C

Fault This bit is set if a fault is detected on the V

OUT_B

Fault This bit is set if a fault is detected on the V

OUT_A

OUT_D

OUT_C

Fault This bit is set if a fault is detected on the I

OUT_B

Fault This bit is set if a fault is detected on the I

OUT_A

OUT_D

OUT_C

OUT_B

OUT_A

OUT_D

OUT_C

OUT_B

OUT_A

pin. pin. pin. pin.

pin. pin.

the SDO pin during every write sequence. Alternatively, if the STATREAD bit is not set, the status register can be read using the normal readback operation.

OUT_D

fault

OUT_C

fault

OUT_B

fault

OUT_A

fault

OUT_D

fault

MAX

OUT_C

fault

Functionality section

Functionality section for

OUT_B

fault

OUT_A

fault

Rev. B | Page 39 of 52

Page 40

AD5755-1 Data Sheet

09226-075

DAC

INPUT

DAC

DAC DATA REGISTER

)1(−++

×= C

DCode

rDACRegiste

DEVICE FEATURES

OUTPUT FAULT

The AD5755-1 is equipped with a open-drain output allowing several AD5755-1 devices to be connected together to one pull-up resistor for global fault detection. The

FAULT

pin is forced active by any one of the

following fault scenarios:

• The voltage at I

attempts to rise above the compliance

OUT_x

range due to an open-loop circuit or insufficient power supply voltage. The internal circuitry that develops the fault output avoids using a comparator with windowed limits because this requires an actual output error before

FAULT

the

output becomes active. Instead, the signal is generated when the internal amplifier in the output stage has less than approximately 1 V of remaining drive capability. Thus, the

FAULT

the compliance limit is reached.

• A short is detected on a voltage output pin. The short-

circuit current is limited to 16 mA or 8 mA, which is programmable by the user. If using the AD5755-1 in unipolar supply mode, a short-circuit fault may be generated if the output voltage is below 50 m V.

• An interface error is detected due to a PEC failure. See the

Packet Error Checking section.

• If the core temperature of the AD5755-1 exceeds

approximately 150°C.

The V

OUT_x

fault, I

fault, PEC error, and over TEMP bits

OUT_x

of the status register are used in conjunction with the output to inform the user which one of the fault conditions

FAULT

caused the

output to be activated.

VOLTAGE OUTPUT SHORT-CIRCUIT PROTECTION

Under normal operation, the voltage output sinks/sources up to 12 mA and maintains specified operation. The maximum output current or short-circuit current is programmable by the user and can be set to 16 mA or 8 mA. If a short circuit is detected, the

FAULT

goes low and the relevant V

in the status register is set.

DIGITAL OFFSET AND GAIN CONTROL

Each DAC channel has a gain (M) and offset (C) register, which allow trimming out of the gain and offset errors of the entire signal chain. Data from the DAC data register is operated on by a digital multiplier and adder controlled by the contents of the M and C registers. The calibrated DAC data is then stored in the DAC input register.

FAULT

pin, an active low

output activates slightly before

FAULT

fault bit

OUT_x

Figure 77. Digital Offset and Gain control

Although Figure 77 indicates a multiplier and adder for each channel, there is only one multiplier and one adder in the device, and they are shared among all four channels. This has implications for the update speed when several channels are updated at once (see Table 3).

Each time data is written to the M or C register, the output is not automatically updated. Instead, the next write to the DAC channel uses these M and C values to perform a new calibration and automatically updates the channel.

The output data from the calibration is routed to the DAC input register. This is then loaded to the DAC as described in the Theory of Operation section. Both the gain register and the offset register have 16 bits of resolution. The correct method to calibrate the gain/offset is to first calibrate out the gain and then calibrate the offset.

The value (in decimal) that is written to the DAC input register can be calculated by

(1)

where:

D is the code loaded to the DAC channel’s input register. M is the code in the gain register (default code = 2 C is the code in the offset register (default code = 2

– 1).

STATUS READBACK DURING A WRITE

The AD5755-1 has the ability to read back the status register contents during every write sequence. This feature is enabled via the STATREAD bit in the main control register. This allows the user to continuously monitor the status register and act quickly in the case of a fault.

When status readback during a write is enabled, the contents of the 16-bit status register (see Tab l e 30) are output on the SDO pin, as shown in Figure 5.

The AD5755-1 powers up with this feature disabled. When this is enabled, the normal readback feature is not available, except for the status register. To read back any other register, clear the STATREAD bit first before following the readback sequence. STATREAD can be set high again after the register read.

Rev. B | Page 40 of 52

Page 41

Data Sheet AD5755-1

SDIN

SYNC

SCLK

UPDATE ON SY NC HIGH

MSB

D23

LSB

24-BIT DATA

24-BIT DATA TRANSFER—NO E RROR CHECKING

SDIN

FAULT

SYNC

SCLK

UPDATE ON SY NC HIGH

ONLY IF ERROR CHECK PASSE D

FAULT PIN GOES LOW

IF ERROR CHE CK FAILS

MSB

D31

LSB

D7 D0

24-BIT DATA 8-BIT CRC

32-BIT DATA TRANSFER WI TH ERROR CHECKING

09226-180

ASYNCHRONOUS CLEAR

CLEAR is an active high, edge-sensitive input that allows the output to be cleared to a preprogrammed 16-bit code. This code is user programmable via a per channel 16-bit clear code register.

For a channel to clear, that channel must be enabled to be cleared via the CLR_EN bit in the channel’s DAC control register. If the channel is not enabled to be cleared, then the output remains in its current state independent of the CLEAR pin level.

When the CLEAR signal is returned low, the relevant outputs remain cleared until a new value is programmed.

PACKET ERROR CHECKING

To verify that data has been received correctly in noisy environments, the AD5755-1 offers the option of packet error checking based on an 8-bit cyclic redundancy check (CRC-8). The device controlling the AD5755-1 should generate an 8-bit frame check sequence using the polynomial

C(x) = x

This is added to the end of the data-word, and 32 bits are sent to the AD5755-1 before taking 32-bit frame, it performs the error check when If the check is valid, the data is written to the selected register. If the error check fails, the error bit in the status register is set. After reading the status register, faults), and the PEC error bit is cleared automatically.

+ x2 + x1 + 1

SYNC

high. If the AD5755-1 sees a

FAULT

pin goes low and the PEC

FAULT

returns high (assuming there are no other

SYNC

goes high.

disabled, the user can still use the normal readback operation to monitor status register activity with PEC.

WATCHDOG TIMER

When enabled, an on-chip watchdog timer generates an alert signal if 0x195 has not been written to the software register within the programmed timeout period. This feature is useful to ensure that communication has not been lost between the MCU and the AD5755-1 and that these datapath lines are working properly (that is, SDIN, SCLK, and

SYNC

). If 0x195 is not received by the software register within the timeout period, the ALERT pin signals a fault condition. The ALERT signal is active high and can be connected directly to the CLEAR pin to enable a clear in the event that communication from the MCU is lost.

The watchdog timer is enabled, and the timeout period (5 ms, 10 ms, 100 ms, or 200 ms) is set in the main control register (see Table 18 and Ta b l e 19).

OUTPUT ALERT

The AD5755-1 is equipped with an ALERT pin. This is an active high CMOS output. The AD5755-1 also has an internal watchdog timer. When enabled, it monitors SPI communications. If 0x195 is not received by the software register within the timeout period, the ALERT pin goes active.

INTERNAL REFERENCE

The AD5755-1 contains an integrated +5 V voltage reference with initial accuracy of ±5 mV maximum and a temperature drift coefficient of ±10 ppm maximum. The reference voltage is buffered and externally available for use elsewhere within the system.

Figure 78. PEC Timing

The PEC can be used for both transmit and receive of data packets. If status readback during a write is enabled, the PEC values returned during the status readback during a write operation should be ignored. If status readback during a write is

EXTERNAL CURRENT SETTING RESISTOR

Referring to Figure 73, R of the voltage-to-current conversion circuitry. The stability of the output current value over temperature is dependent on the stability of the value of R stability of the output current over temperature, an external 15 kΩ low drift resistor can be connected to the R AD5755-1 to be used instead of the internal resistor, R1. The external resistor is selected via the DAC control register (see Table 20).

Table 1 outlines the performance specifications of the AD5755-1 with both the internal R resistor. Using an external R performance over the internal R R

SET

performance depends on the absolute value and temperature coefficient of the resistor used. This directly affects the gain error of the output, and thus the total unadjusted error. To arrive at the gain/TUE error of the output with a particular external R resistor, add the percentage absolute error of the R directly to the gain/TUE error of the AD5755-1 with the external R

Rev. B | Page 41 of 52

is an internal sense resistor as part

SET

. As a method of improving the

SET

pin of the

SET_x

resistor and an external, 15 kΩ R

SET

resistor allows for improved

SET

resistor option. The external

SET

resistor specification assumes an ideal resistor; the actual

resistor

SET

resistor, shown in Ta b l e 1 (expressed in % FSR).

SET

Page 42

AD5755-1 Data Sheet

09226-076

HART MODEM

OUTPUT

CHARTx

1111

0.5

010

SizeLSBFrequencyClockUpdateSizeStep

ChangeOutput

TimeSlew

××

HART

The AD5755-1 has four CHART pins, one corresponding to each output channels. A HART signal can be coupled into these pins. The HART signal appears on the corresponding current output, if the output is enabled. Tabl e 31 shows the recommended input voltages for the HART signal at the CHART pin. If these voltages are used, the current output should meet the HART amplitude specifications. Figure 79 shows the recommended circuit for attenuating and coupling in the HART signal.

Table 31. CHART Input Voltage to HART Output Current

SET

Internal R External R

CHART Input Voltage

150 mV p-p 1 mA p-p

SET

170 mV p-p 1 mA p-p

SET

Current Output (HART)

Table 32. Slew Rate Update Clock Options

SR_CLOCK Update Clock Frequency (Hz)1

0000 64 k 0001 32 k 0010 16 k 0011 8 k 0100 4 k 0101 2 k 0110 1 k 0111 500 1000 250 1001 125 1010 64 1011 32 1100 16 1101 8 1110 4

Figure 79. Coupling HART Signal

A minimum capacitance of C1 + C2 is required to ensure that the 1.2 kHz and 2.2 kHz HART frequencies are not significantly attenuated at the output. The recommended values are C1 = 22 nF, C2 = 47 nF.

Digitally controlling the slew rate of the output is necessary to meet the analog rate of change requirements for HART.

DIGITAL SLEW RATE CONTROL

The slew rate control feature of the AD5755-1 allows the user to control the rate at which the output value changes. This feature is available on both the current and voltage outputs. With the slew rate control feature disabled, the output value changes at a rate limited by the output drive circuitry and the attached load. To reduce the slew rate, this can be achieved by enabling the slew rate control feature. With the feature enabled via the SREN bit of the slew rate control register (see Table 26), the output, instead of slewing directly between two values, steps digitally at a rate defined by two parameters accessible via the slew rate control register, as shown in Tab l e 26.

The parameters are SR_CLOCK and SR_STEP. SR_CLOCK defines the rate at which the digital slew is updated, for example, if the selected update rate is 8 kHz, the output updates every 125 µs. In conjunction with this, SR_STEP defines by how much the output value changes at each update. Together, both parameters define the rate of change of the output value. Tabl e 32 and Tab l e 33 outline the range of values for both the SR_CLOCK and SR_STEP parameters.

These clock frequencies are divided down from the 13 MHz internal

oscillator. See Table 1, Figure 69, and Figure 70.

Table 33. Slew Rate Step Size Options

SR_STEP Step Size (LSBs)

000 1 001 2

011 16 100 32 101 64 110 128 111 256

The following equation describes the slew rate as a function of the step size, the update clock frequency, and the LSB size:

where:

Slew Time is expressed in seconds. Output Change is expressed in amps for I

or volts for V

OUT_x

When the slew rate control feature is enabled, all output changes occur at the programmed slew rate (see the DC-to-DC Converter Settling Time section for additional information). For example, if the CLEAR pin is asserted, the output slews to the clear value at the programmed slew rate (assuming that the clear channel is enabled to be cleared). If a number of channels are enabled for slew, care must be taken when asserting the CLEAR pin. If one of the channels is slewing when CLEAR is asserted, other channels may change directly to their clear values not under slew rate control. The update clock frequency for any given value is the same for all output ranges. The step size, however, varies across output ranges for a given value of step size because the LSB size is different for each output range.

Rev. B | Page 42 of 52

Page 43

Data Sheet AD5755-1

DCDC

4.7µF

FILTER

0.1µF

FILTER

SWx

BOOST_X

≥10µF

10Ω

10µH

09226-077

Symbol

Component

Value

Manufacturer

GRM32ER71H475KA88L

4.7 µF

Murata

28.6

28.7

28.8

28.9

29.0

29.1

29.2

29.3

29.4

29.5

29.6

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0

BOOST_x

VOLTAGE (mV)

TIME (ms)

MAX

0mA TO 24 m A RANGE, 24m A OUTPUT OUTPUT UNLOADED

DC-DCMaxV = 11 (29.5V)

DC_DC BIT

09226-183

DC-DCx BIT = 0

DC-DCx BIT = 1

= 410kHz

= 25°C

POWER DISSIPATION CONTROL

The AD5755-1 contains integrated dynamic power control using a dc-to-dc boost converter circuit, allowing reductions in power consumption from standard designs when using the part in current output mode.

In standard current input module designs, the load resistor values can range from typically 50 Ω to 750 Ω. Output module systems must source enough voltage to meet the compliance voltage requirement across the full range of load resistor values. For example, in a 4 mA to 20 mA loop when driving 20 mA, a compliance voltage of >15 V is required. When driving 20 mA into a 50 Ω load, only 1 V compliance is required.

The AD5755-1 circuitry senses the output voltage and regulates this voltage to meet compliance requirements plus a small headroom voltage. The AD5755-1 is capable of driving up to 24 mA through a 1 kΩ load.

DC-TO-DC CONVERTERS

The AD5755-1 contains four independent dc-to-dc converters. These are used to provide dynamic control of the V voltage for each channel (see Figure 73). Figure 80 shows the discreet components needed for the dc-to-dc circuitry, and the following sections describe component selection and operation of this circuitry.

BOOST

supply

output disabled, the converter regulates the V +15 V (±5%). In current output mode with the output disabled, the converter regulates the V

Within a channel, the V V

supply so that the outputs of the I

BOOST_x

OUT_x

supply to 7.4 V (±5%).

BOOST_x

and I

stages share a common

OUT_x

can be tied together.

DC-to-DC Converter Settling Time

When in current output mode, the settling time for a step greater than ~1 V (I

OUT

× R

) is dominated by the settling time of the

LOA D

dc-to-dc converter. The exception to this is when the required voltage at the I

pin plus the compliance voltage is below

OUT_x

7.4 V (±5%). A typical plot of the output settling time can be found in Figure 49. This plot is for a 1 kΩ load. The settling time for smaller loads is faster. The settling time for current steps less than 24 mA is also faster.

DC-to-DC Converter V

The maximum V

BOOST_x

Functionality

MAX

voltage is set in the dc-to-dc control register (23 V, 2 4.5 V, 27 V, or 29.5 V; see Table 25). On reaching this maximum voltage, the dc-to-dc converter is disabled, and the V V

BOOST_x

voltage is allowed to decay by ~0.4 V. After the

BOOST_x

voltage has decayed by ~0.4 V, the dc-to-dc converter is reenabled, and the voltage ramps up again to V required. This operation is shown in

Figure 81.

BOOST_x

and V

MAX

supply to

stages

OUT_x

, if still

Figure 80. DC-to-DC Circuit

Table 34. Recommended DC-to-DC Components

XAL4040-103 10 µH Coilcraft®

DCDC

PMEG3010BEA 0.38 VF NXP

DCDC

It is recommended to place a 10 Ω, 100 nF low-pass RC filter after C

. This consumes a small amount of power but

DCDC

reduces the amount of ripple on the V

DC-to-DC Converter Operation

The on-board dc-to-dc converters use a constant frequency, peak current mode control scheme to step up an AV

4.5 V to 5.5 V to drive the AD5755-1 output channel. These are designed to operate in discontinuous conduction mode (DCM) with a duty cycle of <90% typical. Discontinuous conduction mode refers to a mode of operation where the inductor current goes to zero for an appreciable percentage of the switching cycle. The dc-to-dc converters are nonsynchronous; that is, they require an external Schottky diode.

DC-to-DC Converter Output Voltage

When a channel current output is enabled, the converter regulates the V

BOOST_x

whichever is greater (see Figure 53 for a plot of headroom supplied vs. output current). In voltage output mode with the

supply to 7.4 V (±5%) or (I

BOOST_x

OUT

× R

supply.

LOA D

input of

+ Headroom),

Rev. B | Page 43 of 52

Figure 81. Operation on Reaching V

MAX

As can be seen in Figure 81, the DC-DCx bit in the status register asserts when the AD5755-1 is ramping to the V deasserts when the voltage is decaying to V

MAX

− ~0.4 V.

MAX

value but

DC-to-DC Converter On-Board Switch

The AD5755-1 contains a 0.425 Ω internal switch. The switch current is monitored on a pulse by pulse basis and is limited to

0.8 A peak current.

DC-to-DC Converter Switching Frequency and Phase

The AD5755-1 dc-to-dc converter switching frequency can be selected from the dc-to-dc control register. The phasing of the channels can also be adjusted so that the dc-to-dc converter can clock on different edges (see Table 25). For typical applications, a 410 kHz frequency is recommended. At light loads (low output

Page 44

AD5755-1 Data Sheet

BOOSTOUT

AVEfficiency

OutPower

BOOST

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0 0.5 1.0 1.5 2.0 2.5

OUT_x

CURRENT (mA )/V

BOOST_x

VOLTAGE (V)

CURRENT (A)

TIME (ms)

OUT

BOOST

0mA TO 24mA RANGE

1kΩ LOAD

= 410kHz

INDUCTOR = 10µ H ( X AL4040-103)

= 25°C

09226-184

current and small load resistor), the dc-to-dc converter enters a pulse-skipping mode to minimize switching power dissipation.

DC-to-DC Converter Inductor Selection

For typical 4 mA to 20 mA applications, a 10 µH inductor (such as the XAL4040-103 from Coilcraft), combined with a switching frequency of 410 kHz, allows up to 24 mA to be driven into a load resistance of up to 1 kΩ with an AV

5.5 V. It is important to ensure that the inductor is able to handle the peak current without saturating, especially at the maximum ambient temperature. If the inductor enters into saturation mode, it results in a decrease in efficiency. The inductance value also drops during saturation and may result in the dc-to-dc converter circuit not being able to supply the required output power.

DC-to-DC Converter External Schottky Selection

The AD5755-1 requires an external Schottky for correct operation. Ensure that the Schottky is rated to handle the maximum reverse breakdown expected in operation and that the rectifier maximum junction temperature is not exceeded. The diode average current is approximately equal to the I current. Diodes with larger forward voltage drops result in a decrease in efficiency.

DC-to-DC Converter Compensation Capacitors

As the dc-to-dc converter operates in DCM, the uncompensated transfer function is essentially a single-pole transfer function. The pole frequency of the transfer function is determined by the dc-to-dc converter’s output capacitance, input and output voltage, and output load. The AD5755-1 uses an external capacitor in conjunction with an internal 150 kΩ resistor to compensate the regulator loop. Alternatively, an external compensation resistor can be used in series with the compensation capacitor, by setting the DC-DC Comp bit in the dc-to-dc control register. In this case, a ~50 kΩ resistor is recommended. A description of the advantages of this can be found in the AI section. For typical applications, a 10 nF dc-to-dc compensation capacitor is recommended.

DC-to-DC Converter Input and Output Capacitor Selection

The output capacitor affects ripple voltage of the dc-to-dc converter and indirectly limits the maximum slew rate at which the channel output current can rise. The ripple voltage is caused by a combination of the capacitance and equivalent series resistance (ESR) of the capacitor. For the AD5755-1, a ceramic capacitor of 4.7 µF is recommended for typical applications. Larger capacitors or paralleled capacitors improve the ripple at the expense of reduced slew rate. Larger capacitors also impact the AV AI at the output of the dc-to-dc converter should be >3 µF under all operating conditions.

The input capacitor provides much of the dynamic current required for the dc-to-dc converter and should be a low ESR

supplies current requirements while slewing (see the

Supply Requirements—Slewing section). This capacitance

Supply Requirements—Slewing

supply of 4.5 V to

component. For the AD5755-1, a low ESR tantalum or ceramic capacitor of 10 µF is recommended for typical applications. Ceramic capacitors must be chosen carefully because they can exhibit a large sensitivity to dc bias voltages and temperature. X5R or X7R dielectrics are preferred because these capacitors remain stable over wider operating voltage and temperature ranges. Care must be taken if selecting a tantalum capacitor to ensure a low ESR value.

AICC SUPPLY REQUIREMENTS—STATIC

LOAD

The dc-to-dc converter is designed to supply a V

= I

BOOST

OUT

× R

+ Headroom (2)

LOAD

See Figure 53 for a plot of headroom supplied vs. output voltage. This means that, for a fixed load and output voltage, the dc-to-dc converter output current can be calculated by the following formula:

where:

is the output current from I

OUT

is the efficiency at V

BOOST

in amps.

OUT_x

as a fraction (see Figure 55

BOOST_x

and Figure 56).

voltage of

BOOST_x

(3)

AICC SUPPLY REQUIREMENTS—SLEWING

The AICC current requirement while slewing is greater than in static operation because the output power increases to charge the output capacitance of the dc-to-dc converter. This transient current can be quite large (see Figure 82), although the methods described in the Reducing AI can reduce the requirements on the AV AI

current can be provided, the AVCC voltage drops. Due to

this AV

drop, the AICC current required to slew increases

further. This means that the voltage at AV Equation 3) and the V

BOOST_x

may never reach its intended value. Because this AV common to all channels, this may also affect other channels.

Figure 82. AI

Rev. B | Page 44 of 52

Current vs. Time for 24 mA Step Through 1 kΩ Load

with Internal Compensation Resistor

Current Requirements section

supply. If not enough

drops further (see

voltage, and thus the output voltage,

voltage is

Page 45

Data Sheet AD5755-1

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

CURRENT (A)

0mA TO 24mA RANGE

1kΩ LOAD

= 410kHz

INDUCTOR = 10µ H ( X AL4040-103) T

= 25°C

09226-185

0 0.5 1.0 1.5 2.0 2.5

OUT_x

CURRENT (mA )/V

BOOST_x

VOLTAGE (V)

TIME (ms)

OUT

BOOST

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

CURRENT (A)

0mA TO 24mA RANGE

500Ω LOAD

= 410kHz

INDUCTOR = 10µ H ( X AL4040-103)

= 25°C

09226-186

0 0.5 1.0 1.5 2.0 2.5

OUT_x

CURRENT (mA )/V

BOOST_x

VOLTAGE (V)

TIME (ms)

OUT

BOOST

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

CURRENT (A)

0mA TO 24mA RANGE

1kΩ LOAD

= 410kHz

INDUCTOR = 10µ H ( X AL4040-103) T

= 25°C

09226-187

0 1 2 3 4 5 6

OUT_x

CURRENT (mA )/V

BOOST_x

VOLTAGE (V)

TIME (ms)

OUT

BOOST

Reducing AICC Current Requirements

There are two main methods that can be used to reduce the AI

current requirements. One method is to add an external

compensation resistor, and the other is to use slew rate control. Both of these methods can be used in conjunction.

A compensation resistor can be placed at the COMP in series with the 10 nF compensation capacitor. A 51 kΩ external compensation resistor is recommended. This compensation increases the slew time of the current output but eases the AI transient current requirements. Figure 83 shows a plot of AI current for a 24 mA step through a 1 kΩ load when using a 51 kΩ compensation resistor. This method eases the current requirements through smaller loads even further, as shown in Figure 84.

DCDC_x

Figure 84. AI

Current vs. Time for 24 mA Step Through 500 Ω Load

with External 51 kΩ Compensation Resistor

Using slew rate control can greatly reduce the AVCC supplies current requirements, as shown in Figure 85. When using slew rate control, attention should be paid to the fact that the output cannot slew faster than the dc-to-dc converter. The dc-to-dc converter slews slowest at higher currents through large (for example, 1 kΩ) loads. This slew rate is also dependent on the configuration of the dc-to-dc converter. Two examples of the dc-to-dc converter output slew are shown in Figure 83 and Figure 84 (V

corresponds to the dc-to-dc converter’s output

BOOST

voltage).

Figure 83. AI

Current vs. Time for 24 mA Step Through 1 kΩ Load

with External 51 kΩ Compensation Resistor

Figure 85. AI

Current vs. Time for 24 mA Step Through 1 kΩ Load

with Slew Rate Control

Rev. B | Page 45 of 52

Page 46

AD5755-1 Data Sheet

APPLICATIONS INFORMATION

VOLTAGE AND CURRENT OUTPUT RANGES ON THE SAME TERMINAL

When using a channel of the AD5755-1, the current and voltage output pins can be connected to two separate terminals or tied together and connected to a single terminal. There is no conflict with tying the two output pins together because only the voltage output or the current output can be enabled at any one time. When the current output is enabled, the voltage output is in tristate mode, and when the voltage output is enabled, the current output is in tristate mode. For this operation, the POC pin must be tied low and the POC bit in the main control register set to 0, or, if the POC pin is tied high, the POC bit in the main control register must be set to 1 before the current output is enabled.

As shown in the Absolute Maximum Ratings section, the output tolerances are the same for both the voltage and current output pins. The +V leakage into these pins is negligible when in current output mode.

CURRENT OUTPUT MODE WITH INTERNAL R

When using the internal R the output is significantly affected by how many other channels using the internal R these channels. The internal R for all channels enabled with the internal R outputting the same code.

For every channel enabled with the internal R decreases. For example, with one current output enabled using the internal R decreases proportionally as more current channels are enabled; the offset error is 0.056% FSR on each of two channels, 0.029% on each of three channels, and 0.01% on each of four channels.

Similarly, the dc crosstalk when using the internal R tional to the number of current output channels enabled with the internal R 0x8000 and one channel going from zero to full scale, the dc crosstalk is −0.011% FSR. With two channels going from zero to full scale, it is −0.019% FSR, and with all three other channels going from zero to full scale, it is −0.025% FSR.

For the full-scale error measurement in Tabl e 1, all channels are at 0xFFFF. This means that, as any channel goes to zero scale, the full-scale error increases due to the dc crosstalk. For example, with the measured channel at 0xFFFF and three

connections are buffered so that current

SENSE_x

resistor in current output mode,

SET

are enabled and by the dc crosstalk from

SET

specifications in Table 1 are

SET

selected and

SET

, the offset error

SET

, the offset error is 0.075% FSR. This value

SET

is propor-

SET

. For example, with the measured channel at

SET

channels at zero scale, the full-scale error is 0.025%. Similarly, if only one channel is enabled in current output mode with the internal R

, the full-scale error is 0.025% FSR + 0.075% FSR =

SET

0.1% FSR.

PRECISION VOLTAGE REFERENCE SELECTION

To achieve the optimum performance from the AD5755-1 over its full operating temperature range, a precision voltage reference must be used. Thought should be given to the selection of a precision voltage reference. The voltage applied to the reference inputs is used to provide a buffered reference for the DAC cores. Therefore, any error in the voltage reference is reflected in the outputs of the device.

There are four possible sources of error to consider when choosing a voltage reference for high accuracy applications: initial accuracy, temperature coefficient of the output voltage, long term drift, and output voltage noise.

Initial accuracy error on the output voltage of an external reference can lead to a full-scale error in the DAC. Therefore, to minimize these errors, a reference with low initial accuracy error specification is preferred. Choosing a reference with an output trim adjustment, such as the ADR425, allows a system designer to trim system errors out by setting the reference voltage to a voltage other than the nominal. The trim adjustment can be used at any temperature to trim out any error.

Long-term drift is a measure of how much the reference output voltage drifts over time. A reference with a tight long-term drift specification ensures that the overall solution remains relatively stable over its entire lifetime.

The temperature coefficient of a reference’s output voltage affects INL, DNL, and TUE. A reference with a tight temperature coefficient specification should be chosen to reduce the dependence of the DAC output voltage to ambient temperature.

In high accuracy applications, which have a relatively low noise budget, reference output voltage noise must be considered. Choosing a reference with as low an output noise voltage as practical for the system resolution required is important. Precision voltage references such as the ADR435 (XFET design) produce low output noise in the 0.1 Hz to 10 Hz region. However, as the circuit bandwidth increases, filtering the output of the reference may be required to minimize the output noise.

Table 35. Recommended Precision References

Initial Accuracy

Part No.

ADR445 ±2 50 3 2.25 ADR02 ±3 50 3 10 ADR435 ±2 40 3 8 ADR395 ±5 50 9 8 AD586 ±2.5 15 10 4

(mV Maximum)

Long-Term Drift (ppm Typical)

Temperature Drift (ppm/°C Maximum)

0.1 Hz to 10 Hz Noise (µV p-p Typical)

Rev. B | Page 46 of 52

Page 47

LOAD

AD5755-1

BOOST_x

OUT_x

AGND

09226-079

FILTER

0.1µF

10Ω

(FROM

DC-TO-DC

CONVERTER)

DCDC

4.7µF

09226-080

AD5755-1

SYNC SCLK SDIN

LDAC

SPORT_TFS

SPORT_TSCK

SPORT_DTO

GPIO0

ADSP-BF527

Data Sheet AD5755-1

DRIVING INDUCTIVE LOADS

When driving inductive or poorly defined loads, a capacitor may be required between I A 0.01 µF capacitor between I

and AGND to ensure stability.

OUT_x

and AGND ensures stability

OUT_x

of a load of 50 mH. The capacitive component of the load may cause slower settling, although this may be masked by the settling time of the AD5755-1. There is no maximum capacitance limit for the current output of the AD5755-1.

TRANSIENT VOLTAGE PROTECTION

The AD5755-1 contains ESD protection diodes that prevent damage from normal handling. The industrial control environment can, however, subject I/O circuits to much higher transients. To protect the AD5755-1 from excessively high voltage transients, external power diodes and a surge current limiting resistor (R typical value for R resistor (R

) must have appro-priate power ratings.

) are required, as shown in Figure 86. A

is 10 Ω. The two protection diodes and the

Figure 86. Output Transient Voltage Protection

Further protection can be provided using transient voltage suppressors (TVSs), also referred to as transorbs. These components are available as unidirectional suppressors, which protect against positive high voltage transients, and as bidirectional suppressors, which protect against both positive and negative high voltage transients. Transient voltage suppressors are available in a wide range of standoff and breakdown voltage ratings. The TVS should be sized with the lowest breakdown voltage possible while not conducting in the functional range of the current output.

It is recommended that all field connected nodes be protected. The voltage output node can be protected with a similar circuit, where D2 and the transorb are connected to AV age output node, the +V

pin should also be protected with

SENSE_x

. For the volt-

a large value series resistance to the transorb, such as 5 kΩ. In this way, the I

OUT_x

and V

pins can also be tied together and

OUT_x

share the same protection circuitry.

MICROPROCESSOR INTERFACING

Microprocessor interfacing to the AD5755-1 is via a serial bus that uses a protocol compatible with microcontrollers and DSP processors. The communications channel is a 3-wire minimum interface consisting of a clock signal, a data signal, and a latch signal. The AD5755-1 requires a 24-bit data-word with data valid on the falling edge of SCLK.

Rev. B | Page 47 of 52

The DAC output update is initiated on either the rising edge of LDAC

or, if

LDAC

is held low, on the rising edge of

SYNC

contents of the registers can be read using the readback function.

AD5755-1-TO-ADSP-BF527 INTERFACE

The AD5755-1 can be connected directly to the SPORT interface of the ADSP-BF527, an Analog Devices, Inc., Blackfin® DSP. Figure 87 shows how the SPORT interface can be connected to control the AD5755-1.

Figure 87. AD5755-1-to-ADSP-BF527 SPORT Interface

LAYOUT GUIDELINES

Grounding

In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. The printed circuit board on which the AD5755-1 is mounted should be designed so that the analog and digital sections are separated and confined to certain areas of the board. If the AD5755-1 is in a system where multiple devices require an AGND-to-DGND connection, the connection should be made at one point only. The star ground point should be established as close as possible to the device.

The GNDSW referred to as PGND. PGND should be confined to certain areas of the board, and the PGND-to-AGND connection should be made at one point only.

Supply Decoupling

The AD5755-1 should have ample supply bypassing of 10 µF in parallel with 0.1 µF on each supply located as close to the package as possible, ideally right up against the device. The 10 µF capacitors are the tantalum bead type. The 0.1 µF capacitor should have low effective series resistance (ESR) and low effective series inductance (ESL), such as the common ceramic types, which provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching.

Traces

The power supply lines of the AD5755-1 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast switching signals such as clocks should be shielded with digital ground to prevent radiating noise to other parts of the board and should never be run near the reference inputs. A ground line routed between the SDIN and SCLK lines helps reduce crosstalk between them (not required on a multilayer board that has a

and ground connection for th e AVCC supply are

. The

Page 48

AD5755-1 Data Sheet

09226-081

SERIAL CLOCK

OUT

TO SCLK

ENCODE

DECODE

SERIAL DATA

OUT

TO SDIN

ENCODE

DECODE

SYNC OUT

ENCODE

DECODE

CONTROL O UT

ENCODE

DECODE

MICROCONTROLLER

ADuM1400*

*ADDITIONAL PINS O MITTED FO R CL ARITY.

TO SYNC

TO LDAC

separate ground plane, but separating the lines helps). It is essential to minimize noise on the REFIN line because it couples through to the DAC output.

Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This reduces the effects of feedthrough on the board. A microstrip technique is by far the best but not always possible with a double-sided board. In this technique, the component side of the board is dedicated to ground plane, whereas signal traces are placed on the solder side.

DC-to-DC Converters

To achieve high efficiency, good regulation, and stability, a welldesigned printed circuit board layout is required.

Follow these guidelines when designing printed circuit boards (see Figure 80):

• Keep the low ESR input capacitor, C

, close to AVCC and

PGND.

• Keep the high current path from C

, to SWX and PGND as short as possible.

DCDC

• Keep the high current path from C

rectifier, D

, to the output capacitor, C

DCDC

through the inductor,

through L

DCDC

and the

DCDC

, as short as

possible.

• Keep high current traces as short and as wide as possible.

The path from C

through the inductor, L

, to SWX and

DCDC

PGND should be able to handle a minimum of 1 A.

• Place the compensation components as close as possible to

COMP

DCDC_x

• Avoid routing high impedance traces near any node

connected to SW

or near the inductor to prevent radiated

noise injection.

GALVANICALLY ISOLATED INTERFACE

In many process control applications, it is necessary to provide an isolation barrier between the controller and the unit being controlled to protect and isolate the controlling circuitry from any hazardous common-mode voltages that may occur. The Analog Devices iCoupler® products can provide voltage isolation in excess of 2.5 kV. The serial loading structure of the AD57551 makes it ideal for isolated interfaces because the number of interface lines is kept to a minimum. Figure 88 shows a 4channel isolated interface to the AD5755-1 using an

ADuM1400. For more information, visit www.analog.com.

Figure 88. Isolated Interface

Rev. B | Page 48 of 52

Page 49

Data Sheet AD5755-1

COMPLI ANT TO JEDEC STANDARDS MO-220-V M M D- 4

080108-C

0.25 MIN

TOP VIEW

8.75

BSC SQ

9.00

BSC SQ

0.50

0.40

0.30

0.50

BSC

0.20 REF

12° MAX

0.80 MAX

0.65 TYP

1.00

0.85

0.80

7.50 REF

0.05 MAX

0.02 NOM

0.60 MAX

0.60

MAX

EXPOSED PAD

(BOTTOM VIEW)

SEATING

PLANE

PIN 1 INDICATOR

7.25

7.10 SQ

6.95

PIN 1

INDICATOR

0.30

0.23

0.18

FOR PROP E R CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CO NFIGURATI ON AND FUNCTIO N DE S CRIPTIONS SECTION OF THIS DATA SHEET.

AD5755-1ACPZ-REEL7

−40°C to +105°C

64-lead LFCSP_VQ

CP-64-3

OUTLINE DIMENSIONS

Figure 89. 64-

Lead Lead Frame Chip Scale Package [LFCSP_VQ]

9 mm × 9 mm Body, Very Thin Quad

(CP-64-3)

Dimensions shown in millimeters

ORDERING GUIDE

Model1 Resolution (Bits) Temperature Range Package Description Package Option

AD5755-1ACPZ 16 −40°C to +105°C 64-lead LFCSP_VQ CP-64-3

EVAL-AD5755-1SDZ Evaluation Board

Z = RoHS Compliant Part.

Rev. B | Page 49 of 52

Page 50

AD5755-1 Data Sheet

NOTES

Rev. B | Page 50 of 52

Page 51

Data Sheet AD5755-1

NOTES

Rev. B | Page 51 of 52

Page 52

AD5755-1 Data Sheet

NOTES

Rev. B | Page 52 of 52