Page 1
Complete Quad, 14-Bit, High Accuracy,
Serial Input, Bipolar Voltage Output DAC
FEATURES
Complete quad, 14-bit digital-to-analog converter (DAC)
Programmable output range: ±10 V, ±10.2564 V, or
±10.5263 V
±1 LSB maximum INL error, ±1 LSB maximum DNL error
Low noise: 60 nV/√Hz
Settling time: 10 μs maximum
Integrated reference buffers
Internal reference: 10 ppm/°C maximum
On-chip die temperature sensor
Output control during power-up/brownout
Programmable short-circuit protection
Simultaneous updating via
Asynchronous
Digital offset and gain adjust
Logic output control pins
DSP-/microcontroller-compatible serial interface
Temperature range: −40°C to +85°C
iCMOS process technology
CLR
to zero code
APPLICATIONS
Industrial automation
Open-loop/closed-loop servo control
Process control
Data acquisition systems
Automatic test equipment
Automotive test and measurement
High accuracy instrumentation
LDAC
AD5744R
GENERAL DESCRIPTION
The AD5744R is a quad, 14-bit, serial input, bipolar voltage output
DAC that operates from supply voltages of ±11.4 V to ±16.5 V.
Nominal full-scale output range is ±10 V. The AD5744R provides
integrated output amplifiers, reference buffers, and proprietary
power-up/power-down control circuitry. The part also features
a digital I/O port, programmed via the serial interface, and an
analog temperature sensor. The part incorporates digital offset
and gain adjust registers per channel.
The AD5744R is a high performance converter that provides
guaranteed monotonicity, integral nonlinearity (INL) of ±1 LSB,
low noise, and 10 μs settling time. The AD5744R includes an onchip 5 V reference with a reference temperature coefficient of
10 ppm/°C maximum. During power-up when the supply voltages
are changing, VOUTx is clamped to 0 V via a low impedance path.
The AD5744R is based on the iCMOS® technology platform, which
is designed for analog systems designers within industrial/instrumentation equipment OEMs who need high performance ICs at
higher voltage levels. iCMOS enables the development of analog
ICs capable of 30 V and operation at ±15 V supplies, while allowing
reductions in power consumption and package size, coupled with
increased ac and dc performance.
The AD5744R uses a serial interface that operates at clock rates
of up to 30 MHz and is compatible with DSP and microcontroller
interface standards. Double buffering allows the simultaneous
updating of all DACs. The input coding is programmable to either
twos complement or offset binary formats. The asynchronous clear
function clears all DATA registers to either bipolar zero or zero
scale, depending on the coding used. The AD5744R is ideal for
both closed-loop servo control and open-loop control applications.
The AD5744R is available in a 32-lead TQFP and offers guaranteed
specifications over the −40°C to +85°C industrial temperature
range (see Figure 1 for the functional block diagram).
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2008–2009 Analog Devices, Inc. All rights reserved.
Page 2
AD5744R
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Functional Block Diagram .............................................................. 3
Specifications ..................................................................................... 4
AC Performance Characteristics ................................................ 6
Timing Characteristics ................................................................ 7
Absolute Maximum Ratings .......................................................... 10
Thermal Resistance .................................................................... 10
ESD Caution ................................................................................ 10
Pin Configuration and Function Descriptions ........................... 11
Typical Performance Characteristics ........................................... 13
Terminology .................................................................................... 19
Theory of Operation ...................................................................... 21
DAC Architecture ....................................................................... 21
Reference Buffers ........................................................................ 21
Serial Interface ............................................................................ 21
Simultaneous Updating via
Transfer Function ....................................................................... 23
Asynchronous Clear (
LDAC
........................................... 23
CLR
) ....................................................... 23
Registers ........................................................................................... 24
Function Register ....................................................................... 24
Data Register ............................................................................... 25
Coarse Gain Register ................................................................. 25
Fine Gain Register ...................................................................... 25
Design Features ............................................................................... 26
Analog Output Control ............................................................. 26
Programmable Short-Circuit Protection ................................ 26
Digital I/O Port ........................................................................... 26
Die Temperature Sensor ............................................................ 26
Local Ground Offset Adjust ...................................................... 26
Applications Information .............................................................. 27
Typical Operating Circuit ......................................................... 27
Layout Guidelines ........................................................................... 29
Galvanically Isolated Interface ................................................. 29
Microprocessor Interfacing ....................................................... 29
Outline Dimensions ....................................................................... 30
Ordering Guide .......................................................................... 30
REVISION HISTORY
8/09—Rev. B to Rev. C
Deleted Endnote 1 in Table 1 .......................................................... 4
Deleted Endnote 1 in Table 2 .......................................................... 6
Deleted Endnote 1 and Changes to t
2/09—Rev. A to Rev. B
Changes to Figure 1 .......................................................................... 3
Changes to Table 1 Conditions and Added Endnote
to Table 1 ............................................................................................ 4
Added Endnote to Table 2 ............................................................... 6
Added Endnote to Table 3 ............................................................... 7
Changes to Table 5 .......................................................................... 10
1/09—Rev. 0 to Rev. A
Changes to Figure 1 .......................................................................... 3
10/08—Revision 0: Initial Version
Parameter in Table 3 ...... 7
6
Rev. C | Page 2 of 32
Page 3
AD5744R
FUNCTIONAL BLOCK DIAGRAM
DV
DGND
AVDDAVSSAV
PGND
CC
AD5744R
AV
DD
SS
REFOUT
5V
REFERENCE
REFABREFGND
REFERENCE
BUFFERS
VOLTAGE
MONITOR
AND
CONTROL
RSTINRSTOUT
ISCC
SDIN
SCLK
SYNC
SDO
BIN/2sCOMP
CLR
14
INPUT
SHIFT
REGISTER
AND
CONTROL
LOGIC
D0
D1
INPUT
REG A
GAIN REG A
INPUT
REG B
GAIN REG B
INPUT
REG C
GAIN REG C
INPUT
REG D
GAIN REG D
14
DATA
REG A
DATA
REG B
DATA
REG C
DATA
REG D
LDAC REFCD
14
14
14
DAC A
DAC B
DAC C
DAC D
REFERENCE
BUFFERS
TEMP
SENSOR
TEMP
G1
G1
G1
G1
G2
G2
G2
G2
VOUTA
AGNDA
VOUTB
AGNDB
VOUTC
AGNDC
VOUTD
AGNDD
06065-001
Figure 1.
Rev. C | Page 3 of 32
Page 4
AD5744R
SPECIFICATIONS
AVDD = 11.4 V to 16.5 V, AVSS = −11.4 V to −16.5 V, AGND = DGND = REFGND = PGND = 0 V; REFAB = REFCD = 5 V external;
DV
= 2.7 V to 5.25 V, R
CC
Table 1.
Parameter Min Typ Max Unit Test Conditions/Comments1
ACCURACY Outputs unloaded
Resolution 14 Bits
Relative Accuracy (INL) −1 +1 LSB
Differential Nonlinearity (DNL) −1 +1 LSB Guaranteed monotonic
Bipolar Zero Error −2 +2 mV
−3 +3 mV
Bipolar Zero Tempco2 −2 +2 ppm FSR/°C
Zero-Scale Error −2 +2 mV
−2.5 +2.5 mV
Zero-Scale Tempco2 −2 +2 ppm FSR/°C
Gain Error −0.02 +0.02 % FSR
Gain Tempco2 −2 +2 ppm FSR/°C
DC Crosstalk2 0.125 LSB
REFERENCE INPUT/OUTPUT
Reference Input2
Reference Input Voltage 5 V ±1% for specified performance
DC Input Impedance 1 MΩ Typically 100 MΩ
Input Current −10 +10 μA Typically ±30 nA
Reference Range 1 7 V
Reference Output
Output Voltage 4.995 5 5.005 V 25°C, AVDD/AVSS = ±13.5 V
Reference Tempco2 −10 ±1.7 +10 ppm/°C
2
R
1 MΩ
LOAD
Power Supply Sensitivity1 300 μV/V
Output Noise2 18 μV p-p 0.1 Hz to 10 Hz
Noise Spectral Density2 75 nV/√Hz 10 kHz
Output Voltage Drift vs. Time
Thermal Hysteresis1
OUTPUT CHARACTERISTICS2
Output Voltage Range3 −10.5263 +10.5263 V AVDD/AVSS = ±11.4 V, V
−14.7368 +14.7368 V AVDD/AVSS = ±16.5 V, V
Output Voltage Drift vs. Time ±13 ppm FSR/500 hr
±15 ppm FSR/1000 hr
Short-Circuit Current 10 mA R
Load Current −1 +1 mA For specified performance
Capacitive Load Stability
R
= ∞ 200 pF
LOAD
R
= 10 kΩ 1000 pF
LOAD
DC Output Impedance 0.3 Ω
= 10 kΩ, CL = 200 pF. All specifications T
LOAD
2
±40 ppm/500 hr
±50 ppm/1000 hr
70 ppm First temperature cycle
30 ppm Subsequent temperature cycles
MIN
to T
, unless otherwise noted.
MAX
25°C; error at other temperatures obtained
using bipolar zero tempco
25°C; error at other temperatures
obtained using zero-scale tempco
ISCC
REFIN
REFIN
= 6 kΩ, see Figure 31
= 5 V
= 7 V
Rev. C | Page 4 of 32
Page 5
AD5744R
Parameter Min Typ Max Unit Test Conditions/Comments1
DIGITAL INPUTS2
Input High Voltage, VIH 2.4 V
Input Low Voltage, VIL 0.8 V
Input Current −1.2 +1.2 μA Per pin
Pin Capacitance 10 pF Per pin
DIGITAL OUTPUTS (D0, D1, SDO)2
Output Low Voltage 0.4 V DVCC = 5 V ± 5%, sinking 200 μA
Output High Voltage DVCC − 1 V DVCC = 5 V ± 5%, sourcing 200 μA
Output Low Voltage 0.4 V DVCC = 2.7 V to 3.6 V, sinking 200 μA
Output High Voltage DVCC − 0.5 V DVCC = 2.7 V to 3.6 V, sourcing 200 μA
High Impedance Leakage
Current
High Impedance Output
Capacitance
DIE TEMPERATURE SENSOR2
Output Voltage at 25°C 1.47 V Die temperature
Output Voltage Scale Factor 5 mV/°C
Output Voltage Range 1.175 1.9 V −40°C to +105°C
Output Load Current 200 μA Current source only
Power-On Time 80 ms
POWER REQUIREMENTS
AVDD +11.4 +16.5 V
AVSS −11.4 −16.5
DVCC 2.7 5.25 V
Power Supply Sensitivity2
∆V
/∆ΑVDD −85 dB
OUT
AIDD 3.55 mA/channel Outputs unloaded
AISS 2.8 mA/channel Outputs unloaded
DICC 1.2 mA VIH = DVCC, VIL = DGND, 750 μA typ
Power Dissipation
1
Temperature range: −40°C to +85°C; typical at +25°C. Device functionality is guaranteed to 105°C with degraded performance.
2
Guaranteed by design and characterization; not production tested.
3
Output amplifier headroom requirement is 1.4 V minimum.
DVCC = 2.7 V to 5.25 V
−1 +1 μA SDO only
5 pF SDO only
275 mW ±12 V operation output unloaded
Rev. C | Page 5 of 32
Page 6
AD5744R
AC PERFORMANCE CHARACTERISTICS
AVDD = 11.4 V to 16.5 V, AVSS = −11.4 V to −16.5 V, AGND = DGND = REFGND = PGND = 0 V; REFAB = REFCD = 5 V external;
DV
= 2.7 V to 5.25 V, R
CC
Table 2.
Parameter Min Typ Max Unit Test Conditions/Comments
DYNAMIC PERFORMANCE1
Output Voltage Settling Time 8 μs Full-scale step to ±1 LSB
10 μs
2 μs 512 LSB step settling
Slew Rate 5 V/μs
Digital-to-Analog Glitch Energy 8 nV-sec
Glitch Impulse Peak Amplitude 25 mV
Channel-to-Channel Isolation 80 dB
DAC-to-DAC Crosstalk 8 nV-sec
Digital Crosstalk 2 nV-sec
Digital Feedthrough 2 nV-sec Effect of input bus activity on DAC outputs
Output Noise (0.1 Hz to 10 Hz) 0.025 LSB p-p
Output Noise (0.1 Hz to 100 kHz) 45 μV rms
1/f Corner Frequency 1 kHz
Output Noise Spectral Density 60 nV/√Hz Measured at 10 kHz
Complete System Output Noise
Spectral Density
1
Guaranteed by design and characterization; not production tested.
2
Includes noise contributions from integrated reference buffers, 14-bit DAC, and output amplifier.
2
= 10 kΩ, CL = 200 pF. All specifications T
LOAD
80 nV/√Hz Measured at 10 kHz
MIN
to T
, unless otherwise noted.
MAX
Rev. C | Page 6 of 32
Page 7
AD5744R
TIMING CHARACTERISTICS
AVDD = 11.4 V to 16.5 V, AVSS = −11.4 V to −16.5 V, AGND = DGND = REFGND = PGND = 0 V; REFAB = REFCD = 5 V external;
DV
= 2.7 V to 5.25 V, R
CC
= 10 kΩ, CL = 200 pF. All specifications T
LOAD
MIN
to T
, unless otherwise noted.
MAX
Table 3.
Parameter
1, 2, 3
Limit at T
, T
Unit Description
MIN
MAX
t1 33 ns min SCLK cycle time
t2 13 ns min SCLK high time
t3 13 ns min SCLK low time
t4 13 ns min
4
t
13 ns min
5
t6 90 ns min
falling edge to SCLK falling edge setup time
SYNC
th
SCLK falling edge to SYNC rising edge
24
Minimum SYNC
high time
t7 2 ns min Data setup time
t8 5 ns min Data hold time
t9 1.7 μs min
480 ns min
t10 10 ns min
t11 500 ns max
rising edge to LDAC falling edge (all DACs updated)
SYNC
rising edge to LDAC falling edge (single DAC updated)
SYNC
pulse width low
LDAC
falling edge to DAC output response time
LDAC
t12 10 μs max DAC output settling time
t13 10 ns min
t14 2 μs max
5, 6
t
25 ns max SCLK rising edge to SDO valid
15
t16 13 ns min
t17 2 μs max
t18 170 ns min
1
Guaranteed by design and characterization; not production tested.
2
All input signals are specified with tR = tF = 5 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V.
3
See Figure 2, Figure 3, and Figure 4.
4
Standalone mode only.
5
Measured with the load circuit of Figure 5.
6
Daisy-chain mode only.
pulse width low
CLR
pulse activation time
CLR
rising edge to SCLK falling edge
SYNC
rising edge to DAC output response time (LDAC = 0)
SYNC
falling edge to SYNC rising edge
LDAC
Rev. C | Page 7 of 32
Page 8
AD5744R
Timing Diagrams
t
1
SCLK
SYNC
SDIN
LDAC
VOUTx
LDAC = 0
VOUTx
CLR
VOUTx
12 24
t
6
t
4
t
7
DB23
t
t
3
t
8
t
13
14
t
2
t
10
t
5
DB0
t
t
9
t
18
t
17
10
t
t
11
t
12
12
06065-002
Figure 2. Serial Interface Timing Diagram
t
1
SCLK
SYNC
SDIN
SDO
LDAC
t
6
t
4
t
7
DB23 DB0 DB23 DB0
t
3
t
8
Figure 3. Daisy-Chain Timing Diagram
24 48
t
2
INPUT WORD FOR DAC N–1INPUT WORD FOR DAC N
t
15
DB23
INPUT WORD FOR DAC NUNDEFINED
DB0
t
5
t
16
t
9
t
10
06065-003
Rev. C | Page 8 of 32
Page 9
AD5744R
SYNC
SCLK
24 48
SDIN
SDO
DB23 DB0 DB23 DB0
INPUT WORD SPECIFIES
REGIS TER TO BE READ
UNDEFINED
DB23
NOP CONDITI ON
SELECTED REGISTER DATA
CLOCKED OUT
DB0
06065-004
Figure 4. Readback Timing Diagram
200µA I
TO OUTPUT
PIN
C
L
50pF
200µA I
Figure 5. Load Circuit for SDO Timing Diagram
OL
OH
VOH (MIN) OR
V
(MAX)
OL
06065-005
Rev. C | Page 9 of 32
Page 10
AD5744R
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted. Transient currents of up to
100 mA do not cause SCR latch-up.
Table 4.
Parameter Rating
AVDD to AGND, DGND −0.3 V to +17 V
AVSS to AGND, DGND +0.3 V to −17 V
DVCC to DGND −0.3 V to +7 V
Digital Inputs to DGND
Digital Outputs to DGND −0.3 V to DVCC + 0.3 V
REFAB, REFCD to AGNDx, PGND −0.3 V to AVDD + 0.3 V
REFOUT to AGNDx AVSS to AVDD
TEMP AVSS to AVDD
VOUTx to AGNDx AVSS to AVDD
AGND to DGND −0.3 V to +0.3 V
Operating Temperature Range
Industrial −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Junction Temperature (TJ max) 150°C
Lead Temperature (Soldering) JEDEC Industry Standard
J-STD-020
−0.3 V to (DV
whichever is less
+ 0.3 V) or +7 V,
CC
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 5. Thermal Resistance
Package Type θJA θ
32-Lead TQFP 65 12 °C/W
Unit
JC
ESD CAUTION
Rev. C | Page 10 of 32
Page 11
AD5744R
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
BIN/2sCOMP
AVDDAVSSTEMP
32 31 30 29 28 27 26 25
1
SYNC
SCLK
SDIN
SDO
CLR
LDAC
D0
D1
PIN 1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
RSTIN
RSTOUT
Figure 6. Pin Configuration
Table 6. Pin Function Descriptions
Pin No. Mnemonic Description
1
Active Low Input. This is the frame synchronization signal for the serial interface. While SYNC is low, data is transferred
SYNC
in on the falling edge of SCLK.
2 SCLK
Serial Clock Input. Data is clocked into the shift register on the falling edge of SCLK. This operates at clock
speeds of up to 30 MHz.
3 SDIN Serial Data Input. Data must be valid on the falling edge of SCLK.
4 SDO Serial Data Output. This pin is used to clock data from the serial register in daisy-chain or readback mode.
5
6
CLR
Load DAC. This logic input is used to update the data register and, consequently, the analog outputs. When tied
LDAC
Negative Edge Triggered Input.
1
Asserting this pin sets the data register to 0x0000.
permanently low, the addressed data register is updated on the rising edge of SYNC
the write cycle, the DAC input register is updated, but the output update is held off until the falling edge of
LDAC
. In this mode, all analog outputs can be updated simultaneously on the falling edge of LDAC. The LDAC
pin must not be left unconnected.
7, 8 D0, D1
Digital I/O Port. D0 and D1 form a digital I/O port. The user can set up these pins as inputs or outputs that are
configurable and readable over the serial interface. When configured as inputs, these pins have weak internal
pull-ups to DV
9
Reset Logic Output. This is the output from the on-chip voltage monitor used in the reset circuit. If desired, it
RSTOUT
. When programmed as outputs, D0 and D1 are referenced by DVCC and DGND.
CC
can be used to control other system components.
10
Reset Logic Input. This input allows external access to the internal reset logic. Applying a Logic 0 to this input clamps
RSTIN
the DAC outputs to 0 V. In normal operation, RSTIN
11 DGND Digital Ground Pin.
12 DVCC Digital Supply Pin. Voltage ranges from 2.7 V to 5.25 V.
13, 31 AVDD Positive Analog Supply Pins. Voltage ranges from 11.4 V to 16.5 V.
14 PGND Ground Reference Point for Analog Circuitry.
15, 30 AVSS Negative Analog Supply Pins. Voltage ranges from –11.4 V to –16.5 V.
16 ISCC
This pin is used in association with an optional external resistor to AGND to program the short-circuit current of
the output amplifiers. Refer to the Design Features section for more information.
17 AGNDD Ground Reference Pin for DAC D Output Amplifier.
18 VOUTD
Analog Output Voltage of DAC D. Buffered output with a nominal full-scale output range of ±10 V. The output
amplifier is capable of directly driving a 10 kΩ, 200 pF load.
19 VOUTC
Analog Output Voltage of DAC C. Buffered output with a nominal full-scale output range of ±10 V. The output
amplifier is capable of directly driving a 10 kΩ, 200 pF load.
20 AGNDC Ground Reference Pin for DAC C Output Amplifier.
21 AGNDB Ground Reference Pin for DAC B Output Amplifier.
22 VOUTB
Analog Output Voltage of DAC B. Buffered output with a nominal full-scale output range of ±10 V. The output
amplifier is capable of directly driving a 10 kΩ, 200 pF load.
REFGND
AD5744R
TOP VIEW
(Not to Scale)
CCAVDD
DV
DGND
REFOUT
REFCD
REFAB
24
AGNDA
23
VOUTA
22
VOUTB
21
AGNDB
20
AGNDC
19
VOUTC
VOUTD
18
AGNDD
17
SS
ISCC
AV
PGND
6065-006
. If LDAC is held high during
should be tied to Logic 1. Register values remain unchanged.
Rev. C | Page 11 of 32
Page 12
AD5744R
Pin No. Mnemonic Description
23 VOUTA
24 AGNDA Ground Reference Pin for DAC A Output Amplifier.
25 REFAB
26 REFCD
27 REFOUT
28 REFGND Reference Ground Return for the Reference Generator and Buffers.
29 TEMP
32
1
Internal pull-up device on this logic input. Therefore, it can be left floating; and it defaults to a logic high condition.
BIN/2sCOMP
Analog Output Voltage of DAC A. Buffered output with a nominal full-scale output range of ±10 V. The output
amplifier is capable of directly driving a 10 kΩ, 200 pF load.
External Reference Voltage Input for Channel A and Channel B. The reference input range is 1 V to 7 V, and it
programs the full-scale output voltage. V
= 5 V for specified performance.
REFIN
External Reference Voltage Input for Channel C and Channel D. The reference input range is 1 V to 7 V, and it
programs the full-scale output voltage. V
= 5 V for specified performance.
REFIN
Reference Output. This is the reference output from the internal voltage reference. The internal reference is 5 V ±
3 mV at 25°C, with a reference temperature coefficient of 10 ppm/°C.
This pin provides an output voltage proportional to temperature. The output voltage is 1.47 V typical at 25°C die
temperature; variation with temperature is 5 mV/°C.
This pin determines the DAC coding. This pin should be hardwired to either DVCC or DGND. When hardwired to
, input coding is offset binary (see Tab le 7). When hardwired to DGND, input coding is twos complement
DV
CC
(see Table 8).
Rev. C | Page 12 of 32
Page 13
AD5744R
TYPICAL PERFORMANCE CHARACTERISTICS
0.25
0.20
0.15
0.10
0.05
0
–0.05
INL ERROR (LSB)
–0.10
–0.15
–0.20
–0.25
0 16,00014,00012,00010,0008000600040002000
DAC CODE
Figure 7. Integral Nonlinearity Error vs. DAC Code,
= ±15 V
V
DD/VSS
TA = 25°C
V
DD/VSS
V
= 5V
REFIN
= ±15V
06065-009
0.25
0.20
0.15
0.10
0.05
0
–0.05
DNL ERROR (LSB)
–0.10
–0.15
–0.20
–0.25
0 16,00014,00012,00010,0008000600040002000
DAC CODE
Figure 10. Differential Nonlinearity Error vs. DAC Code,
= ±12 V
V
DD/VSS
TA = 25°C
V
DD/VSS
V
= 5V
REFIN
= ±12V
06065-014
0.25
0.20
0.15
0.10
0.05
0
–0.05
INL ERROR (L SB)
–0.10
–0.15
–0.20
–0.25
0 16,00014,00012,00010,0008000600040002000
DAC CODE
Figure 8. Integral Nonlinearity Error vs. DAC Code,
= ±12 V
V
DD/VSS
0.25
0.20
0.15
0.10
0.05
0
–0.05
DNL ERROR (LSB)
–0.10
–0.15
–0.20
–0.25
0 16,00014,00012,00010,0008000600040002000
DAC CODE
Figure 9. Differential Nonlinearity Error vs. DAC Code,
= ±15 V
V
DD/VSS
TA = 25°C
V
DD/VSS
V
= 5V
REFIN
TA = 25°C
V
DD/VSS
V
= 5V
REFIN
= ±12V
= ±15V
0.12
0.10
0.08
0.06
0.04
0.02
INL ERROR (LSB)
0
–0.02
VDD/VSS = ±15V
REFIN = 5V
–0.04
–40 100–200 20406080
06065-010
TEMPERATURE (° C)
06065-015
Figure 11. Integral Nonlinearity Error vs. Temperature,
= ±15 V
V
DD/VSS
0.12
0.10
0.08
0.06
0.04
0.02
INL ERROR (LSB)
0
–0.02
VDD/VSS = ±12V
REFIN = 5V
–0.04
–40 100–20 0 20 40 60 80
06065-013
TEMPERATURE (°C)
06065-016
Figure 12. Integral Nonlinearity Error vs. Temperature,
= ±12 V
V
DD/VSS
Rev. C | Page 13 of 32
Page 14
AD5744R
0.04
VDD/VSS = ±15V
V
= 5V
REFIN
0
–40 100–20 0 20 40 60 80
TEMPERATURE (°C)
DNL ERROR (LSB)
0.03
0.02
0.01
–0.01
–0.02
–0.03
–0.04
–0.05
–0.06
Figure 13. Differential Nonlinearity Error vs. Temperature,
= ±15 V
V
DD/VSS
0.04
VDD/VSS = ±12V
0.03
V
= 5V
REFIN
0.02
0.01
0
–0.01
–0.02
DNL ERROR (LSB)
–0.03
–0.04
–0.05
–0.06
–40 100–20 0 20 40 60 80
TEMPERATURE (°C)
Figure 14. Differential Nonlinearity Error vs. Temperature,
= ±12 V
V
DD/VSS
0.12
TA = 25°C
V
= 5V
REFIN
–0.10
–0.08
–0.06
–0.04
–0.02
INL ERROR (LSB)
0
–0.02
–0.04
11.4 16.415.414. 413.412.4
SUPPLY VOLTAGE (V)
Figure 15. Integral Nonlinearity Error vs. Supply Voltage
06065-019
06065-020
06065-023
0.15
TA = 25°C
V
= 5V
REFIN
0.10
0.05
0
–0.05
–0.10
DNL ERROR (LSB)
–0.15
–0.20
–0.25
11.4 16.415.414. 413.412.4
SUPPLY VOLTAGE (V)
Figure 16. Differential Nonlinearity Error vs. Supply Voltage
0.20
0.15
0.10
0.05
0
–0.05
–0.10
INL ERROR (LSB)
–0.15
–0.20
TA = 25°C
V
= ±15V
DD/VSS
–0.25
1756432
REFERENCE VOLTAGE (V)
Figure 17. Integral Nonlinearity Error vs. Reference Voltage
V
= ±15 V
DD/VSS
0.10
0.08
0.06
0.04
0.02
0
–0.02
DNL ERROR (LSB)
–0.04
–0.06
–0.08
TA = 25°C
V
= ±16.5V
DD/VSS
–0.10
1756432
REFERENCE VOL TAGE (V)
Figure 18. Differential Nonlinearity Error vs. Reference Voltage
V
= ±16.5 V
DD/VSS
06065-025
06065-027
06065-031
Rev. C | Page 14 of 32
Page 15
AD5744R
0.6
TA = 25°C
0.4
0.2
0
–0.2
–0.4
–0.6
TUE (mV)
–0.8
–1.0
–1.2
–1.4
–1.6
1756432
REFERENCE VOLTAGE (V)
Figure 19. Total Unadjusted Error vs. Reference Voltage,
= ±16.5 V
V
DD/VSS
06065-035
0.8
0.6
0.4
0.2
BIPOLAR ZERO ERROR (mV)
–0.2
–0.4
V
= 5V
REFIN
0
–40 100806040200–20
TEMPERATURE ( °C)
VDD/VSS = ±15V
Figure 22. Bipolar Zero Error vs. Temperature
V
DD/VSS
= ±12V
06065-039
9.0
TA = 25°C
= 5V
V
REFIN
8.5
8.0
7.5
7.0
(mA)
6.5
SS
/I
DD
6.0
I
5.5
5.0
4.5
4.0
11.4 12.4 13.4 14.4 15.4 16.4
|I
|
DD
|
|I
SS
VDD/VSS (V)
Figure 20. IDD/ISS vs. VDD/VSS
0.25
V
ZERO-SCALE ERROR (mV)
0.20
0.15
0.10
0.05
–0.05
–0.10
–0.15
–0.20
–0.25
REFIN
0
–40 100806040200–20
= 5V
VDD/VSS = ±15V
TEMPERATURE ( °C)
V
DD/VSS
Figure 21. Zero-Scale Error vs. Temperature
= ±12V
1.4
V
= 5V
REFIN
1.2
1.0
0.8
0.6
0.4
GAIN ERROR (mV)
0.2
0
–0.2
–40 100806040200–20
06065-037
TEMPERATURE (° C)
V
= ±12V
DD/VSS
VDD/VSS = ±15V
06065-040
Figure 23. Gain Error vs. Temperature
0.0014
TA = 25°C
0.0013
0.0012
0.0011
(mA)
0.0010
CC
DI
0.0009
0.0008
0.0007
0.0006
054.54.03.53.02.52.01.51.00.5
06065-038
Figure 24. DI
5V
3V
V
(V)
LOGIC
vs. Logic Input Voltage
CC
.0
06065-041
Rev. C | Page 15 of 32
Page 16
AD5744R
–
7000
= 25°C
T
A
V
= 5V
REFIN
6000
5000
VDD/VSS = ±15V
= ±12V
V
DD/VSS
4000
3000
2000
1000
OUTPUT VO LTAGE DEL TA (µV)
0
–1000
–10 1050–5
SOURCE/SINK CURRENT (mA)
06065-042
Figure 25. Source and Sink Capability of Output Amplifier with Positive Full
Scale Loaded
10,000
TA = 25°C
V
REFIN
= 5V
VDD/VSS = ±15V
V
DD/VSS
= ±12V
9000
8000
7000
6000
5000
4000
3000
2000
OUTPUT VO LTAGE DEL TA (µV)
1000
0
–1000
–12 83–2–7
SOURCE/SINK CURRENT (mA)
06065-043
Figure 26. Source and Sink Capability of Output Amplifier with Negative Full
Scale Loaded
4
–6
–8
–10
–12
–14
(mV)
–16
OUT
V
–18
–20
–22
–24
–26
–2.0–1.5–1.0–0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD/VSS = ±12V,
V
= 5V,
REFIN
T
= 25°C,
A
0x8000 TO 0x7FF F,
500ns/DIV
TIME (µs)
Figure 28. Major Code Transition Glitch Energy, VDD/VSS = ±12 V
VDD/VSS = ±15V
MIDSCALE LO ADED
V
= 0V
REFIN
4
50µV/DIV
CH4 50.0µV M1.00s CH4 26µV
Figure 29. Peak-to-Peak Noise (100 kHz Bandwidth)
06065-047
06065-048
VDD/VSS = ±15V
T
= 25°C
A
V
= 5V
REFIN
1
1µs/DIV
CH1 3.00V M1.00µs CH1 –120mV
Figure 27. Full-Scale Settling Time
06065-044
Rev. C | Page 16 of 32
1
2
3
CH1 10.0V
CH3 10.0mV
T
VDD/VSS = ±12V,
V
= 5V, TA = 25°C,
REFIN
RAMP TIME = 100µs,
LOAD = 200pF ||10kΩ
B
CH2 10.0V M100µs A CH1 7.80mV
W
B
W
T 29.60%
Figure 30. VOUTx vs. VDD/VSS on Power-Up
06065-055
Page 17
AD5744R
SHORT-CIRCUIT CURRENT (mA)
10
9
8
7
6
5
4
3
2
1
0
0 12010080604020
R
(kΩ)
ISCC
Figure 31. Short-Circuit Current vs. R
VDD/VSS = ±15V
T
= 25°C
A
V
= 5V
REFIN
ISCC
VDD/VSS = ±12V
T
= 25°C
A
1
5µV/DIV
06065-050
M1.00s A CH1 18mV
06065-053
Figure 34. REFOUT Output Noise 0.1 Hz to 10 Hz
1
2
3
CH1 10.0V
CH3 5.00V
T
B
CH2 10.0V M400µs A CH1 7.80mV
W
B
W
T 29.60%
VDD/VSS = ±12V
T
= 25°C
A
Figure 32. REFOUT Turn-On Transient
VDD/VSS = ±12V
T
= 25°C,
A
10µF CAPACITO R ON REFOUT
1
50µV/DIV
CH1 50.0µV M1.00s A CH1 15µV
Figure 33. REFOUT Output Noise 100 kHz Bandwidth
6
TA = 25°C
V
DD/VSS
= ±15V
5
4
3
2
1
REFERENCE OUTPUT VOLT AGE (V)
0
0 20 40 60 80 100 120 140 160 180 200
06065-054
LOAD CURRENT (µA)
06065-032
Figure 35. REFOUT Load Regulation
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
TEMPERATURE OUTPUT VOLTAGE (V)
1.1
1.0
06065-052
–40 –20 0 20 40 60 80 100
TEMPERATURE ( °C)
TA = 25°C
V
DD/VSS
= ±15V
06065-033
Figure 36. Temperature Output Voltage vs. Temperature
Rev. C | Page 17 of 32
Page 18
AD5744R
5.003
5.002
5.001
20 DEVICES SHO WN
40
35
30
25
MAX: 10ppm/°C
TYP: 1.7p pm/°C
5.000
4.999
4.998
REFERENCE OUTPUT VOLT AGE (V)
4.997
–40 –20 0 20 40 60 80 100
TEMPERATURE (°C)
06065-070
20
15
POPULATION (%)
10
5
0
0.51.52.53.54.55.56.57.58.59.5
TEMPERATURE DRI FT (pp m/°C)
06065-072
Figure 37. Reference Output Voltage vs. Temperature Figure 38. Reference Output Temperature Drift (−40°C to +85°C)
Rev. C | Page 18 of 32
Page 19
AD5744R
TERMINOLOGY
Relative Accuracy or Integral Nonlinearity (INL)
For the DAC, a measure of the maximum deviation, in LSBs,
from a straight line passing through the endpoints of the DAC
transfer function.
Differential Nonlinearity (DNL)
The difference between the measured change and the ideal 1 LSB
change between any two adjacent codes. A specified differential
nonlinearity of ±1 LSB maximum ensures monotonicity. This DAC
is guaranteed monotonic.
Monotonicity
A DAC is monotonic if the output either increases or remains
constant for increasing digital input code. The AD5744R is
monotonic over its full operating temperature range.
Bipolar Zero Error
The deviation of the analog output from the ideal half-scale
output of 0 V when the data register is loaded with 0x8000
(offset binary coding) or 0x0000 (twos complement coding).
Figure 22 shows a plot of bipolar zero error vs. temperature.
Bipolar Zero Temperature Coefficient
The measure of the change in the bipolar zero error with a
change in temperature. It is expressed as parts per million of
full-scale range per degree Celsius (ppm FSR/°C).
Full-Scale Error
The measure of the output error when full-scale code is loaded
to the data register. Ideally, the output voltage should be 2 ×
V
− 1 LSB. Full-scale error is expressed as a percentage of
REFIN
full-scale range (% FSR).
Negative Full-Scale Error/Zero-Scale Error
The error in the DAC output voltage when 0x0000 (offset binary
coding) or 0x8000 (twos complement coding) is loaded to the
data register. Ideally, the output voltage should be −2 × V
Figure 21 shows a plot of zero-scale error vs. temperature.
Output Voltage Settling Time
The amount of time it takes for the output to settle to a specified
level for a full-scale input change.
Slew Rate
A limitation in the rate of change of the output voltage. The output
slewing speed of a voltage output DAC is usually limited by the
slew rate of the amplifier used at its output. Slew rate is measured
from 10% to 90% of the output signal and is given in volts per
microsecond (V/μs).
Gain Error
A measure of the span error of the DAC. It is the deviation in
slope of the DAC transfer characteristic from the ideal, expressed
as a percentage of the full-scale range (% FSR). Figure 23 shows
a plot of gain error vs. temperature.
REFIN
.
Tot a l U n ad ju s te d E rr o r ( TU E )
A measure of the output error, considering all the various
errors. Figure 19 shows a plot of total unadjusted error vs.
reference voltage.
Zero-Scale Error Temperature Coefficient
A measure of the change in zero-scale error with a change in
temperature. It is expressed as parts per million of full-scale
range per degree Celsius (ppm FSR/°C).
Gain Error Temperature Coefficient
A measure of the change in gain error with changes in temperature. It is expressed as parts per million of full-scale range per
degree Celsius (ppm FSR/°C).
Digital-to-Analog Glitch Energy
The impulse injected into the analog output when the input
code in the data register changes state. It is normally specified
as the area of the glitch in nanovolt-seconds (nV-sec) and is
measured when the digital input code is changed by 1 LSB at the
major carry transition (0x7FFF to 0x8000), as shown in Figure
28.
Digital Feedthrough
A measure of the impulse injected into the analog output of the
DAC from the digital inputs of the DAC but is measured when
the DAC output is not updated. It is specified in nanovolt-seconds
(nV-sec) and measured with a full-scale code change on the
data bus, that is, from all 0s to all 1s, and vice versa.
Power Supply Sensitivity
Indicates how the output of the DAC is affected by changes in
the power supply voltage.
DC Crosstalk
The dc change in the output level of one DAC in response to a
change in the output of another DAC. It is measured with a fullscale output change on one DAC while monitoring another
DAC, and is expressed in least significant bits (LSBs).
DAC-to-DAC Crosstalk
The glitch impulse transferred to the output of one DAC due
to a digital code change and subsequent output change of
another DAC. This includes both digital and analog crosstalk.
It is measured by loading one of the DACs with a full-scale code
change (from all 0s to all 1s, and vice versa) with
monitoring the output of another DAC. The energy of the glitch
is expressed in nanovolt-seconds (nV-sec).
Channel-to-Channel Isolation
The ratio of the amplitude of the signal at the output of one DAC
to a sine wave on the reference input of another DAC. It is
measured in decibels (dB).
Reference Temperature Coefficient
A measure of the change in the reference output voltage with
a change in temperature. It is expressed in parts per million per
degree Celsius (ppm/°C).
LDAC
low and
Rev. C | Page 19 of 32
Page 20
AD5744R
Digital Crosstalk
A measure of the impulse injected into the analog output of one
DAC from the digital inputs of another DAC but is measured
when the DAC output is not updated. It is specified in nanovoltseconds (nV-sec) and measured with a full-scale code change
on the data bus; that is, from all 0s to all 1s, and vice versa.
Thermal Hysteresis
The change of reference output voltage after the device is cycled
through temperatures from −40°C to +85°C and back to −40°C.
This is a typical value from a sample of parts put through such
a cycle.
Rev. C | Page 20 of 32
Page 21
AD5744R
THEORY OF OPERATION
The AD5744R is a quad, 14-bit, serial input, bipolar voltage output
DAC that operates from supply voltages of ±11.4 V to ±16.5 V and
has a buffered output voltage of up to ±10.5263 V. Data is written to
the AD5744R in a 24-bit word format via a 3-wire serial interface.
The AD5744R also offers an SDO pin that is available for daisy
chaining or readback.
The AD5744R incorporates a power-on reset circuit that ensures
that the data registers are loaded with 0x0000 at power-up. The
AD5744R features a digital I/O port that can be programmed via
the serial interface, an analog die temperature sensor, on-chip
10 ppm/°C voltage reference, on-chip reference buffers, and per
channel digital gain and offset registers.
DAC ARCHITECTURE
The DAC architecture of the AD5744R consists of a 14-bit current
mode segmented R-2R DAC. The simplified circuit diagram for
the DAC section is shown in Figure 39.
V
REF
2R
E15
E14 E1
15 EQUAL SEGMENTS
2R
RR R
2R
S11
Figure 39. DAC Ladder Structure
2R
2R
S10
12-BIT, R- 2R LADDER4 MSBs DECODED I NTO
2RS02R
R/8
I
OUT
AGNDx
VOUTx
The four MSBs of the 14-bit data-word are decoded to drive
15 switches, E1 to E15. Each of these switches connects one of
the 15 matched resistors to either AGNDx or I
. The remaining
OUT
12 bits of the data-word drive Switch S0 to Switch S11 of the 12-bit
R-2R ladder network.
REFERENCE BUFFERS
The AD5744R can operate with either an external or an internal
reference. The reference inputs (REFAB and REFCD) have an
input range of up to 7 V. This input voltage is then used to provide
a buffered positive and negative reference for the DAC cores.
The positive reference is given by
+V
= 2 × V
REF
The negative reference to the DAC cores is given by
−V
= −2 × V
REF
These positive and negative reference voltages (along with the
gain register values) define the output ranges of the DACs.
REFIN
REFIN
06065-060
SERIAL INTERFACE
The AD5744R is controlled over a versatile 3-wire serial interface
that operates at clock rates of up to 30 MHz and is compatible
with SPI, QSPI™, MICROWIRE™, and DSP standards.
Input Shift Register
The input shift register is 24 bits wide. Data is loaded into the
device, MSB first, as a 24-bit word under the control of a serial
clock input, SCLK. The input register consists of a read/write bit,
a reserved bit that must be set to 0, three register select bits, three
DAC address bits, and 16 data bits, as shown in Tab l e 9. The timing
diagram for this operation is shown in Figure 2.
Upon power-up, the data registers are loaded with zero code
(0x0000), and the outputs are clamped to 0 V via a low impedance
path. The outputs can be updated with the zero code value by
asserting either
LDAC
depends on the state of the BIN/
pin is tied to DGND, the data coding is twos complement and the
outputs update to 0 V. If the BIN/
the data coding is offset binary and the outputs update to negative
full scale. To have the outputs power-up with zero code loaded
to the outputs, the
Standalone Operation
The serial interface works with both a continuous and noncontinuous serial clock. A continuous SCLK source can be used only
SYNC
if
is held low for the correct number of clock cycles. In gated
clock mode, a burst clock containing the exact number of clock
cycles must be used, and
clock to latch the data. The first falling edge of
write cycle. Exactly 24 falling clock edges must be applied to SCLK
SYNC
before
the 24
is brought high again. If
th
falling SCLK edge, the data written is invalid. If more
than 24 falling SCLK edges are applied before
high, the input data is also invalid. The input register addressed is
updated on the rising edge of
take place,
SYNC
the serial data transfer, data is automatically transferred from the
input shift register to the addressed register.
When the data has been transferred into the chosen register of
the addressed DAC, all data registers and outputs can be
updated by taking
CLR
or
. The corresponding output voltage
2sCOMP
CLR
pin should be held low during power-up.
SYNC
must be taken high after the final
pin. If the BIN/
2sCOMP
pin is tied to DVCC,
SYNC
SYNC
is brought high before
SYNC
SYNC
. For another serial transfer to
2sCOMP
starts the
is brought
must be brought low again. After the end of
LDAC
low.
Rev. C | Page 21 of 32
Page 22
AD5744R
68HC11*
MOSI
SCK
PC7
PC6
MISO
*ADDITIONAL PINS OMITTED FOR CL ARITY.
Figure 40. Daisy-Chaining the AD5744R
AD5744R*
SDIN
SCLK
SYNC
LDAC
SDIN
AD5744R*
SCLK
SYNC
LDAC
SDIN
AD5744R*
SCLK
SYNC
LDAC
SDO
SDO
SDO
06065-061
Daisy-Chain Operation
For systems that contain several devices, the SDO pin can be
used to daisy-chain several devices together. This daisy-chain
mode can be useful in system diagnostics and in reducing the
number of serial interface lines. The first falling edge of
SYNC
starts the write cycle. The SCLK is continuously applied to the
input shift register when
SYNC
is low. If more than 24 clock
pulses are applied, the data ripples out of the shift register and
appears on the SDO line. This data is clocked out on the rising
edge of SCLK and is valid on the falling edge. By connecting the
SDO of the first device to the SDIN input of the next device in
the chain, a multidevice interface is constructed. Each device in
the system requires 24 clock pulses. Therefore, the total number
of clock cycles must equal 24n, where n is the total number of
AD5744R devices in the chain. When the serial transfer to all
devices is complete,
SYNC
is taken high. This latches the input
data in each device in the daisy chain and prevents any further
data from being clocked into the input shift register. The serial
clock can be a continuous or a gated clock.
A continuous SCLK source can be used only if
SYNC
is held
low for the correct number of clock cycles. In gated clock mode,
a burst clock containing the exact number of clock cycles must
be used, and
SYNC
must be taken high after the final clock to
latch the data.
Readback Operation
Before a readback operation is initiated, the SDO pin must be
enabled by writing to the function register and clearing the SDO
disable bit; this bit is cleared by default. Readback mode is invoked
by setting the R/
With R/
W
W
bit to 1 in the serial input register write.
set to 1, Bit A2 to Bit A0, in association with Bit REG2,
to Bit REG0, select the register to be read. The remaining data
bits in the write sequence are don’t care. During the next SPI write,
the data appearing on the SDO output contain the data from the
previously addressed register. For a read of a single register, the
NOP command can be used in clocking out the data from the
selected register on SDO. The readback diagram in shows
Figure 4
the readback sequence. For example, to read back the fine gain
register of Channel A, implement the following sequence:
1. Write 0xA0XXXX to the input register. This write configures
the AD5744R for read mode with the fine gain register of
Channel A selected. Note that all the data bits, DB15 to DB0,
are don’t care.
2. Follow with a second write: an NOP condition, 0x00XXXX.
During this write, the data from the fine gain register is
clocked out on the SDO line; that is, data clocked out contains
the data from the fine gain register in Bit DB5 to Bit DB0.
Rev. C | Page 22 of 32
Page 23
AD5744R
SIMULTANEOUS UPDATING VIA LDAC
Depending on the status of both
SYNC
data has been transferred into the input register of the DACs,
there are two ways to update the data registers and DAC outputs.
Individual DAC Updating
In individual DAC updating mode,
LDAC
is being clocked into the input shift register. The addressed
DAC output is updated on the rising edge of
Simultaneous Updating of All DACs
In simultaneous updating of all DACs mode,
while data is being clocked into the input shift register. All DAC
outputs are updated by taking
LDAC
has been taken high. The update then occurs on the falling edge
LDAC
of
.
See Figure 41 for a simplified block diagram of the DAC load
circuitry.
REFAB, REFCD
LDAC
14-BIT
DAC
DATA
REGISTER
LDAC
and
, and after
is held low while data
SYNC
.
LDAC
is held high
low any time after
OUTPUT
I/V AMPLIFIER
VOUTx
SYNC
TRANSFER FUNCTION
Tabl e 7 and Tab l e 8 show the ideal input code to output voltage
relationship for offset binary data coding and twos complement
data coding, respectively.
The output voltage expression for the AD5744R is given by
D
⎤
V
OUT
= −2 × V
REFIN
+ 4 × V
REFIN
⎡
⎢
⎣
⎥
384,16
⎦
where:
D is the decimal equivalent of the code loaded to the DAC.
is the reference voltage applied at the REFAB and
V
REFIN
REFCD pins.
ASYNCHRONOUS CLEAR (CLR)
CLR
is a negative edge triggered clear that allows the outputs to
be cleared to either 0 V (twos complement coding) or negative full
scale (offset binary coding). It is necessary to maintain
for a minimum amount of time for the operation to complete
(see ). When the Figure 2
CLR
signal is returned high, the output
remains at the cleared value until a new value is programmed.
CLR
If
is at 0 V at power-on, all DAC outputs are updated with
the clear value. A clear can also be initiated through software by
writing the command of 0x04XXXX to the AD5744R.
CLR
low
INPUT
REGISTER
SCLK
SYNC
SDIN
Figure 41. Simplified Serial Interface of Input Loading Circuitry
INTERFACE
LOGIC
for One DAC Channel
SDO
06065-062
Table 7. Ideal Output Voltage to Input Code Relationship—Offset Binary Data Coding
Digital Input Analog Output
MSB LSB V
11 1111 1111 1111 +2 V
10 0000 0000 0001 +2 V
10 0000 0000 0000
01 1111 1111 1111
00 0000 0000 0000
OUT
× (8191/8192)
REF
× (1/8192)
REF
0 V
−2 V
× (1/8192)
REF
−2 V
× (8191/8192)
REF
Table 8. Ideal Output Voltage to Input Code Relationship—Twos Complement Data Coding
Digital Input Analog Output
MSB LSB V
01 1111 1111 1111 +2 V
00 0000 0000 0001 +2 V
00 0000 0000 0000
11 1111 1111 1111
10 0000 0000 0000
OUT
× (8191/8192)
REF
× (1/8192)
REF
0 V
−2 V
× (1/8192)
REF
−2 V
× (8191/8192)
REF
Rev. C | Page 23 of 32
Page 24
AD5744R
REGISTERS
Table 9. Input Shift Register Format
MSB
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 to DB0
R/W
Table 10. Input Shift Register Bit Function Descriptions
Register Bit Description
R/W
REG2, REG1, REG0
0 0 0 Function register
0 1 0 Data register
0 1 1 Coarse gain register
1 0 0 Fine gain register
A2, A1, A0 Decodes the DAC channels
0 0 0 DAC A
0 0 1 DAC B
0 1 0 DAC C
0 1 1 DAC D
1 0 0 All DACs
Data Data bits
0 REG2 REG1 REG0 A2 A1 A0 Data
Indicates a read from or a write to the addressed register
Used in association with the address bits, determines if a read or write operation is to the data register, offset
register, gain register, or function register.
REG2 REG1 REG0 Function
A2 A1 A0 Channel Address
LSB
FUNCTION REGISTER
The function register is addressed by setting the three REG bits to 000. The values written to the address bits and the data bits determine
the function addressed. The functions available via the function register are outlined in Table 1 1 and Tabl e 12 .
Table 11. Function Register Options
REG2 REG1 REG0 A2 A1 A0 DB15 to DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 0 0 0 NOP, data = don’t care
0 0 0 0 0 1 Don’t care
0 0 0 1 0 0 Clear, data = don’t care
0 0 0 1 0 1 Load, data = don’t care
Table 12. Explanation of Function Register Options
Option Description
NOP No operation instruction used in readback operations.
Local Ground
Offset Adjust
D0, D1 Direction
D0, D1 Value
SDO Disable
Clear Addressing this function resets the DAC outputs to 0 V in twos complement mode and negative full scale in binary mode.
Load Addressing this function updates the data registers and, consequently, the analog outputs.
Set by the user to enable the local ground offset adjust function.
Cleared by the user to disable the local ground offset adjust function (default). See the Design Features section for more
information.
Set by the user to enable the D0 and D1 pins as outputs.
Cleared by the user to enable the D0 and D1 pins as inputs (default). See the Design Features section for more information.
I/O port status bits. Logic values written to these locations determine the logic outputs on the D0 and D1 pins when
configured as outputs. These bits indicate the status of the D0 and D1 pins when the I/O port is active as an input. When
enabled as inputs, these bits are don’t cares during a write operation.
Set by the user to disable the SDO output.
Cleared by the user to enable the SDO output (default).
Local ground
offset adjust
D1
direction
D1
value
D0
direction
D0
value
SDO
disable
Rev. C | Page 24 of 32
Page 25
AD5744R
DATA REGISTER
The data register is addressed by setting the three REG bits to 010. The DAC address bits select the DAC channel with which the data
transfer takes place (see Tabl e 10 ). The data bits are positioned in DB15 to DB2, as shown in Tabl e 13.
Table 13. Programming the Data Register
REG2 REG1 REG0 A2 A1 A0 DB15 to DB2 DB1 DB0
0 1 0 DAC address 14-bit DAC data X X
COARSE GAIN REGISTER
The coarse gain register is addressed by setting the three REG bits to 011. The DAC address bits select the DAC channel with which the
data transfer takes place (see Table 1 0). The coarse gain register is a 2-bit register that allows the user to select the output range of each
DAC as shown in Tab l e 1 5 .
Table 14. Programming the Coarse Gain Register
REG2 REG1 REG0 A2 A1 A0 DB15 to DB2 DB1 DB0
0 1 1 DAC address Don’t care CG1 CG0
Table 15. Output Range Selection
Output Range CG1 CG0
±10 V (Default) 0 0
±10.2564 V 0 1
±10.5263 V 1 0
FINE GAIN REGISTER
The fine gain register is addressed by setting the three REG bits to 100. The DAC address bits select the DAC channel with which the data
transfer takes place (see Tabl e 10 ). The AD5744R fine gain register is a 6-bit register that allows the user to adjust the gain of each DAC
channel by −8 LSBs to +7.75 LSBs in 0.25 LSB steps, as shown in Tabl e 16 and Ta b le 1 7 . The adjustment is made to both the positive fullscale points and the negative full-scale points simultaneously, with each point adjusted by one-half of one step. The fine gain register
coding is twos complement.
Table 16. Programming the Fine Gain Register
REG2 REG1 REG0 A2 A1 A0 DB15 to DB6 DB5 DB4 DB3 DB2 DB1 DB0
1 0 0 DAC address Don’t care FG5 FG4 FG3 FG2 FG1 FG0
Table 17. Fine Gain Register Options
Gain Adjustment FG5 FG4 FG3 FG2 FG1 FG0
+7.75 LSBs 0 1 1 1 1 1
+7.5 LSBs 0 1 1 1 1 0
No Adjustment (Default) 0 0 0 0 0 0
−7.75 LSBs 1 0 0 0 0 1
−8 LSBs 1 0 0 0 0 0
Rev. C | Page 25 of 32
Page 26
AD5744R
DESIGN FEATURES
ANALOG OUTPUT CONTROL
In many industrial process control applications, it is vital that
the output voltage be controlled during power-up and during
brownout conditions. When the supply voltages are changing,
the VOUTx pins are clamped to 0 V via a low impedance path.
To prevent the output amp from being shorted to 0 V during this
time, Transmission Gate G1 is also opened (see Figure 42).
RSTOUT
VOLTAGE
MONITOR
AND
CONTROL
G1
Figure 42. Analog Output Control Circuitry
G2
RSTIN
VOUTA
AGNDA
06065-063
These conditions are maintained until the power supplies stabilize
and a valid word is written to the data register. G2 then opens, and
G1 closes. Both transmission gates are also externally controllable
via the reset in (
RSTIN
) control input. For example, if
driven from a battery supervisor chip, the
RSTIN
RSTIN
is
input is driven
low to open G1 and close G2 on power-off or during a brownout.
Conversely, the on-chip voltage detector output (
RSTOUT
) is
also available to the user to control other parts of the system.
The basic transmission gate functionality is shown in . Figure 42
PROGRAMMABLE SHORT-CIRCUIT PROTECTION
The short-circuit current (ISC) of the output amplifiers can be
programmed by inserting an external resistor between the ISCC
pin and the PGND pin. The programmable range for the current is
500 μA to 10 mA, corresponding to a resistor range of 120 kΩ to
6 kΩ . The resistor value is calculated as follows:
60
R ≈
I
SC
If the ISCC pin is left unconnected, the short-circuit current
limit defaults to 5 mA. It should be noted that limiting the shortcircuit current to a small value can affect the slew rate of the
output when driving into a capacitive load. Therefore, the value
of the short-circuit current that is programmed should take into
account the size of the capacitive load being driven.
DIGITAL I/O PORT
The AD5744R contains a 2-bit digital I/O port (D1 and D0).
These bits can be configured independently as inputs or outputs
and can be driven or have their values read back via the serial
interface. The I/O port signals are referenced to DV
and DGND.
CC
When configured as outputs, they can be used as control signals
to multiplexers or can be used to control calibration circuitry
elsewhere in the system. When configured as inputs, the logic
signals from limit switches, for example, can be applied to D0
and D1 and can be read back using the digital interface.
DIE TEMPERATURE SENSOR
The on-chip die temperature sensor provides a voltage output that
is linearly proportional to the Celsius temperature scale. Its nominal output voltage is 1.47 V at 25°C die temperature, varying at
5 mV/°C, giving a typical output range of 1.175 V to 1.9 V over the
full temperature range. Its low output impedance and linear output
simplify interfacing to temperature control circuitry and analog-todigital converters (ADCs). The temperature sensor is provided
as more of a convenience than as a precise feature; it is intended
for indicating a die temperature change for recalibration purposes.
LOCAL GROUND OFFSET ADJUST
The AD5744R incorporates a local ground offset adjust feature
that, when enabled in the function register, adjusts the DAC
outputs for voltage differences between the individual DAC ground
pins and the REFGND pin, ensuring that the DAC output voltages
are always referenced to the local DAC ground pin. For example, if
the AGNDA pin is at +5 mV with respect to the REFGND pin, and
VOUTA is measured with respect to AGNDA, a −5 mV error
results, enabling the local ground offset adjust feature to adjust
VOUTA by +5 mV, thereby eliminating the error.
Rev. C | Page 26 of 32
Page 27
AD5744R
APPLICATIONS INFORMATION
TYPICAL OPERATING CIRCUIT
Figure 43 shows the typical operating circuit for the AD5744R.
The only external components needed for this precision 14-bit
DAC are decoupling capacitors on the supply pins and reference
inputs and an optional short-circuit current setting resistor.
Because the AD5744R incorporates a voltage reference and
reference buffers, it eliminates the need for an external bipolar
reference and associated buffers, resulting in an overall savings
in both cost and board space.
In Figure 43, AV
to −15 V; but AV
±11.4 V to ±16.5 V. In Figure 43, AGNDx is connected to
REFGND.
Precision Voltage Reference Selection
To achieve the optimum performance from the AD5744R over
its full operating temperature range, an external voltage reference
must be used. Care must be taken in the selection of a precision
voltage reference. The AD5744R has two reference inputs, REFAB
and REFCD. The voltages applied to the reference inputs are used
to provide a buffered positive and negative reference for the DAC
cores. Therefore, any error in the voltage reference is reflected
in the outputs of the device.
There are four possible sources of error to consider when choosing
a voltage reference for high accuracy applications: initial accuracy,
temperature coefficient of the output voltage, long term drift,
and output voltage noise.
is connected to +15 V, and AVSS is connected
DD
and AVSS can operate with supplies from
DD
Initial accuracy error on the output voltage of an external reference could lead to a full-scale error in the DAC. Therefore, to
minimize these errors, a reference with low initial accuracy
error specification is preferred. Choosing a reference with an
output trim adjustment, such as the ADR425, allows a system
designer to trim system errors out by setting the reference
voltage to a voltage other than the nominal. The trim adjustment
can also be used at temperature to trim out any error.
Long term drift is a measure of how much the reference output
voltage drifts over time. A reference with a tight long-term drift
specification ensures that the overall solution remains relatively
stable over its entire lifetime.
The temperature coefficient of a reference output voltage affects
INL, DNL, and TUE. A reference with a tight temperature coefficient specification should be chosen to reduce the dependence
of the DAC output voltage on ambient conditions.
In high accuracy applications, which have a relatively low noise
budget, reference output voltage noise must be considered. It is
important to choose a reference with as low an output noise
voltage as practical for the system resolution that is required.
Precision voltage references, such as the ADR435 (XFET® design),
produce low output noise in the 0.1 Hz to 10 Hz region. However,
as the circuit bandwidth increases, filtering the output of the
reference may be required to minimize the output noise.
Table 18. Some Precision References Recommended for Use with the AD5744R
Initial Accuracy
Part No.
ADR435 ±6 30 3 3.5
ADR425 ±6 50 3 3.4
ADR02 ±5 50 3 10
ADR395 ±6 50 25 5
AD586 ±2.5 15 10 4
(mV Maximum)
Long-Term Drift
(ppm Typical)
Temperature Drift
(ppm/°C Maximum)
0.1 Hz to 10 Hz Noise
(μV p-p Typical)
Rev. C | Page 27 of 32
Page 28
AD5744R
V
–15V
TEMP
BIN/2sCO MP
+5V
SYNC
SCLK
SDIN
SDO
LDAC
D0
D1
1
2
3
4
5
6
7
8
+15
10µF
100nF
32 31 30 29 28 27 26 25
DD
AV
SYNC
BIN/2sCOMP
SCLK
SDIN
SDO
CLR
AD5744R
LDAC
D0
D1
RSTOUT
RSTIN
9 10 11 12 13 14 15 16
SS
AV
DGND
10µF
100nF
TEMP
REFGND
DVCCAVDDPGND
10µF
REFCD
REFAB
REFOUT
AGNDA
VOUTA
VOUTB
AGNDB
AGNDC
VOUTC
VOUTD
AGNDD
24
23
22
21
20
19
18
17
VOUTA
VOUTB
VOUTC
VOUTD
AVSSISCC
RSTOUT
RSTIN
10µF
100nF
100nF
10µF
100nF
+5V
10µF
+15V –15V
Figure 43. Typical Operating Circuit
06065-064
Rev. C | Page 28 of 32
Page 29
AD5744R
LAYOUT GUIDELINES
In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure
the rated performance. Design the PCB on which the AD5744R
is mounted such that the analog and digital sections are separated
and confined to certain areas of the board. If the AD5744R is in
a system where multiple devices require an AGNDx-to-DGND
connection, establish the connection at one point only. Establish
the star ground point as close as possible to the device. The
AD5744R should have ample supply bypassing of 10 μF in parallel
with 0.1 μF on each supply located as close to the package as
possible, ideally right up against the device. The 10 μF capacitors are of the tantalum bead type. The 0.1 μF capacitor should
have low effective series resistance (ESR) and low effective series
inductance (ESI), such as the common ceramic types that
provide a low impedance path to ground at high frequencies to
handle transient currents due to internal logic switching.
The power supply lines of the AD5744R should use as large a
trace as possible to provide low impedance paths and reduce
the effects of glitches on the power supply line. Shield fastswitching signals, such as clocks with digital ground to avoid
radiating noise to other parts of the board; they should never be
run near the reference inputs. A ground line routed between
the SDIN and SCLK lines helps reduce cross-talk between them.
(A ground line is not required on a multi-layer board because
it has a separate ground plane; however, it is helpful to separate
the lines.) It is essential to minimize noise on the reference inputs
because it couples through to the DAC output. Avoid crossover
of digital and analog signals. Run traces on opposite sides of the
board at right angles to each other to reduce the effects of feed-
through on the board. A microstrip technique is recommended
but not always possible with a double-sided board. In this
technique, the component side of the board is dedicated to the
ground plane, and the signal traces are placed on the solder side.
GALVANICALLY ISOLATED INTERFACE
In many process control applications, it is necessary to provide
an isolation barrier between the controller and the unit being
controlled to protect and isolate the controlling circuitry from
any hazardous common-mode voltages that may occur. Isocouplers provide voltage isolation in excess of 2.5 kV. The serial
loading structure of the AD5744R makes it ideal for isolated
interfaces because the number of interface lines is kept to a minimum. Figure 44 shows a 4-channel isolated interface to the
AD5744R using an ADuM1400 iCoupler® product. For more
information on iCoupler products, refer to www.analog.com.
MICROPROCESSOR INTERFACING
Microprocessor interfacing to the AD5744R is accomplished
using a serial bus that uses standard protocol that is compatible
with microcontrollers and DSP processors. The communications
channel is a 3-wire (minimum) interface consisting of a clock
signal, a data signal, and a synchronization signal. The AD5744R
requires a 24-bit data-word with data valid on the falling edge
of SCLK.
For all the interfaces, a DAC output update can be performed
automatically when all the data is clocked in, or it can be done
under the control of
can be read using the readback function.
LDAC
. The contents of the data register
MICROCONTROL LER
SERIAL CLOCK OUT TO SCLK
SERIAL DATA OUT TO SDIN
SYNC OUT TO SYNC
CONTROL OUT TO LDAC
*ADDITIONAL PI NS OMITT ED FOR CLARIT Y.
ADuM1400*
V
IA
V
IB
V
IC
V
ID
ENCODE DECODE
ENCODE DECODE
ENCODE DECODE
ENCODE DECODE
Figure 44. Isolated Interface
V
OA
V
OB
V
OC
V
OD
06065-065
Rev. C | Page 29 of 32
Page 30
AD5744R
OUTLINE DIMENSIONS
1.20
0.75
1.05
1.00
0.95
0.15
SEATING
0.05
PLANE
VIEW A
ROTATED 90° CCW
0° MIN
0.08 MAX
COPLANARIT Y
0.20
0.09
7°
3.5°
0°
0.60
0.45
MAX
VIEW A
32
1
8
9
LEAD PITCH
9.00 BSC SQ
PIN 1
TOP VIEW
(PINS DOWN)
0.80
BSC
0.45
0.37
0.30
25
24
7.00
BSC SQ
17
16
COMPLIANT TO JEDEC STANDARDS MS-026-AB A
020607-A
Figure 45. 32-Lead Thin Plastic Quad Flat Package [TQFP]
(SU-32-2)
Dimensions shown in millimeters
ORDERING GUIDE
Internal
Model Function INL Temperature Range
Reference
Package Description
AD5744RCSUZ1 Quad 14-Bit DAC ±1 LSB Maximum −40°C to +85°C +5 V 32-Lead TQFP SU-32-2
AD5744RCSUZ-REEL71 Quad 14-Bit DAC ±1 LSB Maximum −40°C to +85°C +5 V 32-Lead TQFP SU-32-2
1
Z = RoHS Compliant Part.
Package
Option
Rev. C | Page 30 of 32
Page 31
AD5744R
NOTES
Rev. C | Page 31 of 32
Page 32
AD5744R
NOTES
©2008–2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06065-0-8/09(C)
Rev. C | Page 32 of 32
Loading...