Datasheet AD5737 Datasheet (ANALOG DEVICES)

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Page 1

Quad-Channel, 12-Bit, Serial Input, 4 mA to 20 mA Output

DAC with Dynamic Power Control and HART Connectivity

Data Sheet

FEATURES

12-bit resolution and monotonicity Dynamic power control for thermal management

or external PMOS mode

Current output ranges: 0 mA to 20 mA, 4 mA to 20 mA,

and 0 mA to 24 mA

±0.1% total unadjusted error (TUE) maximum User-programmable offset and gain On-chip diagnostics On-chip reference: ±10 ppm/°C maximum

−40°C to +105°C temperature range

APPLICATIONS

Process control Actuator control PLCs HART network connectivity

GENERAL DESCRIPTION

The AD5737 is a quad-channel current output DAC that operates with a power supply range from 10.8 V to 33 V. On-chip dynamic power control minimizes package power dissipation by regulating the voltage on the output driver from

FUNCTIONAL BLOCK DIAGRAM

+15V

AGND

AD5737

7.4 V to 29.5 V using a dc-to-dc boost converter optimized for minimum on-chip power dissipation.

Each channel has a corresponding CHART pin so that HART signals can be coupled onto the current output of the AD5737.

The AD5737 uses a versatile 3-wire serial interface that operates at clock rates of up to 30 MHz and is compatible with standard SPI, QSPI™, MICROWIRE®, DSP, and microcontroller interface standards. The serial interface also features optional CRC-8 packet error checking, as well as a watchdog timer that monitors activity on the interface.

PRODUCT HIGHLIGHTS

1. Dynamic power control for thermal management.

2. 12-bit performance.

3. Quad channel.

4. HART compliant.

COMPANION PRODUCTS

Product Family: AD5755, AD5755-1, AD5757, AD5735 External References: ADR445, ADR02 Digital Isolators: ADuM1410, ADuM1411 Power: ADP2302, ADP2303 Additional companion products on the AD5737 product page

5.0V

BOOST_x

DGND

LDAC

SCLK

SDIN

SYNC

SDO

CLEAR

FAU LT

ALERT

AD1

AD0

REFOUT

REFIN

NOTES

1. x = A, B, C, OR D.

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

DIGITAL

INTERFACE

REFERENCE

AD5737

GAIN REG A

OFFSET REG A

DAC CHANNEL A

DAC CHANNEL B

DAC CHANNEL C

DAC CHANNEL D

7.4V TO 29.5V

DC-TO-DC

CONVERTER

OUT_x

DAC A

CURRENT

OUTPUT RANGE

SCALING

SET_x

CHARTx

10067-101

Figure 1.

Page 2

AD5737 Data Sheet

Features .............................................................................................. 1

Applications ....................................................................................... 1 

General Description ......................................................................... 1

Product Highlights ........................................................................... 1

Companion Products ....................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Detailed Functional Block Diagram .............................................. 3

Specifications ..................................................................................... 4

AC Performance Characteristics ................................................ 6

Timing Characteristics ................................................................ 6

Absolute Maximum Ratings ............................................................ 9

Thermal Resistance ...................................................................... 9

ESD Caution .................................................................................. 9

Pin Configuration and Function Descriptions ........................... 10

Typical Performance Characteristics ........................................... 13

Current Outputs ......................................................................... 13

DC-to-DC Converter ................................................................. 17

Reference ..................................................................................... 18

General ......................................................................................... 19

Terminology .................................................................................... 20

Theory of Operation ...................................................................... 21

DAC Architecture ....................................................................... 21

Power-On State of the AD5737 ................................................ 21

Serial Interface ............................................................................ 21

Transfer Function ....................................................................... 22

Registers ........................................................................................... 23

Enabling the Output ................................................................... 24

Reprogramming the Output Range ......................................... 24

Data Registers ............................................................................. 25

REVISION HISTORY

11/11—Rev. 0 to Rev. A

Change to Accuracy, External R

Changes to Power-On State of the AD5737 Section .................. 21

Changes to Readback Operation Section and Readback

Example Section.............................................................................. 30

7/11—Revision 0: Initial Version

Parameter in Table 1 ............ 4

SET

Control Registers ........................................................................ 27

Readback Operation .................................................................. 30

Device Features ............................................................................... 32

Fault Output ................................................................................ 32

Digital Offset and Gain Control ............................................... 32

Status Readback During a Write .............................................. 32

Asynchronous Clear ................................................................... 32

Packet Error Checking ............................................................... 33

Watchdog Timer ......................................................................... 33

Alert Output ................................................................................ 33

Internal Reference ...................................................................... 33

External Current Setting Resistor ............................................ 33

HART Connectivity ................................................................... 34

Digital Slew Rate Control .......................................................... 34

Dynamic Power Control ............................................................ 35

DC-to-DC Converters ............................................................... 35

AICC Supply Requirements—Static .......................................... 36

AICC Supply Requirements—Slewing ...................................... 37

External PMOS Mode ................................................................ 38

Applications Information .............................................................. 39

Current Output Mode with Internal R

Precision Voltage Reference Selection ..................................... 39

Driving Inductive Loads ............................................................ 39

Transient Voltage Protection .................................................... 40

Microprocessor Interfacing ....................................................... 40

Layout Guidelines....................................................................... 40

Galvanically Isolated Interface ................................................. 41

Outline Dimensions ....................................................................... 42

Ordering Guide .......................................................................... 42

................................ 39

SET

Rev. A | Page 2 of 44

Page 3

Data Sheet AD5737

DETAILED FUNCTIONAL BLOCK DIAGRAM

5.0V

+15V

BOOST_A

AGND

DGND

LDAC

CLEAR

SCLK

SDIN

SYNC

SDO

FAULT

ALERT

REFOUT

REFIN

AD1

AD0

POWER-ON

RESET

INPUT SHIFT

REGIS TER

AND

CONTROL

STATUS

REGIS TER

WATCHDOG

TIMER

(SPI ACTIVITY)

REF

REFERENCE

BUFFERS

AD5737

DAC

REG A

GAIN REG A

OFFSET REG A

DAC CHANNEL A

DAC CHANNEL B

DAC CHANNEL C

DAC CHANNEL D

DC-TO-DC

CONVERT ER

DYNAMIC

POWER

CONTROL

DAC

INPUTDATA REG A

DAC A

SWB, SWC, SW

7.4V TO 29.5V

R2 R3

SEN1VSEN2

BOOST_ B,VBOOST_C,VBOOST_D

OUT_A

SET_A

CHARTA

, I

SET_B

OUT_C

, R

SET_C

, I

OUT_D

, R

SET_D

OUT_B

CHARTB, CHARTC, CHARTD

10067-001

Figure 2.

Rev. A | Page 3 of 44

Page 4

AD5737 Data Sheet

SPECIFICATIONS

AVDD = V REFIN = 5 V; R

Table 1.

Parameter

CURRENT OUTPUT

Output Current Ranges 0 24 mA 0 20 mA 4 20 mA

Resolution 12 Bits ACCURACY, EXTERNAL R

Total Unadjusted Error (TUE) −0.1 ±0.019 +0.1 % FSR

TUE Long-Term Stability 100 ppm FSR Drift after 1000 hours, TJ = 150°C

Relative Accuracy (INL) −0.032 ±0.006 +0.032 % FSR

Differential Nonlinearity (DNL) −1 +1 LSB Guaranteed monotonic

Offset Error −0.1 ±0.012 +0.1 % FSR

Offset Error Drift

Gain Error −0.1 ±0.004 +0.1 % FSR

Gain TC

Full-Scale Error −0.1 ±0.014 +0.1 % FSR

Full-Scale TC

DC Crosstalk 0.0005 % FSR External R ACCURACY, INTERNAL R

Total Unadjusted Error (TUE)

TUE Long-Term Stability 180 ppm FSR Drift after 1000 hours, TJ = 150°C

Relative Accuracy (INL) −0.032 ±0.006 +0.032 % FSR

Differential Nonlinearity (DNL) −1 +1 LSB Guaranteed monotonic

Offset Error

Offset Error Drift

Gain Error −0.12 ±0.004 +0.12 % FSR

Gain TC

Full-Scale Error

Full-Scale TC

DC Crosstalk OUTPUT CHARACTERISTICS

Current Loop Compliance Voltage

Output Current Drift vs. Time Drift after 1000 hours, ¾ scale output, TJ = 150°C 90 ppm FSR External R 140 ppm FSR Internal R

Resistive Load 1000 Ω

DC Output Impedance 100 MΩ

DC PSRR 0.02 1 μA/V REFERENCE INPUT/OUTPUT

Reference Input

Reference Input Voltage 4.95 5 5.05 V For specified performance DC Input Impedance 45 150 MΩ

Reference Output

Output Voltage 4.995 5 5.005 V TA = 25°C Reference TC

= 15 V; DVDD = 2.7 V to 5.5 V; AVCC = 4.5 V to 5.5 V; dc-to-dc converter disabled; AGND = DGND = GNDSWx = 0 V;

BOOST_x

= 300 Ω; all specifications T

SET

Min Typ Max Unit Test Conditions/Comments

MIN

to T

, unless otherwise noted.

MAX

Assumes ideal resistor (see the External Current Setting Resistor section for more information)

±3 ppm FSR/°C

±5 ppm FSR/°C

SET

3, 4

−0.1 ±0.017 +0.1 % FSR

±6 ppm FSR/°C

±9 ppm FSR/°C

3, 4

−0.14 ±0.02 +0.14 % FSR

±4 ppm FSR/°C

−0.14 ±0.022 +0.14 % FSR

±14 ppm FSR/°C

−0.011 % FSR Internal R

BOOST_x

2.4

−

BOOST_x

2.7

−

SET

The dc-to-dc converter has been characterized with a maximum load of 1 kΩ, chosen such that compliance is not exceeded; see Figure 30 and the DC-DC MaxV bits in Table 27

−10 ±5 +10 ppm/°C

Rev. A | Page 4 of 44

Page 5

Data Sheet AD5737

Parameter

Output Noise (0.1 Hz to 10 Hz)

Noise Spectral Density Output Voltage Drift vs. Time

Capacitive Load

Min Typ Max Unit Test Conditions/Comments

7 μV p-p 100 nV/√Hz At 10 kHz

180 ppm Drift after 1000 hours, TJ = 150°C

1000 nF Load Current 9 mA See Figure 41 Short-Circuit Current 10 mA Line Regulation Load Regulation Thermal Hysteresis

3 ppm/V See Figure 42

95 ppm/mA See Figure 41

160 ppm First temperature cycle

5 ppm Second temperature cycle DC-TO-DC CONVERTER

Switch

Switch On Resistance 0.425 Ω Switch Leakage Current 10 nA Peak Current Limit 0.8 A

Oscillator

Oscillator Frequency 11.5 13 14.5 MHz

This oscillator is divided down to provide the dc-to-dc converter switching frequency

Maximum Duty Cycle 89.6 % At 410 kHz dc-to-dc switching frequency

DIGITAL INPUTS

JEDEC compliant

Input High Voltage, VIH 2 V Input Low Voltage, VIL 0.8 V Input Current −1 +1 μA Per pin Pin Capacitance 2.6 pF Per pin

DIGITAL OUTPUTS

SDO, ALERT Pins

Output Low Voltage, VOL 0.4 V Sinking 200 μA Output High Voltage, VOH DVDD − 0.5 V Sourcing 200 μA High Impedance Leakage

−1 +1 μA

Current

High Impedance Output

2.5 pF

Capacitance

FAU LT Pin

Output Low Voltage, VOL 0.4 V 10 kΩ pull-up resistor to DVDD

0.6 V At 2.5 mA Output High Voltage, VOH 3.6 V 10 kΩ pull-up resistor to DVDD

POWER REQUIREMENTS

AVDD 9 33 V DVDD 2.7 5.5 V AVCC 4.5 5.5 V AIDD 7 7.5 mA DICC 9.2 11 mA

= DVDD, VIL = DGND, internal oscillator

running, over supplies

AICC 1 mA Outputs unloaded, over supplies

BOOST

Power Dissipation 155 mW

1 mA Per channel, 0 mA output

= 15 V, DVDD = 5 V, dc-to-dc converter

enabled, outputs disabled

Temperature range: −40°C to +105°C; typical at +25°C.

Guaranteed by design and characterization; not production tested.

For current outputs with internal R

and loaded with the same code.

See the Current Output Mode with Internal R

Efficiency plots in Figure 32 through Figure 35 include the I

, the offset, full-scale, and TUE measurements exclude dc crosstalk. The measurements are made with all four channels enabled

SET

section for more information about dc crosstalk.

SET

quiescent current.

BOOST

Rev. A | Page 5 of 44

Page 6

AD5737 Data Sheet

AC PERFORMANCE CHARACTERISTICS

AVDD = V REFIN = 5 V; R

= 15 V; DVDD = 2.7 V to 5.5 V; AVCC = 4.5 V to 5.5 V; dc-to-dc converter disabled; AGND = DGND = GNDSWx = 0 V;

BOOST_x

= 300 Ω; all specifications T

MIN

to T

, unless otherwise noted.

MAX

Table 2.

Parameter

DYNAMIC PERFORMANCE, CURRENT

Min Typ Max Unit Test Conditions/Comments

OUTPUT Output Current Settling Time 15 μs To 0.1% FSR, 0 mA to 24 mA range See Test Conditions/Comments ms

For settling times when using the dc-to-dc converter, see Figure 25, Figure 26, and Figure 27

Output Noise (0.1 Hz to 10 Hz

0.15 LSB p-p 12-bit LSB, 0 mA to 24 mA range

Bandwidth)

Output Noise Spectral Density 0.5 nA/√Hz

Measured at 10 kHz, midscale output, 0 mA to 24 mA range

Guaranteed by design and characterization; not production tested.

TIMING CHARACTERISTICS

AVDD = V REFIN = 5 V; R

Table 3.

Parameter

t1 33 ns min SCLK cycle time t2 13 ns min SCLK high time t3 13 ns min SCLK low time t4 13 ns min t5 13 ns min

t6 198 ns min t7 5 ns min Data setup time

t8 5 ns min Data hold time t9 20 μs min

5 μs min t10 10 ns min t11 500 ns max t12 See Table 2 μs max DAC output settling time

t13 10 ns min CLEAR high time t14 5 μs max CLEAR activation time t15 40 ns max SCLK rising edge to SDO valid t16 21 μs min All DACs updated 5 μs min Single DAC updated t17 500 ns min

t18 800 ns min

20 μs min All DACs updated 5 μs min Single DAC updated

Guaranteed by design and characterization; not production tested.

All input signals are specified with t

See Figure 3, Figure 4, Figure 5, and Figure 6.

This specification applies if

= 15 V; DVDD = 2.7 V to 5.5 V; AVCC = 4.5 V to 5.5 V; dc-to-dc converter disabled; AGND = DGND = GNDSWx = 0 V;

BOOST_x

= 300 Ω; all specifications T

1, 2, 3

Limit at T

MIN

, T

Unit Description

MAX

MIN

to T

, unless otherwise noted.

MAX

falling edge to SCLK falling edge setup time

SYNC 24th/32nd SCLK falling edge to SYNC

high time

SYNC

rising edge to LDAC falling edge (all DACs updated or any channel has

SYNC

rising edge (see ) Figure 53

digital slew rate control enabled)

rising edge to LDAC falling edge (single DAC updated)

SYNC

pulse width low

LDAC

falling edge to DAC output response time

LDAC

rising edge to DAC output response time (LDAC = 0)

SYNC

falling edge to SYNC rising edge

LDAC

pulse width

RESET

high to next SYNC low (digital slew rate control enabled)

SYNC

= t

= 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.2 V.

RISE

FALL

LDAC

is held low during the write cycle; otherwise, see t9.

Rev. A | Page 6 of 44

Page 7

Data Sheet AD5737

Timing Diagrams

SCLK

SYNC

SDIN

LDAC

OUT_x

LDAC = 0

OUT_x

CLEAR

OUT_x

12 24

MSB

LSB

RESET

10067-002

Figure 3. Serial Interface Timing Diagram

SCLK

SYNC

SDIN

SDO

1 1

MSB MSBLSB LSB

INPUT WORD SPECIFIES REGISTER TO BE RE AD

UNDEFINED SELECTED REGISTER DATA

24 24

NOP CONDITI ON

MSB LSB

CLOCKED OUT

Figure 4. Readback Timing Diagram

10067-003

Rev. A | Page 7 of 44

Page 8

AD5737 Data Sheet

SCLK

SYN

SDIN

SDO

LSB MSB

12 16

DUT_

R/W

DUT_

AD1

SDO DISABLED

XXXD15D14 D1D0

AD0

SDO_ ENAB

STATUSSTATUSSTATUSSTATUS

10067-004

Figure 5. Status Readback During Write, Timing Diagram

200µA I

TO OUTPUT

50pF

200µA I

Figure 6. Load Circuit for SDO Timing Diagrams

VOH (MIN) OR V

(MAX)

10067-005

Rev. A | Page 8 of 44

Page 9

Data Sheet AD5737

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted. Transient currents of up to 100 mA do not cause SCR latch-up.

Table 4.

Parameter Rating

AVDD, V

to AGND, DGND −0.3 V to +33 V

BOOST_x

AVCC to AGND −0.3 V to +7 V DVDD to DGND −0.3 V to +7 V Digital Inputs to DGND

−0.3 V to DV

+ 0.3 V or +7 V

(whichever is less)

Digital Outputs to DGND

−0.3 V to DV

+ 0.3 V or +7 V

(whichever is less)

REFIN, REFOUT to AGND

−0.3 V to AV

+ 0.3 V or +7 V

(whichever is less)

OUT_x

to AGND

AGND to V

BOOST_x

or 33 V if

using the dc-to-dc converter SWx to AGND −0.3 V to +33 V AGND, GNDSWx to DGND −0.3 V to +0.3 V Operating Temperature Range ( TA)

Industrial1 −40°C to +105°C Storage Temperature Range −65°C to +150°C Junction Temperature (TJ max) 125°C Power Dissipation (TJ max − TA)/θJA Lead Temperature JEDEC industry standard

Soldering J-STD-020

Power dissipated on chip must be derated to keep the junction temperature

below 125°C.

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

THERMAL RESISTANCE

Junction-to-air thermal resistance (θJA) is specified for a JEDEC 4-layer test board.

Table 5. Thermal Resistance

Package Type θJA Unit

64-Lead LFCSP (CP-64-3) 20 °C/W

ESD CAUTION

Rev. A | Page 9 of 44

Page 10

AD5737 Data Sheet

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

DCDC_D

INDI

PIN 1

ATO R

SET_CRSET_D

REFOUT

REFINNCCHARTD

646362616059585756555453525150

BOOST_ D

OUT_D

IGATED

COMP

AGNDNCCHARTCNCIGATEC

SET_B

SET_A

AD0

AD1 SYNC SCLK

SDIN

SDO

DGND

LDAC

CLEAR ALERT

FAU LT

3 4 5 6 7 8

9 10 11

12 13 14 15 16

171819202122232425262728293031

DGND

RESET

AD5737

TOP VIEW

(Not to Scale)

DCDC_A

IGATEA

BOOST_A

CHARTA

COMP

OUT_A

AGND

DCDC_B

IGATEB

CHARTB

COMP

REFGND REFGND

NOTES

1. NC = NO CONNEC T. DO NOT CONNECT TO THIS PIN. . THE EXPOSED PADDLE SHOULD BE CONNECTED TO AGND, OR, ALTERNATIVELY,

IT CAN BE LEFT ELECTRI CALLY UNCONNECTED. IT IS RECOMMENDED THAT THE PADDLE BE THERMALLY CONNECTED TO A COPPER PLANE F OR ENHANCED THERMAL PERFO RMANCE.

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

COMP I

OUT_C

BOOST_C

GNDSW GNDSW

AGND SW

GNDSW GNDSW

AGND V

BOOST_B

OUT_B

DCDC_C

10067-006

Figure 7. Pin Configuration

Table 6. Pin Function Descriptions

Pin No. Mnemonic Description

1 R

2 R

SET_B

SET_A

An external, precision, low drift, 15 kΩ current setting resistor can be connected to this pin to improve the

temperature drift performance. For more information, see the External Current Setting Resistor section.

OUT_B

An external, precision, low drift, 15 kΩ current setting resistor can be connected to this pin to improve the

temperature drift performance. For more information, see the External Current Setting Resistor section.

OUT_A

3 REFGND Ground Reference Point for Internal Reference. 4 REFGND Ground Reference Point for Internal Reference. 5 AD0 Address Decode for the Device Under Test (DUT) on the Board. 6 AD1 Address Decode for the DUT on the Board. 7

Frame Synchronization Signal for the Serial Interface. Active low input. When SYNC is low, data is clocked

SYNC

into the input shift register on the falling edge of SCLK.

8 SCLK

Serial Clock Input. Data is clocked into the input shift register on the falling edge of SCLK. The serial interface

operates at clock speeds of up to 30 MHz. 9 SDIN Serial Data Input. Data must be valid on the falling edge of SCLK. 10 SDO Serial Data Output. Used to clock data from the serial register in readback mode (see Figure 4 and Figure 5). 11 DVDD Digital Supply Pin. The voltage range is from 2.7 V to 5.5 V. 12 DGND Digital Ground. 13

Load DAC. This active low input is used to update the DAC register and, consequently, the DAC outputs.

LDAC

When LDAC is tied permanently low, the addressed DAC data register is updated on the rising edge of

SYNC. If LDAC is held high during the write cycle, the DAC input register is updated, but the DAC output

(see ). Using this mode, all analog outputs can be

is updated only on the falling edge of LDAC

updated simultaneously. The

LDAC pin must not be left unconnected.

Figure 3

Rev. A | Page 10 of 44

Page 11

Data Sheet AD5737

Pin No. Mnemonic Description

14 CLEAR

15 ALERT

FAU LT

17 DGND Digital Ground. 18

RESET 19 AVDD Positive Analog Supply Pin. The voltage range is from 9 V to 33 V. 20 NC No Connect. Do not connect to this pin. 21 CHARTA HART Input Connection for DAC Channel A. For more information, see the HART Connectivity section. 22 IGATEA

23 COMP

24 V

BOOST_A

DCDC_A

25 NC No Connect. Do not connect to this pin. 26 I

Current Output Pin for DAC Channel A.

OUT_A

27 AGND Ground Reference Point for Analog Circuitry. This pin must be connected to 0 V. 28 NC No Connect. Do not connect to this pin. 29 CHARTB HART Input Connection for DAC Channel B. For more information, see the HART Connectivity section. 30 NC No Connect. Do not connect to this pin. 31 IGATEB

32 COMP

33 I 34 V

DCDC_B

Current Output Pin for DAC Channel B.

OUT_B

BOOST_B

35 AGND Ground Reference Point for Analog Circuitry. This pin must be connected to 0 V. 36 SWB

37 GNDSWB Ground Connection for DC-to-DC Switching Circuit. This pin should always be connected to ground. 38 GNDSWA Ground Connection for DC-to-DC Switching Circuit. This pin should always be connected to ground. 39 SWA

40 AGND Ground Reference Point for Analog Circuitry. This pin must be connected to 0 V. 41 SWD

42 GNDSWD Ground Connection for DC-to-DC Switching Circuit. This pin should always be connected to ground. 43 GNDSWC Ground Connection for DC-to-DC Switching Circuit. This pin should always be connected to ground. 44 SWC

45 AVCC Supply for DC-to-DC Circuitry. The voltage range is from 4.5 V to 5.5 V. 46 V

47 I 48 COMP

BOOST_C

Current Output Pin for DAC Channel C.

OUT_C

DCDC_C

Active High, Edge Sensitive Input. When this pin is asserted, the output current is set to the programmed clear code bit setting. Only channels enabled to be cleared are cleared. For more information, see the Asynchronous Clear section. When CLEAR is active, the DAC output register cannot be written to.

Active High Output. This pin is asserted when there is no SPI activity on the interface pins for a preset time. For more information, see the Alert Output section.

Active Low, Open-Drain Output. This pin is asserted low when any of the following conditions is detected: open circuit, PEC error, or an overtemperature condition (see the Fault Output section).

Hardware Reset, Active Low Input.

Optional Connection for External Pass Transistor. Leave this pin unconnected when using the dc-to-dc converter. For more information, see the External PMOS Mode section.

DC-to-DC Compensation Capacitor. Connect a 10 nF capacitor from this pin to ground. Used to regulate the feedback loop of the Channel A dc-to-dc converter. Alternatively, if using an external compensation resistor, place a resistor in series with a capacitor to ground from this pin. For more information, see the DC-to-DC Converter Compensation Capacitors section and the AI

Supply Requirements—Slewing section.

Supply for Channel A Current Output Stage (see Figure 48). To use the dc-to-dc converter, connect this pin as shown in Figure 55.

Optional Connection for External Pass Transistor. Leave this pin unconnected when using the dc-to-dc converter. For more information, see the External PMOS Mode section.

DC-to-DC Compensation Capacitor. Connect a 10 nF capacitor from this pin to ground. Used to regulate the feedback loop of the Channel B dc-to-dc converter. Alternatively, if using an external compensation resistor, place a resistor in series with a capacitor to ground from this pin. For more information, see the DC-to-DC Converter Compensation Capacitors section and the AI

Supply Requirements—Slewing section.

Supply for Channel B Current Output Stage (see Figure 48). To use the dc-to-dc converter, connect this pin as shown in Figure 55.

Switching Output for Channel B DC-to-DC Circuitry. To use the dc-to-dc converter, connect this pin as shown in Figure 55.

Switching Output for Channel A DC-to-DC Circuitry. To use the dc-to-dc converter, connect this pin as shown in Figure 55.

Switching Output for Channel D DC-to-DC Circuitry. To use the dc-to-dc converter, connect this pin as shown in Figure 55.

Switching Output for Channel C DC-to-DC Circuitry. To use the dc-to-dc converter, connect this pin as shown in Figure 55.

Supply for Channel C Current Output Stage (see Figure 48). To use the dc-to-dc converter, connect this pin as shown in Figure 55.

DC-to-DC Compensation Capacitor. Connect a 10 nF capacitor from this pin to ground. Used to regulate the feedback loop of the Channel C dc-to-dc converter. Alternatively, if using an external compensation resistor, place a resistor in series with a capacitor to ground from this pin. For more information, see the DC-to-DC Converter Compensation Capacitors section and the AI

Rev. A | Page 11 of 44

Supply Requirements—Slewing section.

Page 12

AD5737 Data Sheet

Pin No. Mnemonic Description

49 IGATEC

50 NC No Connect. Do not connect to this pin. 51 CHARTC HART Input Connection for DAC Channel C. For more information, see the HART Connectivity section. 52 NC No Connect. Do not connect to this pin. 53 AGND Ground Reference Point for Analog Circuitry. This pin must be connected to 0 V. 54 I

Current Output Pin for DAC Channel D.

OUT_D

55 NC No Connect. Do not connect to this pin. 56 V

57 COMP

BOOST_D

DCDC_D

58 IGATED

59 CHARTD HART Input Connection for DAC Channel D. For more information, see the HART Connectivity section. 60 NC No Connect. Do not connect to this pin. 61 REFIN External Reference Voltage Input. 62 REFOUT

63 R

64 R

SET_D

SET_C

EPAD

Optional Connection for External Pass Transistor. Leave this pin unconnected when using the dc-to-dc converter. For more information, see the External PMOS Mode section.

Supply for Channel D Current Output Stage (see Figure 48). To use the dc-to-dc converter, connect this pin as shown in Figure 55.

DC-to-DC Compensation Capacitor. Connect a 10 nF capacitor from this pin to ground. Used to regulate the feedback loop of the Channel D dc-to-dc converter. Alternatively, if using an external compensation resistor, place a resistor in series with a capacitor to ground from this pin. For more information, see the DC-to-DC Converter Compensation Capacitors section and the AICC Supply Requirements—Slewing section.

Optional Connection for External Pass Transistor. Leave this pin unconnected when using the dc-to-dc converter. For more information, see the External PMOS Mode section.

Internal Reference Voltage Output. It is recommended that a 0.1 μF capacitor be placed between REFOUT and REFGND.

An external, precision, low drift, 15 kΩ current setting resistor can be connected to this pin to improve the

temperature drift performance. For more information, see the External Current Setting Resistor section.

OUT_D

An external, precision, low drift, 15 kΩ current setting resistor can be connected to this pin to improve the

temperature drift performance. For more information, see the External Current Setting Resistor section.

OUT_C

Exposed Pad. The exposed paddle should be connected to AGND, or, alternatively, it can be left electrically unconnected. It is recommended that the paddle be thermally connected to a copper plane for enhanced thermal performance.

Rev. A | Page 12 of 44

Page 13

Data Sheet AD5737

TYPICAL PERFORMANCE CHARACTERISTICS

CURRENT OUTPUTS

0.008

0.006

4mA TO 20mA, INTERNAL R 4mA TO 20mA, EXTERNAL R 4mA TO 20mA, INTERNAL R 4mA TO 20mA, EXTERNAL R

, WITH DC- TO-DC CONVERT ER

SET

,WITHDC-TO-DCCONVERTER

SET

0.004

0.002

INL ERROR (%FSR)

–0.002

–0.004

–0.006

AVDD=15V T

=25°C

0 1000 2000 3000 4000

CODE

Figure 8. Integral Nonlinearity Error vs. DAC Code Figure 11. Integral Nonlinearity Error vs. Temperature, Internal R

10067-231

0.008

0.006

0.004

0.002

–0.002

INL ERROR (%FSR)

4mA TO 20mA RANGE M AX INL 0mA TO 24mA RANGE M AX INL 0mA TO 20mA RANGE MAX INL

4mA TO 20mA RANGE MIN INL 0mA TO 24mA RANGE MIN INL 0mA TO 20mA RANGE MIN INL

AVDD=15V

–0.004

–0.006

–0.008

–40 –20 0 20 40 60 80 100

TEMPERATURE (°C)

10067-234

SET

1.0

4mA TO 20mA, INTERNAL R

0.8

4mA TO 20mA, EXTERNAL R 4mA TO 20mA, INTERNAL R 4mA TO 20mA, EXTERNAL R

0.6

,WITH DC-TO-DC CONVERTER

SET

,WITHDC-TO-DCCONVERTER

SET

0.4

0.2

–0.2

DNL ERROR (LSB)

–0.4

AVDD=15V

–0.6

=25°C

–0.8

–1.0

0 1000 2000 3000 4000

CODE

10067-232

0.008

0.006

0.004

–0.002

INL ERROR (%FSR)

0.002

4mA TO 20mA RANGE MAX INL 0mA TO 24mA RANGE MAX INL 0mA TO 20mA RANGE MAX INL

4mA TO 20mA RANGE MIN INL 0mA TO 24mA RANGE MIN INL 0mA TO 20mA RANGE MIN INL

AVDD=15V

–0.004

–0.006

–0.008

–40 –20 0 20 40 60 80 100

TEMPERATURE (°C)

Figure 9. Differential Nonlinearity Error vs. DAC Code Figure 12. Integral Nonlinearity Error vs. Temperature, External R

0.06

0.05

4mA TO 20mA, INTERNAL R 4mA TO 20mA, INTERNAL R

SET

, WITH DC- TO-DC CONVERT ER

SET

0.04

0.03

0.02

0.01

AVDD=15V

=25°C

–0.01

–0.02

TOTAL UNADJUSTED ERROR (%FSR)

–0.03

–0.04

4mA TO 20mA, EXTERNAL R 4mA TO 20mA, EXTERNAL R

SET

,WITHDC-TO-DCCONVERTER

SET

0 1000 2000 3000 4000

CODE

10067-233

1.0

0.8

0.6

0.4

MAX DNL

0.2

–0.2

DNL ERROR (LSB)

–0.4

–0.6

–0.8

–1.0

–40 –20 0 20 40 60 80 100

MIN DNL

AVDD=15V ALL RANGES INTERNAL AND EXTERNA L R

SET

TEMPERATURE (°C)

Figure 10. Total Unadjusted Error vs. DAC Code Figure 13. Differential Nonlinearity Error vs. Temperature

10067-235

SET

10067-236

Rev. A | Page 13 of 44

Page 14

AD5737 Data Sheet

0.025

0.020

0.015

0.010

0.005

–0.005

–0.010

AVDD = 15V

–0.015

TOTAL UNADJUSTED ERROR (%FSR)

–0.020

–0.025

–40 –20 0 20 40 60 80 100

4mA TO 20mA RANGE, INTERNAL R 4mA TO 20mA RANGE, EXTERNAL R

TEMPERATURE (°C)

Figure 14. Total Unadjusted Error vs. Temperature

0.020

0.015

0.010

0.005

–0.005

–0.010

FULL-SCAL E ERROR (%FSR)

–0.015

–0.020

AVDD = 15V

4mA TO 20mA RANGE, INT ERNAL R 4mA TO 20mA RANGE, EXT ERNAL R

–40 –20 0 20 40 60 80 100

TEMPERATURE (°C)

Figure 15. Full-Scale Error vs. Temperature

SET

10067-155

10067-157

0.008

0.006

0.004

MAX INL

4mA TO 20mA RANGE TA = 25°C

0.002

INL ERROR (%FSR)

–0.002

–0.004

–0.006

51015202530

MIN INL

SUPPLY (V)

Figure 17. Integral Nonlinearity Error vs. Supply, External R

0.008

MAX INL

0.006

0.004

4mA TO 20mA RANGE

0.002

TA = 25°C

INL ERROR (%FSR)

–0.002

–0.004

–0.006

51015202530

MIN INL

SUPPLY (V)

Figure 18. Integral Nonlinearity Error vs. Supply, Internal R

10067-240

SET

10067-241

SET

0.005

–0.005

–0.010

–0.015

GAIN ERROR (%FS R)

AVDD = 15V

–0.020

–0.025

–40 –20 0 20 40 60 80 100

4mA TO 20mA RANGE, I NTERNAL R 4mA TO 20mA RANGE, EXT ERNAL R

TEMPERATURE (°C)

Figure 16. Gain Error vs. Temperature

SET

10067-159

Rev. A | Page 14 of 44

1.0

ALL RANGES

0.8 TA = 25°C

0.6

0.4

0.2

MAX DNL

–0.2

DNL ERROR (LSB)

–0.4

MIN DNL

–0.6

–0.8

–1.0

5 1015202530

SUPPLY (V)

Figure 19. Differential Nonlinearity Error vs. Supply

10067-242

Page 15

Data Sheet AD5737

0.005

–0.005

–0.010

–0.015

4mA TO 20mA RANGE T

= 25°C

MAX TUE

AVDD = 15V T

= 25°C

A LOAD

= 300Ω

–0.020

MIN TUE

–0.025

TOTAL UNADJUSTED ERROR (%FSR)

–0.030

–0.035

105 15202530

SUPPLY (V)

Figure 20. Total Unadjusted Error vs. Supply, External R

0.07

0.06

0.05

(%FSR)

MAX TUE

0.04 4mA TO 20mA RANGE

= 25°C

0.03

0.02

0.01

TOTAL UNADJUSTED ERROR

–0.01

–0.02

105 15202530

MIN TUE

SUPPLY (V)

Figure 21. Total Unadjusted Error vs. Supply, Internal R

CURRENT (µA)

0215105

10067-060

SET

Figure 23. Current vs. Time on Power-Up

TIME (µs)

10067-062

–2

–4

CURRENT (µA)

–6

–8

–10

10067-061

0123456

SET

Figure 24. Current vs. Time on Output Enable

TIME (µs)

AVDD = 15V T

= 25°C

= 300Ω

LOAD

INT_ENABLE = 1

10067-063

0.006

0.004

MAX TUE

0.002

–0.002

–0.004

–0.006

TA = 25°C EXTERNAL PMOS (NTL JS4149) 4mA TO 20mA RANGE R

= 300Ω

LOAD

–0.008

TOTAL UNADJUST ED ERROR (%FSR)

–0.010

–0.012

10 15 20 25 30

MIN TUE

BOOST_x

SUPPLY (V)

Figure 22. Total Unadjusted Error vs. V

Using External PMOS Mode

BOOST_x

Supply

10067-188

Rev. A | Page 15 of 44

VOLTAGE (V)

BOOST_ x

OUTPUT CURRENT (mA) AND V

–0.50 –0.25 0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00

0mA TO 24mA RANGE 1kΩ LOAD

= 410kHz

INDUCTOR = 10µ H (XAL4040-103) AV

= 5V

= 25°C

OUT_x

BOOST_x

TIME (ms)

Figure 25. Output Current and V

Settling Time

BOOST_x

with DC-to-DC Converter (See Figure 55)

10067-167

Page 16

AD5737 Data Sheet

TA = –40°C T

= +25°C

TA = +105°C

OUTPUT CURRENT (mA)

–0.25 0 0.25 0.50 0.75 1.00 1. 25 1.50 1.75

0mA TO 24mA RANGE 1kΩ LOAD

= 410kHz

INDUCTOR = 10µ H (XAL4040-103) AV

= 5V

TIME (ms)

Figure 26. Output Current Settling Time with DC-to-DC Converter

over Temperature (See Figure 55)

10067-168

20mA OUTPUT 10mA OUTPUT

–2

–4

CURRENT (AC-COUPLED) (µA)

–6

–8

–10

02468101214

AVCC = 5V

= 410kHz

INDUCTOR = 10µH (XAL4040-103)

0mA TO 24mA RANG E

1kΩ LOAD

EXTERNAL R

TIME (µs)

Figure 29. Output Current, AC-Coupled vs. Time

with DC-to-DC Converter (See Figure 55)

TA = 25°C

SET

10067-170

AVCC = 4.5V AV

= 5.0V

AVCC = 5.5V

OUTPUT CURRENT (mA)

–0.25 0 0.25 0.50 0.75 1.00 1. 25 1.50 1.75

0mA TO 24mA RANGE 1kΩ LOAD

= 410kHz

INDUCTOR = 10µ H (XAL4040-103) T

= 25°C

TIME (ms)

Figure 27. Output Current Settling Time with DC-to-DC Converter

(See Figure 55)

over AV

(4mA TO 20mA STEP)

OUTPUT CURRENT (mA)

OUT

TA = 25°C EXTERNAL PMOS (NTLJS4149) 4mA TO 20mA RANGE

= 300Ω

LOAD

= 24V

BOOST_x

(20mA TO 4mA STEP)

OUT

0mA TO 24mA RANGE

1kΩ LOAD

= 410kHz

INDUCTOR = 10µH (XAL4040-103) T

= 25°C

HEADROOM VOLTAGE (V)

0 5 10 15 20

10067-169

OUTPUT CURRENT (mA)

10067-067

Figure 30. DC-to-DC Converter Headroom vs. Output Current (See Figure 55)

AVDD = 15V V

= 15V

–20

–40

–60

PSRR (dB)

OUT_x

–80

–100

BOOST_ x

= 25°C

–5 501015

TIME (µs)

10067-189

Figure 28. Output Current Settling Time with External PMOS Transistor

Rev. A | Page 16 of 44

–120

10 100 1k 10k 100k 1M 10M

FREQUENCY (Hz)

Figure 31. I

PSRR vs. Frequency

OUT_x

10067-068

Page 17

Data Sheet AD5737

DC-TO-DC CONVERTER

AVCC = 4.5V AV

= 5V

= 5.5V

20mA OUTPUT

EFFICIENCY (%)

BOOST_x

0220161284

Figure 32. Efficiency at V

EFFICIENCY (%)

BOOST_ x

–40 10040 60 80200–20

20mA OUTPUT

0mA TO 24mA RANGE 1kΩ LOAD EXTERNAL R AVCC = 5V

= 410kHz

INDUCTOR = 10µ H (XAL4040-103) T

= 25°C

Figure 33. Efficiency at V

0mA TO 24mA RANGE 1kΩ LOAD EXTERNAL R

INDUCTOR = 10µ H (XAL4040-103) T

OUTPUT CURRENT (mA)

vs. Output Current (See Figure 55)

BOOST_x

SET

TEMPERATURE (°C)

vs. Temperature (See Figure 55)

BOOST_x

= 410kHz

= 25°C

SET

EFFICIENCY (%)

OUT_x

10067-016

0mA TO 24mA RANGE 1kΩ LOAD EXTERNAL R AVCC = 5V

INDUCTOR = 10µH (XAL4040-103)

–40 10040 60 80200–20

SET

= 410kHz

TEMPERATURE (°C)

Figure 35. Output Efficiency vs. Temperature (See Figure 55)

0.6

0.5

0.4

0.3

0.2

SWITCH RESI STANCE (Ω)

0.1

0 –40 –20 0 20 40 60 80 100

10067-017

TEMPERATURE (°C)

Figure 36. Switch Resistance vs. Temperature

10067-019

10067-123

Y (%)

EFFICIEN

OUT_x

Figure 34. Output Efficiency vs. Output Current (See Figure 55)

0220161284

AVCC = 4.5V AV

= 5V

= 5.5V

OUTPUT CURRENT (mA)

0mA TO 24mA RANGE 1kΩ LOAD EXTERNAL R

INDUCTOR = 10µH (XAL4040-103) T

= 410kHz

= 25°C

SET

10067-018

Rev. A | Page 17 of 44

Page 18

AD5737 Data Sheet

REFERENCE

VOLTAGE (V)

–2

0 0.2 0.4 0.6 0.8 1.0 1.2

Figure 37. REFOUT Voltage Turn-On Transient

AVDD = 15V T

AV REFOUT T

= 25°C

TIME (ms)

10067-010

5.0050

5.0045

5.0040

5.0035

5.0030

5.0025

5.0020

5.0015

5.0010

REFERENCE OUTPUT VOLTAGE (V)

5.0005

5.0000 –40 –20 0 20 40 60 80 100

Figure 40. REFOUT Voltage vs. Temperature (When the AD5737 is soldered

onto a PCB, the reference shifts due to thermal shock on the package. The

average output voltage shift is −4 mV. Measurement of these parts after seven

days shows that the outputs typically shift back 2 mV toward their initial values.

This second shift is due to the relaxation of stress incurred during soldering.)

5.002

5.001

30 DEVICES SHOWN AV

= 15V

TEMPERATURE (°C)

AVDD = 15V T

= 25°C

10067-163

VOLTAGE (µV)

–1

–2

–3

0246 81

TIME (s)

Figure 38. REFOUT Output Noise (0.1 Hz to 10 Hz Bandwidth)

AGE (µV)

VOL

150

100

–50

–100

AVDD = 15V T

= 25°C

10067-011

5.000

AGE (V)

4.999

4.998

4.997

REFERENCE OUTPUT VOL

4.996

4.995 024681

LOAD CURRENT (mA)

Figure 41. REFOUT Voltage vs. Load Current

5.00000

4.99995

4.99990

4.99985

4.99980

4.99975

4.99970

REFERENCE OUTPUT VOLTAGE (V)

4.99965

TA = 25°C

10067-014

–150

0 5 10 15 20

TIME (ms)

Figure 39. REFOUT Output Noise (100 kHz Bandwidth)

10067-012

4.99960

10 15 20 25 30

AVDD (V)

Figure 42. REFOUT Voltage vs. AVDD

10067-015

Rev. A | Page 18 of 44

Page 19

Data Sheet AD5737

GENERAL

450

400

350

300

250

(µA)

200

150

100

01234

SDIN VOLTAGE (V)

Figure 43. DICC vs. Logic Input Voltage

DVDD = 5V T

= 25°C

10067-007

13.4

13.3

13.2

13.1

13.0

12.9

FREQUENCY (MHz)

12.8

12.7

DVDD = 5.5V

12.6 –40 –20 0 2 0 40 60 80 100

Figure 45. Internal Oscillator Frequency vs. Temperature

TEMPERATURE (°C)

10067-020

CURRENT (mA)

10 15 20 25 30

VO LTAG E (V )

AI TA = 25°C I

OUT

Figure 44. Supply Current (AIDD) vs. Supply Voltage (AVDD)

= 0mA

10067-009

14.4

14.2

14.0

13.8

13.6

FREQUENCY (MHz)

13.4

13.2

TA = 25°C

13.0

2.5 3.0 3.5 4.0 4 .5 5.0 5.5

VO LTAG E (V )

Figure 46. Internal Oscillator Frequency vs. DVDD Supply Voltage

10067-021

Rev. A | Page 19 of 44

Page 20

AD5737 Data Sheet

TERMINOLOGY

Relative Accuracy or Integral Nonlinearity (INL)

Relative accuracy, or integral nonlinearity (INL), is a measure of the maximum deviation from the best fit line through the DAC transfer function. INL is expressed in percent of full-scale range (% FSR). A typical INL vs. code plot is shown in Figure 8.

Differential Nonlinearity (DNL)

Differential nonlinearity (DNL) is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified DNL of ±1 LSB maximum ensures monotonicity. The AD5737 is guaranteed monotonic by design. A typical DNL vs. code plot is shown in Figure 9.

Monotonicity

A DAC is monotonic if the output either increases or remains constant for increasing digital input code. The AD5737 is monotonic over its full operating temperature range.

Offset Error

Offset error is the deviation of the analog output from the ideal zero-scale output when all DAC registers are loaded with 0x0000. It is expressed in % FSR.

Offset Error Drift or Offset TC

Offset error drift, or offset TC, is a measure of the change in offset error with changes in temperature and is expressed in ppm FSR/°C.

Gain Error

Gain error is a measure of the span error of the DAC. It is the deviation in slope of the DAC transfer function from the ideal, expressed in % FSR.

Gain Temperature Coefficient (TC)

Gain TC is a measure of the change in gain error with changes in temperature and is expressed in ppm FSR/°C.

Full-Scale Error

Full-scale error is a measure of the output error when full-scale code is loaded to the DAC register. Ideally, the output should be full-scale − 1 LSB. Full-scale error is expressed in % FSR.

Full-Scale Temperature Coefficient (TC)

Full-scale TC is a measure of the change in full-scale error with changes in temperature and is expressed in ppm FSR/°C.

Tot a l U n ad ju s te d E rr o r ( TU E )

Total unadjusted error (TUE) is a measure of the output error that includes all the error measurements: INL error, offset error, gain error, temperature, and time. TUE is expressed in % FSR.

DC Crosstalk

DC crosstalk is the dc change in the output level of one DAC in response to a change in the output of another DAC. It is measured with a full-scale output change on one DAC while monitoring another DAC, which is at midscale.

Current Loop Compliance Voltage

The current loop compliance voltage is the maximum voltage at the I

pin for which the output current is equal to the

OUT_x

programmed value.

Voltage Reference Thermal Hysteresis

Voltage reference thermal hysteresis is the difference in output voltage measured at +25°C compared to the output voltage measured at +25°C after cycling the temperature from +25°C to

−40°C to +105°C and back to +25°C. The hysteresis is specified for the first and second temperature cycles and is expressed in ppm.

Power-On Glitch Energy

Power-on glitch energy is the impulse injected into the analog output when the AD5737 is powered on. It is specified as the area of the glitch in nV-sec (see Figure 23).

Power Supply Rejection Ratio (PSRR)

PSRR indicates how the output of the DAC is affected by changes in the power supply voltage.

Reference Temperature Coefficient (TC)

Reference TC is a measure of the change in the reference output voltage with changes in temperature. It is expressed in ppm/°C.

Line Regulation

Line regulation is the change in the reference output voltage due to a specified change in supply voltage. It is expressed in ppm/V.

Load Regulation

Load regulation is the change in the reference output voltage due to a specified change in load current. It is expressed in ppm/mA.

DC-to-DC Converter Headroom

DC-to-DC converter headroom is the difference between the voltage required at the current output and the voltage supplied by the dc-to-dc converter (see Figure 30).

Output Efficiency

Output efficiency is defined as the ratio of the power delivered to a channel’s load and the power delivered to the channel’s dc-to-dc input. The V

quiescent current is considered

BOOST_x

part of the dc-to-dc converter’s losses.

OUT

Efficiency at V

The efficiency at V delivered to a channel’s V to the channel’s dc-to-dc input. The V

LOAD

AIAVRI×

CCCC

BOOST_x

is defined as the ratio of the power

BOOST_x

supply and the power delivered

BOOST_x

quiescent current is

BOOST_x

considered part of the dc-to-dc converter’s losses.

xBOOSTOUT

AIAV

CCCC

Rev. A | Page 20 of 44

Page 21

Data Sheet AD5737

THEORY OF OPERATION

The AD5737 is a quad, precision digital-to-current loop converter designed to meet the requirements of industrial process control applications. It provides a high precision, fully integrated, low cost, single-chip solution for generating current loop outputs. The current ranges available are 0 mA to 20 mA, 4 mA to 20 mA, and 0 mA to 24 mA. The output configuration is user-selectable via the DAC control register.

On-chip dynamic power control minimizes package power dissipation (see the Dynamic Power Control section).

DAC ARCHITECTURE

The DAC core architecture of the AD5737 consists of two matched DAC sections. A simplified circuit diagram is shown in Figure 47. The four MSBs of the 12-bit data-word are decoded to drive 15 switches, E1 to E15. Each switch connects one of 15 matched resistors either to ground or to the reference buffer output. The remaining eight bits of the data-word drive Switch S0 to Switch S7 of an 8-bit voltage mode R-2R ladder network.

OUT_x

OUT

10067-069

2R 2R

8-BIT R-2R LADDE R FOUR MSBs DECODED I NTO

2R 2R 2R 2R 2R

S0 S1 S7 E1 E2 E15

15 EQUAL SEGMENTS

Figure 47. DAC Ladder Structure

The voltage output from the DAC core is converted to a current, which is then mirrored to the supply rail so that the application sees only a current source output (see Figure 48). The current outputs are supplied by V

12-BIT

DAC

BOOST_x

POWER-ON STATE OF THE AD5737

When the AD5737 is first powered on, the I tristate mode. After a device power-on or a device reset, it is recommended that the user wait at least 100 μs before writing to the device to allow time for internal calibrations to take place.

pins are in

OUT_x

SERIAL INTERFACE

The AD5737 is controlled by a versatile 3-wire serial interface that operates at clock rates of up to 30 MHz and is compatible with SPI, QSPI, MICROWIRE, and DSP standards. Data coding is always straight binary.

Input Shift Register

The input shift register is 24 bits wide. Data is loaded into the device MSB first as a 24-bit word under the control of the serial clock input, SCLK. Data is clocked in on the falling edge of SCLK.

If packet error checking (PEC) is enabled, an additional eight bits must be written to the AD5737, creating a 32-bit serial interface (see the Packet Error Checking section).

The DAC outputs can be updated in one of two ways: individual DAC updating or simultaneous updating of all DACs.

Individual DAC Updating

12-BIT

DAC

LDAC

is held low while data is

SYNC

. See Table 3 and Figure 3

LDAC

is held high while

OUTPUT

AMPLIFIERS

LDAC

OUT_x

is taken

low

To update an individual DAC, clocked into the DAC data register. The addressed DAC output is updated on the rising edge of for timing information.

Simultaneous Updating of All DACs

To update all DACs simultaneously, data is clocked into the DAC data register. After high, only the first write to the DAC data register of each channel is valid; subsequent writes to the DAC data register are ignored, although these subsequent writes are returned if a readback is initiated. All DAC outputs are updated by taking

SYNC

after

is taken high.

REFIN

SET

10067-071

Figure 48. Voltage-to-Current Conversion Circuitry

Reference Buffers

The AD5737 can operate with either an external or internal reference. The reference input requires a 5 V reference for specified performance. This input voltage is then buffered

LDAC

DAC

DAC INPUT

DAC DATA

OFFSET

AND GAIN

CALIBRATION

before it is applied to the DAC.

Rev. A | Page 21 of 44

SCLK

SYNC

SDIN

Figure 49. Simplified Serial Interface of the Input Loading Circuitry

INTERFACE

LOGIC

for One DAC Channel

SDO

10067-072

Page 22

AD5737 Data Sheet

TRANSFER FUNCTION

For the 0 mA to 20 mA, 0 mA to 24 mA, and 4 mA to 20 mA current output ranges, the output current is expressed by the following equations:

For the 0 mA to 20 mA range

mA20

⎛

⎜

OUT

⎜ ⎝

For the 0 mA to 24 mA range

⎛

⎜

OUT

⎜ ⎝

⎞

⎟

⎠

mA24

⎞

⎟

⎠

For the 4 mA to 20 mA range

mA16

OUT

⎛

= DI

⎜

⎜ ⎝

⎞ ⎟

⎟

⎠

mA4

+×

where:

D is the decimal equivalent of the code loaded to the DAC. N is the bit resolution of the DAC.

Rev. A | Page 22 of 44

Page 23

Data Sheet AD5737

REGISTERS

Tabl e 7, Ta b le 8 , and Tabl e 9 provide an overview of the registers for the AD5737.

Table 7. Data Registers for the AD5737

DAC Data Registers

Gain Registers

Offset Registers

Clear Code Registers

Table 8. Control Registers for the AD5737

Main Control Register

DAC Control Registers

Software Register

DC-to-DC Control Register

Slew Rate Control Registers

The four DAC data registers (one register per DAC channel) are used to write a DAC code to each DAC channel. The DAC data bits are D15 to D4.

The four gain registers (one register per DAC channel) are used to program the gain trim on a per-channel basis. The gain data bits are D15 to D4.

The four offset registers (one register per DAC channel) are used to program the offset trim on a per-channel basis. The offset data bits are D15 to D4.

The four clear code registers (one register per DAC channel) are used to program the clear code on a perchannel basis. The clear code data bits are D15 to D4.

The main control register is used to configure functions for the entire part. These functions include the following: enabling status readback during a write; enabling the output on all four DAC channels simultaneously; power-on of the dc-to-dc converter on all four DAC channels simultaneously; and enabling and configuring the watchdog timer. For more information, see the Main Control Register section.

The four DAC control registers (one register per DAC channel) are used to configure the following functions on a per-channel basis: output range (for example, 4 mA to 20 mA); selection of the internal current sense resistor or an external current sense resistor; enabling/disabling the use of a clear code; enabling/disabling the internal circuitry (dc-to-dc converter, DAC, and internal amplifiers); power-on/power-off of the dc-to-dc converter; and enabling/disabling the output channel.

The software register is used to perform a reset, to toggle the user bit in the status register, and, as part of the watchdog timer feature, to verify correct data communication operation.

The dc-to-dc control register is used to set the control parameters for the dc-to-dc converter: maximum output voltage, phase, and switching frequency. This register is also used to select the internal compensation resistor or an external compensation resistor for the dc-to-dc converter.

The four slew rate control registers (one register per DAC channel) are used to program the slew rate of the DAC output.

Table 9. Readback Register for the AD5737

Status Register The status register contains any fault information, as well as a user toggle bit.

Rev. A | Page 23 of 44

Page 24

AD5737 Data Sheet

ENABLING THE OUTPUT

To correctly write to and set up the part from a power-on condition, use the following sequence:

Perform a hardware or software reset after initial power-on. Configure the dc-to-dc converter supply block. Set the

2. dc-to-dc switching frequency, the maximum output voltage allowed, and the dc-to-dc converter phase between channels.

Configure the DAC control register on a per-channel basis.

3. Select the output range, and enable the dc-to-dc converter block (DC_DC bit). Other control bits can also be configured. Set the INT_ENABLE bit, but do not set the OUTEN (output enable) bit.

Write the required code to the DAC data register. This step

4. implements a full internal DAC calibration. For reduced output glitch, allow at least 200 μs before performing Step 5.

Write to the DAC control register again to enable the

5. output (set the OUTEN bit).

REPROGRAMMING THE OUTPUT RANGE

When changing the range of an output, the same sequence described in the Enabling the Output section should be used. It is recommended that the range be set to 0 V (zero scale or midscale) before the output is disabled. Because the dc-to-dc switching frequency, maximum output voltage, and phase have already been selected, there is no need to reprogram these values. Figure 51 provides a flowchart of this sequence.

CHANNEL OUT PUT IS ENABLE D.

STEP 1: WRI TE TO CHANNEL’S DAC DATA

STEP 2: WRI TE TO DAC CONTROL REGISTER.

DISABLE THE OUTPUT (O UTEN = 0) AND SET THE NEW OUTPUT RANG E. KEEP THE DC_DC BIT AND THE INT _ENABLE BIT SET.

Figure 50 provides a flowchart of this sequence.

POWER ON.

STEP 1: PERFORM A SOFTWARE/HARDWARE RESET.

STEP 2: WRI TE TO DC-TO-DC CONT ROL REGI STER TO

SET DC-TO-DC CLOCK FREQUENCY, PHASE, AND MAXIMUM VOLTAGE.

STEP 3: WRI TE TO DAC CONTROL REGISTER. SELECT THE DAC CHANNEL AND OUT PUT RANGE. SET THE DC_DC BIT AND OTHER CONTROL BITS AS REQUIRED. SET THE INT_ENABLE BIT BUT DO NOT SET THE OUTEN BIT.

STEP 4: WRITE TO ONE OR MORE DAC DATA REGISTERS. ALLOW AT LEAST 200µs BETWEEN STEP 3 AND STEP 5 F OR REDUCED OUTP UT GLIT CH.

STEP 5: WRI TE TO DAC CONTROL REGISTER. RELOAD

SEQUENCE AS IN STEP 3. SET THE OUTEN BIT TO ENABLE THE OUT PUT.

Figure 50. Programming Sequence to Correctly Enable the Output

STEP 3: WRITE VALUE TO THE DAC DATA REGISTER.

STEP 4: WRI TE TO DAC CONTROL REGISTER.

RELOAD SEQ UENCE AS IN STEP 2. SET THE OUT EN BIT TO ENABLE THE OUTPUT.

10067-074

Figure 51. Programming Sequence to Change the Output Range

10067-073

Rev. A | Page 24 of 44

Page 25

Data Sheet AD5737

DATA REGISTERS

The input shift register is 24 bits wide. When PEC is enabled, the input shift register is 32 bits wide, with the last eight bits corresponding to the PEC code (see the Packet Error Checking section for more information about PEC). When writing to a data register, the format shown in Tab le 1 0 must be used.

Table 10. Input Shift Register for a Write Operation to a Data Register

MSB LSB D23 D22 D21 D20 D19 D18 D17 D16 D15 to D0

R/W

Table 11. Descriptions of Data Register Bits[D23:D16]

Bit Name Description

R/W

DUT_AD1, DUT_AD0

0 0 Pin AD1 = 0, Pin AD0 = 0 0 1 Pin AD1 = 0, Pin AD0 = 1 1 0 Pin AD1 = 1, Pin AD0 = 0 1 1 Pin AD1 = 1, Pin AD0 = 1 DREG2, DREG1, DREG0

0 0 0 Write to DAC data register (one DAC channel) 0 0 1 Reserved 0 1 0 Write to gain register (one DAC channel) 0 1 1 Write to gain registers (all DAC channels) 1 0 0 Write to offset register (one DAC channel) 1 0 1 Write to offset registers (all DAC channels) 1 1 0 Write to clear code register (one DAC channel) 1 1 1 Write to a control register DAC_AD1, DAC_AD0

0 0 DAC A 0 1 DAC B 1 0 DAC C 1 1 DAC D

DUT_AD1 DUT_AD0 DREG2 DREG1 DREG0 DAC_AD1 DAC_AD0 Data

This bit indicates whether the addressed register is written to or read from. 0 = write to the addressed register.

1 = read from the addressed register. Used in association with the external pins AD1 and AD0, these bits determine which AD5737 device is being

addressed by the system controller.

DUT_AD1 DUT_AD0 Part Addressed

These bits select the register to be written to. If a control register is selected (DREG[2:0] = 111), the CREG bits in the control register select the specific control register to be written to (see Table 19).

DREG2 DREG1 DREG0 Function

These bits are used to specify the DAC channel. If a write to the part does not apply to a specific DAC channel, these bits are don’t care bits.

DAC_AD1 DAC_AD0 DAC Channel

DAC Data Register

When writing to a DAC data register, Bit D15 to Bit D4 are the DAC data bits. Tabl e 12 shows the register format, and Tab l e 1 1 describes the functions of Bit D23 to Bit D16.

Table 12. Programming the DAC Data Register

D23 D22 D21 D20 D19 D18 D17 D16 D15 to D4 D3 to D0

R/W

X = don’t care.

DUT_AD1 DUT_AD0 0 0 0 DAC_AD1 DAC_AD0 DAC data X1

Rev. A | Page 25 of 44

Page 26

AD5737 Data Sheet

Gain Register

The 12-bit gain register allows the user to adjust the gain of each channel in steps of 1 LSB. To write to the gain register of one DAC channel, set the DREG[2:0] bits to 010 (see Tab le 1 3). To write the same gain code to all four DAC channels at the same time, set the DREG[2:0] bits to 011. The gain register coding is straight binary, as shown in Tab l e 1 4 . The default code in the gain register is 0xFFFF. The maximum recommended gain trim is approximately 50% of the programmed range to maintain accuracy (for more information, see the Digital Offset and Gain Control section).

Offset Register

The 12-bit offset register allows the user to adjust the offset of each channel by −2048 LSB to +2047 LSB in steps of 1 LSB. To write to the offset register of one DAC channel, set the

Table 13. Programming the Gain Register

0 Device address 0 1 0 DAC channel address Gain adjustment 1111

DUT_AD1 DUT_AD0 DREG2 DREG1 DREG0 DAC_AD1 DAC_AD0 D15 to D4 D3 to D0

DREG[2:0] bits to 100 (see Tab le 1 5 ). To write the same offset code to all four DAC channels at the same time, set the DREG[2:0] bits to 101. The offset register coding is straight binary, as shown in Tabl e 16 . The default code in the offset register is 0x8000, which results in zero offset programmed to the output (for more information, see the Digital Offset and Gain Control section).

Clear Code Register

The 12-bit clear code register allows the user to set the clear value of each channel. To configure a channel to be cleared when the CLEAR pin is activated, set the CLR_EN bit in the DAC control register for that channel (see Ta bl e 23). To write to the clear code register, set the DREG[2:0] bits to 110 (see Tabl e 17 ). The default clear code is 0x0000 (for more information, see the Asynchronous Clear section).

Table 14. Gain Register Bit Descriptions

Gain Adjustment G15 G14 G13 to G5 G4 G3 to G0

+4096 LSB 1 1 111111111 1 1111 +4095 LSB 1 1 111111111 0 1111 … … … … … 1111 1 LSB 0 0 000000000 1 1111 0 LSB 0 0 000000000 0 1111

Table 15. Programming the Offset Register

0 Device address 1 0 0 DAC channel address Offset adjustment 0000

DUT_AD1 DUT_AD0 DREG2 DREG1 DREG0 DAC_AD1 DAC_AD0 D15 to D4 D3 to D0

Table 16. Offset Register Bit Descriptions

Offset Adjustment OF15 OF14 OF13 OF12 to OF5 OF4 OF3 to OF0

+2047 LSB 1 1 1 11111111 1 0000 +2046 LSB 1 1 1 11111111 0 0000 … … … … … … 0000 No Adjustment (Default) 1 0 0 00000000 0 0000 … … … … … … 0000

−2047 LSB 0 0 0 00000000 1 0000

−2048 LSB 0 0 0 00000000 0 0000

Table 17. Programming the Clear Code Register

0 Device address 1 1 0 DAC channel address Clear code 0000

DUT_AD1 DUT_AD0 DREG2 DREG1 DREG0 DAC_AD1 DAC_AD0 D15 to D4 D3 to D0

Rev. A | Page 26 of 44

Page 27

Data Sheet AD5737

CONTROL REGISTERS

When writing to a control register, the format shown in Tab le 18 must be used. See Ta b l e 11 for information about the configuration of Bit D23 to Bit D16. The control registers are addressed by setting the DREG[2:0] bits (Bits[D20:D18] in the input shift register) to 111 and then setting the CREG[2:0] bits to select the specific control register (see Tab l e 19 ).

Table 18. Input Shift Register for a Write Operation to a Control Register

MSB D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 to D0

R/W

Table 19. Control Register Addresses (CREG[2:0] Bits)

CREG2 (D15) CREG1 (D14) CREG0 (D13) Control Register

0 0 0 Slew rate control register (one per channel) 0 0 1 Main control register 0 1 0 DAC control register (one per channel) 0 1 1 DC-to-DC control register 1 0 0 Software register

DUT_AD1 DUT_AD0 1 1 1 DAC_AD1 DAC_AD0 CREG2 CREG1 CREG0 Data

Main Control Register

The main control register options are shown in Tab l e 2 0 and Tabl e 21 . See the Device Features section for more information about the features controlled by the main control register.

LSB

Table 20. Programming the Main Control Register

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 to D0

0 0 1 0 STATREAD EWD WD1 WD0 X1 X

X = don’t care.

OUTEN_ALL DCDC_ALL X1

Table 21. Main Control Register Bit Descriptions

Bit Name Description

STATREAD Enable status readback during a write. See the Status Readback During a Write section.

0 = disable status readback (default). 1 = enable status readback.

EWD Enable the watchdog timer. See the Watchdog Timer section.

0 = disable the watchdog timer (default). 1 = enable the watchdog timer.

WD1, WD0 Timeout select bits. Used to select the timeout period for the watchdog timer.

WD1 WD0 Timeout Period (ms)

0 0 5 0 1 10 1 0 100 1 1 200 OUTEN_ALL

Setting this bit to 1 enables the output on all four DACs simultaneously. Do not use the OUTEN_ALL bit when using the OUTEN bit in the DAC control register.

DCDC_ALL

Setting this bit to 1 powers up the dc-to-dc converter on all four channels simultaneously. To power down the dc-to-dc converters, all channel outputs must first be disabled. Do not use the DCDC_ALL bit when using the DC_DC bit in the DAC control register.

Rev. A | Page 27 of 44

Page 28

AD5737 Data Sheet

DAC Control Register

The DAC control register is used to configure each DAC channel. The DAC control register options are shown in Tab l e 22 and Ta bl e 23.

Table 22. Programming the DAC Control Register

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

0 1 0 X1 X1 X1 X1 INT_ENABLE CLR_EN OUTEN RSET DC_DC X1 R2 R1 R0

X = don’t care.

Table 23. DAC Control Register Bit Descriptions

Bit Name Description

INT_ENABLE

CLR_EN Per-channel clear enable bit. This bit specifies whether the selected channel is cleared when the CLEAR pin is activated.

OUTEN Enables or disables the selected output channel.

RSET Selects the internal current sense resistor or an external current sense resistor for the selected DAC channel.

DC_DC

R2, R1, R0 Selects the output range to be enabled.

0 0 0 Reserved 0 0 1 Reserved 0 1 0 Reserved 0 1 1 Reserved 1 0 0 4 mA to 20 mA current range 1 0 1 0 mA to 20 mA current range 1 1 0 0 mA to 24 mA current range

Powers up the dc-to-dc converter, DAC, and internal amplifiers for the selected channel. This bit applies to individual channels only; it does not enable the output. After setting this bit, it is recommended that a >200 μs delay be observed before enabling the output to reduce the output enable glitch. See Figure 24 for plots of this glitch.

0 = channel is not cleared when the part is cleared (default). 1 = channel is cleared when the part is cleared.

0 = channel disabled (default). 1 = channel enabled.

0 = external resistor selected (default). 1 = internal resistor selected.

Powers up or powers down the dc-to-dc converter on the selected channel. All dc-to-dc converters can be powered up simultaneously using the DCDC_ALL bit in the main control register. To power down the dc-to-dc converter, the OUTEN and INT_ENABLE bits must also be set to 0.

0 = dc-to-dc converter is powered down (default). 1 = dc-to-dc converter is powered up.

R2 R1 R0 Output Range Selected

Rev. A | Page 28 of 44

Page 29

Data Sheet AD5737

Software Register

The software register allows the user to perform a software reset of the part. This register is also used to set the user toggle bit, D11, in the status register and as part of the watchdog timer feature when that feature is enabled.

Bit D12 in the software register can be used to ensure that communication has not been lost between the MCU and the

AD5737 and that the datapath lines are working properly (that

SYNC

is, SDIN, SCLK, and

Table 24. Programming the Software Register

D15 D14 D13 D12 D11 to D0

1 0 0 User program Reset code/SPI code

Table 25. Software Register Bit Descriptions

Bit Name Description

User Program

This bit is mapped to Bit D11 of the status register. When this bit is set to 1, Bit D11 of the status register is set to 1. When this bit is set to 0, Bit D11 of the status register is also set to 0. This feature can be used to ensure that the SPI pins are working correctly by writing a known bit value to this register and then reading back Bit D11 from the status register.

Reset Code/SPI Code

Option Description

Reset code Writing 0x555 to Bits[D11:D0] performs a software reset of the AD5737. SPI code

If the watchdog timer feature is enabled, 0x195 must be written to the software register (Bits[D11:D0]) within the programmed timeout period (see Table 21).

When the watchdog timer feature is enabled, the user must write 0x195 to Bits[D11:D0] of the software register within the timeout period. If this command is not received within the timeout period, the ALERT pin signals a fault condition. This command is only required when the watchdog timer feature is enabled.

DC-to-DC Control Register

The dc-to-dc control register allows the user to configure the dc-to-dc switching frequency and phase, as well as the maximum allowable dc-to-dc output voltage. The dc-to-dc control register options are shown in Ta b l e 2 6 and Tabl e 27 .

Table 26. Programming the DC-to-DC Control Register

D15 D14 D13 D12 to D7 D6 D5 to D4 D3 to D2 D1 to D0

0 1 1 X1 DC-DC comp DC-DC phase DC-DC freq DC-DC MaxV

X = don’t care.

Table 27. DC-to-DC Control Register Bit Descriptions

Bit Name Description

DC-DC Comp

Selects the internal compensation resistor or an external compensation resistor for the dc-to-dc converter. See the DC-to-DC Converter Compensation Capacitors section and the AI

Supply Requirements—Slewing section.

0 = selects the internal 150 kΩ compensation resistor (default). 1 = bypasses the internal compensation resistor. When this bit is set to 1, an external compensation resistor must

be used; this resistor is placed at the COMP

pin in series with the 10 nF dc-to-dc compensation capacitor to

DCDC_x

ground. Typically, a resistor of ~50 kΩ is recommended.

DC-DC Phase User-programmable dc-to-dc converter phase (between channels).

00 = all dc-to-dc converters clock on the same edge (default). 01 = Channel A and Channel B clock on the same edge; Channel C and Channel D clock on the opposite edge. 10 = Channel A and Channel C clock on the same edge; Channel B and Channel D clock on the opposite edge. 11 = Channel A, Channel B, Channel C, and Channel D clock 90° out of phase from each other.

DC-DC Freq

Switching frequency for the dc-to-dc converter; this frequency is divided down from the internal 13 MHz oscillator (see Figure 45 and Figure 46). 00 = 250 kHz ± 10%. 01 = 410 kHz ± 10% (default). 10 = 650 kHz ± 10%.

DC-DC MaxV Maximum allowed V

voltage supplied by the dc-to-dc converter.

BOOST_x

00 = 23 V + 1 V/−1.5 V (default). 01 = 24.5 V ± 1 V. 10 = 27 V ± 1 V. 11 = 29.5 V ± 1 V.

Rev. A | Page 29 of 44

Page 30

AD5737 Data Sheet

Slew Rate Control Register

This register is used to program the slew rate control for the selected DAC channel. The slew rate control is enabled/disabled and programmed on a per-channel basis. See Tabl e 28 and the Digital Slew Rate Control section for more information.

READBACK OPERATION

Readback mode is invoked by setting the R/W bit = 1 in the serial input register write. See for the bits associated with a readback operation. The DUT_AD1 and DUT_AD0 bits, in association with Bits[RD4:RD0], select the register to be read (see ). The remaining data bits in the write sequence are don’t care bits.

During the next SPI transfer, the data that appears on the SDO output contains the data from the previously addressed register

Table 28. Programming the Slew Rate Control Register

D15 D14 D13 D12 D11 to D7 D6 to D3 D2 to D0

0 0 0 SREN X1 SR_CLOCK SR_STEP

X = don’t care.

Table 29. Input Shift Register for a Read Operation

MSB D23 D22 D21 D20 D19 D18 D17 D16 D15 to D0

R/W

X = don’t care.

Table 30. Read Addresses (Bits[RD4:RD0])

RD4 RD3 RD2 RD1 RD0 Function

0 0 0 0 0 Read DAC A data register 0 0 0 0 1 Read DAC B data register 0 0 0 1 0 Read DAC C data register 0 0 0 1 1 Read DAC D data register 0 0 1 0 0 Read DAC A control register 0 0 1 0 1 Read DAC B control register 0 0 1 1 0 Read DAC C control register 0 0 1 1 1 Read DAC D control register 0 1 0 0 0 Read DAC A gain register 0 1 0 0 1 Read DAC B gain register 0 1 0 1 0 Read DAC C gain register 0 1 0 1 1 Read DAC D gain register 0 1 1 0 0 Read DAC A offset register 0 1 1 0 1 Read DAC B offset register 0 1 1 1 0 Read DAC C offset register 0 1 1 1 1 Read DAC D offset register 1 0 0 0 0 Read DAC A clear code register 1 0 0 0 1 Read DAC B clear code register 1 0 0 1 0 Read DAC C clear code register 1 0 0 1 1 Read DAC D clear code register 1 0 1 0 0 Read DAC A slew rate control register 1 0 1 0 1 Read DAC B slew rate control register 1 0 1 1 0 Read DAC C slew rate control register 1 0 1 1 1 Read DAC D slew rate control register 1 1 0 0 0 Read status register 1 1 0 0 1 Read main control register 1 1 0 1 0 Read dc-to-dc control register

Tabl e 29

Table 3 0

DUT_AD1 DUT_AD0 RD4 RD3 RD2 RD1 RD0 X1

Rev. A | Page 30 of 44

(see Figure 4). This second SPI transfer should be either a request to read another register on a third data transfer or a no operation command. The no operation command for DUT Address 00 is 0x1CE000; for other DUT addresses, Bits[D22:D21] are set accordingly.

Readback Example

To read back the gain register of AD5737 Device 1, Channel A, implement the following sequence:

Write 0xA80000 to the input register to configure Device

Address 1 for read mode with the gain register of Channel A selected. The data bits, D15 to D0, are don’t care bits.

Execute another read command or a no operation com-

2. mand (0x3CE000). During this command, the data from the Channel A gain register is clocked out on the SDO line.

LSB

Page 31

Data Sheet AD5737

Status Register

The status register is a read-only register. This register contains any fault information, as a well as a ramp active bit (Bit D9) and a user toggle bit (Bit D11). When the STATREAD bit in the main control register is set, the status register contents can be

Table 31. Decoding the Status Register

MSB LSB D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

DC-DCD DC-DCC DC-DCB DC-DCA

X = don’t care.

User toggle

PEC error

Ramp active

Over temp

Table 32. Status Register Bit Descriptions

Bit Name Description

DC-DCD

This bit is set if the dc-to-dc converter on Channel D cannot maintain compliance, for example, if the dc-to-dc converter is reaching its V

voltage; in this case, the I

MAX

fault bit is also set. See the DC-to-DC Converter V

OUT_D

more information about the operation of this bit under this condition.

DC-DCC

This bit is set if the dc-to-dc converter on Channel C cannot maintain compliance, for example, if the dc-to-dc converter is reaching its V

voltage; in this case, the I

MAX

fault bit is also set. See the DC-to-DC Converter V

OUT_C

more information about the operation of this bit under this condition.

DC-DCB

This bit is set if the dc-to-dc converter on Channel B cannot maintain compliance, for example, if the dc-to-dc converter is reaching its V

voltage; in this case, the I

MAX

fault bit is also set. See the DC-to-DC Converter V

OUT_B

more information about the operation of this bit under this condition.

DC-DCA

This bit is set if the dc-to-dc converter on Channel A cannot maintain compliance, for example, if the dc-to-dc converter is reaching its V

voltage; in this case, the I

MAX

fault bit is also set. See the DC-to-DC Converter V

OUT_A

more information about the operation of this bit under this condition. User Toggle User toggle bit. This bit is set or cleared via the software register and can be used to verify data communications, if needed. PEC Error Denotes a PEC error on the last data-word received over the SPI interface. Ramp Active This bit is set while any output channel is slewing (digital slew rate control is enabled on at least one channel). Over Temp This bit is set if the AD5737 core temperature exceeds approximately 150°C. I

Fault This bit is set if a fault is detected on the I

OUT_D

Fault This bit is set if a fault is detected on the I

OUT_C

Fault This bit is set if a fault is detected on the I

OUT_B

Fault This bit is set if a fault is detected on the I

OUT_A

OUT_D

OUT_C

OUT_B

OUT_A

pin. pin. pin. pin.

read back on the SDO pin during every write sequence. Alternatively, if the STATREAD bit is not set, the status register can be read using the normal readback operation (see the Readback Operation section).

X1 X1 X1

OUT_D

fault

Functionality section for

MAX

Functionality section for

MAX

Functionality section for

MAX

Functionality section for

MAX

OUT_C

I fault

OUT_B

OUT_A

fault

Rev. A | Page 31 of 44

Page 32

AD5737 Data Sheet

DEVICE FEATURES

FAULT OUTPUT

The AD5737 is equipped with a open-drain output that allows several devices to be connected together to one pull-up resistor for global fault

FAU LT

detection. The

pin is forced active by any one of the

following fault conditions:

• The voltage at I

OUT_x

range due to an open-loop circuit or insufficient power supply voltage. The internal circuitry that develops the fault output avoids using a comparator with windowed limits because this requires an actual output error before

FAU LT

the

output becomes active. Instead, the signal is generated when the internal amplifier in the output stage has less than approximately 1 V of remaining drive capability. Thus, the before the compliance limit is reached.

• An interface error is detected due to a PEC failure (see the

Packet Error Checking section).

• The core temperature of the AD5737 exceeds approxi-

mately 150°C.

The I

fault, PEC error, and over temp bits of the status

OUT_x

FAU LT

pin, an active low,

AD5737

attempts to rise above the compliance

FAU LT

output is activated slightly

FAU LT

output to

FAU LT

DIGITAL OFFSET AND GAIN CONTROL

Each DAC channel has a gain (M) register and an offset (C) register, which allow trimming out of the gain and offset errors of the entire signal chain. Data from the DAC data register is operated on by a digital multiplier and adder controlled by the contents of the gain and offset registers; the calibrated DAC data is then stored in the DAC input register (see Figure 52).

DAC DATA REGISTER

GAIN (M)

OFFSET (C)

Figure 52. Digital Offset and Gain Control

Although Figure 52 indicates a multiplier and adder for each channel, the device has only one multiplier and one adder, which are shared by all four channels. This design has implications for the update speed when several channels are updated at once (see Ta b le 3).

DAC

INPUT

DAC

10067-075

When data is written to the gain (M) or offset (C) register, the output is not automatically updated. Instead, the next write to the DAC channel uses the new gain and offset values to perform a new calibration and automatically updates the channel.

The output data from the calibration is routed to the DAC input register. This data is then loaded to the DAC, as described in the Serial Interface section. Both the gain register and the offset register have 12 bits of resolution. The correct order to calibrate the gain and offset is to first calibrate the gain and then calibrate the offset.

The value (in decimal) that is written to the DAC input register can be calculated as follows:

DCode

rDACRegiste

×= C

(1)

)1(−++

where:

D is the code loaded to the DAC data register of the

DAC channel.

M is the code in the gain register (default code = 2 C is the code in the offset register (default code = 2

− 1).

STATUS READBACK DURING A WRITE

The AD5737 can be configured to read back the contents of the status register during every write sequence. This feature is enabled using the STATREAD bit in the main control register. When this feature is enabled, the user can continuously monitor the status register and act quickly in the case of a fault.

When status readback during a write is enabled, the contents of the 16-bit status register (see Tabl e 32 ) are output on the SDO pin, as shown in Figure 5.

When the AD5737 is powered up, the status readback during a write feature is disabled. When this feature is enabled, readback of registers other than the status register is not available. To read back any other register, clear the STATREAD bit before following the readback sequence (see the Readback Operation section). The STATREAD bit can be set high again after the register read.

ASYNCHRONOUS CLEAR

CLEAR is an active high, edge sensitive input that allows the output to be cleared to a preprogrammed 12-bit code. This code is user-programmable via a per-channel 12-bit clear code register.

For a channel to be cleared, set the CLR_EN bit in the DAC control register for that channel. If the clear function on a channel is not enabled, the output remains in its current state, independent of the level of the CLEAR pin.

When the CLEAR signal returns low, the relevant outputs remain cleared until a new value is programmed to them.

Rev. A | Page 32 of 44

Page 33

Data Sheet AD5737

PACKET ERROR CHECKING

To verify that data has been received correctly in noisy environments, the AD5737 offers the option of packet error checking based on an 8-bit cyclic redundancy check (CRC-8). The device controlling the AD5737 should generate an 8-bit frame check sequence using the following polynomial:

C(x) = x

This value is added to the end of the data-word, and 32 bits are sent to the AD5737 before 32-bit frame, it performs the error check when If the error check is valid, the data is written to the selected register. If the error check fails, the bit in the status register is set. After the status register is read, FAU LT and the PEC error bit is cleared automatically.

SYNC

SCLK

SDIN

SYNC

SCLK

SDIN

FAULT

Packet error checking can be used for transmitting and receiving data packets. If status readback during a write is enabled, the PEC values returned during the status readback operation should be ignored. If status readback during a write is disabled, the user can still use the normal readback operation to monitor status register activity with PEC.

+ x2 + x1 + 1

SYNC

goes high. If the sees a

FAU LT

pin goes low and the PEC error

AD5737

SYNC

goes high.

returns high (assuming that there are no other faults),

UPDATE ON SYNC HIGH

MSB

D23

24-BIT DATA

24-BIT DATA TRANSFER—NO ERROR CHECKING

MSB

D31

24-BIT DATA 8-BIT CRC

32-BIT DATA TRANSFER WITH ERRO R CHECKING

Figure 53. PEC Timing

LSB

UPDATE ON SYNC HIGH

ONLY IF ERROR CHECK PASSED

LSB

D7 D0

FAULT PIN GOES LOW

IF ERROR CHECK FAILS

WATCHDOG TIMER

When enabled, an on-chip watchdog timer generates an alert signal if 0x195 is not written to the software register within the programmed timeout period. This feature is useful to ensure that communication has not been lost between the MCU and the AD5737 and that the datapath lines are working properly

SYNC

(that is, SDIN, SCLK, and

). If 0x195 is not received by the software register within the timeout period, the ALERT pin signals a fault condition. The ALERT pin is active high and can be connected directly to the CLEAR pin to enable a clear in the event that communication from the MCU is lost.

To enable the watchdog timer and set the timeout period (5 ms, 10 ms, 100 ms, or 200 ms), program the main control register (see Tabl e 20 and Ta ble 2 1).

ALERT OUTPUT

The AD5737 is equipped with an ALERT pin. This pin is an active high CMOS output. The AD5737 also has an internal watchdog timer. When enabled, the watchdog timer monitors SPI communications. If 0x195 is not received by the software register within the timeout period, the ALERT pin is activated.

INTERNAL REFERENCE

The AD5737 contains an integrated 5 V voltage reference with initial accuracy of ±5 mV maximum and a temperature coefficient of ±10 ppm/°C maximum. The reference voltage is buffered and is externally available for use elsewhere within the system.

EXTERNAL CURRENT SETTING RESISTOR

is an internal sense resistor that is part of the voltage-to-

SET

current conversion circuitry (see Figure 48). The stability of the output current value over temperature is dependent on the stability of the R over temperature, the internal R and an external, 15 kΩ, low drift resistor can be connected to the R via the DAC control register (see Tab le 23 ).

10067-180

Tabl e 1 provides the performance specifications for the AD5737 with both the internal R resistor. The use of an external R performance over the internal R R

SET

performance depends on the absolute value and temperature coefficient of the resistor used. This directly affects the gain error of the output and, thus, the total unadjusted error. To arrive at the gain/TUE error of the output with a specific external R resistor, add the absolute error percentage of the R directly to the gain/TUE error of the AD5737 with the external R

SET

value. To improve the stability of the output current

SET

resistor, R1, can be bypassed

SET

pin of the AD5737. The external resistor is selected

SET_x

resistor and an external, 15 kΩ R

SET

resistor allows for improved

SET

resistor option. The external

SET

resistor specifications assume an ideal resistor; the actual

resistor, as shown in Ta b le 1 (expressed in % FSR).

resistor

SET

Rev. A | Page 33 of 44

Page 34

AD5737 Data Sheet

HART CONNECTIVITY

The AD5737 has four CHART pins, one corresponding to each output channel. A HART signal can be coupled into these pins. The HART signal appears on the corresponding current output, if the output is enabled. Table 3 3 shows the recommended input voltages for the HART signal at the CHART pin. If these voltages are used, the current output should meet the HART amplitude specifications.

Table 33. CHART Input Voltage to HART Output Current

CHART Input Voltage Current Output (HART)

SET

Internal R External R

150 mV p-p 1 mA p-p

SET

170 mV p-p 1 mA p-p

SET

Figure 54 shows the recommended circuit for attenuating and coupling the HART signal. A minimum capacitance of C1 + C2 is required to ensure that the 1.2 kHz and 2.2 kHz HART frequencies are not significantly attenuated at the output. The recommended values are C1 = 22 nF and C2 = 47 nF.

HART MODEM

OUTPUT

Figure 54. Coupling the HART Signal

CHARTx

10067-076

Digitally controlling the slew rate of the output is necessary to meet the analog rate of change requirements for HART.

DIGITAL SLEW RATE CONTROL

The digital slew rate control feature of the AD5737 allows the user to control the rate at which the output value changes. With the slew rate control feature disabled, the output value changes at a rate limited by the output drive circuitry and the attached load. To reduce the slew rate, the user can enable the digital slew rate control feature using the SREN bit of the slew rate control register (see Ta b le 2 8 ).

When slew rate control is enabled, the output, instead of slewing directly between two values, steps digitally at a rate defined by the SR_CLOCK and SR_STEP parameters. These parameters are accessible via the slew rate control register (see Tabl e 28 ).

• SR_CLOCK defines the rate at which the digital slew is

updated; for example, if the selected update rate is 8 kHz, the output is updated every 125 μs.

• SR_STEP defines by how much the output value changes

at each update.

Together, these parameters define the rate of change of the output value. Ta ble 3 4 and Ta b le 3 5 list the range of values for the SR_CLOCK and SR_STEP parameters, respectively.

Table 34. Slew Rate Update Clock Options

SR_CLOCK Update Clock Frequency1

0000 64 kHz 0001 32 kHz 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110

16 kHz 8 kHz 4 kHz 2 kHz 1 kHz 500 Hz 250 Hz 125 Hz 64 Hz 32 Hz 16 Hz 8 Hz 4 Hz

1111 0.5 Hz

These clock frequencies are divided down from the 13 MHz internal

oscillator (see Table 1, Figure 45, and Figure 46).

Table 35. Slew Rate Step Size Options

SR_STEP Step Size (LSB)

000 1 001 2 010 011 100 101 110

4 16 32 64 128

111 256

The following equation describes the slew rate as a function of the step size, the update clock frequency, and the LSB size.

RateSlew

ChangeOutput

××

SizeLSBFrequencyClockUpdateSizeStep

where:

Slew Rate is expressed in seconds. Output Change is expressed in amperes.

The update clock frequency for any given value is the same for all output ranges. The step size, however, varies across output ranges for a given value of step size because the LSB size is different for each output range.

Rev. A | Page 34 of 44

Page 35

Data Sheet AD5737

When the slew rate control feature is enabled, all output changes occur at the programmed slew rate (see the DC-to-DC Converter Settling Time section for more information). For example, if the CLEAR pin is asserted, the output slews to the clear value at the programmed slew rate (assuming that the channel is enabled to be cleared).

If more than one channel is enabled for digital slew rate control, care must be taken when asserting the CLEAR pin. If a channel under slew rate control is slewing when the CLEAR pin is asserted, other channels under slew rate control may change directly to their clear code not under slew rate control.

DYNAMIC POWER CONTROL

The AD5737 provides integrated dynamic power control using a dc-to-dc boost converter circuit. This circuit reduces power consumption compared with standard designs.

In standard current input module designs, the load resistor values can range from typically 50 Ω to 750 Ω. Output module systems must source enough voltage to meet the compliance voltage requirement across the full range of load resistor values. For example, in a 4 mA to 20 mA loop when driving 20 mA, a compliance voltage of >15 V is required. When driving 20 mA into a 50 Ω load, a compliance voltage of only 1 V is required.

The AD5737 circuitry senses the output voltage and regulates this voltage to meet the compliance requirements plus a small headroom voltage. The AD5737 is capable of driving up to 24 mA through a 1 kΩ load.

DC-TO-DC CONVERTERS

The AD5737 contains four independent dc-to-dc converters. These are used to provide dynamic control of the V voltage for each channel (see Figure 48). Figure 55 shows the discrete components needed for the dc-to-dc circuitry, and the following sections describe component selection and operation of this circuitry.

≥10µF

DCDC

10µH

DCDC

4.7µF

FILTER

10Ω

Figure 55. DC-to-DC Circuit

FILTER

0.1µF

Table 36. Recommended Components for a DC-to-DC Converter

Symbol Component Value Manufacturer

XAL4040-103 10 μH Coilcraft®

DCDC

GRM32ER71H475KA88L 4.7 μF Murata

DCDC

PMEG3010BEA 0.285 VF NXP

DCDC

It is recommended that a 10 Ω, 100 nF low-pass RC filter be placed after C but reduces the amount of ripple on the V

. This filter consumes a small amount of power

DCDC

supply.

BOOST_x

supply

10067-077

DC-to-DC Converter Operation

The on-board dc-to-dc converters use a constant frequency, peak current mode control scheme to step up an AV

input of 4.5 V

to 5.5 V to drive the AD5737 output channel. These converters are designed to operate in discontinuous conduction mode with a duty cycle of <90% typical. Discontinuous conduction mode refers to a mode of operation where the inductor current goes to zero for an appreciable percentage of the switching cycle. The dc-to-dc converters are nonsynchronous; that is, they require an external Schottky diode.

DC-to-DC Converter Output Voltage

When a channel current output is enabled, the converter regulates the V

supply to 7.4 V (±5%) or (I

BOOST_x

OUT

× R

LOAD

+ Headroom), whichever is greater (see Figure 30 for a plot of headroom supplied vs. output current). When the output is disabled, the converter regulates the V

supply to 7.4 V (±5%).

BOOST_x

DC-to-DC Converter Settling Time

The settling time for a step greater than ~1 V (I

OUT

× R

LOAD

) is dominated by the settling time of the dc-to-dc converter. The exception to this is when the required voltage at the I

OUT_x

pin plus the compliance voltage is below 7.4 V (±5%). Figure 25 shows a typical plot of the output settling time. This plot is for a 1 kΩ load. The settling time for smaller loads is faster. The settling time for current steps less than 24 mA is also faster.

DC-to-DC Converter V

The maximum V

BOOST_x

Functionality

MAX

voltage is set in the dc-to-dc control register (23 V, 24.5 V, 27 V, or 29.5 V; see Tab l e 2 7 ). When the maximum voltage is reached, the dc-to-dc converter is disabled, and the V V

voltage decays by ~0.4 V, the dc-to-dc converter is

BOOST_x

reenabled, and the voltage ramps up again to V

voltage is allowed to decay by ~0.4 V. After the

BOOST_x

MAX

, if still

required. This operation is shown in Figure 56.

29.6 V

MAX

DC-DCx BIT

29.5

29.4

29.3

29.2

29.1

VOLTAGE (mV)

DC-DCx BIT = 1

29.0

28.9

BOOST_ x

28.8

28.7

DC-DCx BIT = 0

28.6

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0

Figure 56. Operation on Reaching V

0mA TO 24mA RANGE, 24mA OUTPUT OUTPUT UNLOADED

DC-DC MaxV BITS = 29.5V

= 410kHz

= 25°C

TIME (ms)

MAX

10067-183

As shown in Figure 56, the DC-DCx bit in the status register is asserted when the AD5737 ramps up to the V is deasserted when the voltage decays to V

MAX

value but

MAX

− ~0.4 V.

Rev. A | Page 35 of 44

Page 36

AD5737 Data Sheet

DC-to-DC Converter On-Board Switch

The AD5737 contains a 0.425 Ω internal switch. The switch current is monitored on a pulse-by-pulse basis and is limited to 0.8 A peak current.

DC-to-DC Converter Switching Frequency and Phase

The AD5737 dc-to-dc converter switching frequency can be selected from the dc-to-dc control register (see Tabl e 27 ). The phasing of the channels can also be adjusted so that the dc-to-dc converters can clock on different edges. For typical applications, a 410 kHz frequency is recommended. At light loads (low output current and small load resistor), the dc-to-dc converter enters a pulse-skipping mode to minimize switching power dissipation.

DC-to-DC Converter Inductor Selection

For typical 4 mA to 20 mA applications, a 10 μH inductor (such as the XAL4040-103 from Coilcraft), combined with a switching frequency of 410 kHz, allows up to 24 mA to be driven into a load resistance of up to 1 kΩ with an AV

supply of 4.5 V to

5.5 V. It is important to ensure that the inductor can handle the peak current without saturating, especially at the maximum ambient temperature. If the inductor enters saturation mode, efficiency decreases. The inductance value also drops during saturation and may result in the dc-to-dc converter circuit not being able to supply the required output power.

DC-to-DC Converter External Schottky Diode Selection

The AD5737 requires an external Schottky diode for correct operation. Ensure that the Schottky diode is rated to handle the maximum reverse breakdown voltage expected in operation and that the maximum junction temperature of the diode is not exceeded. The average current of the diode is approximately equal to the I

current. Diodes with larger forward voltage

LOAD

drops result in a decrease in efficiency.

DC-to-DC Converter Compensation Capacitors

Because the dc-to-dc converter operates in discontinuous conduction mode, the uncompensated transfer function is essentially a single-pole transfer function. The pole frequency of the transfer function is determined by the output capacitance, input and output voltage, and output load of the dc-to-dc converter. The AD5737 uses an external capacitor in conjunction with an internal 150 kΩ resistor to compensate the regulator loop.

Alternatively, an external compensation resistor can be used in series with the compensation capacitor by setting the DC-DC comp bit in the dc-to-dc control register (see Tab le 2 7 ). In this case, a resistor of ~50 kΩ is recommended. The advantages of this configuration are described in the AI

Supply Requirements—

Slewing section. For typical applications, a 10 nF dc-to-dc compensation capacitor is recommended.

DC-to-DC Converter Input and Output Capacitor Selection

The output capacitor affects the ripple voltage of the dc-to-dc converter and indirectly limits the maximum slew rate at which the channel output current can rise. The ripple voltage is caused by a combination of the capacitance and the equivalent series resistance (ESR) of the capacitor. For typical applications, a ceramic capacitor of 4.7 μF is recommended. Larger capacitors or parallel capacitors improve the ripple at the expense of reduced slew rate. Larger capacitors also affect the current requirements of the AV

supply while slewing (see the AICC

Supply Requirements—Slewing section). The capacitance at the output of the dc-to-dc converter should be >3 μF under all operating conditions.

The input capacitor provides much of the dynamic current required for the dc-to-dc converter and should be a low ESR component. For the AD5737, a low ESR tantalum or ceramic capacitor of 10 μF is recommended for typical applications. Ceramic capacitors must be chosen carefully because they can exhibit a large sensitivity to dc bias voltages and temperature. X5R or X7R dielectrics are preferred because these capacitors remain stable over wider operating voltage and temperature ranges. Care must be taken if selecting a tantalum capacitor to ensure a low ESR value.

AICC SUPPLY REQUIREMENTS—STATIC

The dc-to-dc converter is designed to supply a V

= I

BOOST_x

OUT

× R

+ Headroom (2)

LOAD

See Figure 30 for a plot of headroom supplied vs. output current. Therefore, for a fixed load and output voltage, the output current of the dc-to-dc converter can be calculated by the following formula:

AVEfficiency

BOOST

BOOSTOUT

AVη

Power

where:

is the output current from I

OUT

is the efficiency at V

BOOST

BOOST_x

in amperes.

OUT_x

as a fraction (see Figure 32

and Figure 33).

voltage of

BOOST_x

(3)

Rev. A | Page 36 of 44

Page 37

Data Sheet AD5737

AICC SUPPLY REQUIREMENTS—SLEWING

The AICC current requirement while slewing is greater than in static operation because the output power increases to charge the output capacitance of the dc-to-dc converter. This transient current can be quite large (see Figure 57), although the methods described in the Reducing AI can reduce the requirements on the AV

If not enough AI drops. Due to this AV

current can be provided, the AVCC voltage

slewing increases further, causing the voltage at AV further (see Equation 3). In this case, the V therefore, the output voltage, may never reach their intended values. Because the AV

this voltage drop may also affect other channels.

0.8

0.7

0.6

0.5

0.4

CURRENT (A)

0.3

0.2

0.1

0 0.5 1.0 1.5 2.0 2.5

Figure 57. AI

OUT

BOOST

Current vs. Time for 24 mA Step Through 1 kΩ Load

with Internal Compensation Resistor

Reducing AICC Current Requirements

Two main methods can be used to reduce the AICC current requirements. One method is to add an external compensation resistor, and the other is to use slew rate control. These methods can be used together.

Current Requirements section

supply.

drop, the AICC current required for

to drop

voltage and,

BOOST_x

voltage is common to all channels,

0mA TO 24mA RANGE

INDUCTOR = 10µH (XAL4040-103)

TIME (ms)

1kΩ LOAD

= 410kHz

= 25°C

VOLTAGE (V)

BOOST_x

CURRENT (mA)/ V

OUT_x

Rev. A | Page 37 of 44

10067-184

Adding an External Compensation Resistor

A compensation resistor can be placed at the COMP

DCDC_x

pin in series with the 10 nF compensation capacitor. A 51 kΩ external compensation resistor is recommended. This compensation increases the slew time of the current output but reduces the AI transient current requirements. Figure 58 shows a plot of AI

current for a 24 mA step through a 1 kΩ load when using a 51 kΩ compensation resistor. The compensation resistor reduces the current requirements through smaller loads even further, as shown in Figure 59.

0.8 0mA TO 24mA RANGE

1kΩ LOAD

= 410kHz

0.7

INDUCTOR = 10µH (XAL4040-103) T

= 25°C

0.6

0.5

0.4

CURRENT (A)

0.3

0.2

0.1

0 0.5 1.0 1.5 2.0 2.5

Figure 58. AI

Current vs. Time for 24 mA Step Through 1 kΩ Load

OUT

BOOST

TIME (ms)

with External 51 kΩ Compensation Resistor

VOLTAGE (V)

BOOST_ x

CURRENT (mA)/ V

OUT_x

0.8

0.7

0.6

0.5

0.4

CURRENT (A)

0.3

0.2

0.1

Figure 59. AI

OUT

BOOST

0 0.5 1.0 1.5 2.0 2.5

Current vs. Time for 24 mA Step Through 500 Ω Load

INDUCTOR = 10µH (XAL4040-103)

TIME (ms)

0mA TO 24mA RANGE

500Ω LOAD

with External 51 kΩ Compensation Resistor

= 410kHz

= 25°C

VOLTAGE (V)

BOOST_ x

CURRENT (mA)/ V

OUT_x

10067-185

10067-186

Page 38

AD5737 Data Sheet

Using Slew Rate C ontrol

Using slew rate control can greatly reduce the current requirements of the AV

0.8

0.7

0.6

0.5

0.4

CURRENT (A)

0.3

0.2

0.1

01 2345 6

Figure 60. AI

supply, as shown in Figure 60.

0mA TO 24mA RANGE 1kΩ LOAD

= 410kHz

INDUCTOR = 10µ H (XAL4040-103) T

= 25°C

OUT

BOOST

TIME (ms)

Current vs. Time for 24 mA Step Through 1 kΩ Load

with Slew Rate Control

VOLTAGE (V)

BOOST_ x

CURRENT (mA)/ V

OUT_x

When using slew rate control, it is important to remember that the output cannot slew faster than the dc-to-dc converter. The dc-to-dc converter slews slowest at higher currents through large loads (for example, 1 kΩ). The slew rate is also dependent on the configuration of the dc-to-dc converter. Two examples of the dc-to-dc converter output slew are shown in Figure 58 and Figure 59. (V

corresponds to the output voltage of the

BOOST

dc-to-dc converter.)

5.0V

(LEFT FLOATING)

BOOST_A

10067-187

EXTERNAL PMOS MODE

The AD5737 can also be used with an external PMOS transistor per channel, as shown in Figure 61. This mode can be used to limit the on-chip power dissipation of the AD5737, although this mode does not reduce the power dissipation of the total system. The IGATEx functionality is not typically required when using the dynamic power control feature; therefore, Figure 61 shows the configuration of the device for a fixed V

In this configuration, the SW pin is grounded. The V

pin is left floating, and the GNDSWx

pin is connected to a minimum

BOOST_x

supply of 7.4 V and a maximum supply of 33 V. This supply can be sized according to the maximum load required to be driven.

The IGATEx functionality works by holding the gate of the external PMOS transistor at (V

− 5 V). This means that

BOOST_x

the majority of the channel’s power dissipation takes place in the external PMOS transistor.

The external PMOS transistor should be selected to tolerate a

voltage of at least the V

voltage, as well as to handle

BOOST_x

the power dissipation required. The external PMOS transistor typically has minimal effect on the current output performance.

BOOST_x

supply.

R2 R3

DAC A

DAC CHANNEL A

GNDSW

BOOST_ A

– 5V)

OUT_A

IGATEA

SET_A

CHARTA

CURRENT OUTPUT

LOAD

10067-190

Figure 61. Configuration of Channel A Using IGATEx

Rev. A | Page 38 of 44

Page 39

Data Sheet AD5737

APPLICATIONS INFORMATION

CURRENT OUTPUT MODE WITH INTERNAL R

When using the internal R significantly affected by how many other channels using the internal R

are enabled and by the dc crosstalk from these

SET

channels. The internal R four channels enabled with the internal R outputting the same code.

For every channel enabled with the internal R decreases. For example, with one current output enabled using the internal R

, the offset error is 0.075% FSR. This value decreases

SET

proportionally as more current channels are enabled; the offset error is 0.056% FSR on each of two channels, 0.029% FSR on each of three channels, and 0.01% FSR on each of four channels.

Similarly, the dc crosstalk when using the internal R tional to the number of current output channels enabled with the internal R

. For example, with the measured channel at 0x8000

SET

and another channel going from zero to full scale, the dc crosstalk is −0.011% FSR. With two other channels going from zero to full scale, the dc crosstalk is −0.019% FSR, and with all three other channels going from zero to full scale, it is −0.025% FSR.

For the full-scale error measurement in Tab le 1 , all channels are at 0xFFFF. This means that as any channel goes to zero scale, the full-scale error increases due to the dc crosstalk. For example, with the measured channel at 0xFFFF and three channels at zero scale, the full-scale error is 0.025% FSR. Similarly, if only one channel is enabled with the internal R is 0.025% FSR + 0.075% FSR = 0.1% FSR.

resistor, the current output is

SET

specifications in Ta b le 1 are for all

SET

selected and

SET

, the offset error

SET

, the full-scale error

SET

PRECISION VOLTAGE REFERENCE SELECTION

To achieve the optimum performance from the AD5737 over its full operating temperature range, a precision voltage reference must be used. Care should be taken with the selection of the precision voltage reference. The voltage applied to the reference inputs is used to provide a buffered reference for the DAC cores. Therefore, any error in the voltage reference is reflected in the outputs of the AD5737.

SET

is propor-

Four possible sources of error must be considered when choosing a voltage reference for high accuracy applications: initial accuracy, long-term drift, temperature coefficient of the output voltage, and output voltage noise.

Initial accuracy error on the output voltage of an external reference can lead to a full-scale error in the DAC. Therefore, to minimize these errors, a reference with a low initial accuracy error specification is preferred. Choosing a reference with an output trim adjustment, such as the ADR435, allows a system designer to trim out system errors by setting the reference voltage to a voltage other than the nominal. The trim adjustment can be used at any temperature to trim out any error.

Long-term drift is a measure of how much the reference output voltage drifts over time. A reference with a tight long-term drift specification ensures that the overall solution remains relatively stable over its entire lifetime.

The temperature coefficient of the reference output voltage affects INL, DNL, and TUE. A reference with a tight temperature coefficient specification should be chosen to reduce the dependence of the DAC output voltage on ambient temperature.

In high accuracy applications, which have a relatively low noise budget, reference output voltage noise must be considered. Choosing a reference with as low an output noise voltage as practical for the system resolution required is important. Precision voltage references such as the ADR435 (XFET® design) produce low output noise in the 0.1 Hz to 10 Hz bandwidth. However, as the circuit bandwidth increases, filtering the output of the reference may be required to minimize the output noise.

DRIVING INDUCTIVE LOADS

When driving inductive or poorly defined loads, a capacitor may be required between the I ensure stability. A 0.01 μF capacitor between I ensures stability of a load of 50 mH. The capacitive component of the load may cause slower settling, although this may be masked by the settling time of the AD5737. There is no maximum capacitance limit for the current output of the AD5737.

pin and the AGND pin to

OUT_x

and AGND

OUT_x

Table 37. Recommended Precision Voltage References

Initial Accuracy

Part No.

ADR445 ±2 50 3 2.25 ADR02 ±3 50 3 10 ADR435 ±2 40 3 8 ADR395 ±5 50 9 8 AD586 ±2.5 15 10 4

(mV Maximum)

Long-Term Drift (ppm Typical)

Temperature Coefficient (ppm/°C Maximum)

0.1 Hz to 10 Hz Noise (μV p-p Typical)

Rev. A | Page 39 of 44

Page 40

AD5737 Data Sheet

TRANSIENT VOLTAGE PROTECTION

The AD5737 contains ESD protection diodes that prevent damage from normal handling. The industrial control environment can, however, subject I/O circuits to much higher transients. To protect the AD5737 from excessively high voltage transients, external power diodes and a surge current limiting resistor (R are required, as shown in Figure 62. A typical value for R The two protection diodes and the resistor (R

) must have appro-

is 10 Ω.

priate power ratings.

(FROM

DC-TO- DC

CONVERTER)

FILTER

DCDC

4.7µF

10Ω

Figure 62. Output Transient Voltage Protection

FILTER

0.1µF

BOOST_x

AD5737

OUT_x

AGND

LOAD

Further protection can be provided using transient voltage suppressors (TVSs), also referred to as transorbs. These components are available as unidirectional suppressors, which protect against positive high voltage transients, and as bidirectional suppressors, which protect against both positive and negative high voltage transients. Transient voltage suppressors are available in a wide range of standoff and breakdown voltage ratings. The TVS should be sized with the lowest breakdown voltage possible while not conducting in the functional range of the current output.

It is recommended that all field connected nodes be protected.

MICROPROCESSOR INTERFACING

Microprocessor interfacing to the AD5737 is via a serial bus that uses a protocol compatible with microcontrollers and DSP processors. The communication channel is a 3-wire minimum interface consisting of a clock signal, a data signal, and a latch signal. The AD5737 requires a 24-bit data-word with data valid on the falling edge of SCLK.

The DAC output update is initiated either on the rising edge of

or, if

LDAC

is held low, on the rising edge of

LDAC contents of the registers can be read using the readback function.

SYNC

. The

)

10067-079

AD5737-to-ADSP-BF527 Interface

The AD5737 can be connected directly to the SPORT interface of the ADSP-BF527, an Analog Devices, Inc., Blackfin® DSP. Figure 63 shows how the SPORT interface can be connected to control the AD5737.

AD5737

SPORT_TFS

SPORT_TSCLK

SPORT_DT0

ADSP-BF527

Figure 63. AD5737-to-ADSP-BF527 SPORT Interface

GPIO0

SYNC

SCLK

SDIN

LDAC

10067-080

LAYOUT GUIDELINES

Grounding

In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. The printed circuit board on which the AD5737 is mounted should be designed so that the analog and digital sections are separated and confined to certain areas of the board. If the AD5737 is in a system where multiple devices require an AGND-to-DGND connection, the connection should be made at one point only. The star ground point should be established as close as possible to the device.

The GNDSW supply are referred to as PGND. PGND should be confined to certain areas of the board, and the PGND-to-AGND connection should be made at one point only.

Supply Decoupling

The AD5737 should have ample supply bypassing of 10 μF in parallel with 0.1 μF on each supply, located as close to the package as possible, ideally right up against the device. The 10 μF capacitors are the tantalum bead type. The 0.1 μF capacitors should have low effective series resistance (ESR) and low effective series inductance (ESL), such as the common ceramic types, which provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching.

pin and the ground connection for the AVCC

Rev. A | Page 40 of 44

Page 41

Data Sheet AD5737

Traces

The power supply lines of the AD5737 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast switching signals such as clocks should be shielded with digital ground to prevent radiating noise to other parts of the board and should never be run near the reference inputs. A ground line routed between the SDIN and SCLK traces helps reduce crosstalk between them (not required on a multilayer board that has a separate ground plane, but separating the lines helps). It is essential to minimize noise on the REFIN line because it couples through to the DAC output.

Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other to reduce the effects of feedthrough on the board. A microstrip technique is by far the best method, but it is not always possible with a double-sided board. In this technique, the component side of the board is dedicated to ground plane, and signal traces are placed on the solder side.

DC-to-DC Converters

To achieve high efficiency, good regulation, and stability, a well-designed printed circuit board layout is required.

Follow these guidelines when designing printed circuit boards (see Figure 55):

• Keep the low ESR input capacitor, C

, close to AVCC and

PGND.

• Keep the high current path from C

) to SWx and PGND as short as possible.

DCDC

• Keep the high current path from C

DCDC

), the diode (D

), and the output capacitor (C

DCDC

through the inductor

DCDC

)

as short as possible.

• Keep high current traces as short and as wide as possible.

The path from C

through the inductor (L

DCDC

) to SWx

and PGND should be able to handle a minimum of 1 A.

• Place the compensation components as close as possible to

the COMP

DCDC_x

pin.

• Avoid routing high impedance traces near any node

connected to SW

or near the inductor to prevent radiated

noise injection.

GALVANICALLY ISOLATED INTERFACE

In many process control applications, it is necessary to provide an isolation barrier between the controller and the unit being controlled to protect and isolate the controlling circuitry from any hazardous common-mode voltages that may occur. The Analog Devices in excess of 2.5 kV. The serial loading structure of the AD5737 makes it ideal for isolated interfaces because the number of interface lines is kept to a minimum. Figure 64 shows a 4-channel isolated interface to the AD5737 using an ADuM1411. For more information, visit www.analog.com.

MICRO CONTROLLER

SERIAL CLOCK

CONTRO L OUT

iCoupler® products can provide voltage isolation

ADuM1411

OUT

SERIAL DATA

OUT

SYNC OUT

ENCODE DECODE

Figure 64. 4-Channel Isolated Interface to the AD5737

TO SCLK

TO SDIN

TO SYNC

TO LDAC

10067-081

Rev. A | Page 41 of 44

Page 42

AD5737 Data Sheet

OUTLINE DIMENSIONS

0.60 MAX

EXPOSED PAD

(BOTTOM VIEW)

PIN 1

INDICATOR

7.25

7.10 SQ

6.95

PIN 1

INDICATOR

9.00

BSC SQ

TOP VIEW

8.75

BSC SQ

0.60

MAX

0.50

BSC

1.00

0.85

0.80

SEATING

PLANE

12° MAX

0.50

0.40

0.30

0.80 MAX

0.65 TYP

0.30

0.23

0.18

COMPLIANT TO JEDEC S TANDARDS MO-220-VMMD-4

0.05 MAX

0.02 NOM

0.20 REF

7.50 REF

FOR PROPER CONNECTION O F THE EXPOSED PAD, REFER TO THE PIN CONF IGURATIO N AND FUNCTION DESCRIPTIO NS SECTION O F THIS DAT A SHEET.

0.25 MIN

080108-C

Figure 65. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

9 mm × 9 mm Body, Very Thin Quad

(CP-64-3)

Dimensions shown in millimeters

ORDERING GUIDE

Model

AD5737ACPZ 12 −40°C to +105°C 64-Lead LFCSP_VQ CP-64-3 AD5737ACPZ-RL7 12 −40°C to +105°C 64-Lead LFCSP_VQ CP-64-3

Z = RoHS Compliant Part.

Resolution (Bits) Temperature Range Package Description Package Option

Rev. A | Page 42 of 44

Page 43

Data Sheet AD5737

NOTES

Rev. A | Page 43 of 44

Page 44

AD5737 Data Sheet

NOTES

Rev. A | Page 44 of 44

Datasheet AD5737 Datasheet (ANALOG DEVICES)

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

PRODUCT HIGHLIGHTS

COMPANION PRODUCTS

TABLE OF CONTENTS

REVISION HISTORY

DETAILED FUNCTIONAL BLOCK DIAGRAM

SPECIFICATIONS

AC PERFORMANCE CHARACTERISTICS

TIMING CHARACTERISTICS

Timing Diagrams

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS

CURRENT OUTPUTS

DC-TO-DC CONVERTER

REFERENCE

GENERAL

TERMINOLOGY

THEORY OF OPERATION

DAC ARCHITECTURE

POWER-ON STATE OF THE AD5737

SERIAL INTERFACE

Input Shift Register

Individual DAC Updating

Simultaneous Updating of All DACs

Reference Buffers

TRANSFER FUNCTION

REGISTERS

ENABLING THE OUTPUT

REPROGRAMMING THE OUTPUT RANGE

DATA REGISTERS

DAC Data Register

Gain Register

Offset Register

Clear Code Register

CONTROL REGISTERS

Main Control Register

DAC Control Register

Software Register

DC-to-DC Control Register

Slew Rate Control Register

READBACK OPERATION

Readback Example

Status Register

DEVICE FEATURES

FAULT OUTPUT

DIGITAL OFFSET AND GAIN CONTROL

STATUS READBACK DURING A WRITE

ASYNCHRONOUS CLEAR

PACKET ERROR CHECKING

WATCHDOG TIMER

ALERT OUTPUT

INTERNAL REFERENCE

EXTERNAL CURRENT SETTING RESISTOR

HART CONNECTIVITY

DIGITAL SLEW RATE CONTROL

DYNAMIC POWER CONTROL

DC-TO-DC CONVERTERS

DC-to-DC Converter Operation

DC-to-DC Converter Output Voltage

DC-to-DC Converter Settling Time

DC-to-DC Converter On-Board Switch

DC-to-DC Converter Switching Frequency and Phase

DC-to-DC Converter Inductor Selection

DC-to-DC Converter External Schottky Diode Selection

DC-to-DC Converter Compensation Capacitors

DC-to-DC Converter Input and Output Capacitor Selection

AICC SUPPLY REQUIREMENTS—STATIC

AICC SUPPLY REQUIREMENTS—SLEWING

Reducing AICC Current Requirements

Adding an External Compensation Resistor