Datasheet AD5724R, AD5734R, AD5754R Datasheet (ANALOG DEVICES)

Page 1

Complete, Quad, 12-/14-/16-Bit, Serial Input,

FEATURES

Complete, quad, 12-/14-/16-bit DACs Operates from single/dual supplies Software programmable output range

+5 V, +10 V, +10.8 V, ±5 V, ±10 V, ±10.8 V INL error: ±16 LSB maximum, DNL error: ±1 LSB maximum Total unadjusted error (TUE): 0.1% FSR maximum Settling time: 10 μs typical Integrated reference: ±5 ppm/°C maximum Integrated reference buffers Output control during power-up/brownout Simultaneous updating via Asynchronous DSP/microcontroller-compatible serial interface 24-lead TSSOP Operating temperature range: −40°C to +85°C iCMOS process technology

to zero scale/midscale

CLR

APPLICATIONS

Industrial automation Closed-loop servo control, process control Automotive test and measurement Programmable logic controllers

LDAC

Unipolar/Bipolar Voltage Output DACs

AD5724R/AD5734R/AD5754R

GENERAL DESCRIPTION

The AD5724R/AD5734R/AD5754R are quad, 12-/14-/16-bit serial input, voltage output, digital-to-analog converters (DACs). They operate from single supply voltages of +4.5 V up to +16.5 V or dual supply voltages from ±4.5 V up to ±16.5 V. Nominal full-scale output range is software selectable from +5 V, +10 V, +10.8 V, ±5 V, ±10 V, or ±10.8 V. Integrated output amplifiers, reference buffers, and proprietary power-up/power-down control circuitry are also provided.

The parts offer guaranteed monotonicity, integral nonlinearity (INL) of ±16 LSB maximum, low noise, 10 µs typical settling time, and an on-chip +2.5 V reference.

The AD5724R/AD5734R/AD5754R use a serial interface that operates at clock rates up to 30 MHz and are compatible with DSP and microcontroller interface standards. Double buffering allows the simultaneous updating of all DACs. The input coding is user-selectable twos complement or offset binary for a bipolar output (depending on the state of Pin BIN/ binary for a unipolar output. The asynchronous clear function clears all DAC registers to a user-selectable zero-scale or midscale output. The parts are available in a 24-lead TSSOP and offer guaranteed specifications over the −40°C to +85°C industrial temperature range.

2sCOMP

) and straight

iCMOS®, Reg. U.S. Patent and Trademark Office.

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

Table 1. Pin Compatible Devices

Part Number Description

AD5724/AD5734/AD5754

AD5722/AD5732/AD5752

AD5722R/AD5732R/AD5752R

AD5724R/AD5734R/AD5754R without internal reference.

Complete, dual, 12-/14-/16-bit, serial input, unipolar/bipolar, voltage output DACs.

AD5722/AD5732/AD5752 with internal reference.

Page 2

AD5724R/AD5734R/AD5754R

Features .............................................................................................. 1

Applications ....................................................................................... 1 

General Description ......................................................................... 1

Revision History ............................................................................... 2

Functional Block Diagram .............................................................. 3

Specifications ..................................................................................... 4

AC Performance Characteristics ................................................ 6

Timing Characteristics ................................................................ 6

Timing Diagrams .......................................................................... 7

Absolute Maximum Ratings ............................................................ 9

ESD Caution .................................................................................. 9

Pin Configuration and Function Descriptions ........................... 10

Typical Performance Characteristics ........................................... 11

Terminology .................................................................................... 18

Theory of Operation ...................................................................... 20

Architecture ................................................................................. 20

Serial Interface ............................................................................ 20

Load DAC (

Asynchronous Clear (

Configuring the AD5724R/AD5734R/AD5754R .................. 22

LDAC

) ..................................................................... 22

CLR

) ....................................................... 22

Transfer Function ....................................................................... 22

Input Register .............................................................................. 26

DAC Register .............................................................................. 27

Output Range Select Register ................................................... 27

Control Register ......................................................................... 28

Power Control Register ............................................................. 29

Design Features ............................................................................... 30

Analog Output Control ............................................................. 30

Power-Down Mode .................................................................... 30

Overcurrent Protection ............................................................. 30

Thermal Shutdown .................................................................... 30

Internal Reference ...................................................................... 30

Applications Information .............................................................. 31

+5 V/±5 V Operation ................................................................ 31

Layout Guidelines....................................................................... 31

Galvanically Isolated Interface ................................................. 31

Microprocessor Interfacing ....................................................... 31

Outline Dimensions ....................................................................... 32

Ordering Guide .......................................................................... 32

REVISION HISTORY

5/10—Rev. A to Rev. B

Changes to Table 5 ............................................................................ 9

Changes to Table 6 .......................................................................... 10

3/09—Rev. 0 to Rev. A

Added AD5724R Model ............................................... Throughout

Added 12-Bit Resolution .............................................. Throughout

Changes to Resolution and Integral Nonlinearity (INL)

Parameters (Table 2) ......................................................................... 4

Changes to Endnote 2 (Table 2) ...................................................... 5

Added Endnote 4 (Table 4) ............................................................. 6

Added Figure 8 and Figure 11 ....................................................... 11

Added Figure 39 .............................................................................. 16

Added Ideal Output Voltage to Input Code

Relationship—AD5724R Section ................................................. 25

Added Table 21 ............................................................................... 27

Changes to Ordering Guide .......................................................... 32

1/09—Revision 0: Initial Version

Rev. B | Page 2 of 32

Page 3

AD5724R/AD5734R/AD5754R

FUNCTIONAL BLOCK DIAGRAM

AD5724R/AD5734R/AD5754R

2.5V

REFERENCE

REFIN/REFOUT

REFERENCE

BUFFERS

SDIN SCLK SYNC

SDO

CLR

BIN/2sCOMP

INPUTSHIFT

AND

CONTROL

LOGIC

AD5724R: n = 12-BI T AD5734R: n = 14-BI T AD5754R: n = 16-BI T

GND

INPUT

DAC

LDAC

DAC A

DAC B

DAC C

DAC D

DAC_GND (2) SIG_GND (2)

OUT

06465-001

Figure 1.

Rev. B | Page 3 of 32

Page 4

AD5724R/AD5734R/AD5754R

SPECIFICATIONS

AVDD = 4.5 V1 to 16.5 V, AVSS = −4.5 V1 to −16.5 V or AVSS = 0 V, GND = 0 V, REFIN= +2.5 V external, DVCC = 2.7 V to 5.5 V, R

= 2 kΩ, C

LOAD

Table 2.

Parameter Min Typ Max Unit Test Conditions/Comments

ACCURACY Outputs unloaded

Resolution

AD5754R 16 Bits AD5734R 14 Bits AD5724R 12 Bits

Total Unadjusted Error (TUE) −0.1 +0.1 % FSR

Integral Nonlinearity (INL)2

AD5754R −16 +16 LSB AD5734R −4 +4 LSB

AD5724R −1 +1 LSB Differential Nonlinearity (DNL) −1 +1 LSB All models, guaranteed monotonic Bipolar Zero Error −6 +6 mV TA = 25°C, error at other temperatures obtained using

Bipolar Zero TC3 ±4 ppm FSR/°C Zero-Scale Error −6 +6 mV TA = 25°C, error at other temperatures obtained using

Zero-Scale TC Offset Error −6 +6 mV TA = 25°C, error at other temperatures obtained using

Offset Error TC Gain Error −0.025 +0.025 % FSR ±10 V range, TA = 25°C, error at other temperatures

Gain Error

Gain TC DC Crosstalk

REFERENCE INPUT/OUTPUT

Reference Input

Reference Input Voltage 2.5 V ±1% for specified performance DC Input Impedance 1 5 MΩ Input Current −2 ±0.5 +2 μA Reference Range 2 3 V

Reference Output

Output Voltage 2.497 2.501 V TA = 25°C Reference TC

2.2 10 ppm/°C TA = −40°C to +85°C Output Noise (0.1 Hz to 10 Hz)3 Noise Spectral Density

OUTPUT CHARACTERISTICS

Output Voltage Range −10.8 +10.8 V AVDD/AVSS = ±11.7 V min, REFIN = +2.5 V

−12 +12 V AVDD/AVSS = ±12.9 V min, REFIN = +3 V Headroom 0.5 0.9 V Output Voltage TC ±4 ppm FSR/°C Output Voltage Drift vs. Time ±12 ppm FSR/500 hr ±15 ppm FSR/1000 hr Short-Circuit Current 20 mA Load 2 kΩ For specified performance Capacitive Load Stability 4000 pF DC Output Impedance 0.5 Ω

= 200 pF, all specifications T

LOAD

MIN

to T

, unless otherwise noted.

MAX

bipolar zero TC

zero-scale TC

±4 ppm FSR/°C

offset error TC

±4 ppm FSR/°C

obtained using gain TC

−0.065 0 +10 V and +5 V ranges, T

temperatures obtained using gain TC

0 +0.08 ±5 V range, T

= 25°C, error at other temperatures

obtained using gain TC

3, 4

1.8 5 ppm/°C TA = 0°C to 85°C

±4 ppm FSR/°C 120 μV

5 μV p-p

75 nV/√Hz @ 10 kHz

Rev. B | Page 4 of 32

= 25°C, error at other

Page 5

AD5724R/AD5734R/AD5754R

Parameter Min Typ Max Unit Test Conditions/Comments

DIGITAL INPUTS

Input High Voltage, VIH 2 V Input Low Voltage, VIL 0.8 V Input Current ±1 μA Per pin Pin Capacitance 5 pF Per pin

DIGITAL OUTPUTS (SDO)

Output Low Voltage, VOL 0.4 V DVCC = 5 V ± 10%, sinking 200 μA Output High Voltage, VOH DVCC − 1 V DV Output Low Voltage, VOL 0.4 V DVCC = 2.7 V to 3.6 V, sinking 200 μA Output High Voltage, VOH DVCC − 0.5 V DVCC = 2.7 V to 3.6 V, sourcing 200 μA High Impedance Leakage Current ±1 μA High Impedance Output

Capacitance

POWER REQUIREMENTS

AVDD 4.5 16.5 V AVSS −4.5 −16.5 V DVCC 2.7 5.5 V Power Supply Sensitivity

∆V

AIDD 2.5 mA/channel Outputs unloaded

1.75 mA/channel AVSS = 0 V, outputs unloaded AISS 2.2 mA/channel Outputs unloaded DICC 0.5 3 μA VIH = DVCC, VIL = GND, 0.5 μA typical Power Dissipation 310 mW ±16.5 V operation, outputs unloaded 115 mW +16.5 V operation, outputs unloaded Power-Down Currents All DAC channels and internal reference

AIDD 40 μA AISS 40 μA DICC 300 nA

For specified performance, headroom requirement is 0.9 V.

INL is the relative accuracy. It is measured from Code 512, Code 128, Code 32 for the AD5754R, AD5734R, AD5724R respectively.

Guaranteed by characterization; not production tested.

The on-chip reference is production trimmed and tested at 25°C and 85°C. It is characterized from −40°C to +85°C.

DVCC = 2.7 V to 5.5 V, JEDEC compliant

= 5 V ± 10%, sourcing 200 μA

5 pF

/∆ΑVDD −65 dB 200 mV sine wave superimposed on AVSS/AVDD @

OUT

50 Hz/60 Hz

powered-down

Rev. B | Page 5 of 32

Page 6

AD5724R/AD5734R/AD5754R

AC PERFORMANCE CHARACTERISTICS

AVDD = 4.5 V1 to 16.5 V, AVSS = −4.5 V1 to −16.5 V or 0 V, GND = 0 V, REFIN= 2.5 V external, DVCC = 2.7 V to 5.5 V, R C

= 200 pF, all specifications T

LOAD

MIN

to T

, unless otherwise noted.

MAX

Table 3.

Parameter2 Min Typ Max Unit Test Conditions/Comments

DYNAMIC PERFORMANCE

Output Voltage Settling Time 10 12 μs 20 V step to ±0.03 % FSR

7.5 8.5 μs 10 V step to ±0.03 % FSR 5 μs 512 LSB step settling (16-bit resolution)

Slew Rate 3.5 V/μs Digital-to-Analog Glitch Energy 13 nV-sec Glitch Impulse Peak Amplitude 35 mV Digital Crosstalk 10 nV-sec DAC-to-DAC Crosstalk 10 nV-sec Digital Feedthrough 0.6 nV-sec Output Noise

0.1 Hz to 10 Hz Bandwidth 15 μV p-p 0x8000 DAC code 100 kHz Bandwidth 80 μV rms

Output Noise Spectral Density 320 nV/√Hz Measured at 10 kHz, 0x8000 DAC code

For specified performance, headroom requirement is 0.9 V.

Guaranteed by design and characterization; not production tested.

LOAD

= 2 kΩ,

TIMING CHARACTERISTICS

AVDD = 4.5 V to 16.5 V, AVSS = −4.5 V to −16.5 V or 0 V, GND = 0 V, REFIN = 2.5 V external, DVCC = 2.7 V to 5.5 V, R C

= 200 pF, all specifications are T

LOAD

Table 4.

1, 2, 3

Parameter

33 ns min SCLK cycle time

Limit at T

t2 13 ns min SCLK high time t3 13 ns min SCLK low time t4 13 ns min

t5 13 ns min t6 100 ns min t7 5 ns min Data setup time

t8 0 ns min Data hold time t9 20 ns min

t10 20 ns min t11 20 ns min t12 10 μs typ DAC output settling time t13 20 ns min t14 2.5 μs max

40 ns max SCLK rising edge to SDO valid (C

13 ns min

t17 200 ns min

Guaranteed by characterization; not production tested.

All input signals are specified with tR = tF = 5 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V.

See Figure 2, Figure 3, and Figure 4.

To accommodate t16, in readback and daisy-chain modes the SCLK cycle time must be increased to 90 ns.

Daisy-chain and readback mode.

= capacitive load on SDO output.

L SDO

MIN

, T

MIN

MAX

to T

, unless otherwise noted.

MAX

Unit Description

falling edge to SCLK falling edge setup time

SYNC SCLK falling edge to SYNC Minimum SYNC

falling edge to SYNC falling edge

LDAC

rising edge to LDAC falling edge

SYNC

pulse width low

LDAC

pulse width low

CLR

pulse activation time

CLR

rising edge to SCLK falling edge

SYNC

Minimum SYNC

rising edge

high time (write mode)

= 15 pF)

L SDO

high time (readback/daisy-chain mode)

LOAD

= 2 kΩ,

Rev. B | Page 6 of 32

Page 7

AD5724R/AD5734R/AD5754R

TIMING DIAGRAMS

SCLK

SYNC

SDIN

LDAC

OUT

CLR

OUT

DB23

4221

DB0

06465-002

Figure 2. Serial Interface Timing Diagram

SCLK

SYNC

SDIN

SDO

LDAC

INPUTWORDFORDACN-1INPUTWORD FOR DACN

DB23

INPUT WORD F OR DAC NUNDEFINED

8442

DB0

0BD32BD0BD32BD

06465-003

Figure 3. Daisy-Chain Timing Diagram

Rev. B | Page 7 of 32

Page 8

AD5724R/AD5734R/AD5754R

SCLK

SYNC

4242

SDIN

SDO

UNDEFINED

Figure 4. Readback Timing Diagram

NOP CONDITIONINPUT WORD SPECIFIES

SELECTED REGISTER DATA

CLOCKED OUT

0BD32BD0BD32BD

06465-004

Rev. B | Page 8 of 32

Page 9

AD5724R/AD5734R/AD5754R

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted. Transient currents of up to 100 mA do not cause SCR latch-up.

Table 5.

Parameter Rating

AVDD to GND −0.3 V to +17 V AVSS to GND +0.3 V to −17 V DVCC to GND −0.3 V to +7 V Digital Inputs to GND

Digital Outputs to GND

REFIN/REFOUT to GND −0.3 V to +5 V V

x to GND AVSS to AVDD

OUT

DAC_GND to GND −0.3 V to +0.3 V SIG_GND to GND −0.3 V to +0.3 V Operating Temperature Range, TA

Industrial −40°C to +85°C Storage Temperature Range −65°C to +150°C Junction Temperature, TJ max 150°C 24-Lead TSSOP Package

θJA Thermal Impedance 42°C/W

θJC Thermal Impedance 9°C/W Power Dissipation (TJ max – TA)/θJA Lead Temperature JEDEC industry standard

Soldering J-STD-020 ESD (Human Body Model) 3.5 kV

−0.3 V to DV (whichever is less)

+ 0.3 V or 7 V

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

Rev. B | Page 9 of 32

Page 10

AD5724R/AD5734R/AD5754R

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

AD5724R/

OUT

BIN/2sCOMP

SYNC SCLK

SDIN

LDAC

NOTES

1. NC = NO CONNECT

2. IT IS RE COMMENDED THAT THE EXPOSED PAD BE THERMALLY CONNECTED TO A COPPER PLANE FOR ENHANCED THERMA L PERFORMANCE.

CLR

5 6 7 8

9 10 11 12

AD5734R/

AD5754R

TOP VIEW

(Not to Scale)

Figure 5. Pin Configuration

Table 6. Pin Function Descriptions

Pin No. Mnemonic Description

1 AVSS

Negative Analog Supply Pin. Voltage range is from –4.5 V to –16.5 V. This pin can be connected to 0 V if

output ranges are unipolar. 2, 6, 12, 13 NC No Connect. Do not connect to these pins. 3 V 4 V 5

A Analog Output Voltage of DAC A. The output amplifier is capable of directly driving a 2 kΩ, 4000 pF load.

OUT

B Analog Output Voltage of DAC B. The output amplifier is capable of directly driving a 2 kΩ, 4000 pF load.

OUT

BIN/2sCOMP

This pin determines the DAC coding for a bipolar output range. This pin should be hardwired to either DV

or GND. When hardwired to DV

, input coding is offset binary. When hardwired to GND, input coding is twos

complement. (For unipolar output ranges, coding is always straight binary.) 7

Active Low Input. This is the frame synchronization signal for the serial interface. While SYNC is low, data is

SYNC

transferred on the falling edge of SCLK. Data is latched on the rising edge of SYNC. 8 SCLK

Serial Clock Input. Data is clocked into the shift register on the falling edge of SCLK. This operates at clock

speeds up to 30 MHz. 9 SDIN Serial Data Input. Data must be valid on the falling edge of SCLK. 10

LDAC

Load DAC, Logic Input. This is used to update the DAC registers and, consequently, the analog output. When

tied permanently low, the addressed DAC register is updated on the rising edge of SYNC

during the write cycle, the DAC input register is updated, but the output update is held off until the falling

CLR

edge of LDAC

The LDAC

Active Low Input. Asserting this pin sets the DAC registers to zero-scale code or midscale code (user selectable).

. In this mode, all analog outputs can be updated simultaneously on the falling edge of LDAC.

pin should not be left unconnected.

14 DVCC Digital Supply Pin. Voltage range is from 2.7 V to 5.5 V. 15 GND Ground Reference Pin. 16 SDO

Serial Data Output. Used to clock data from the serial register in daisy-chain or readback mode. Data is

clocked out on the rising edge of SCLK and is valid on the falling edge of SCLK. 17 REFIN/REFOUT

External Reference Voltage Input and Internal Reference Voltage Output. Reference input range is 2 V to 3 V.

REFIN = 2.5 V for specified performance. REFOUT = 2.5 V ± 2 mV @ 25°C. 18, 19 DAC_GND Ground reference pins for the four digital-to-analog converters. 20, 21 SIG_GND Ground reference pins for the four output amplifiers. 22 V 23 V

D Analog Output Voltage of DAC D. The output amplifier is capable of directly driving a 2 kΩ, 4000 pF load.

OUT

C Analog Output Voltage of DAC C. The output amplifier is capable of directly driving a 2 kΩ, 4000 pF load.

OUT

24 AVDD Positive Analog Supply Pin. Voltage range is from 4.5 V to 16.5 V. 25 (EPAD)

Exposed Paddle (EPAD)

The exposed paddle should be connected to the potential of the AV

electrically unconnected. It is recommended that the paddle be thermally connected to a copper plane for

enhanced thermal performance.

OUT

SIG_GND SIG_GND

20 19

DAC_GND

REFIN/REFOUT

SDO

GND DV

06465-005

. If LDAC is held high

pin or, alternatively, it can be left

Rev. B | Page 10 of 32

Page 11

AD5724R/AD5734R/AD5754R

TYPICAL PERFORMANCE CHARACTERISTICS

AVDD/AVSS = +12V/0V, RANGE = +10V AV

/AVSS = ±12V, RANGE = ±10V

/AVSS = ±6.5V, RANGE = ±5V

/AVSS = +6.5V/0V, RANGE = +5V

0.6

0.4

0.2

–2

INL ERROR (LSB)

–4

–6

–8

0 10,000 20,000 30,000 40,000 50,000 60,000

CODE

Figure 6. AD5754R Integral Nonlinearity Error vs. Code

1.5

1.0

0.5

–0.5

INL ERROR (LSB)

–1.0

–1.5

–2.0

0 2000 4000 6000 8000 10,000 12,000 14,000 16,000

AVDD/AVSS = +12V/0V, RANGE = +10V AV

/AVSS = ±12V, RANGE = ±10V

/AVSS = ±6.5V, RANGE = ±5V

/AVSS = +6.5V/0V, RANGE = +5V

CODE

Figure 7. AD5734R Integral Nonlinearity Error vs. Code

–0.2

DNL ERROR (LS B)

–0.4

AVDD/AVSS = +12V/0V, RANGE = +10V

–0.6

/AVSS = ±12V, RANGE = ±10 V

/AVSS = ±6.5V, RANGE = ±5V

/AVSS = +6.5V/0V, RANGE = +5V

–0.8

6465-013

0 10,000 20,000 30,000 40,000 50,000 60,000

CODE

06465-016

Figure 9. AD5754R Differential Nonlinearity Error vs. Code

0.15

0.10

0.05

–0.05

DNL ERROR (LSB)

–0.10

AVDD/AVSS = +12V/0V, RANGE = +10V

–0.15

/AVSS = ±12V, RANGE = ±10V

/AVSS = ±6.5V, RANGE = ±5V

/AVSS = +6.5V/0V, RANGE = +5V

–0.20

6465-014

0 2000 4000 6000 8000 10,000 12,000 14,000 16,000

CODE

06465-017

Figure 10. AD5734R Differential Nonlinearity Error vs. Code

0.3

0.2

0.1

–0.1

–0.2

INL ERROR (LSB)

–0.3

–0.4

–0.5

0 500 1000 1500 2000 2500 3000 3500 4000

AVDD/AVSS = +12V/0V, RANGE = +10V AV

/AVSS = ±12V, RANGE = ±10 V

/AVSS = ±6.5V, RANGE = ±5V

/AVSS = +6.5V/0V, RANGE = +5V

CODE

Figure 8. AD5724R Integral Nonlinearity Error vs. Code

06465-015

Rev. B | Page 11 of 32

0.04 AVDD/AVSS = +12V/0V, RANGE = +10V

/AVSS = ±12V, RANGE = ±10V

/AVSS = ±6.5V, RANGE = ±5V

/AVSS = +6.5V/0V, RANGE = +5V

0 500 1000 1500 2000 2500 3000 3500 4000

CODE

DNL ERROR (LSB)

0.03

0.02

0.01

–0.01

–0.02

–0.03

–0.04

–0.05

Figure 11. AD5724R Differential Nonlinearity Error vs. Code

06465-018

Page 12

AD5724R/AD5734R/AD5754R

MAX INL ±10V

–2

INL ERROR (LSB)

–4

–6

–8

–40 –20 0 20 40 60 80

TEMPE R ATURE ( °C)

MAX INL ±5V MIN INL ±10V MIN INL ±5V MAX INL + 10V MIN INL +10V MAX INL +5V MIN INL +5V

Figure 12. AD5754R Integral Nonlinearity Error vs. Temperature

06465-044

–2

INL ERROR (LSB)

–4

–6

–8

–10

5.5 8.56.5 7.5 10.5 11.59.5 12.513.514.515.516.5 SUPPLY VOLTAGE (V)

BIPOLAR 5V M IN UNIPOLAR 5V M IN BIPOLAR 5V M AX UNIPOLAR 5V M AX

Figure 15. AD5754R Integral Nonlinearity Error vs. Supply Voltage

06465-050

0.1

–0.1

–0.2

–0.3

DNL ERROR (LSB)

–0.4

–0.5

–0.6

–40 –20 0 20 40 60 80

TEMPE R ATURE ( °C)

MAX DNL ±10V MAX DNL ±5V MIN DNL ±10V MIN DNL ±5V MAX DNL +10V MIN DNL +10 V MAX DNL +5V MIN DNL +5V

Figure 13. AD5754R Differential Nonlinearity Error vs. Temperature

–2

INL ERROR (LSB)

–4

–6

–8

–10

11.5 12.512.0 13.5 14.013.0 14.5 15.0 15.5 16.0 16.5 SUPPLY VOLT AGE ( V)

BIPOLAR 10V MIN UNIPOLAR 10V M IN BIPOLAR 10V MAX UNIPOLAR 10V M AX

Figure 14. AD5754R Integral Nonlinearity Error vs. Supply Voltage

1.0

0.8

0.6

0.4

0.2

–0.2

DNL ERROR (LSB)

–0.4

–0.6

–0.8 –1.0

11.5 12.512.0 13.5 14.013.0 14.5 15.0 15.5 16.0 16.5

06465-045

SUPPLY VOLTAGE (V)

BIPOLAR 10V M IN UNIPOLAR 10V MIN BIPOLAR 10V M A X UNIPOLAR 10V MAX

06465-033

Figure 16. AD5754R Differential Nonlinearity Error vs. Supply Voltage

1.0

0.8

0.6

0.4

0.2

–0.2

DNL ERROR (LSB)

–0.4

–0.6

–0.8

–1.0

5.5 8.56.5 7.5 10.5 11.59.5 12.5 13.5 14.5 15.5 16.5

06465-032

SUPPLY VOLTAGE (V)

BIPOLAR 5V MIN UNIPOLAR 5V MIN BIPOLAR 5V MAX UNIPOLAR 5V MAX

06465-034

Figure 17. AD5754R Differential Nonlinearity Error vs. Supply Voltage

Rev. B | Page 12 of 32

Page 13

AD5724R/AD5734R/AD5754R

0.02

0.01

–0.01

TUE (%)

–0.02

–0.03

–0.04

11.5 12.512.0 13.5 14.013.0 14.5 15.0 15.5 16.0 16.5 SUPPLY (V)

BIPOLAR 10V M IN UNIPOLAR 10V M IN BIPOLAR 10V M AX UNIPOLAR 10V M AX

Figure 18. AD5754R Total Unadjusted Error vs. Supply Voltage

06465-036

0.8

0.6

0.4

0.2

–0.2

–0.4

–0.6

BIPOLAR ZE RO ERROR (mV)

–0.8

–1.0

–40–200 20406080

±5V RANGE

±10V RANGE

TEMPERATURE (°C)

Figure 21. Bipolar Zero Error vs. Temperature

06465-047

0.04

0.03

0.02

0.01

–0.01

TUE (%)

–0.02

–0.03

–0.04

–0.05

5.5 8.56.5 7.5 10.5 11.59.5 12.5 13.5 14.5 15.5 16.5 SUPPLY (V)

BIPOLAR 5V M IN UNIPOLAR 5V M IN BIPOLAR 5V M AX UNIPOLAR 5V M AX

Figure 19. AD5754R Total Unadjusted Error vs. Supply Voltage

–1

ZERO-SCAL E E RROR (mV)

–2

–3

–40 –20 0 20 40 60 80

+10V

±10V

±5V

TEMPERATURE (°C)

Figure 20. Zero-Scale Error vs. Temperature

0.06 ±5V

0.04

0.02

–0.02

GAIN ER ROR (% FSR)

–0.04

–0.06

–40 –20 0 20 40 60 80

06465-037

±10V

+10V

TEMPERATURE ( ° C)

6465-048

Figure 22. Gain Error vs. Temperature

1000

900 800 700 600 500

(µA)

400

300 200 100

–100

0123456

06465-046

= 3V

LOGIC

DVCC = 5V

(V)

06465-043

Figure 23. Digital Current vs. Logic Input Voltage

Rev. B | Page 13 of 32

Page 14

AD5724R/AD5734R/AD5754R

0.010 ±5V RANGE, CODE = 0xFFFF

±10V RANGE, CODE = 0xFFFF +10V RANGE, CO DE = 0xFFFF +5V RANG E , CODE = 0 xFFFF

0.005 ±5V RANGE, CODE = 0 x0000

±10V RANGE, CODE = 0x0000

–0.005

–0.010

OUTPUT VOLTAGE DELTA (V)

–0.015

–0.020

–25 –20 –15 –10 –5 0 5 10 15 20 25

OUTPUT CURRENT ( mA)

Figure 24. Output Source and Sink Capability

–5

OUTPUT VO LTAGE (V)

–10

–15

–3–11357911

TIME (µs)

Figure 25. Full-Scale Settling Time, ±10 V Range

OUTPUT VOLTAGE (V)

–3–11357911

06465-040

TIME (µs)

06465-024

Figure 27. Full-Scale Settling, +10 V Range

OUTPUT VOLTAGE (V)

–3–11357911

06465-022

TIME (µs)

06465-025

Figure 28. Full-Scale Settling, +5 V Range

–1

–3

OUTPUT VOLTAGE (V)

–5

–7

–3–11357911

TIME (µs)

Figure 26. Full-Scale Settling, ±5 V Range

06465-023

Rev. B | Page 14 of 32

0.020

0.015

0.010

0.005

–0.005

OUTPUT VOLTAGE (V)

–0.010

–0.015

–1012345

±10V RANGE, 0x7FFF TO 0x8000 ±10V RANGE, 0x8000 TO 0x7FFF ±5V RANGE, 0x7FFF TO 0x8000 ±5V RANGE, 0x8000 TO 0x7FFF +10V RANGE, 0x7 FFF TO 0x8000 +10V RANGE, 0x8 000 TO 0x7FFF +5V RANGE, 0x7FFF TO 0x8000 +5V RANGE, 0x8000 TO 0x7FF F

TIME (µs)

± ± ± ±

Figure 29. Digital-to-Analog Glitch Energy

06465-039

Page 15

AD5724R/AD5734R/AD5754R

RANGE = ±5V RANGE = +5V

CH1 5µV M 5s LINE 73.8V

RANGE = +10V RANGE = ±10V

Figure 30. Peak-to-Peak Noise, 0.1 Hz to 10 Hz Bandwidth

RANGE = ±5V RANGE = +5V

CH1 5µV M5s LINE 73.8V

RANGE = +10V RANGE = ±10V

Figure 31. Peak-to-Peak Noise, 100 kHz Bandwidth

0.10

0.08

AVDD/AVSS = ±16.5V AV

= +16.5V, AVSS = 0V

06465-026

CH1 5V CH2 500mV M 200µs CH1 2.9V

06465-028

Figure 33. REFOUT Turn-On Transient

06465-027

CH1 10µV M 5s LINE 1.2V

06465-029

Figure 34. REFOUT Output Noise (100 kHz Bandwidth)

0.06

0.04

0.02

OUTPUT VOLTAGE ( V)

–0.02

–0.04

–0.06

–50–30–101030507090

TIME (µs)

Figure 32. Output Glitch on Power-Up

06465-041

Rev. B | Page 15 of 32

CH1 1µV M 5s LINE 1.2V

Figure 35. REFOUT Output Noise (0.1 Hz to 10 Hz Bandwidth)

06465-030

Page 16

AD5724R/AD5734R/AD5754R

3.0

2.9

2.8

2.7

2.6

2.5

2.4

2.3

REFOUT VOLTAGE (V)

2.2

2.1

2.0 –0.18 –0.13 –0.08 –0.03 0.02 0.07 0.12 0.17

LOAD CURRENT (mA)

Figure 36. REFOUT Voltage vs. Load Current

06465-031

1.0 AVDD/AVSS = +12V/0V, RANGE = +10V

/AVSS = ±12V, RANGE = ± 10V

/AVSS = ±6.5V, RANGE = ±5V

0.5

–0.5

–1.0

TUE (LSB)

–1.5

–2.0

–2.5

/AVSS = +6.5V/0V, RANGE = +5V

0 500 1000 1500 2000 2500 3000 3500 4000

CODE

Figure 39. AD5724R Total Unadjusted Error vs. Code

06465-021

AVDD/AVSS = +12V/0V, RANGE = +10V AV

/AVSS = ±12V, RANGE = ±1 0V

/AVSS = ±6.5V, RANGE = ± 5V

/AVSS = +6.5V/0V, RANGE = +5V

–5

–10

TUE (LSB)

–15

–20

–25

–30

–35

0 1000 2000 3000 4000 5000 6000

CODE

Figure 37. AD5754R Total Unadjusted Error vs. Code

AVDD/AVSS = +12V/0V, RANGE = +10V AV

/AVSS = ±12V, RANGE = ±10V

/AVSS = ±6.5V, RANGE = ±5V

/AVSS = +6.5V/0V, RANGE = +5V

–2

–4

TUE (LSB)

–6

–8

–10

0 2000 4000 6000 8000 10,000 12,000 14,000 16,000

CODE

Figure 38. AD5734R Total Unadjusted Error vs. Code

POPULATION (%)

06465-019

1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 TEMPERATURE COEFFI CIENT (ppm/°C)

06465-051

Figure 40. Reference Output TC (−40°C to +85°C)

POPULATION (%)

06465-020

1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 TEMPERATURE COEFFI CIENT (ppm/°C)

06465-052

Figure 41. Reference Output TC (0°C to 85°C)

Rev. B | Page 16 of 32

Page 17

AD5724R/AD5734R/AD5754R

2.50120 20 DEVICES SHOWN

2.50100

2.50120 20 DEVICES SHOWN

2.50100

2.50080

2.50060

2.50040

2.50020

REFERENCE OUT PUT VOLTAGE (V)

2.50000

2.49980 020–20–40 40 60 80

TEMPERATURE ( °C)

06465-054

2.50080

2.50060

2.50040

2.50020

REFERENCE OUT PUT VOLTAGE (V)

2.50000

2.49980 0 1020304050607080

TEMPERATURE ( °C)

Figure 42. Reference Output Voltage vs. Temperature (−40°C to+ 85°C) Figure 43. Reference Output Voltage vs. Temperature (0°C to 85°C)

06465-053

Rev. B | Page 17 of 32

Page 18

AD5724R/AD5734R/AD5754R

TERMINOLOGY

Relative Accuracy or Integral Nonlinearity (INL)

For the DAC, relative accuracy, or integral nonlinearity, is a measure of the maximum deviation in LSBs from a straight line passing through the endpoints of the DAC transfer function. A typical INL vs. code plot can be seen in Figure 6.

Differential Nonlinearity (DNL)

Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ±1 LSB maximum ensures monotonicity. This DAC is guaranteed monotonic by design. A typical DNL vs. code plot can be seen in Figure 9.

Monotonicity

A DAC is monotonic if the output either increases or remains constant for increasing digital input code. The AD5724R/ AD5734R/AD5754R are monotonic over their full operating temperature range.

Bipolar Zero Error

Bipolar zero error is the deviation of the analog output from the ideal half-scale output of 0 V when the DAC register is loaded with 0x8000 (straight binary coding) or 0x0000 (twos complement coding). A plot of bipolar zero error vs. temperature can be seen in Figure 21.

Bipolar Zero TC

Bipolar zero TC is a measure of the change in the bipolar zero error with a change in temperature. It is expressed in ppm FSR/°C.

Zero-Scale Error/Negative Full-Scale Error

Zero-scale error is the error in the DAC output voltage when 0x0000 (straight binary coding) or 0x8000 (twos complement coding) is loaded to the DAC register. Ideally, the output voltage should be negative full-scale − 1 LSB. A plot of zero-scale error vs. temperature can be seen in Figure 20.

Zero-Scale TC

Zero-scale TC is a measure of the change in zero-scale error with a change in temperature. It is expressed in ppm FSR/°C.

Output Voltage Settling Time

Output voltage settling time is the amount of time it takes for the output to settle to a specified level for a full-scale input change. A plot of full-scale settling time can be seen in Figure 25.

Slew Rate

The slew rate of a device is a limitation in the rate of change of the output voltage. The output slewing speed of a voltage output DAC is usually limited by the slew rate of the amplifier used at its output. Slew rate is measured from 10% to 90% of the output signal and is given in V/µs.

Gain Error

Gain error is a measure of the span error of the DAC. It is the deviation in slope of the DAC transfer characteristic from ideal expressed in % FSR. A plot of gain error vs. temperature can be seen in Figure 22.

Gain TC

Gain TC is a measure of the change in gain error with changes in temperature. It is expressed in ppm FSR/°C.

Tot a l U n ad ju s te d E rr o r ( TU E )

Total unadjusted error is a measure of the output error taking all the various errors into account, namely INL error, offset error, gain error, and output drift over supplies, temperature, and time. TUE is expressed in % FSR.

Digital-to-Analog Glitch Impulse

Digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the DAC register changes state, but the output voltage remains constant. It is normally specified as the area of the glitch in nV-sec and is measured when the digital input code is changed by 1 LSB at the major carry transition (0x7FFF to 0x8000). See Figure 29.

Glitch Impulse Peak Amplitude

Glitch impulse peak amplitude is the peak amplitude of the impulse injected into the analog output when the input code in the DAC register changes state. It is specified as the amplitude of the glitch in millivolts and is measured when the digital input code is changed by 1 LSB at the major carry transition (0x7FFF to 0x8000). See Figure 29.

Digital Feedthrough

Digital feedthrough is a measure of the impulse injected into the analog output of the DAC from the digital inputs of the DAC but is measured when the DAC output is not updated. It is specified in nV-sec and measured with a full-scale code change on the data bus.

Power Supply Sensitivity

Power supply sensitivity indicates how the output of the DAC is affected by changes in the power supply voltage. It is measured by superimposing a 50 Hz/60 Hz, 200 mV p-p sine wave on the supply voltages and measuring the proportion of the sine wave that transfers to the outputs.

Rev. B | Page 18 of 32

Page 19

AD5724R/AD5734R/AD5754R

DC Crosstalk

DC crosstalk is the dc change in the output level of one DAC in response to a change in the output of another DAC. It is measured with a full-scale output change on one DAC while monitoring another DAC. It is expressed in LSBs.

Digital Crosstalk

Digital crosstalk is a measure of the impulse injected into the analog output of one DAC from the digital inputs of another DAC but is measured when the DAC output is not updated. It is specified in nV-sec and measured with a full-scale code change on the data bus.

DAC-to-DAC Crosstalk

DAC-to-DAC crosstalk is the glitch impulse transferred to the output of one DAC due to a digital code change and subsequent output change of another DAC. This includes both digital and analog crosstalk. It is measured by loading one of the DACs with a full-scale code change (all 0s to all 1s and vice versa) with

low and monitoring the output of another DAC.

LDAC

The energy of the glitch is expressed in nV-sec.

Volt age R efe r en c e TC

Voltage reference TC is a measure of the change in the reference output voltage with a change in temperature. The reference TC is calculated using the box method, which defines the TC as the maximum change in the reference output over a given temperature range expressed in ppm/°C as follows;

⎡

⎢ ⎢

REFnom

⎣

−

REFminREFmax

TempRangeV

⎤

10×

⎥ ⎥

⎦

where:

is the maximum reference output measured over the

REFmax

total temperature range.

is the minimum reference output measured over the total

REFmin

temperature range.

is the nominal reference output voltage, 2.5 V.

REFnom

Temp R an ge is the specified temperature range, either 0°C to

85°C or −40°C to +85°C.

Rev. B | Page 19 of 32

Page 20

AD5724R/AD5734R/AD5754R

THEORY OF OPERATION

The AD5724R/AD5734R/AD5754R are quad, 12-/14-/16-bit, serial input, unipolar/bipolar, voltage output DACs. They operate from single supply voltages of +4.5 V to +16.5 V or dual supply voltages of ±4.5 V to ±16.5 V. In addition, the parts have software-selectable output ranges of +5 V, +10 V, +10.8 V, ±5 V, ±10 V, and ±10.8 V. Data is written to the AD5724R/AD5734R/ AD5754R in a 24-bit word format via a 3-wire serial interface. The devices also offer an SDO pin to facilitate daisy chaining or readback.

The AD5724R/AD5734R/AD5754R incorporate a power-on reset circuit to ensure that the DAC registers power up loaded with 0x0000. When powered on, the outputs are clamped to 0 V via a low impedance path. The parts also feature on-chip reference and reference buffers.

ARCHITECTURE

The DAC architecture consists of a string DAC followed by an output amplifier. Figure 44 shows a block diagram of the DAC architecture. The reference input is buffered before being applied to the DAC.

REFIN

REF (+)

DAC REGISTER

Figure 44. DAC Architecture Block Diagram

The resistor string structure is shown in Figure 45. It is a string of resistors, each of value R. The code loaded to the DAC register determines the node on the string where the voltage is to be tapped off and fed into the output amplifier. The voltage is tapped off by closing one of the switches connecting the string to the amplifier. Because it is a string of resistors, it is guaranteed monotonic.

RESISTOR

STRING

REF (–)

GND

OUTPUT

RANGE CONTROL

OUT

CONFIGURABLE OUTPUT AMPLIFIER

REFIN

Figure 45. Resistor String Structure

TO OUT P U T AMPLIFIER

06465-007

Output Amplifiers

The output amplifiers are capable of generating both unipolar and bipolar output voltages. They are capable of driving a load of 2 kΩ in parallel with 4000 pF to GND. The source and sink capabilities of the output amplifiers can be seen in Figure 24. The slew rate is 3.5 V/µs with a full-scale settling time of 10 µs.

Reference Buffers

06465-006

The AD5724R/AD5734R/AD5754R can operate with either an external or internal reference. The reference input has an input range of 2 V to 3 V with 2.5 V for specified performance. This input voltage is then buffered before it is applied to the DAC cores.

SERIAL INTERFACE

The AD5724R/AD5734R/AD5754R are controlled over a versatile 3-wire serial interface that operates at clock rates up to 30 MHz. It is compatible with SPI, QSPI™, MICROWIRE™, and DSP standards.

Input Shift Register

The input shift register is 24 bits wide. Data is loaded into the device MSB first as a 24-bit word under the control of a serial clock input, SCLK. The input register consists of a read/write bit, three register select bits, three DAC address bits, and 16 data bits. The timing diagram for this operation is shown in Figure 2.

Rev. B | Page 20 of 32

Page 21

AD5724R/AD5734R/AD5754R

Standalone Operation

The serial interface works with both a continuous and a noncontinuous serial clock. A continuous SCLK source can

SYNC

only be used if

is held low for the correct number of

clock cycles. In gated clock mode, a burst clock containing the

SYNC

exact number of clock cycles must be used, and

must be

taken high after the final clock to latch the data. The first falling

SYNC

edge of edges must be applied to SCLK before again. If

starts the write cycle. Exactly 24 falling clock

SYNC

is brought high

SYNC

is brought high before the 24th falling SCLK edge, the data written is invalid. If more than 24 falling SCLK edges are applied before

SYNC

is brought high, the input data

is also invalid. The input register addressed is updated on the

SYNC

rising edge of SYNC

must be brought low again. After the end of the serial

. For another serial transfer to take place,

data transfer, data is automatically transferred from the input shift register to the addressed register.

When the data has been transferred into the chosen register of the addressed DAC, all DAC registers and outputs can be

LDAC

updated by taking

68HC11

MISO

ADDITIONAL P INS OMIT TED FOR CLARITY.

Figure 46. Daisy Chaining the AD5724R/AD5734R/AD5754R

low while

MOSI

SCK

PC7 PC6

SYNC

SDIN SCLK SYNC LDAC

SCLK SYNC LDAC

is high.

AD5724R/ AD5734R/

AD5754R*

SDO

SDIN

AD5724R/ AD5734R/

AD5754R*

SDO

SDIN

AD5724R/ AD5734R/

AD5754R*

SDO

06465-008

Daisy-Chain Operation

For systems that contain several devices, the SDO pin can be used to daisy-chain several devices together. Daisy-chain mode can be useful in system diagnostics and in reducing the number

SYNC

of serial interface lines. The first falling edge of

starts the

write cycle. SCLK is continuously applied to the input shift

SYNC

is low. If more than 24 clock pulses are applied, the data ripples out of the shift register and appears on the SDO line. This data is clocked out on the rising edge of SCLK and is valid on the falling edge. By connecting the SDO of the first device to the SDIN input of the next device in the chain, a multidevice interface is constructed. Each device in the system requires 24 clock pulses. Therefore, the total number of clock cycles must equal 24 × N, where N is the total number of AD5724R/AD5734R/AD5754R devices in the chain. When the

SYNC

serial transfer to all devices is complete,

is taken high. This latches the input data in each device in the daisy chain and prevents any further data from being clocked into the input shift register. The serial clock can be a continuous or gated clock.

SYNC

A continuous SCLK source can only be used if

is held low for the correct number of clock cycles. In gated clock mode, a burst clock containing the exact number of clock cycles must be used, and

SYNC

must be taken high after the final clock to

latch the data.

Readback Operation

Readback mode is invoked by setting the R/W bit to 1 in the write operation to the serial input shift register. (If the SDO output is disabled via the SDO disable bit in the control register, it is automatically enabled for the duration of the read operation,

after which it is disabled again.) With R/

set to 1, Bit A2 to Bit A0 in association with Bit REG2 to Bit REG0 select the register to be read. The remaining data bits in the write sequence are don’t care bits. During the next SPI write, the data appearing on the SDO output contains the data from the previously addressed register. For a read of a single register, the NOP command can be used in clocking out the data from the selected register on SDO. The readback diagram in shows the readback

Figure 4 sequence. For example, to read back the DAC register of Channel A, the following sequence should be implemented:

Write 0x800000 to the AD5724R/AD5734R/AD5754R

input register. This configures the part for read mode with the DAC register of Channel A selected. Note that all the data bits, DB15 to DB0, are don’t care bits.

Follow this with a second write, a NOP condition, 0x180000.

During this write, the data from the register is clocked out on the SDO line.

Rev. B | Page 21 of 32

Page 22

AD5724R/AD5734R/AD5754R

LOAD DAC (LDAC) CONFIGURING THE AD5724R/AD5734R/AD5754R

After data has been transferred into the input register of the DACs, there are two ways to update the DAC registers and DAC outputs. Depending on the status of both

SYNC

and

LDAC

, one of two update modes is selected: individual DAC updating or simultaneous updating of all DACs.

OUTPUT

AMPLIFIER

REFIN

LDAC

SCLK

SYNC

SDIN

Figure 47. Simplified Diagram of Input Loading Circuitry for One DAC

12-/14-/16-BIT

DAC

INPUT

INTERFACE

LOGIC

SDO

OUT

06465-009

Individual DAC Updating

In this mode,

LDAC

is held low while data is clocked into the

input shift register. The addressed DAC output is updated on

SYNC

the rising edge of

Simultaneous Updating of All DACs

LDAC

In this mode,

is held high while data is clocked into the

input shift register. All DAC outputs are asynchronously updated

LDAC

by taking

low after

update now occurs on the falling edge of

SYNC

has been taken high. The

LDAC

ASYNCHRONOUS CLEAR (CLR)

CLR

is an active low clear that allows the outputs to be cleared to either zero-scale code or midscale code. The clear code value is user selectable via the CLR select bit of the control register

CLR

(see the section). It is necessary to keep Control Register low for a minimum amount of time to complete the operation

CLR

(see ). When the Figure 2

signal is returned high, the output remains at the cleared value until a new value is programmed. The outputs cannot be updated with a new value while the pin is low. A clear operation can also be performed via the clear command in the control register.

CLR

When the power supplies are applied to the AD5724R/ AD5734R/ AD5754R, the power-on reset circuit ensures that all registers default to 0. This places all channels and the internal reference in power-down mode. The first communication to the AD5724R/AD5734R/AD5754R should be to set the required output range on all channels (the default range is the 5 V unipolar range) by writing to the output range select register. The user should then write to the power-control register to power-on the required channels and the internal reference, if required. If an external reference source is being used, the internal reference must remain in power-down mode. To program an output value on a channel, that channel must first be powered up; any writes to a channel while it is in power-down mode are ignored. The AD5724R/AD5734R/AD5754R operate with a wide power supply range. It is important that the power supply applied to the parts provide adequate headroom to support the chosen output ranges.

TRANSFER FUNCTION

Tabl e 8 to Ta b le 1 6 show the relationships of the ideal input code to output voltage for the AD5754R, AD5734R, and AD5724R for all output voltage ranges. For unipolar output ranges, the data coding is straight binary. For bipolar output ranges, the data coding is user selectable via the BIN/

2sCOMP

either offset binary or twos complement.

For a unipolar output range, the output voltage expression is given by

⎡

OUT

REFIN

×=

GainVV

⎤

⎢

⎥

⎣

⎦

For a bipolar output range, the output voltage expression is given by

⎡

OUT

×=

GainVV

REFIN

⎤

−

⎢

⎥

⎣

⎦

where:

D is the decimal equivalent of the code loaded to the DAC. N is the bit resolution of the DAC. V

is the reference voltage applied at the REFIN pin.

REFIN

Gain is an internal gain the value of which depends on the

output range selected by the user as shown in Tabl e 7.

Table 7. Internal Gain Values

Output Range (V) Gain Value

+5 2 +10 4 +10.8 4.32 ±5 4 ±10 8 ±10.8 8.64

pin and can be

VGain

REFIN

Rev. B | Page 22 of 32

Page 23

AD5724R/AD5734R/AD5754R

Ideal Output Voltage to Input Code Relationship—AD5754R

Table 8. Bipolar Output, Offset Binary Coding

Digital Input Analog Output

MSB LSB ±5 V Output Range ±10 V Output Range ±10.8 V Output Range

1111 1111 1111 1111 +2 × REFIN × (32,767/32,768) +4 × REFIN × (32,767/32,768) +4.32 × REFIN × (32,767/32,768) 1111 1111 1111 1110 +2 × REFIN × (32,766/32,768) +4 × REFIN × (32,766/32,768) +4.32 × REFIN × (32,766/32,768) … … … … … … … 1000 0000 0000 0001 +2 × REFIN × (1/32,768) +4 × REFIN × (1/32,768) +4.32 × REFIN × (1/32,768) 1000 0000 0000 0000 0 V 0 V 0 V 0111 1111 1111 1111 −2 × REFIN × (1/32,768) −4 × REFIN × (1/32,768) −4.32 × REFIN × (32,766/32,768) … … … … … … … 0000 0000 0000 0001 −2 × REFIN × (32,766/32,768) −4 × REFIN × (32,766/32,768) −4.32 × REFIN × (32,766/32,768) 0000 0000 0000 0000 −2 × REFIN × (32,767/32,768) −4 × REFIN × (32,767/32,768) −4.32 × REFIN × (32,767/32,768)

Table 9. Bipolar Output, Twos Complement Coding

Digital Input Analog Output

MSB LSB ±5 V Output Range ±10 V Output Range ±10.8 V Output Range

0111 1111 1111 1111 +2 × REFIN × (32,767/32,768) +4 × REFIN × (32,767/32,768) +4.32 × REFIN × (32,767/32,768) 0111 1111 1111 1110 +2 × REFIN × (32,766/32,768) +4 × REFIN × (32,766/32,768) +4.32 × REFIN × (32,766/32,768) … … … … … … … 0000 0000 0000 0001 +2 × REFIN × (1/32,768) +4 × REFIN × (1/32,768) +4.32 × REFIN × (1/32,768) 0000 0000 0000 0000 0 V 0 V 0 V 1111 1111 1111 1111 −2 × REFIN × (1/32,768) −4 × REFIN × (1/32,768) −4.32 × REFIN × (1/32,768) … … … … … … … 1000 0000 0000 0001 −2 × REFIN × (32,766/32,768) −4 × REFIN × (32,766/32,768) −4.32 × REFIN × (32,766/32,768) 1000 0000 0000 0000 −2 × REFIN × (32,767/32,768) −4 × REFIN × (32,767/32,768) −4.32 × REFIN × (32,767/32,768)

Table 10. Unipolar Output, Straight Binary Coding

Digital Input Analog Output

MSB LSB +5 V Output Range +10 V Output Range +10.8 V Output Range

1111 1111 1111 1111 +2 × REFIN × (65,535/65,536) +4 × REFIN × (65,535/65,536) +4.32 × REFIN × (65,535/65,536) 1111 1111 1111 1110 +2 × REFIN × (65,534/65,536) +4 × REFIN × (65,534/65,536) +4.32 × REFIN × (65,534/65,536) … … … … … … … 1000 0000 0000 0001 +2 × REFIN × (32,769/65,536) +4 × REFIN × (32,769/65,536) +4.32 × REFIN × (32,769/65,536) 1000 0000 0000 0000 +2 × REFIN × (32,768/65,536) +4 × REFIN × (32,768/65,536) +4.32 × REFIN × (32,768/65,536) 0111 1111 1111 1111 +2 × REFIN × (32,767/65,536) +4 × REFIN × (32,767/65,536) +4.32 × REFIN × (32,767/65,536) … … … … … … … 0000 0000 0000 0001 +2 × REFIN × (1/65,536) +4 × REFIN × (1/65,536) +4.32 × REFIN × (1/65,536) 0000 0000 0000 0000 0 V 0 V 0 V

Rev. B | Page 23 of 32

Page 24

AD5724R/AD5734R/AD5754R

Ideal Output Voltage to Input Code Relationship—AD5734R

Table 11. Bipolar Output, Offset Binary Coding

Digital Input Analog Output

MSB LSB ±5 V Output Range ±10 V Output Range ±10.8 V Output Range

11 1111 1111 1111 +2 × REFIN × (8191/8192) +4 × REFIN × (8191/8192) +4.32× REFIN × (8191/8192) 11 1111 1111 1110 +2 × REFIN × (8190/8192) +4 × REFIN × (8190/8192) +4.32 × REFIN × (8190/8192) … … … … … … … 10 0000 0000 0001 +2 × REFIN × (1/8192) +4 × REFIN × (1/8192) +4.32 × REFIN × (1/8192) 10 0000 0000 0000 0 V 0 V 0 V 01 1111 1111 1111 −2 × REFIN × (1/8192) −4 × REFIN × (1/8192) −4.32 × REFIN × (1/8192) … … … … … … … 00 0000 0000 0001 −2 × REFIN × (8190/8192) −4 × REFIN × (8190/8192) −4.32 × REFIN × (8190/8192) 00 0000 0000 0000 −2 × REFIN × (8191/8191) −4 × REFIN × (8191/8192) −4.32 × REFIN × (8191/8192)

Table 12. Bipolar Output, Twos Complement Coding

Digital Input Analog Output

MSB LSB ±5 V Output Range ±10 V Output Range ±10.8 V Output Range

01 1111 1111 1111 +2 × REFIN × (8191/8192) +4 × REFIN × (8191/8192) +4.32 × REFIN × (8191/8192) 01 1111 1111 1110 +2 × REFIN × (8190/8192) +4 × REFIN × (8190/8192) +4.32 × REFIN × (8190/8192) … … … … … … … 00 0000 0000 0001 +2 × REFIN × (1/8192) +4 × REFIN × (1/8192) +4.32 × REFIN × (1/8192) 00 0000 0000 0000 0 V 0 V 0 V 11 1111 1111 1111 −2 × REFIN × (1/8192) −4 × REFIN × (1/8192) −4.32 × REFIN × (1/8192) … … … … … … … 10 0000 0000 0001 −2 × REFIN × (8190/8192) −4 × REFIN × (8190/8192) −4.32 × REFIN × (8190/8192) 10 0000 0000 0000 −2 × REFIN × (8191/8192) −4 × REFIN × (8191/8192) −4.32 × REFIN × (8191/8192)

Table 13. Unipolar Output, Straight Binary Coding

Digital Input Analog Output

MSB LSB +5 V Output Range +10 V Output Range +10.8 V Output Range

11 1111 1111 1111 +2 × REFIN × (16,383/16,384) +4 × REFIN × (16,383/16,384) +4.32 × REFIN × (16,383/16,384) 11 1111 1111 1110 +2 × REFIN × (16,382/16,384) +4 × REFIN × (16,382/16,384) +4.32 × REFIN × (16,382/16,384) … … … … … … … 10 0000 0000 0001 +2 × REFIN × (8193/16,384) +4 × REFIN × (8193/16,384) +4.32 × REFIN × (8193/16,384) 10 0000 0000 0000 +2 × REFIN × (8192/16,384) +4 × REFIN × (8192/16,384) +4.32 × REFIN × (8192/16,384) 01 1111 1111 1111 +2 × REFIN × (8191/16,384) +4 × REFIN × (8191/16,384) +4.32 × REFIN × (8191/16,384) … … … … … … … 00 0000 0000 0001 +2 × REFIN × (1/16,384) +4 × REFIN × (1/16,384) +4.32 × REFIN × (1/16,384) 00 0000 0000 0000 0 V 0 V 0 V

Rev. B | Page 24 of 32

Page 25

AD5724R/AD5734R/AD5754R

Ideal Output Voltage to Input Code Relationship—AD5724R

Table 14. Bipolar Output, Offset Binary Coding

Digital Input Analog Output

MSB LSB ±5 V Output Range ±10 V Output Range ±10.8 V Output Range

1111 1111 1111 +2 × REFIN × (2047/2048) +4 × REFIN × (2047/2048) +4.32 × REFIN × (2047/2048) 1111 1111 1110 +2 × REFIN × (2046/2048) +4 × REFIN × (2046/2048) +4.32 × REFIN × (2046/2048) … … … … … … 1000 0000 0001 +2 × REFIN × (1/2048) +4 × REFIN × (1/2048) +4.32 × REFIN × (1/2048) 1000 0000 0000 0 V 0 V 0 V 0111 1111 1111 −2 × REFIN × (1/2048) −4 × REFIN × (1/2048) −4.32 × REFIN × (1/2048) … … … … … … 0000 0000 0001 −2 × REFIN × (2046/2048) −4 × REFIN × (2046/2048) −4.32 × REFIN × (2046/2048) 0000 0000 0000 −2 × REFIN × (2047/2047) −4 × REFIN × (2047/2048) −4.32 × REFIN × (2047/2048)

Table 15. Bipolar Output, Twos Complement Coding

Digital Input Analog Output

MSB LSB ±5 V Output Range ±10 V Output Range ±10.8 V Output Range

0111 1111 1111 +2 × REFIN × (2047/2048) +4 × REFIN × (2047/2048) +4.32 × REFIN × (2047/2048) 0111 1111 1110 +2 × REFIN × (2046/2048) +4 × REFIN × (2046/2048) +4.32 × REFIN × (2046/2048) … … … … … … 0000 0000 0001 +2 × REFIN × (1/2048) +4 × REFIN × (1/2048) +4.32 × REFIN × (1/2048) 0000 0000 0000 0 V 0 V 0 V 1111 1111 1111 −2 × REFIN × (1/2048) −4 × REFIN × (1/2048) −4.32 × REFIN × (1/2048) … … … … … … 1000 0000 0001 −2 × REFIN × (2046/2048) −4 × REFIN × (2046/2048) −4.32 × REFIN × (2046/2048) 1000 0000 0000 −2 × REFIN × (2047/2048) −4 × REFIN × (2047/2048) −4.32 × REFIN × (2047/2048)

Table 16. Unipolar Output, Straight Binary Coding

Digital Input Analog Output

MSB LSB +5 V Output Range +10 V Output Range +10.8 V Output Range

1111 1111 1111 +2 × REFIN × (4095/4096) +4 × REFIN × (4095/4096) +4.32 × REFIN × (4095/4096) 1111 1111 1110 +2 × REFIN × (4094/4096) +4 × REFIN × (4094/4096) +4.32 × REFIN × (4094/4096) … … … … … … 1000 0000 0001 +2 × REFIN × (2049/4096) +4 × REFIN × (2049/4096) +4.32 × REFIN × (2049/4096) 1000 0000 0000 +2 × REFIN × (2048/4096) +4 × REFIN × (2048/4096) +4.32 × REFIN × (2048/4096) 0111 1111 1111 +2 × REFIN × (2047/4096) +4 × REFIN × (2047/4096) +4.32 × REFIN × (2047/4096) … … … … … … 0000 0000 0001 +2 × REFIN × (1/4096) +4 × REFIN × (1/4096) +4.32 × REFIN × (1/4096) 0000 0000 0000 0 V 0 V 0 V

Rev. B | Page 25 of 32

Page 26

AD5724R/AD5734R/AD5754R

INPUT REGISTER

The input register is 24 bits wide and consists of a read/write bit (R/W), a reserved bit (zero) which must always be set to 0, three register select bits (REG1, REG2, REG3), three DAC address bits (A2, A1, A0), and 16 data bits (data). The register data is clocked in MSB first on the SDIN pin. shows the register format, while describes the function of each bit in the register. All registers are read/ write registers.

Table 17. AD5754R Input Register Format

MSB LSB DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 to DB0

Table 18. Input Register Bit Functions

Data Description

R/W REG2, REG1, REG0

0 0 0 DAC register 0 0 1 Output range select register 0 1 0 Power control register 0 1 1 Control register A2, A1, A0 These bits are used to decode the DAC channels

0 0 0 DAC A 0 0 1 DAC B 0 1 0 DAC C 0 1 1 DAC D 1 0 0 All four DACs DB15 to DB0 Data bits

Table 1 7 Tabl e 18

Zero REG2 REG1 REG0 A2 A1 A0 Data

Indicates a read from or a write to the addressed register Used in association with the address bits to determine if a write operation is to the DAC register, output range

select register, power control register, or control register

REG2 REG1 REG0 Function

A2 A1 A0 Channel Address

Rev. B | Page 26 of 32

Page 27

AD5724R/AD5734R/AD5754R

DAC REGISTER

The DAC register is addressed by setting the three REG bits to 000. The DAC address bits select the DAC channel which the data transfer is to take place (see Tab l e 1 8 ). The data bits are in positions DB15 to DB0 for the AD5754R (see Tab l e 19), DB15 to DB2 for the AD5734R (see Tabl e 20 ), and DB15 to DB4 for the AD5724R (see Ta b le 2 1 ).

Table 19. Programming the AD5754R DAC Register

MSB LSB

0 0 0 0 0 DAC address 16-bit DAC data

Table 20. Programming the AD5734R DAC Register

MSB LSB

0 0 0 0 0 DAC address 14-bit DAC data X X

Table 21. Programming the AD5724R DAC Register

MSB LSB

0 0 0 0 0 DAC address 12-bit DAC data X X X X

OUTPUT RANGE SELECT REGISTER

The output range select register is addressed by setting the three REG bits to 001. The DAC address bits select the DAC channel, while the range bits (R2, R1, R0) select the required output range (see Tab l e 22 and Ta ble 2 3).

Zero REG2 REG1 REG0 A2 A1 A0 DB15 to DB0

Zero REG2 REG1 REG0 A2 A1 A0 DB15 to DB2 DB1 DB0

Zero REG2 REG1 REG0 A2 A1 A0 DB15 to DB4 DB3 DB2 DB1 DB0

Table 22. Programming the Required Output Range

MSB LSB

Zero REG2 REG1 REG0 A2 A1 A0 DB15 to DB3 DB2 DB1 DB0

1/0 0 0 0 1 DAC address Don’t care R2 R1 R0

Table 23. Output Range Options

R2 R1 R0 Output Range (V)

0 0 0 +5 0 0 1 +10 0 1 0 +10.8 0 1 1 ±5 1 0 0 ±10 1 0 1 ±10.8

Rev. B | Page 27 of 32

Page 28

AD5724R/AD5734R/AD5754R

CONTROL REGISTER

The control register is addressed by setting the three REG bits to 011. The value written to the address and data bits determines the control function selected. The control register options are shown in Ta ble 2 4 and Tabl e 25 .

Table 24. Programming the Control Register

MSB LSB

Zero REG2 REG1 REG0 A2 A1 A0 DB15 to DB4 DB3 DB2 DB1 DB0

0 0 0 1 1 0 0 0 NOP, data = don’t care 0 0 0 1 1 0 0 1 Don’t care TSD enable Clamp enable CLR select SDO disable 0 0 0 1 1 1 0 0 Clear, data = don’t care 0 0 0 1 1 1 0 1 Load, data = don’t care

Table 25. Control Register Functions

Option Description

NOP No operation instruction used in readback operations. Clear Addressing this function sets the DAC registers to the clear code and updates the outputs. Load Addressing this function updates the DAC registers and, consequently, the DAC outputs. SDO disable Set by the user to disable the SDO output. Cleared by the user to enable the SDO output (default). CLR select See Ta ble 26 for a description of the CLR select operation. Clamp enable

TSD enable

Set by the user to enable the current limit clamp (default). The channel does not power down on detection of overcurrent; the current is clamped at 20 mA. Cleared by the user to disable the current-limit clamp. The channel powers down on detection of overcurrent.

Set by the user to enable the thermal shutdown feature. Cleared by the user to disable the thermal shutdown feature (default).

Table 26. CLR Select Options

Output CLR Value

CLR Select Setting

0 0 V 0 V 1 Midscale Negative full scale

Unipolar Output Range Bipolar Output Range

Rev. B | Page 28 of 32

Page 29

AD5724R/AD5734R/AD5754R

POWER CONTROL REGISTER

The power control register is addressed by setting the three REG bits to 010. This register allows the user to control and determine the power and thermal status of the AD5724R/AD5734R/AD5754R. The power control register options are shown in Tab le 2 7 and Tabl e 28 .

Table 27. Programming the Power Control Register

MSB LSB

Zero REG2 REG1 REG0 A2 A1 A0

0 0 0 1 0 0 0 0 X OCD OCC OCB OCA 0 TSD PU

Table 28. Power Control Register Functions

Option Description

PUA

DAC A power-up. When set, this bit places DAC A in normal operating mode. When cleared, this bit places DAC A in power-down mode (default). If the clamp enable bit of the control register is cleared, DAC A powers down automatically on detection of an

is cleared to reflect this.

PUB

overcurrent, and PU DAC B power-up. When set, this bit places DAC B in normal operating mode. When cleared, this bit places DAC B in power-down

mode (default). If the clamp enable bit of the control register is cleared, DAC B powers down automatically on detection of an

is cleared to reflect this.

PUC

overcurrent, and PU DAC C power-up. When set, this bit places DAC C in normal operating mode. When cleared, this bit places DAC C in power-down

mode (default). If the clamp enable bit of the control register is cleared, DAC C powers down automatically on detection of an

is cleared to reflect this.

PUD

overcurrent, and PU DAC D power-up. When set, this bit places DAC D in normal operating mode. When cleared, this bit places DAC D in power-down

mode (default). If the clamp enable bit of the control register is cleared, DACD powers down automatically on detection of an

is cleared to reflect this.

overcurrent, and PU Reference power-up. When set, this bit places the internal reference in normal operating mode. When cleared, this bit places the

REF

internal reference in power-down mode (default).

TSD

Thermal shutdown alert. Read-only bit. In the event of an overtemperature situation, the four DACs are powered down and this

bit is set. OCA DAC A overcurrent alert. Read-only bit. In the event of an overcurrent situation on DAC A, this bit is set. OCB DAC B overcurrent alert. Read-only bit. In the event of an overcurrent situation on DAC B, this bit is set. OCC DAC C overcurrent alert. Read-only bit. In the event of an overcurrent situation on DAC C, this bit is set. OCD DAC D overcurrent alert. Read-only bit. In the event of an overcurrent situation on DAC D, this bit is set.

DB15 to DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

PUD PUC PUB PUA

REF

Rev. B | Page 29 of 32

Page 30

AD5724R/AD5734R/AD5754R

DESIGN FEATURES

ANALOG OUTPUT CONTROL

In many industrial process control applications, it is vital that the output voltage be controlled during power-up. When the supply voltages change during power-up, the V

x pins are

OUT

clamped to 0 V via a low impedance path (approximately 4 k). To prevent the output amplifiers from being shorted to 0 V during this time, Transmission Gate G1 is also opened (see Figure 48). These conditions are maintained until the power supplies have stabilized and a valid word is written to a DAC register. At this time, G2 opens and G1 closes.

VOLTAGE

MONITOR

AND

CONTROL

Figure 48. Analog Output Control Circuitry

OUT

6465-010

POWER-DOWN MODE

Each DAC channel of the AD5724R/AD5734R/AD5754R can be individually powered down. By default, all channels are in power-down mode. The power status is controlled by the power control register (see Ta ble 2 7 and Tab l e 28 for details). When a channel is in power-down mode its output pin is clamped to ground through a resistance of approximately 4 k and the output of the amplifier is disconnected from the output pin.

OVERCURRENT PROTECTION

Each DAC channel of the AD5724R/AD5734R/AD5754R incorporates individual overcurrent protection. The user has two options for the configuration of the overcurrent protection: constant current clamp or automatic channel power-down. The configuration of the overcurrent protection is selected via the clamp enable bit in the control register.

Constant Current Clamp (Clamp Enable = 1)

If a short circuit occurs in this configuration, the current is clamped at 20 mA. This event is signaled to the user by the setting of the appropriate overcurrent (OC

) bit in the power

control register. Upon removal of the short-circuit fault, the

bit is cleared.

Automatic Channel Power-Down (Clamp Enable = 0)

If a short circuit occurs in this configuration, the shorted channel powers down and its output is clamped to ground via a resistance of approximately 4 k. Also, at this time, the output of the amplifier is disconnected from the output pin. The shortcircuit event is signaled to the user via the overcurrent bits (OC while the power-up bits (PU

) indicate which channels have

powered down. After the fault is rectified, the channels can be powered up again by setting the PU

bits.

THERMAL SHUTDOWN

The AD5724R/AD5734R/AD5754R incorporate a thermal shutdown feature that automatically shuts down the device if the core temperature exceeds approximately 150°C. The thermal shutdown feature is disabled by default and can be enabled via the TSD enable bit of the control register. In the event of a thermal shutdown, the TSD bit of the power control register is set.

INTERNAL REFERENCE

The on-chip voltage reference is powered down by default. If an external voltage reference source is to be used, the internal reference must remain powered down at all times. If the internal reference is to be used as the reference source, it must be powered up via the PU reference voltage is accessible at the REFIN/REFOUT pin for use as a reference source for other devices within the system. If the internal reference is to be used external to the AD5724R/ AD5734R/AD5754R, it must first be buffered.

bit of the power control register. The internal

REF

Rev. B | Page 30 of 32

Page 31

AD5724R/AD5734R/AD5754R

APPLICATIONS INFORMATION

+5 V/±5 V OPERATION

When operating from a single +5 V supply or a dual ±5 V supply, an output range of +5 V or ±5 V is not achievable because sufficient headroom for the output amplifier is not available. In this situation, a reduced reference voltage can be used; for instance, if a 2 V reference produces an output range of +4 V or ±4 V, the 1 V of headroom is more than enough for full operation. A standard value voltage reference of 2.048 V can be used to produce output ranges of +4.096 V and ±4.096 V. Refer to the Typical Performance Characteristics plots for performance data at a range of voltage reference values.

LAYOUT GUIDELINES

In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. Design the printed circuit board on which the AD5724R/AD5734R/AD5754R are mounted so that the analog and digital sections are separated and confined to certain areas of the board. If the AD5724R/AD5734R/ AD5754R are in a system which multiple devices require an AGND-toDGND connection, the connection should be made at one point only. Establish the star ground point as close as possible to the device.

Bypass the AD5724R/AD5734R/AD5754R with an ample supply of a 10 µF capacitor in parallel with a 0.1 µF capacitor on each supply located as close to the package as possible, ideally right up against the device. The 10 µF capacitors are the tantalum bead type. The 0.1 µF capacitor should have low effective series resistance (ESR) and low effective series inductance (ESI) such as the common ceramic types, which provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching.

The power supply lines of the AD5724R/AD5734R/AD5754R should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Shield fast switching signals such as clocks with digital ground to avoid radiating noise to other parts of the board and never run them near the reference inputs. A ground line routed between the SDIN and SCLK lines helps reduce crosstalk between them (this is not required on a multilayer board that has a separate ground plane, but separating the lines does help). It is essential to minimize noise on the REFIN line because it couples through to the DAC output.

Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This reduces the effects of feed through the board. A microstrip technique is by far the best but not always possible with a double-sided board. In this technique, the component side of the board is dedicated to the ground plane, while signal traces are placed on the solder side.

Rev. B | Page 31 of 32

GALVANICALLY ISOLATED INTERFACE

In many process control applications, it is necessary to provide an isolation barrier between the controller and the unit being controlled to protect and isolate the controlling circuitry from any hazardous common-mode voltages that may occur. The

iCoupler® family of products from Analog Devices, Inc., provides

voltage isolation in excess of 2.5 kV. The serial loading structure of the AD5724R/AD5734R/AD5754R makes them ideal for isolated interfaces because the number of interface lines is kept to a minimum. Figure 49 shows a 4-channel isolated interface to the AD5724R/AD5734R/AD5754R using an ADuM1400. For further information, visit http://www.analog.com/icouplers.

MICROCONTROLLER

SERIAL CLOCK OUT

SERIAL DATA OUT

SYNC OUT

CONTRO L OUT

*ADDITIONAL PINS OMIT TED FOR CLARITY.

Figure 49. Isolated Interface

DuM1400*

ENCODE DECODE

TO SCLK

TO SDIN

TO SYNC

TO LDAC

MICROPROCESSOR INTERFACING

Microprocessor interfacing to the AD5724R/AD5734R/AD5754R is via a serial bus that uses a standard protocol compatible with microcontrollers and DSP processors. The communications channel is a 3-wire (minimum) interface consisting of a clock signal, a data signal, and a synchronization signal. The AD5724R/ AD5734R/AD5754R require a 24-bit data-word with data valid on the falling edge of SCLK.

For all interfaces, the DAC output update can be initiated automatically when all the data is clocked in, or it can be

LDAC

performed under the control of registers can be read using the readback function.

AD5724R/AD5734R/AD5754R to Blackfin® DSP interface

Figure 50 shows how the AD5724R/AD5734R/AD5754R can be interfaced to a Blackfin DSP from Analog Devices. The Blackfin has an integrated SPI port that can be connected directly to the SPI pins of the AD5724R/AD5734R/AD5754R and the programmable I/O pins that can be used to set the state of a digital input

LDAC

such as the

Figure 50. AD5724R/AD5734R/AD5754R-to-Blackfin Interface

pin.

SPISELx

SCK

MOSI

ADSP-BF531

PF10

. The contents of the

SYNC SCLK

SDIN

AD5724R/ AD5734R/ AD5754R

LDAC

06465-012

06465-011

Page 32

AD5724R/AD5734R/AD5754R

OUTLINE DIMENSIONS

7.90

7.80

7.70

5.02

5.00

4.95

1.20 MAX

0.15 SEATING

0.05

0.10 COPLANARITY

PLANE

TOP VIEW

0.65 BSC

4.50

4.40

4.30

6.40 BSC

1.05

1.00

0.80

COMPLIANT TO JEDEC STANDARDS MO-153-ADT

8° 0°

0.20

0.09

0.30

0.19

121

EXPOSED

PAD

(Pins Up)

BOTTOM VIEW

3.25

3.20

3.15

FOR PROPER CONNE CT I O N O F THE EXPOSED PAD, REFER TO THE PIN CONF IGURATIO N AND FUNCTION DES CRIPTIONS SECTION OF THIS DATA SHEET.

0.75

0.60

0.45

061708-A

Figure 51. 24-Lead Thin Shrink Small Outline Package, Exposed Pad [TSSOP_EP]

(RE-24)

Dimensions shown in millimeters

ORDERING GUIDE

Model1 Resolution Temperature Range INL Package Description Package Option

AD5724RBREZ 12 −40°C to +85°C ±1 LSB 24-Lead TSSOP_EP RE-24 AD5724RBREZ-REEL7 12 −40°C to +85°C ±1 LSB 24-Lead TSSOP_EP RE-24 AD5734RBREZ 14 −40°C to +85°C ±4 LSB 24-Lead TSSOP_EP RE-24 AD5734RBREZ-REEL7 14 −40°C to +85°C ±4 LSB 24-Lead TSSOP_EP RE-24 AD5754RBREZ 16 −40°C to +85°C ±16 LSB 24-Lead TSSOP_EP RE-24 AD5754RBREZ-REEL7 16 −40°C to +85°C ±16 LSB 24-Lead TSSOP_EP RE-24 EVAL-AD5754REBZ Evaluation Board

Z = RoHS Compliant Part.

Rev. B | Page 32 of 32

Datasheet AD5724R, AD5734R, AD5754R Datasheet (ANALOG DEVICES)

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

TABLE OF CONTENTS

REVISION HISTORY

FUNCTIONAL BLOCK DIAGRAM

SPECIFICATIONS

AC PERFORMANCE CHARACTERISTICS

TIMING CHARACTERISTICS

TIMING DIAGRAMS

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS

TERMINOLOGY

THEORY OF OPERATION

ARCHITECTURE

Output Amplifiers

Reference Buffers

SERIAL INTERFACE

Input Shift Register

Standalone Operation

Daisy-Chain Operation

Readback Operation

LOAD DAC (LDAC) CONFIGURING THE AD5724R/AD5734R/AD5754R

Individual DAC Updating

Simultaneous Updating of All DACs

ASYNCHRONOUS CLEAR (CLR)

TRANSFER FUNCTION

Ideal Output Voltage to Input Code Relationship—AD5754R

Ideal Output Voltage to Input Code Relationship—AD5734R

Ideal Output Voltage to Input Code Relationship—AD5724R

INPUT REGISTER

DAC REGISTER

OUTPUT RANGE SELECT REGISTER

CONTROL REGISTER

POWER CONTROL REGISTER

DESIGN FEATURES

ANALOG OUTPUT CONTROL

POWER-DOWN MODE

OVERCURRENT PROTECTION

Constant Current Clamp (Clamp Enable = 1)

Automatic Channel Power-Down (Clamp Enable = 0)

THERMAL SHUTDOWN

INTERNAL REFERENCE

APPLICATIONS INFORMATION

+5 V/±5 V OPERATION

LAYOUT GUIDELINES

GALVANICALLY ISOLATED INTERFACE

MICROPROCESSOR INTERFACING

AD5724R/AD5734R/AD5754R to Blackfin® DSP interface

OUTLINE DIMENSIONS

ORDERING GUIDE