Datasheet AD5700, AD5700-1 Datasheet (ANALOG DEVICES)

V

Low Power HART Modem

Data Sheet

FEATURES

HART-compliant fully integrated FSK modem
1200 Hz and 2200 Hz sinusoidal shift frequencies
115 μA maximum supply current in receive mode
Suitable for intrinsically safe applications
Integrated receive band-pass filter

Minimal external components required

Clocking optimized for various system configurations

Ultralow power crystal oscillator (60 μA maximum)
External CMOS clock source

Precision internal oscillator (AD5700-1 only)
Buffered HART output—extra drive capability
8 kV HBM ESD rating
2 V to 5.5 V power supply

1.71 V to 5.5 V interface

−40°C to +125°C operation
4 mm × 4 mm LFCSP package
HART physical layer compliant
UART interface

APPLICATIONS

Field transmitters
HART multiplexers
PLC and DCS analog I/O modules
HART network connectivity

FUNCTIONAL BLOCK DIAGRAM

REG_CAP

CLKOUT

XTAL1

XTAL2

AD5700/AD5700-1

GENERAL DESCRIPTION

The AD5700/AD5700-1 are single-chip solutions, designed
and specified to operate as a HART® FSK half-duplex modem,
complying with the HART physical layer requirements. The

AD5700/AD5700-1 integrate all of the necessary filtering, signal

detection, modulating, demodulating and signal generation
functions, thus requiring few external components. The 0.5%
precision internal oscillator on the AD5700-1 greatly reduces
the board space requirements, making it ideal for line-powered
applications in both master and slave configurations. The maxi­mum supply current consumption is 115 µA, making the AD5700/

AD5700-1 an optimal choice for low power loop-powered applica-

tions. Transmit waveforms are phase continuous 1200 Hz and
2200 Hz sinusoids. The AD5700/AD5700-1 contain accurate
carrier detect circuitry and use a standard UART interface.

Table 1. Related Products

Part No. Description

AD5755-1 Quad-channel, 16-bit, serial input, 4 mA to 20 mA and

AD5421 16-bit, serial input, loop powered, 4 mA to 20 mA DAC
AD5410/

AD5420
AD5412/

AD5422

XTAL_EN

voltage output DAC, dynamic power control, HART
connectivity

Single-channel, 12-bit/16-bit, serial input, 4 mA to 20 mA
current source DACs

Single-channel, 12-bit/16-bit, serial input, current
source and voltage output DACs

CC

IOV

CC

DUPLEX

CD

RXD

TXD

DEMODULATOR

RTS

CLK_CFG0

CLK_CFG1

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of p atents or other
rights of third parties that may result from its use. Specifications subject to chan ge without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

CONTROL L OGIC

RESET

OSC

FSK

MODULATOR

FSK

VO LTAGE

REFERENCE

REF REF_EN AGNDDGND FILTER_SEL

AD5700/AD5700-1

BUFFER

DAC

BAND-PASS

ADC

Figure 1.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2012 Analog Devices, Inc. All rights reserved.

FILTER AND

BIASING

HART_OUT

ADC_IP

HART_IN

10435-001

AD5700/AD5700-1 Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1 

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Timing Characteristics ................................................................ 5

Absolute Maximum Ratings ............................................................ 6

Thermal Resistance ...................................................................... 6

ESD Caution .................................................................................. 6

Pin Configuration and Function Descriptions ............................. 7

Typical Performance Characteristics ............................................. 9

Terminology .................................................................................... 12

REVISION HISTORY

4/12—Rev. 0 to Rev. A

RTS

Change to Transmit Impedance Parameter,

Changes to Figure 3, Figure 4, Figure 5, and Figure 7 ................. 9

Changes to Figure 10 and Figure 11............................................. 10

Changed AD5755 to AD5755-1 Throughout ............................. 17

Change to Figure 27 ....................................................................... 18

2/12—Revision 0: Initial Version

Low, Table 2 .. 4

Theory of Operation ...................................................................... 13

FSK Modulator ........................................................................... 13

Connecting to HART_OUT ..................................................... 14

FSK Demodulator ...................................................................... 14

Connecting to HART_IN or ADC_IP .................................... 14

Clock Configuration .................................................................. 15

Power-Down Mode .................................................................... 16

Full Duplex Operation ............................................................... 16

Applications Information .............................................................. 17

Supply Decoupling ..................................................................... 17

Typical Connection Diagrams .................................................. 17

Outline Dimensions ....................................................................... 20

Ordering Guide .......................................................................... 20

Rev. A | Page 2 of 20

Data Sheet AD5700/AD5700-1

SPECIFICATIONS

VCC = 2 V to 5.5 V, IOVCC = 1.71 V to 5.5 V, AGND = DGND, CLKOUT disabled, HART_OUT with 5 nF load, internal and external
receive filter, internal reference, all specifications are from −40°C to +125°C and relate to both A and B models, unless otherwise noted.

Table 2.

Parameter1 Min Typ Max Unit Test Conditions/Comments

POWER REQUIREMENTS2

VCC 2 5.5 V

IOVCC 1.71 5.5 V

VCC and IOVCC Current Consumption

Demodulator 86 115 μA B model, external clock, −40°C to +85°C
179 μA B model, external clock, −40°C to +125°C
69 97 μA

157 μA

260 μA A model, external clock, −40°C to +125°C

Modulator 124 140 μA B model, external clock, −40°C to +85°C
193 μA B model, external clock, −40°C to +125°C
73 96 μA

153 μA

270 μA A model, external clock, −40°C to +125°C

Crystal Oscillator3 33 60 μA External crystal, 16 pF at XTAL1 and XTAL2
44 71 μA External crystal, 36 pF at XTAL1 and XTAL2

Internal Oscillator4 218 285 μA AD5700-1 only, external crystal not required
Power-Down Mode

VCC and IOVCC Current Consumption 16 35 μA Internal reference disabled, −40°C to +85°C

75 μA Internal reference disabled, −40°C to +125°C

INTERNAL VOLTAGE REFERENCE

Internal Reference Voltage 1.47 1.5 1.52 V

Load Regulation 18 ppm/μA Tested with 50 μA load

OPTIONAL EXTERNAL VOLTAGE

REFERENCE
External Reference Input Voltage 2.47 2.5 2.53 V

External Reference Input Current

Demodulator 16 21 μA

Modulator 28 33 μA

Internal Oscillator 5.5 7 μA

Power-Down 4.6 8.6 μA

DIGITAL INPUTS

VIH, Input High Voltage 0.7 × IOVCC V
VIL, Input Low Voltage 0.3 × IOVCC V
Input Current −0.1 +0.1 μA
Input Capacitance5 5 pF Per pin

B model, external clock, −40°C to +85°C,
external reference

B model, external clock, −40°C to +125 °C,
external reference

B model, external clock, −40°C to +85°C,
external reference

B model, external clock, −40°C to +125°C,
external reference

= REF_EN = DGND

RESET

REF_EN = IOV
reference

REF_EN = DGND to enable use of external
reference, VCC = 2.7 V minimum

Current required by external reference in
receive mode

Current required by external reference in
transmit mode

Current required by external reference if
using internal oscillator

to enable use of internal

CC

Rev. A | Page 3 of 20

AD5700/AD5700-1 Data Sheet

Parameter1 Min Typ Max Unit Test Conditions/Comments

DIGITAL OUTPUTS

VOH, Output High Voltage IOVCC − 0.5 V
VOL, Output Low Voltage 0.4 V
CD Assert6 85 100 110 mV p-p

HART_IN INPUT

Input Voltage Range 0 REF V External reference source
0 1.5 V Internal reference enabled

HART_OUT OUTPUT

Output Voltage 459 493 505 mV p-p

Mark Frequency7 1200 Hz Internal oscillator
Space Frequency7 2200 Hz Internal oscillator
Frequency Error −0.5 +0.5 % Internal oscillator, −40°C to +85°C

−1 +1 % Internal oscillator, −40°C to +125°C
Phase Continuity Error5 0 Degrees
Maximum Load Current5 160 Ω

Transmit Impedance 7 Ω
70 kΩ

1

Temperature range: −40°C to +125°C; typical at 25°C.

2

Current consumption specifications are based on mean current values.

3

The demodulator and modulator currents are specified using an external clock. If using an external crystal oscillator, the crystal oscillator current specification must be

added to the corresponding VCC and IOVCC demodulator/modulator current specification to obtain the total supply current required in this mode.

4

The demodulator and modulator currents are specified using an external clock. If using the internal oscillator, the internal oscillator current specification must be

added to the corresponding VCC and IOVCC demodulator/modulator current specification to obtain the total supply current required in this mode.

5

Guaranteed by design and characterization, but not production tested.

6

Specification set assuming a sinusoidal input signal containing preamble characters at the input and an ideal external filter (see Figure 21).

7

If the internal oscillator is not used, frequency accuracy is dependent on the accuracy of the crystal or clock source used.

5

AC-coupled (2.2 μF), measured at HART_OUT
pin with 160 Ω load (worst-case load), see
Figure 15 and Figure 16 for HART_OUT
voltage vs. load

Worst-case load is 160 Ω, ac-coupled with

2.2 μF, see Figure 19 for recommended
configuration if driving a resistive load

low, at the HART_OUT pin

RTS

high, at the HART_OUT pin

RTS

Rev. A | Page 4 of 20

Data Sheet AD5700/AD5700-1

TIMING CHARACTERISTICS

VCC = 2 V to 5.5 V, IOVCC = 1.71 V to 5.5 V, T

Table 3.

Parameter1 Limit at T

MIN

, T

Unit Description

MAX

t1 1 Bit time2 max

t2 1 Bit time2 max

t3 1 Bit time2 max

t4 6 Bit times2 max Carrier detect on. Time from carrier on to CD rising edge. See Figure 5.
t5 6 Bit times2 max Carrier detect off. Time from carrier off to CD falling edge. See Figure 6.
t6 10 Bit times2 max

t7 2.1 ms typ

t8 6 ms typ Crystal oscillator power-up time. Crystal load capacitors = 18 pF.
t9 25 μs typ

t10 10 ms typ Reference power-up time.
t11 30 μs typ

1

Specifications apply to AD5700/AD5700-1 configured with internal or external receive filter.

2

Bit time is the length of time to transfer one bit of data.

MIN

to T

, unless otherwise noted, 1 bit time = 1/1200 Hz = 833.333 µs.

MAX

Carrier start time. Time from RTS

falling edge to carrier reaching its first peak. See

Figure 3.
Carrier stop time. Time from RTS

rising edge to carrier amplitude dropping to ac

zero. See Figure 4.
Carrier decay time. Time from RTS

rising edge to carrier amplitude dropping to ac

zero. See Figure 4.

Carrier detect on when switching from transmit mode to receive mode in the
presence of a constant valid carrier. Time from RTS

rising edge to CD rising edge.

See Figure 7.
Crystal oscillator power-up time. On application of a valid power supply voltage at

or on enabling of the oscillator via the XTAL_EN pin. Crystal load capacitors =

V

CC

8 pF.

Internal oscillator power-up time. On application of a valid power supply voltage
at V

or on enabling of the oscillator via the CLK_CFG0 and CLK_CFG1 pins.

CC

Transition time from power-down mode to normal operating mode (external
clock source, external reference).

Rev. A | Page 5 of 20

AD5700/AD5700-1 Data Sheet

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.
Transient currents of up to 100 mA do not cause SCR latch-up.

Table 4.

Parameter Rating

VCC to GND −0.3 V to +7 V
IOVCC to GND −0.3 V to +7 V
Digital Inputs to DGND −0.3 V to IOVCC + 0.3 V or

Digital Output to DGND −0.3 V to IOVCC + 0.3 V or

HART_OUT to AGND −0.3 V to +2.5 V
HART_IN to AGND −0.3 V to VCC + 0.3 V or

ADC_IP −0.3 V to VCC + 0.3 V or

AGND to DGND −0.3 V to +0.3 V
Operating Temperature Range (TA)

Industrial −40°C to +125°C
Storage Temperature Range −65°C to +150°C
Junction Temperature (TJ
Power Dissipation (TJ
Lead Temperature, JEDEC industry standard

Soldering J-STD-020
ESD

Human Body Model

(ANSI/ESDA/JEDEC JS-001-2010)

Field Induced Charge Model

(JEDEC JESD22_C101E)

Machine Model

(ANSI/ESD S5.2-2009)

) 150°C

MAX

+7 V (whichever is less)

+7 V (whichever is less)

+7 V (whichever is less)

+7 V (whichever is less)

– TA)/θJA

MAX

8 kV

1.5 kV

400 V

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.

Table 5. Thermal Resistance

Package Type θJA θ

Unit

JC

24-Lead LFCSP 30 3 °C/W

ESD CAUTION

Rev. A | Page 6 of 20

Data Sheet AD5700/AD5700-1

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

XTAL2

AGND

XTAL1

DGND

REF_EN

FILTER_SEL
24

23

20

21

22

19

1

TAL_EN

X

2

CLKOUT

3

LK_CFG0

C

CLK_CFG1

NOTES

1. THE EXPOSED

B
RECOMMENDED THAT THE PADDLE
CONNECTED
THERMAL PERFORMANC

4

5

RESET

6

CD

D OR DGND, OR, ALTERNATIVELY, IT CA

TO

AGN

E LEFT ELEC

AD5700/

AD5700-1

TOP VIEW

(Not to Scale)

9

8

7

TXD

PADDLE SHOULD BE CONNECTED

TRICALLY UNCONNECTED.

TO A COPPER PL

10

TS
R

RXD

DUPLEX

E.

18

17

16

15

14

13

11

12

CC

IOV

DGND

BE THERMALLY

ANE

FOR ENHANCED

V

CC

ADC_IP

T_IN

HAR

REF

HART

REG_CAP

IT IS

_OUT

N

10435-002

Figure 2. AD5700/AD5700-1 Pin Configuration

Table 6. AD5700/AD5700-1 Pin Function Descriptions

Pin No. Mnemonic Description

1

XTAL_EN

Crystal Oscillator Circuit Enable. A low state enables the crystal oscillator circuit, and an external crystal is

required. A high state disables the crystal oscillator circuit, and an external clock source or the internal oscillator
(AD5700-1 only) provides the clock source. This pin is used in conjunction with the CLK_CFG0 and CLK_CFG1
pins in configuring the required clock generation scheme.

2 CLKOUT

Clock Output. If using the crystal oscillator or the internal RC oscillator, a clock output can be configured at the
CLKOUT pin. Enabling the clock output consumes extra current to drive the load on this pin. See the CLKOUT

section for more details.
3 CLK_CFG0 Clock Configuration Control. See Table 7.
4 CLK_CFG1 Clock Configuration Control. See Table 7.
5

Active Low Digital Input. Holding RESET low places the AD5700/AD5700-1 in power-down mode. A high state on

RESET

RESET returns the AD5700/AD5700-1 to their power-on state. If not using this pin, tie this pin to IOVCC.
6 CD Carrier Detect—Digital Output. A high on CD indicates a valid carrier is detected.
7 TXD Transmit Data—Digital Input. Data input to the modulator.
8

Request to Send—Digital Input. A high state enables the demodulator and disables the modulator. A low state

RTS

enables the modulator and disables the demodulator.
9 DUPLEX

A high state on this pin enables full duplex operation. See the Theory of Operation section. A low state disables

this feature.
10 RXD Receive Data—UART Interface Digital Data Output. Data output from the demodulator is accessed on this pin.
11 IOVCC

Digital Interface Supply. Digital threshold levels are referenced to the voltage applied to this pin. The applied

voltage can be in the range of 1.71 V to 5.5 V.
12 DGND

Digital Circuitry Ground Reference Connection. For typical operation, it is recommended to connect this pin to

AGND.
13 REG_CAP Capacitor Connection for Internal Voltage Regulator. Connect a 1 μF capacitor from this pin to ground.
14 HART_OUT HART FSK Signal Output. See the FSK Modulator section and Figure 26 for typical connections.
15 REF

16 HART_IN

Internal Reference Voltage Output, or External 2.5 V Reference Voltage Input. Connect a 1 μF capacitor from this

pin to ground. When supplying an external reference, the V

supply requires a minimum voltage of 2.7 V.

CC

HART FSK Signal. When using the internal filter, couple the HART input signal into this pin using a 2.2 nF series

capacitor. If using an external band-pass filter as shown in Figure 21, do not connect to this pin.
17 ADC_IP

If using the internal band-pass filter, connect 680 pF to this pin. Alternatively, this pin allows direct connection to

the ADC input, in which case an external band-pass filter network must be used, as shown in Figure 21.
18 VCC

Power Supply Input. 2 V to 5.5 V can be applied to this pin. V

should be decoupled to ground with low ESR

CC

10 μF and 0.1 μF capacitors (see the Supply Decoupling section).
19 AGND Analog Circuitry Ground Reference Connection.

Rev. A | Page 7 of 20

AD5700/AD5700-1 Data Sheet

Pin No. Mnemonic Description

20 XTAL2

21 XTAL1

22 DGND

23 REF_EN

24 FILTER_SEL

EPAD AGND Analog Ground Reference Connection. For typical operation, it is recommended to connect this pin to AGND.

Connection for External 3.6864 MHz Crystal. Do not connect to this pin if using the internal RC oscillator
(AD5700-1 only) or an external clock source.

Connection for External 3.6864 MHz Crystal or External Clock Source Input. Tie this pin to ground if using the
internal RC oscillator (AD5700-1 only).

Digital Circuitry Ground Reference Connection. For typical operation, it is recommended to connect this pin to
AGND.

Reference Enable. A high state enables the internal 1.5 V reference and buffer. A low state disables the internal
reference and input buffer, and a buffered external 2.5 V reference source must be applied at REF. If REF_EN is
tied low, V

Band-Pass Filter Select. A high state enables the internal filter and the HART signal should be applied to the
HART_IN pin. A low state disables the internal filter and an external band-pass filter must then be connected at
the ADC_IP input pin. In this case, the HART signal should be applied to the ADC_IP pin.

must be greater than 2.7 V.

CC

Rev. A | Page 8 of 20

Data Sheet AD5700/AD5700-1

TYPICAL PERFORMANCE CHARACTERISTICS

1.4
TA = 25°C; VCC = IOVCC = 3.3V; INT V

RTS AND TXD DC L EVELS HAVE BEEN ADJUST ED FOR

1.2
CLARITY. IN REALITY, BO TH OF T HESE SIGNALS RANG E

FROM 0V TO 3.3V.

1.0

RTS

0.8

0.6
TXD

0.4

HART_OUT (V)

0.2

0

HART_OUT

–0.2

–0.4

–0.3 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1

TIME (ms)

REF

Figure 3. Carrier Start Time

1.4
TA = 25°C; VCC = IOVCC = 3.3V; INT V

RTS AND TXD DC LEVELS HAVE BEEN ADJUSTED FOR

1.2
CLARITY. IN REALITY, BOTH OF THESE SIGNALS RANGE

FROM 0V TO 3.3V.

1.0

RTS

0.8

TXD

0.6

0.4

HART_OUT

HART_OUT (V)

0.2

0

–0.2

–0.4

–2.0 –1.5 –1.0 –0.5 0 0.5 1.0

TIME (ms)

REF

Figure 4. Carrier Stop/Decay Time

1.4
TA = 25°C; VCC = IOVCC = 3.3V; I NT V

CD AND RXD DC LEVELS HAVE BEEN ADJUSTED FOR

1.2
CLARITY. IN REALITY, BOTH OF THESE SIGNALS RANGE
FROM 0V TO 3.3V.

1.0

CD

0.8

0.6

RXD

0.4

HART SIG NAL (V)

0.2

0

HART SIG NAL

–0.2

–0.4

–0.5 0 0.5 1.0 1.5 2.0 2.5

TIME (ms)

REF

Figure 5. Carrier Detect On Timing

10435-003

10435-004

10435-005

1.4
TA = 25°C; VCC = IOVCC = 3.3V; INT V

CD AND RXD DC LEVELS HAVE BEEN ADJUSTED FOR

1.2
CLARITY. IN REALITY, BOTH OF THESE SIGNALS RANGE
FROM 0V TO 3.3V.

1.0
CD

0.8

0.6

RXD

0.4

HART SIG NAL (V)

0.2

0

–0.2

–0.4

–5 –4 –3 –2 –1 0 1

TIME (ms)

REF

HART SIG NAL

10435-006

Figure 6. Carrier Detect Off Timing

1.50
TA = 25°C; VCC = IOVCC = 3.3V; INT V

RTS AND CD DC LEVELS HAVE BEEN ADJUSTED FOR

1.25
CLARITY. IN REALITY, BOTH OF THESE SIGNALS RANGE

FROM 0V TO 3.3V.

1.00

RTS

0.75

CD

0.50

0.25

0

HART_OUT (V)

–0.25

–0.50

–0.75

–1.00

–10 –7. 5 –5. 0 –2.5 0 2.5

HART SIG NAL

TIME (ms)

REF

HART SIG NAL HAS ALS O

BEEN OFFSET BY –0.6V.

HART_OUT

10435-007

Figure 7. Carrier Detect on When Switching from Transmit Mode to Receive

Mode in the Presence of a Constant Valid Carrier

100

TA = 25°C

= IOVCC = 2.7V TO 5.5V

V

CC

90

DEV 1 EXT REF

80

70

60

50

40

30

SUPPLY CURRENT (µA)

20

10

0

2.0 2.5 3.0 3.5 4.0 4.5 5. 0 5.5 6.0

MOD ICCAND IOI

DEMOD ICC AND IOI

= IOVCC (V)

V

CC

MOD I

DEMOD I

CC

CC

REF

REF

10435-008

Figure 8. Supply Currents vs. Supply Voltage—External Reference

Rev. A | Page 9 of 20

AD5700/AD5700-1 Data Sheet

200

180

160

TA = 25°C

= IOVCC = 2V TO 5.5V

V

CC

DEV 1 INT REF

140

(µA)

120

CC

MOD ICCAND IOI

CC

100

80

AND IOI

CC

I

60

DEMOD ICC AND IOI

CC

40

20

0

1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

= IOVCC (V)

V

CC

Figure 9. Supply Currents vs. Supply Voltage—Internal Reference

700

600

500

400

300

CURRENT (µA)

CC

I

200

HART_OUT

100

0

0 200 400 600 800 1000 1200

TA = 25°C; VCC = IOVCC = 3.3V; INT V
CLK CONFIG = XT AL OSCILL ATOR
IOI

= 41µA

CC

2.2µF

22nF R

R

LOAD

LOAD

(Ω) WITH 22nF TO GND

TXD = 1
TXD = 0

REF

Figure 10. Current in Tx Mode vs. Resistive Load

250

TA = 25°C; VCC = IOVCC = 3.3V; I NT V

225

CLK CONFI G = XTAL OSCIL LATOR
CAPACITI VE LOAD O NLY

200

IOI

= 41µA

CC

REF

175

150

125

100

CURRENT (µA)

CC

I

75

50

TXD = 1
TXD = 0

25

0

0 102030405060

C

LOAD

(nF)

Figure 11. Current in Tx Mode vs. Capacitive Load

10435-026

10435-009

10435-010

0

TA = 25°C

–2

= IOVCC = 3.3V

V

CC

INT V

REF

–4

–6

–8

–10

GAIN (dB)

–12

–14

EXTERNAL FILTER
INTERNAL FILTER

–16

–18

–20

100 1k 10k

FREQUENCY (Hz)

Figure 12. Input Filter Frequency Response

1.5012
TA = 25°C
V

= IOVCC = 2V TO 5.5V

CC

1.5010

1.5008

1.5006

1.5004

INTERNAL (V)

1.5002

REF

V

1.5000

1.4998

1.4996

1.01.52.02.53.03.54.04.55.05.56.0

Figure 13. Reference Voltage vs. V

1.5006

VCC = IOVCC = 2.7V
TEMPERATURE = –40°C TO +125°C

1.5004

(V)

V

CC

CC

1.5002

1.5000

1.4998

INTERNAL (V)

1.4996

REF

V

1.4994

1.4992

1.4990

–40 –20 0 20 40 60 80 100 120

TEMPERATURE (° C)

Figure 14. Reference Voltage vs. Temperature

10435-011

10435-012

10435-013

Rev. A | Page 10 of 20

Data Sheet AD5700/AD5700-1

500

TA = 25°C

= IOVCC = 3.3V

V

CC

495

INT V

REF

490

485

480

HART_OUT (mV p-p)

475

470

465

0 200 400 600 800 1000 1200

R

LOAD

Figure 15. HART_OUT Voltage vs. R

1200Hz
2200Hz

HART_OUT

(Ω) || WITH 22nF TO GND

22nF R

2.2µF

LOAD

10435-014

Figure 16. HART_OUT Voltage vs. C

LOAD

505

TA = 25°C

504

= IOVCC = 3.3V

V

CC

INT V

503

502

501

500

499

HART_OUT (mV p-p)

498

497

496

495

REF

CAPACITIVE LOAD ONLY

1200Hz
2200Hz

0 102030405060

C

LOAD

(nF)

LOAD

10435-015

Rev. A | Page 11 of 20

AD5700/AD5700-1 Data Sheet

TERMINOLOGY

VCC and IOVCC Current Consumption

This specification gives a summation of the current consump­tion of both the V
separate measurements for V

and the IOVCC supplies. Figure 11 shows

CC

and IOVCC currents vs. varying

CC

capacitive loads, in transmit mode.

Load Regulation

Load regulation is the change in reference output voltage due to
a specified change in load current. It is expressed in ppm/µA.

CD Assert

The minimum value at which the carrier detect signal asserts is
85 mV p-p and the maximum value it asserts at is 110 mV p-p. CD
is already high (asserted) for HART input signals greater than
110 mV p-p. This specification was set assuming a sinusoidal
input signal containing preamble characters at the input and an
ideal external filter (see Figure 21).

HART_OUT Output Voltage

This is the peak-to-peak HART_OUT output voltage. The
specification in Table 2 was set using a worst-case load of 160 Ω,
ac-coupled with a 2.2 µF capacitor. Figure 15 and Figure 16 show
HART_OUT output voltages for both resistive and purely
capacitive loads.

Mark/Space Frequency

A 1.2 kHz signal represents a digital 1, or mark, whereas a

2.2 kHz signal represents a 0, or space.

Phase Continuity Error

The DDS engine in this design inherently generates continuous
phase signals, thus avoiding any output discontinuity when
switching between frequencies. This attribute is desirable for
signals that are to be transmitted over a band limited channel,
because discontinuities in a signal introduce wideband fre­quency components. As the name suggests, for a signal to be
continuous, the phase continuity error must be 0

o

.

Rev. A | Page 12 of 20

Data Sheet AD5700/AD5700-1

THEORY OF OPERATION

Highway Addressable Remote Transducer (HART) Communica­tion is the global standard for sending and receiving digital
information across analog wires between smart field devices
and control systems. This is a digital two-way communication
system, in which a 1 mA p-p frequency shift keyed (FSK) signal
is modulated on top of a 4 mA to 20 mA analog current signal.
The AD5700/AD5700-1 are designed and specified to operate
as a single-chip, low power, HART FSK half-duplex modem,
complying with the HART physical layer requirements
(Revision 8.1).

A single-chip solution, the AD5700/AD5700-1 not only inte­grate the modulation and demodulation functions, but also
contain an internal reference, an integrated receive band-pass
filter (which has the flexibility of being bypassed if required),
and an internally buffered HART output, giving a high output
drive capability and removing the need for external buffering.
The AD5700-1 option also contains a precision internal RC
oscillator. The block diagram in Figure 1 shows a graphical
illustration of how these circuit blocks are connected together.
As a result of such extensive integration options, minimal
external components are required. The AD5700/AD5700-1
are suitable for use in both HART field instrument and master
configurations.

The AD5700/AD5700-1 either transmit or receive 1.2 kHz and

2.2 kHz carrier signals. A 1.2 kHz signal represents a digital 1,
or mark, whereas a 2.2 kHz signal represents a 0, or space.
There are three main clocking configurations supported by
these parts, two of which are available on the AD5700 option,
whereas all three are available on the AD5700-1 device:

 External crystal
 CMOS clock input
 Internal RC oscillator (AD5700-1 only)

FSK MODULATOR

The modulator converts a bit stream of UART-encoded HART
data at the TXD input to a sequence of 1200 Hz and 2200 Hz
tones (see Figure 17). This sinusoidal signal is internally buff­ered and output on the HART_OUT pin. The modulator is
enabled by bringing the

TXD

HART_OUT

START

Figure 17. AD5700/AD5700-1 Modulator Waveform

The modulator block contains a DDS engine that produces a

1.2 kHz or 2.2 kHz sine wave in digital form and then performs
a digital-to-analog conversion. This DDS engine inherently
generates continuous phase signals, thus avoiding any output
discontinuity when switching between frequencies. For more
information on DDS fundamentals, see MT-085, Fundamentals
of Direct Digital Synthesizers (DDS). Figure 18 demonstrates a
simple implementation of this FSK encoding.

1

DATA

0

RTS

signal low.

"1" = MARK

8-BIT DATA + PARITY

1.2kHz

"0" = SPACE

2.2kHz

STOP

10435-016

The device is controlled via a standard UART interface. The
relevant signals are

RTS

, CD, TXD, and RXD (see Table 6 for

more detail on individual pin descriptions).

Rev. A | Page 13 of 20

1.2kHz
WORD

2.2kHz
WORD

Figure 18. DDS-Based FSK Encoder

DDS

MUX

CLOCK

DAC FSK

10435-017

AD5700/AD5700-1 Data Sheet

CONNECTING TO HART_OUT

The HART_OUT pin is dc biased to 0.75 V and should be
capacitively coupled to the load. The current consumption
specifications in Table 2 are based on driving a 5 nF load. If
the application requires a larger load value, more current is
required. This value can be calculated from the following
formula:

TOTAL

I



RMSLOAD

III 



24

where:

is the current drawn by the AD5700/AD5700-1 in

I

AD5700

transmit mode as per specifications (see Table 2). Note that the
specifications in Table 2 assume a 5 nF C
f is the output frequency (1.2 kHz or 2.2 kHz).

is the capacitive load to ground on HART_OUT.

C

LOAD

is the resistive load on the loop.

R

LOAD

When driving a purely capacitive load, the load should be in the
range of 5 nF to 52 nF. See Figure 11 for a typical plot of supply
current vs. capacitive load.

Example

Assume use of an internal reference, and C

I

+ IOICC = 140 µA maximum (from Table 2

CC

specification)

Note that this is incorporating a 5 nF load.

Therefore, to calculate the load current required to drive the
extra 47 nF, use the Equation 1.

Substituting f = 1200 Hz, C
the formula results in I

LOAD

If using the crystal oscillator, this adds 60 µA maximum (see
Table 2 for conditions).

Thus, the total worst-case current in this example is:

140 µA + 62.6 µA + 60 µA = 262.6 µA

If driving a load with a resistive element, it is recommended to
place a 22 nF capacitor to ground at the HART_OUT pin. The
load should be coupled with a 2.2 µF series capacitor. For low
impedance devices, the R

HART_OUT

22nF R

Figure 19. AD5700/AD5700-1 with Resistive Load at HART_OUT

RMSLOADAD5700

mV500

Cf

LOAD

2







LOAD



LOAD

R

.

2

LOAD

= 52 nF.

= 0 Ω into

LOAD






2





= 47 nF, and R

LOAD

1



of 62.6 µA.

range is typically 230 Ω to 600 Ω.

LOAD

2.2µF

LOAD

10435-018

(1)

FSK DEMODULATOR

HART_IN

8-BIT DATA + PARIT Y

RXD

STOP

When

START

Figure 20. AD5700/AD5700-1 Demodulator Waveform

RTS

is logic high, the modulator is disabled and the

(Preamble Message 0xFF)

demodulator is enabled, that is, the AD5700/AD5700-1 are in
receive mode. A high on CD indicates a valid carrier is detected.
The demodulator accepts an FSK signal at the HART_IN pin
and restores the original modulated signal at the UART
interface digital data output pin, RXD. The combination of the
ADC, digital filtering and digital demodulation results in a
highly accurate output on the RXD pin. The HART bit stream
follows a standard UART frame with a start bit, 8-bit data, one
parity, and a stop bit (see Figure 20).

CONNECTING TO HART_IN OR ADC_IP

The AD5700/AD5700-1 have two filter configuration options:
an external filter (HART signal is applied to ACP_IP) and an
internal filter (HART signal is applied to HART_IN).

The external filter configuration is shown in Figure 21. In this
case, the HART signal is applied to the ADC_IP pin through an
external filter circuit. In safety critical applications, the AD5700/

AD5700-1 must be isolated from the high voltage of the loop

supply. The recommended external band-pass filter includes a
150 kΩ resistor, which limits current to a sufficiently low level
to adhere to intrinsic safety requirements. In this case, the input
has higher transient voltage protection and should, therefore,
not require additional protection circuitry, even in the most
demanding of industrial environments. Assuming the use of a
1% accurate resistor and 10% accurate capacitor components,
the calculated variation in CD trip voltage levels vs. the ideal is
±3.5 mV.

HART_OUT

AD5700/

AD5700-1

Figure 21. AD5700/AD5700-1 with External Filter on ADC_IP

REF

ADC_IP

1µF

1.2MΩ

1.2MΩ

300pF

150kΩ

150pF

HART
NETWORK

10435-020

10435-019

Rev. A | Page 14 of 20

Data Sheet AD5700/AD5700-1

The internal filter configuration is shown in Figure 22. This
option is beneficial where cost or board space is a large concern
because it removes the need for multiple external components.
This configuration achieves an 8 kV ESD HBM rating but
requires extra external protection circuitry for EMC and surge
protection purposes if used in harsh industrial environments.

CMOS Clock Input

A CMOS clock input can also be used to generate a clock for the

AD5700/AD5700-1. To use this mode, connect an external clock

source to the XTAL 1 pin, and leave XTAL2 open circuit (see
Figure 24).

HART_OUT

AD5700/

AD5700-1

Figure 22. AD5700/AD5700-1 Using Internal Filter on HART_IN

HART_IN

ADC_IP

2.2nF

680pF

HART
NETWORK

10435-021

CLOCK CONFIGURATION

The AD5700/AD5700-1 support numerous clocking configura­tions to allow the optimal trade-off between cost and power:

External crystal



CMOS clock input




Internal RC oscillator (AD5700-1 only)

XTAL1

XTAL_EN

18pF18pF

XTAL2

pins configure

10435-022

The CLK_CFG0, CLK_CFG1, and
the clock generation as shown in Table 7. The AD5700/AD5700-1
can also provide a clock output at CLKOUT (for more details,
see the CLKOUT section).

External Crystal

The typical connection for an external crystal (ABLS-3.6864MHZ­L4Q-T) is shown in Figure 23. To ensure minimum current
consumption and to minimize stray capacitances, connections
between the crystal, capacitors, and ground should be made as
close to the AD5700/AD5700-1 as possible. Consult individual
crystal vendors for recommended load information and crystal
performance specifications.

ABLS-3-6864MHZ-L4Q-T

AD5700/AD5700-1

Figure 23. Crystal Oscillator Connection

The ABLS-3.6864MHZ-L4Q-T crystal oscillator data sheet
recommended two 18 pF capacitors. Because the crystal current
consumption is dominated by the load capacitance, in an effort
to reduce the crystal current consumption, two 8 pF capacitors
were used on the XTAL1 and XTAL2 pins. The AD5700/AD5700-1
still functioned as expected, even with the resulting reduction in
frequency performance from the crystal due to the smaller
capacitance values. Crystals are available that support 8 pF
capacitors. It is recommended to consult the relevant crystal
manufacturers for this information.

XTAL1

XTAL2

AD5700/AD5700-1

10435-027

Figure 24. CMOS Clock Connection

Internal Oscillator (AD5700-1 only)

Consuming typically 218 µA, the low power, internal, 0.5 %
precision RC oscillator, available only on the AD5700-1, has an
oscillation frequency of 1.2288 MHz. To use this mode, tie the
XTAL1 pin to ground and leave the XTAL2 pin open circuit
(see Figure 25).

XTAL1

XTAL2

AD5700-1

10435-028

Figure 25. Internal Oscillator Connection

CLKOUT

The AD5700/AD5700-1 can provide a clock output at CLKOUT
(see Table 7).

If using the crystal oscillator, this clock output can be



configured as a 3.6864 MHz, 1.8432 MHz, or 1.2288 MHz
buffer clock.

If using a CMOS clock, no clock output can be configured



at the CLKOUT pin.

If using the internal RC oscillator, this clock output is only



available as a 1.2288 MHz buffer clock.

The amplitude of the clock output depends on the IOV

level;

CC

therefore, the clock output can be in the range of 1.71 V p-p to

5.5 V p-p. Enabling the clock output of the AD5700/AD5700-1
increases the current consumption of the device. This increase
is due to the current required to drive any load at the CLKOUT
pin, which should not be more than 30 pF.

This capacitance should be minimized to reduce current
consumption and provide the clock with the cleanest edges.
The additional current drawn from the IOV

supply can be

CC

calculated using the following equation:

I = C × V × f

Rev. A | Page 15 of 20

AD5700/AD5700-1 Data Sheet

Table 7. Clock Configuration Options

XTAL_EN

1 0 0 No output 3.6864 MHz CMOS clock connected at XTAL1 pin
1 0 1 No output 1.2288 MHz CMOS clock connected at XTAL1 pin
1 1 0 No output Internal oscillator enabled (AD5700-1 only)
1 1 1 1.2288 MHz output Internal oscillator enabled, CLKOUT enabled (AD5700-1 only)
0 0 0 No output Crystal oscillator enabled
0 0 1 3.6864 MHz output Crystal oscillator enabled, CLKOUT enabled
0 1 0 1.8432 MHz output Crystal oscillator enabled, CLKOUT enabled
0 1 1 1.2288 MHz output Crystal oscillator enabled, CLKOUT enabled

CLK_CFG1 CLK_CFG0 CLKOUT Description

POWER-DOWN MODE

The AD5700/AD5700-1 can be placed into power-down mode

RESET

by holding the
is recommended to tie the REF_EN pin to the
that it is also powered down. If the reference is not powered
down while
approximately 1.7 V until

In this mode, the receive, transmit, and oscillator circuits are all
switched off, and the device consumes a typical current of 16 µA.

RESET

pin low. If using the internal reference, it

RESET

pin so

is low, the output voltage on the REF pin is

RESET

is brought high again.

FULL DUPLEX OPERATION

Full duplex operation means that the modulator and demodula­tor of the AD5700/AD5700-1 are enabled at the same time. This
is a powerful feature, enabling a self-test procedure of not only
the HART device but also the complete signal path between the
HART device and the host controller. This provides verification
that the local communications loop is functional. This increased
level of system diagnostics is useful in production self-test and
is advantageous in improving the application’s safety integrity
level (SIL) rating. The full duplex mode of operation is enabled by
connecting the DUPLEX pin to logic high.

Rev. A | Page 16 of 20

Data Sheet AD5700/AD5700-1

APPLICATIONS INFORMATION

SUPPLY DECOUPLING

It is recommended to decouple the VCC and IOVCC supplies with
10 F in parallel with 0.1 F capacitors to ground. For many
applications, 1 F in parallel with 0.1 F ceramic capacitors to
ground should be sufficient. The REG_CAP voltage of 1.8 V is
used to supply the AD5700/AD5700-1 internal circuitry and is
derived from the V

supply using a high efficiency clocking

CC

LDO. Decouple this REG_CAP supply with a 1 µF ceramic
capacitor to ground. It is also required to decouple the REF pin
with a 1 µF ceramic capacitor to ground. Place decoupling
capacitors as close to the relevant pins as possible.

For loop-powered applications, it is recommended to connect a
resistance in series with the V

supply to minimize the effect of

CC

any noise, which may, depending on the system configuration, be
introduced onto the loop as a result of current draw variations
from the AD5700/AD5700-1. For typical applications, 470 Ω of
resistance has proven most effective. However, depending on the
application conditions, alternative values may also be acceptable
(see R1 in Figure 27).

TYPICAL CONNECTION DIAGRAMS

Figure 26 shows a typical connection diagram for the AD5700/

AD5700-1 using the external and internal options. See the

Connecting to HART_IN or ADC_IP section for more details.

2V TO 5.5V1.71V TO 5.5V

10µF

1µF

10µF

+

0.1µF

+

0.1µF

The AD5700/AD5700-1 are designed to interface easily with
Analog Devices, Inc., innovative portfolio of industrial
converters like the AD5421 loop-powered current-output DAC,
the AD5410/AD5420 and AD5412/AD5422 family of line­powered current-output DACs, and the AD5755-1, a quad DAC
with innovative dynamic power control technology. The
combination of Analog Devices industrial converters and the

AD5700/AD5700-1 greatly simplifies system design, enhancing

reliability while reducing overall PCB size.

Figure 27 shows how the AD5700/AD5700-1 HART modem
can be interfaced with the AD5421 (4 mA to 20 mA loop-powered
DAC) and a microcontroller to construct a loop powered transmit­ter circuit. The HART signal from HART_OUT is introduced to
the AD5421 via the C

pin.

IN

The HART enabled smart transmitter reference demo circuit
(the block diagram shown in Figure 28) was developed by
Analog Devices and uses the AD5421, a 16-bit, loop-powered,
4 mA to 20 mA DAC, and the AD5700 modem. This circuit has
been compliance tested, verified, and registered as an approved
HART solution by the HART Communication Foundation.
Contact your sales representative for further information about
this demo circuit.

In conclusion, the AD5700/AD5700-1 enable quick and easy
deployment of a robust HART-compliant system.

0.1µF10µF

2V TO 5.5V

10µF

0.1µF

+

1.71V TO 5. 5V

1µF

+

IOVCCV

CC

HART_OUT

XTAL1

CD

RXD

TXD

RTS

ADuC7060 MICROCO NTROLL ER

RESET

REG_CAP

AD5700/AD5700-1

REF_EN

FILTER_SEL

DUPLEX

CONFIGURATION

PINS

XTAL2

CLKOUT

REF

ADC_IP

HART_IN

AGND

DGND

CLK_CFG0

CLK_CFG1

XTAL_EN

1µF

1.2MΩ

1.2MΩ

300pF

150kΩ

150pF

HART NETWO RK

CD

RXD

TXD

RTS

ADuC7060 MICROCO NTROLL ER

RESET

REG_CAP

AD5700/AD5700-1

REF_EN

FILTER_SEL

DUPLEX

CLK_CFG0

CONFIGURATION

PINS

IOVCCV

CC

HART_OUT

XTAL1

XTAL2

CLKOUT

ADC_IP

HART_IN

AGND

DGND

CLK_CFG1

XTAL_EN

REF

1µF

680pF

2.2nF

HART NETWORK

10435-023

Figure 26. AD5700/AD5700-1 Typical Connection Diagram for External and Internal Filter Options

Rev. A | Page 17 of 20

AD5700/AD5700-1 Data Sheet

OPTIONAL

EMC FILTER

4.7µF

10µF

0.1µF

OPTIO NAL

MOSFET

DN2540
BSP129

T1

200kΩ

MCU

R1

0.1µF

470Ω

1µF

AD5700/AD5700-1

TXD
RXD
RTS
CD

IODVDDDVDDREG

RANGE0

RANGE1

ALARM_CURRENT _DIRECTI ON
R

INT/REXT

SYNC
SCLK
SDIN
SDO
FAULT
LDAC

COM

REFOUT2

0.1µF

V

CC

HART_OUT

REF

ADC_IP

GND

OUT

AD5421

REG_SEL0

SETS REGULATOR

VOLTAGE

1µF

REG

IN

DRIVE

V

LOOP

LOOP–

R

EXT1

R

EXT2

C

REG_SEL1

1.2MΩ

1.2MΩ 150pF

COMREFOUT1 REFIN

REG_SEL2

IN

47nF 168nF

300pF

Figure 27. Loop-Powered Transmitter Diagram

R1

OPTIONAL
RESISTOR

150kΩ

19MΩ

1MΩ

VZ = 4.7V

V

LOOP

R

L

10435-025

Rev. A | Page 18 of 20

Data Sheet AD5700/AD5700-1

PRESSURE
SENSOR
SIMULATION

TEMPERAT URE
SENSOR
PT100

3.3V

TEST CONNECTOR

T1: CD

T2: RTS

T3: COM

T4: TEST

LEXC

MCU

ADC 0

ADC 1

AD5700

HART MODEM

MICRO-

CONTROL LER

SRAM
FLASH
CLOCK
RESET

WATCHDOG

UART

COM

V

DD

SPI

COM

V

CC

HART_OUT

REF

ADC_IP

3.3V

3.3V

ADC

DAC

WATCHDOG

TIMER

C_HART

HART
INPUT
FILTER

AD5421

V-RE GUL ATOR

TEMPERAT URE

SENSOR

C

IN

C_SLEW

50Ω

LOOP–

Figure 28. Block Diagram—Analog Devices HART-Enabled Smart Transmitter Reference Demo Circuit

REG

V

LOOP

COM

IN

+

–

10435-029

Rev. A | Page 19 of 20

AD5700/AD5700-1 Data Sheet

OUTLINE DIMENSIONS

PIN 1

INDICATOR

0.80

0.75

0.70

SEATING

PLANE

4.10

4.00 SQ

3.90

0.50
BSC

0.50

0.40

0.30

0.05 MAX

0.02 NOM

0.20 REF

0.30

0.25

0.20

19

18

13

12

BOTTOM VIEWTOP VIEW

COPLANARITY

0.08

1

P

N

I

T

D

C

I

A

N

I

24

1

EXPOSED

PAD

7

FORPROPERCONNECTIONOF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.

2.20

2.10 SQ

2.00

6

0.25 MIN

R

O

COMPLIANTTOJEDEC STANDARDS MO-220-WGGD-8.

072809A

Figure 29. 24-Lead Lead Frame Chip Scale Package [LFCSP_WQ]

4 mm × 4 mm Body, Very Thin Quad

(CP-24-10)

Dimensions shown in millimeters

ORDERING GUIDE

Receive Supply

Model1 Temperature Range Oscillator Options

Current Package Description

AD5700BCPZ-R5 −40°C to +125°C External clock, crystal 157 μA 24-Lead LFCSP_WQ CP-24-10
AD5700BCPZ-RL7 −40°C to +125°C External clock, crystal 157 μA 24-Lead LFCSP_WQ CP-24-10
AD5700ACPZ-RL7 −40°C to +125°C External clock, crystal 260 μA 24-Lead LFCSP_WQ CP-24-10
AD5700-1BCPZ-R5 −40°C to +125°C

External clock, crystal

442 μA 24-Lead LFCSP_WQ CP-24-10

or internal oscillator

AD5700-1BCPZ-RL7 −40°C to +125°C

External clock, crystal

442 μA 24-Lead LFCSP_WQ CP-24-10

or internal oscillator

AD5700-1ACPZ-RL7 −40°C to +125°C

External clock, crystal

540 μA 24-Lead LFCSP_WQ CP-24-10

or internal oscillator

EVAL-AD5700-1EBZ

Evaluation Board for
AD5700 and AD5700-1

1

Z = RoHS Compliant Part.

Package
Option

©2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D10435-0-3/12(A)

Rev. A | Page 20 of 20