Page 1
5 V 18-Bit nanoDAC®
V
V
FEATURES
Single 18-bit nanoDAC
18-bit monotonic
12-bit accuracy guaranteed
Tiny 8-lead SOT-23 package
Power-on reset to zero scale/midscale
4.5 V to 5.5 V power supply
Serial interface
Rail-to-rail operation
SYNC
interrupt facility
Temperature range: −40°C to +105°C
APPLICATIONS
Closed-loop process control
Low bandwidth data acquisition systems
Portable battery-powered instruments
Gain and offset adjustment
Precision setpoint control
GENERAL DESCRIPTION
The AD5680, a member of the nanoDAC family, is a single,
18-bit buffered voltage-out digital-to-analog converter that
operates from a single 4.5 V to 5.5 V supply and is 18-bit
monotonic.
The AD5680 requires an external reference voltage to set the
output range of the DAC. The part incorporates a power-on
reset circuit that ensures the DAC output powers up to 0 V
(AD5680-1) or to midscale (AD5680-2) and remains there until
a valid write takes place.
The low power consumption of this part in normal operation
makes it ideally suited to portable battery-operated equipment.
The power consumption is 1.6 mW at 5 V.
The AD5680 on-chip precision output amplifier allows rail-torail output swing to be achieved. For remote sensing applications,
the output amplifier’s inverting input is available to the user.
in a SOT-23
AD5680
FUNCTIONAL BLOCK DIAGRAM
GND
REF
POWER-ON
RESET
DAC
REGISTER
INPUT
CONTROL
LOGIC
REF(+)
18-BIT DAC
DINSCLKSYNC
The AD5680 uses a versatile 3-wire serial interface that operates
at clock rates up to 30 MHz, and is compatible with standard
SPI®, QSPI™, MICROWIRE™, and DSP interface standards.
PRODUCT HIGHLIGHTS
1. 18 bits of resolution.
2. 12-bit accuracy guaranteed for 18-bit DAC.
3. Available in an 8-lead SOT-23.
4. Low power; typically consumes 1.6 mW at 5 V.
5. Power-on reset to zero scale or to midscale.
RELATED DEVICES
AD5662—16-bit DAC in SOT-23.
Figure 1.
DD
OUTPUT
BUFFER
AD5680
V
FB
V
OUT
05854-001
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2006–2007 Analog Devices, Inc. All rights reserved.
Page 2
AD5680
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Product Highlights........................................................................... 1
Related Devices................................................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Characteristics ................................................................ 4
Absolute Maximum Ratings............................................................ 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
Typical Performance Characteristics............................................. 7
Te r mi n ol o g y .................................................................................... 10
Theory of Operation ...................................................................... 11
DAC Section................................................................................ 11
Resistor String............................................................................. 11
Output Amplifier........................................................................ 11
Interpolator Architecture .......................................................... 11
Serial Interface............................................................................ 12
Input Shift Register .................................................................... 12
SYNC
Interrupt .......................................................................... 12
Power-On Reset .......................................................................... 12
Microprocessor Interfacing....................................................... 13
Applications..................................................................................... 14
Closed-Loop Applications ........................................................ 14
Filter ............................................................................................. 14
Choosing a Reference for the AD5680.................................... 15
Using a Reference as a Power Supply for the AD5680.......... 16
Using the AD5680 with a Galvanically Isolated Interface ....16
Power Supply Bypassing and Grounding................................ 16
Outline Dimensions .......................................................................17
Ordering Guide .......................................................................... 17
REVISION HISTORY
3/07—Rev. 0 to Rev. A
Changes to Input Shift Register Section ......................................12
Changes to Figure 25...................................................................... 12
6/06—Revision 0: Initial Version
Rev. A | Page 2 of 20
Page 3
AD5680
SPECIFICATIONS
VDD = 4.5 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; V
= VDD; all specifications T
REF
MIN
to T
, unless otherwise noted.
MAX
Table 1.
B Grade
1
Parameter Min Typ Max Unit Conditions/Comments
STATIC PERFORMANCE
2
Resolution 18 Bits
Relative Accuracy ±32 ±64 LSB
Differential Nonlinearity
3
±1 LSB Measured in 50 Hz system bandwidth
±2 LSB Measured in 300 Hz system bandwidth
Zero-Code Error 2 10 mV All 0s loaded to DAC register
Full-Scale Error −0.2 −1 % FSR All 1s loaded to DAC register
Offset Error ±10 mV
Gain Error ±1.5 % FSR
Zero-Code Error Drift ±2 µV/°C
Gain Temperature Coefficient ±2.5 ppm Of FSR/°C
DC Power Supply Rejection Ratio −100 dB DAC code = midscale; VDD = 5 V ± 10%
OUTPUT CHARACTERISTICS
Output Voltage Range 0 V
Output Voltage Settling Time 80 85 µs
3
DD
V
¼ to ¾ scale change settling to ±8 LSB,
= 2 kΩ; 0 pF < CL < 200 pF
R
L
Slew Rate 1.5 V/µs ¼ to ¾ scale
Capacitive Load Stability 2 nF RL = ∞
10 nF RL = 2 kΩ
Output Noise Spectral Density
Output Noise (0.1 Hz to 10 Hz)
Total Harmonic Distortion (THD)
4
4
4
80 nV/√Hz DAC code = midscale, 10 kHz
25 µV p-p DAC code = midscale
−80 dB V
= 2 V ± 300 mV p-p, f = 200 Hz
REF
Digital-to-Analog Glitch Impulse 5 nV-s 1 LSB change around major carry
Digital Feedthrough 0.2 nV-s
DC Output Impedance 0.5 Ω
Short-Circuit Current
4
30 mA VDD = 5 V
REFERENCE INPUT
Reference Current 40 75 µA V
Reference Input Range
5
0.75 V
DD
V
= VDD = 5 V
REF
Reference Input Impedance 125 kΩ
LOGIC INPUTS
Input Current ±2 µA All digital inputs
V
, Input Low Voltage 0.8 V VDD = 5 V
INL
V
, Input High Voltage 2 V VDD = 5 V
INH
Pin Capacitance 3 pF
POWER REQUIREMENTS
VDD 4.5 5.5 V All digital inputs at 0 V or V
DD
IDD (Normal Mode) DAC active and excluding load current
VDD = 4.5 V to 5.5 V 325 450 A VIH = VDD and VIL = GND
POWER EFFICIENCY
I
OUT/IDD
1
Temperature range for B version is −40°C to +105°C, typical at +25°C.
2
DC specifications tested with the outputs unloaded, unless otherwise stated. Linearity calculated using a reduced code range of 2048 to 260,096.
3
Guaranteed by design and characterization; not production tested.
4
Output unloaded.
5
Reference input range at ambient where maximum DNL specification is achievable.
85 % I
= 2 mA, VDD = 5 V
LOAD
Rev. A | Page 3 of 20
Page 4
AD5680
TIMING CHARACTERISTICS
All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 2.
V
= 4.5 V to 5.5 V; all specifications T
DD
Table 2.
Limit at T
MIN
Parameter VDD = 4.5 V to 5.5 V Unit Conditions/Comments
1
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
t
10
1
Maximum SCLK frequency is 30 MHz at VDD = 4.5 V to 5.5 V.
33 ns min SCLK cycle time
13 ns min SCLK high time
13 ns min SCLK low time
13 ns min
5 ns min Data setup time
4.5 ns min Data hold time
0 ns min
33 ns min
13 ns min
0 ns min
t
10
SCLK
t
8
SYNC
DIN
, T
MAX
DB23
MIN
to T
t
4
, unless otherwise noted.
MAX
t
t
3
t
6
t
5
Figure 2. Serial Write Operation
SYNC to SCLK falling edge setup time
SCLK falling edge to
Minimum
SYNC high time
SYNC rising edge
SYNC rising edge to SCLK fall ignore
SCLK falling edge to
1
t
2
DB0
t
9
t
7
SYNC fall ignore
05854-002
Rev. A | Page 4 of 20
Page 5
AD5680
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter Rating
VDD to GND −0.3 V to +7 V
V
to GND −0.3 V to VDD + 0.3 V
OUT
VFB to GND −0.3 V to VDD + 0.3 V
V
to GND −0.3 V to VDD + 0.3 V
REF
Digital Input Voltage to GND −0.3 V to VDD + 0.3 V
Operating Temperature Range
Industrial (B Version) −40°C to +105°C
Storage Temperature Range −65°C to +150°C
Junction Temperature (TJ max) 150°C
Power Dissipation (TJ max − TA)/θ
θJA Thermal Impedance
SOT-23 Package (4-Layer Board) 119°C/W
Reflow Soldering Peak Temperature
Pb-free 260°C
JA
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Rev. A | Page 5 of 20
Page 6
AD5680
V
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
V
DD
AD5680
2
V
REF
TOP VIEW
3
V
(Not to Scale)
FB
4
OUT
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1 VDD Power Supply Input. The part can be operated from 4.5 V to 5.5 V. VDD should be decoupled to GND.
2 V
Reference Voltage Input.
REF
3 VFB Feedback Connection for the Output Amplifier. VFB should be connected to V
4 V
5
Analog Output Voltage from DAC. The output amplifier has rail-to-rail operation.
OUT
SYNC Level-Triggered Control Input (Active Low). This is the frame synchronization signal for the input data. When SYNC
goes low, it enables the input shift register and data is transferred in on the falling edges of the following clocks.
The DAC is updated following the 24
th
clock cycle unless SYNC is taken high before this edge, in which case the
rising edge of SYNC acts as an interrupt and the write sequence is ignored by the DAC. SYNC
6 SCLK
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can
be transferred at rates up to 30 MHz.
7 DIN
Serial Data Input. This device has a 24-bit shift register. Data is clocked into the register on the falling edge of the
serial clock input.
8 GND Ground. Ground reference point for all circuitry on the part.
GND
8
7
DIN
6
SCLK
SYNC
5
05854-003
for normal operation.
OUT
Rev. A | Page 6 of 20
Page 7
AD5680
TYPICAL PERFORMANCE CHARACTERISTICS
40
VDD = V
T
32
24
16
8
0
–8
INL ERROR (LSB)
–16
–24
–32
–40
0 40k 80k 120k 160k 200k 240k
= 25°C
A
REF
= 5V
CODE
Figure 4. Typical INL Plot
05854-028
0
VDD = 5V
–0.02
–0.04
–0.06
–0.08
–0.10
–0.12
ERROR (% FSR)
–0.14
–0.16
–0.18
–0.20
–40 –20 40200 1008060
GAIN ERROR
FULL-SCALE ERROR
TEMPERATURE (°C)
Figure 7. Gain Error and Full-Scale Error vs. Temperature
05854-044
1.0
VDD = V
T
0.8
0.6
0.4
0.2
0
–0.2
DNL ERROR (LSB)
–0.4
–0.6
–0.8
–1.0
0 25k 50k 100k75k 125k 150k 225k200k175k 250k
= 25°C
A
REF
= 5V
CODE
Figure 5. Typical DNL Plot in 50 Hz System Bandwidth
±4
VDD = 4.5V TO 5.5V
T = –40°C TO +105°C
±2
)
B
S
L
(
L
N
D
±1
0
0
50
SYSTEM BANDW IDTH (Hz)
300 >300
Figure 6. DNL Performance vs. System Bandwidth
1.5
1.0
0.5
0
–0.5
ERROR (mV)
–1.0
–1.5
–2.0
05854-029
–2.5
–40 –20 40200860 100
ZERO-SCALE ERROR
OFFSET ERROR
TEMPERATURE (°C)
0
05854-043
Figure 8. Zero-Scale Error and Offset Error vs. Temperature
0.20
VDD= V
T
0.15
0.10
0.05
0
–0.05
–0.10
ERROR VOLTAGE (V)
–0.15
–0.20
–0.25
05854-042
–5 –4 –3 –2 –1 0 1 2 435
= 5V, 3V
REF
= 25°C
A
DAC LOADED WITH
FULL SCALE –
SOURCING CURRENT
DAC LOADED WITH
ZERO SCALE –
SINKING CURRENT
I (mA)
05854-014
Figure 9. Headroom at Rails vs. Source and Sink Current
Rev. A | Page 7 of 20
Page 8
AD5680
450
VDD = V
T
400
350
300
250
(µA)
DD
200
I
150
100
50
0
0
350
300
250
= 5V
REF
= 25°C
A
4000 8000 12000 16000 20000 24000
CODE
Figure 10. Supply Current vs. Code
VDD = V
REF
= 5V
SCLK
1
D
IN
2
Δ: 1.52V
Δ: 64.8µs
@: 1.20V
3
CH1 2.00V
05854-007
CH3 1.00V
CH2 2.00V M 20. 0µs CH4 1.30V
V
OUT
05854-015
Figure 13. Full-Scale Settling Time, 5 V
V
DD
1
200
(µA)
DD
I
150
100
50
0
–40 –20 0 20 40 60 80 100
TEMPERATURE (°C)
05854-006
Figure 11. Supply Current vs. Temperature
700
= 25°C
T
A
600
500
400
(µA)
DD
I
300
200
100
0
05
1234
VDD = 5V
V
LOGIC
(V)
05854-004
Figure 12. Supply Current vs. Logic Input Voltage
V
REF
2
V
OUT
3
CH1 3.00V
CH3 100mV
V
DD
1
2
V
REF
V
OUT
3
CH1 3.00V
CH3 500mV
CH2 3.00V M 100µs CH1 2.40V
Figure 14. Power-On Reset to 0 V
CH2 3.00V M 100µs CH1 2.40V
Figure 15. Power-On Reset to Midscale
V
OUT
C3 MAX
284mV
V
OUT
C3 MIN
–52mV
V
OUT
C3 MAX
2.5V
V
OUT
C3 MIN
–40mV
05854-016
05854-017
Rev. A | Page 8 of 20
Page 9
AD5680
–
2.502500
2.502250
2.502000
2.501750
2.501500
2.501250
2.501000
2.500750
2.500500
2.500250
AMPLITUDE
2.500000
2.499750
2.499500
2.499250
2.499000
2.498750
0 150 200 25050 100 300 350 400 450 500 550
VDD = V
REF
T
= 25°C
A
13ns/SAMPLE NUMBER
1 LSB CHANGE AROUND
MIDSCALE ( 0x20000 TO 0x1FFFF)
GLITCH IMPULSE = 2.723nV-s
SAMPLE NUMBER
Figure 16. Digital-to-Analog Glitch Impulse (Negative)
= 5V
05854-005
16
V
= V
REF
DD
TA = 25°C
14
V
3V
=
12
10
TIME (µs)
8
6
4
012 34 567 981
CAPACITANCE (nF)
DD
V
5V
=
DD
Figure 19. Settling Time vs. Capacitive Load
05854-027
0
2.5010
2.5008
2.5006
2.5004
2.5002
2.5000
2.4998
2.4996
AMPLITUDE
2.4994
2.4992
2.4990
2.4988
2.4986
50 100 150 200 250 300 350 400 450 500
0
Figure 17. Digital Feedthrough
20
–30
–40
–50
–60
(dB)
–70
–80
–90
–100
01
123456789
VDD = V
REF
T
= 25°C
A
DAC LOADED WITH MIDSCALE
DIGITAL FEEDTHROUGH
= 0.201nV
SAMPLES × 6.5ns
VDD = 5V
T
= 25°C
A
FULL SCALE LOADED
V
REF
FREQUENCY (kHz)
= 5V
= 2V ±300mV p-p
VDD= V
REF
= 25°C
T
A
DAC LOADED WITH MIDSCALE
V
REF
1
5µV/DIV
05854-020
Figure 20. 0.1 Hz to 10 Hz Output Noise Plot
1000
900
800
700
600
500
400
NOISE (nV/ Hz)
300
200
100
05854-018
0
0
100 1M
Figure 18. Total Harmonic Distortion
= 5V
5s/DIV
VDD = V
T
A
MIDSCALE LOADED
1k 10k 100k
FREQUENCY ( Hz)
Figure 21. Noise Spectral Density
= 25°C
REF
05854-019
= 5V
05854-013
Rev. A | Page 9 of 20
Page 10
AD5680
TERMINOLOGY
Relative Accuracy or Integral Nonlinearity (INL)
For the DAC, relative accuracy or integral nonlinearity is a
measurement of the maximum deviation, in LSBs, from a
straight line passing through the endpoints of the DAC transfer
function.
Figure 4 shows a typical INL vs. code plot.
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of ±1 LSB maximum
ensures monotonicity.
Figure 5 shows a typical DNL vs. code
plot.
Zero-Code Error
Zero-code error is a measurement of the output error when
zero code (0x00000) is loaded to the DAC register. Ideally, the
output should be 0 V. The zero-code error is always positive in
the AD5680 because the output of the DAC cannot go below
0 V. It is due to a combination of the offset errors in the DAC
and the output amplifier. Zero-code error is expressed in mV. A
plot of zero-code error vs. temperature can be seen in
Figure 8.
Full-Scale Error
Full-scale error is a measurement of the output error when fullscale code (0x3FFFF) is loaded to the DAC register. Ideally, the
output should be V
− 1 LSB. Full-scale error is expressed in
DD
percent of full-scale range.
Gain Error
This is a measure of the span error of the DAC. It is the deviation
in slope of the DAC transfer characteristic from ideal, expressed
as a percent of the full-scale range.
Zero-Code Error Drift
This is a measurement of the change in zero-code error with a
change in temperature. It is expressed in μV/°C.
Gain Temperature Coefficient
This is a measurement of the change in gain error with a change
in temperature. It is expressed in (ppm of full-scale range)/°C.
Offset Error
Offset error is a measure of the difference between V
and V
(ideal), expressed in mV in the linear region of the
OUT
(actual)
OUT
transfer function. Offset error is measured on the AD5680 with
Code 2048 loaded in the DAC register. It can be negative or
positive.
DC Power Supply Rejection Ratio (PSRR)
This indicates how the output of the DAC is affected by changes
in the supply voltage. PSRR is the ratio of the change in V
a change in V
in dB. V
for full-scale output of the DAC. It is measured
DD
is held at 2 V, and VDD is varied by ±10%.
REF
OUT
to
Output Voltage Settling Time
This is the amount of time it takes for the output of a DAC to
settle to a specified level for a ¼ to ¾ full-scale input change
and is measured from the 24
th
falling edge of SCLK.
Digital-to-Analog Glitch Impulse
Digital-to-analog glitch impulse is injected into the analog
output when the input code in the DAC register changes state.
It is normally specified as the area of the glitch in nV-s, and is
measured when the digital input code is changed by 1 LSB at
the major carry transition (0x1FFFF to 0x20000). See
Figure 16.
Digital Feedthrough
Digital feedthrough is a measure of the impulse injected into
the analog output of the DAC from the digital inputs of the
DAC, but is measured when the DAC output is not updated. It
is specified in nV-s and measured with a full-scale code change
on the data bus, that is, from all 0s to all 1s and vice versa.
Total Harmonic Distortion (THD)
This is the difference between an ideal sine wave and its
attenuated version using the DAC. The sine wave is used as the
reference for the DAC. The THD is a measurement of the
harmonics present on the DAC output. It is measured in dB.
Noise Spectral Density
This is a measurement of the internally generated random
noise. Random noise is characterized as a spectral density
(voltage per √Hz). It is measured by loading the DAC to
midscale and measuring noise at the output. It is measured in
nV/√Hz.
Figure 21 shows a plot of noise spectral density.
Rev. A | Page 10 of 20
Page 11
AD5680
V
R
THEORY OF OPERATION
DAC SECTION
The AD5680 DAC is fabricated on a CMOS process. The
architecture consists of a string DAC followed by an output
buffer amplifier.
Figure 22 shows a block diagram of the DAC
architecture.
DAC REGISTER
DD
REF (+)
RESISTOR
STRING
REF (–)
GND
Figure 22. DAC Architecture
R
R
OUTPUT
AMPLIFIER
V
FB
V
OUT
05854-030
Because the input coding to the DAC is straight binary, the ideal
output voltage is given by
OUT
⎛
⎜
×=
VV
REF
⎜
⎝
D
262,144
⎞
⎟
⎟
⎠
where D is the decimal equivalent of the binary code that is
loaded to the DAC register. It can range from 0 to 262,143.
RESISTOR STRING
The resistor string section is shown in Figure 23. It is simply a
string of resistors, each of value R. The code loaded to the DAC
register determines at which node on the string the voltage is
tapped off to be fed into the output amplifier. The voltage is
tapped off by closing one of the switches connecting the string
to the amplifier. Because it is a string of resistors, it is guaranteed
monotonic.
R
R
OUTPUT AMPLIFIER
The output buffer amplifier can generate rail-to-rail voltages on
its output, which gives an output range of 0 V to V
. This output
DD
buffer amplifier has a gain of 2 derived from a 50 kΩ resistor
divider network in the feedback path. The output amplifier’s
inverting input is available to the user, allowing for remote
sensing. This V
pin must be connected to V
FB
for normal
OUT
operation. It can drive a load of 2 kΩ in parallel with 1000 pF to
GND. The source and sink capabilities of the output amplifier can
be seen in
Figure 9. The slew rate is 1.5 V/μs with a ¼ to ¾ full-
scale settling time of 10 μs.
INTERPOLATOR ARCHITECTURE
The AD5680 contains a 16-bit DAC with an internal clock
generator and interpolator. The voltage levels generated by the
16-bit, 1 LSB step can be subdivided using the interpolator to
increase the resolution to 18 bits.
The 18-bit input code can be divided into two segments:
16-bit DAC code (DB19 to DB4) and 2-bit interpolator code
(DB3 and DB2). The input to the DAC is switched between a
16-bit code (for example, Code 1023) and a 16-bit code + 1 LSB
(for example, Code 1024). The 2-bit interpolator code determines the duty cycle of the switching and hence the 18-bit
code level. See
Table 5.
18-Bit Code
DB19 to DB2 DB19 to DB4 DB3 DB2
4092 1023 0 0 0
4093 1023 0 1 25%
4094 1023 1 0 50%
4095 1023 1 1 75%
4096 1024 0 0 0
Table 5 for an example.
16-Bit
DAC Code
2-Bit
Interpolator Code
Duty
Cycle
R
TO OUTP UT
AMPLIFI ER
The DAC output voltage is given by the average value of
the waveform switching between 16-bit code (C) and 16-bit
code + 1 (C + 1). The output voltage is a function of the duty
cycle of the switching.
FILTE
OUT
PLANT
75% DUTY CYCLE
50% DUTY CYCLE
25% DUTY CYCLE
05854-032
18-BIT INPUT CODE
18
R
R
05854-031
Figure 23. Resistor String
Rev. A | Page 11 of 20
C
C + 1
16
+1
INTERPO LATOR
2
CLK
MUX
DAC
16
C + 1
C
C + 1
C
C + 1
C
Figure 24. Interpolation Architecture
V
Page 12
AD5680
SERIAL INTERFACE
The AD5680 has a 3-wire serial interface (
DIN) that is compatible with SPI, QSPI, and MICROWIRE
interface standards as well as with most DSPs. See
a timing diagram of a typical write sequence.
The write sequence begins by bringing the
from the DIN line is clocked into the 24-bit shift register on the
falling edge of SCLK. The serial clock frequency can be as high
as 30 MHz, making the AD5680 compatible with high speed
DSPs. On the 24
th
falling clock edge, the last data bit is clocked
in and the programmed function is executed, that is, a change
in DAC register contents occurs. At this stage, the
can be kept low or brought high. In either case, it must be
brought high for a minimum of 33 ns before the next write
sequence so that a falling edge of
write sequence. Because the
when V
= 2 V than it does when VIN = 0.8 V,
IN
SYNC
can initiate the next
SYNC
buffer draws more current
idled low between write sequences for even lower power
operation. As mentioned previously, it must, however, be
brought high again just before the next write sequence.
DB23 (MSB) DB0 (LSB)
SYNC
SYNC
SYNC
, SCLK, and
Figure 2 for
line low. Data
line
SYNC
should be
INPUT SHIFT REGISTER
The input shift register is 24 bits wide (see Figure 25). The first
two bits are don’t care bits. Bit DB21 and Bit DB20 are reserved
bits and should be set to 0. The next 18 bits are the data bits
followed by two don’t care bits. These are transferred to the
DAC register on the 24
th
falling edge of SCLK.
SYNC INTERRUPT
In a normal write sequence, the
least 24 falling edges of SCLK, and the DAC is updated on the
th
24
falling edge. However, if
th
24
falling edge, this acts as an interrupt to the write sequence.
SYNC
The shift register is reset and the write sequence is seen as invalid.
Neither an update of the DAC register contents nor a change in
the operating mode occurs (see
line is kept low for at
SYNC
is brought high before the
Figure 26).
POWER-ON RESET
The AD5680 family contains a power-on reset circuit that
controls the output voltage during power-up. The AD5680-1
DAC output powers up to 0 V, and the AD5680-2 DAC output
powers up to midscale. The output remains there until a valid
write sequence is made to the DAC. This is useful in applications
where it is important to know the output state of the DAC while
it is in the process of powering up.
XX
00 XXD17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
DATA BITS
RESERVED BITS
Figure 25. Input Register Contents
SCLK
SYNC
DIN
DB23 DB23 DB0DB0
INVALID WRITE SEQUENCE:
SYNC HIGH BEFO RE 24
TH
FAL LI NG E DG E
Figure 26.
SYNC
Interrupt Facility
OUTPUT UPDATES O N THE 24THFALL I NG E DG E
VALID WRITE SEQUENCE:
05854-033
05854-034
Rev. A | Page 12 of 20
Page 13
AD5680
MICROPROCESSOR INTERFACING
AD5680 to Blackfin® ADSP-BF53x Interface
Figure 27 shows a serial interface between the AD5680 and
the Blackfin ADSP-BF53x microprocessor. The ADSP-BF53x
processor family incorporates two dual-channel synchronous
serial ports, SPORT1 and SPORT0, for serial and multiprocessor
communications. Using SPORT0 to connect to the AD5680, the
setup for the interface is as follows. DT0PRI drives the DIN pin
of the AD5680, while TSCLK0 drives the SCLK of the part. The
SYNC
is driven from TFS0.
ADSP-BF53x*
TFS0
DTOPRI
TSCLK0
*ADDITIONAL PINS OMIT TED FOR CL ARITY.
Figure 27. AD5680 to Blackfin ADSP-BF53x Interface
AD5680 to 68HC11/68L11 Interface
Figure 28 shows a serial interface between the AD5680 and the
68HC11/68L11 microcontroller. SCK of the 68HC11/68L11
drives the SCLK of the AD5680, while the MOSI output drives
the serial data line of the DAC.
SYNC
The
signal is derived from a port line (PC7). The setup
conditions for correct operation of this interface are as follows:
The 68HC11/68L11 is configured with its CPOL bit as 0 and its
CPHA bit as 1. When data is being transmitted to the DAC, the
SYNC
line is taken low (PC7). When the 68HC11/68L11 is
configured this way, data appearing on the MOSI output is valid
on the falling edge of SCK. Serial data from the 68HC11/68L11
is transmitted in 8-bit bytes with only eight falling clock edges
occurring in the transmit cycle. Data is transmitted MSB first. To
load data to the AD5680, PC7 is left low after the first eight bits
are transferred, and a second serial write operation is performed
to the DAC; PC7 is taken high at the end of this procedure.
68HC11/68L11*
PC7
SCK
MOSI
*ADDITIONAL PINS OMIT TED FOR CL ARITY.
Figure 28. AD5680 to 68HC11/68L11 Interface
AD5680*
SYNC
DIN
SCLK
AD5680*
SYNC
SCLK
DIN
05854-035
05854-036
AD5680 to 80C51/80L51 Interface
Figure 29 shows a serial interface between the AD5680 and the
80C51/80L51 microcontroller. The setup for the interface is as
follows. TxD of the 80C51/80L51 drives SCLK of the AD5680,
while RxD drives the serial data line of the part. The
SYNC
signal is again derived from a bit-programmable pin on the port.
In this case, port line P3.3 is used. When data is to be transmitted
to the AD5680, P3.3 is taken low. The 80C51/80L51 transmits
data in 8-bit bytes only; thus, only eight falling clock edges occur
in the transmit cycle. To load data to the DAC, P3.3 is left low
after the first eight bits are transmitted, and a second write cycle
is initiated to transmit the second byte of data. P3.3 is taken
high following the completion of this cycle. The 80C51/80L51
outputs the serial data in a format that has the LSB first. The
AD5680 must receive data with the MSB first. The 80C51/80L51
transmit routine should take this into account.
80C51/80L51*
P3.3
TxD
RxD
*ADDITIONA L PINS OMITTED FOR CLARITY.
Figure 29. AD5680 to 80C51/80L51 Interface
AD5680*
SYNC
SCLK
DIN
AD5680 to MICROWIRE Interface
Figure 30 shows an interface between the AD5680 and any
MICROWIRE-compatible device. Serial data is shifted out on
the falling edge of the serial clock and is clocked into the AD5680
on the rising edge of the SK.
MICROWIRE*
CS
SK
SO
*ADDITIONA L PINS OMITTED FOR CLARITY.
Figure 30. AD5680 to MICROWIRE Interface
AD5680*
SYNC
SCLK
DIN
05854-037
05854-038
Rev. A | Page 13 of 20
Page 14
AD5680
APPLICATIONS
CLOSED-LOOP APPLICATIONS
The AD5680 is suitable for closed-loop low bandwidth applications. Ideally, the system bandwidth acts as a filter on the DAC
output. (See the
prefiltering and postfiltering.) The DAC updates at the
interpolation frequency of 10 kHz.
CONTROLL ER
Filter section for details of the DAC output
PLANT
DAC
2
1
CODE 4092
Δ: 2.09ms
@: 1.28ms
CODE 4094
ADC
05854-039
Figure 31. Typical Closed-Loop Application
FILTER
The DAC output voltage for code transition 4092 to 4094 can be
Figure 32. This is the DAC output unfiltered. Code 4092
seen in
does not have any interpolation but Code 4094 has interpolation
with a 50% duty cycle (see
output with a 50 Hz passive RC filter and
output with a 300 Hz passive RC filter. An RC combination of
320 kΩ and 10 nF has been used to achieve the 50 Hz cutoff
frequency, and an RC combination of 81 kΩ and 10 nF has
been used to achieve the 300 Hz cutoff frequency.
Table 5). Figure 33 shows the DAC
Figure 34 shows the
CH1 20.0µV CH2 5V
M 500µs CH2 1.4V
05854-025
Figure 33. DAC Output with 50 Hz Filter on Output
Δ: 2.09ms
2
1
CODE 4092
CH1 20.0µV CH2 5V
M 500µs CH2 1.4V
Figure 34. DAC Output with 300 Hz Filter on Output
@: 1.28ms
CODE 4094
05854-026
1
CH1 20.0µV
CODE 4092
M 500µs CH4 0V
CODE 4094
05854-024
Figure 32. DAC Output Unfiltered
Rev. A | Page 14 of 20
Page 15
AD5680
CHOOSING A REFERENCE FOR THE AD5680
To achieve the optimum performance from the AD5680, choose
a precision voltage reference carefully. The AD5680 has only
one reference input, V
used to supply the positive input to the DAC. Therefore, any
error in the reference is reflected in the DAC.
When choosing a voltage reference for high accuracy applications, the sources of error are initial accuracy, ppm drift, longterm drift, and output voltage noise. Initial accuracy on the
output voltage of the DAC leads to a full-scale error in the DAC.
To minimize these errors, a reference with high initial accuracy
is preferred. In addition, choosing a reference with an output
trim adjustment, such as the
to trim out system errors by setting a reference voltage to a
voltage other than the nominal. The trim adjustment can also
be used at temperature to trim out any error.
Table 6. Partial List of Precision References for Use with the AD5680
Part No. Initial Accuracy (mV max) Temperature Drift (ppm/°C max) 0.1 Hz to 10 Hz Noise (μV p-p typ) V
ADR425 ±2 3 3.4 5
ADR395 ±6 25 5 5
REF195 ±2 5 50 5
. The voltage on the reference input is
REF
ADR425, allows a system designer
Long-term drift is a measurement of how much the reference
drifts over time. A reference with a tight long-term drift specification ensures that the overall solution remains relatively stable
during its entire lifetime.
The temperature coefficient of a reference’s output voltage
affects INL, DNL, and TUE. A reference with a tight temperature
coefficient specification should be chosen to reduce temperature
dependence of the DAC output voltage in ambient conditions.
In high accuracy applications, which have a relatively low noise
budget, reference output voltage noise needs to be considered. It
is important to choose a reference with as low an output noise
voltage as is practical for the system noise resolution required.
Precision voltage references such as the
ADR425 produce low
output noise in the 0.1 Hz to 10 Hz range. Examples of recommended precision references for use as supply to the AD5680
are shown in the
Table 6 .
(V)
OUT
Rev. A | Page 15 of 20
Page 16
AD5680
V
V
S
USING A REFERENCE AS A POWER SUPPLY FOR THE AD5680
Because the supply current required by the AD5680 is extremely
low, an alternative option is to use a voltage reference to supply
the required voltage to the part (see
Figure 35). This is especially
useful if the power supply is quite noisy, or if the system supply
voltages are at some value other than 5 V, for example, 15 V.
The voltage reference outputs a steady supply voltage for the
AD5680; see
Table 6 for a suitable reference. If the low dropout
REF195 is used, it must supply 325 μA of current to the AD5680,
with no load on the output of the DAC. When the DAC output
is loaded, the
REF195 also needs to supply the current to the
load. The total current required (with a 5 kΩ load on the DAC
output) is
325 μA + (5 V/5 kΩ) = 1.33 mA
The load regulation of the
REF195 is typically 2 ppm/mA,
which results in a 2.7 ppm (13.5 μV) error for the 1.33 mA
current drawn from it. This corresponds to a 0.177 LSB error.
15
5V
V
DD
AD5680
250µA
V
REF
V
OUT
= 0V TO 5
05854-040
3-WIRE
SERIAL
INTERFACE
REF195
SYNC
SCLK
DIN
Figure 35. REF195 as Power Supply to the AD5680
USING THE AD5680 WITH A GALVANICALLY ISOLATED INTERFACE
In process-control applications in industrial environments, it is
often necessary to use a galvanically isolated interface to protect
and isolate the controlling circuitry from any hazardous commonmode voltages that might occur in the area where the DAC is
functioning. Isocouplers provide isolation in excess of 3 kV. The
AD5680 uses a 3-wire serial logic interface, so the ADuM130x
3-channel digital isolator provides the required isolation (see
Figure 36). The power supply to the part also needs to be isolated,
which is done by using a transformer. On the DAC side of the
transformer, a 5 V regulator provides the 5 V supply required
for the AD5680.
POWER
CLK
DATA
V
IA
ADuM130x
V
SDI
IB
V
IC
Figure 36. AD5680 with a Galvanically Isolated Interface
POWER SUPPLY BYPASSING AND GROUNDING
When accuracy is important in a circuit, it is helpful to carefully
consider the power supply and ground return layout on the board.
The printed circuit board containing the AD5680 should have
separate analog and digital sections, each having its own area of
the board. If the AD5680 is in a system where other devices
require an AGND-to-DGND connection, the connection should
be made at one point only. This ground point should be as close
as possible to the AD5680.
The power supply to the AD5680 should be bypassed with 10 μF
and 0.1 μF capacitors. The capacitors should be located as close
as possible to the device, with the 0.1 μF capacitor ideally right
up against the device. The 10 μF capacitors should be the tantalum bead type. It is important that the 0.1 μF capacitor has low
effective series resistance (ESR) and effective series inductance
(ESI), for example, common ceramic types of capacitors. This
0.1 μF capacitor provides a low impedance path to ground for
high frequencies caused by transient currents due to internal
logic switching.
The power supply line itself should have as large a trace as
possible to provide a low impedance path and to reduce glitch
effects on the supply line. Clocks and other fast switching digital
signals should be shielded from other parts of the board by
digital ground. Avoid crossover of digital and analog signals if
possible. When traces cross on opposite sides of the board,
ensure that they run at right angles to each other to reduce
feedthrough effects on the board. The best board layout technique is the microstrip technique where the component side of
the board is dedicated to the ground plane only and the signal
traces are placed on the solder side. However, this is not always
possible with a 2-layer board.
REGULATOR
V
OA
V
OB
V
OC
5V
10µF
0.1µF
V
SCLK
SYNC
DIN
DD
AD5680
GND
V
OUT
05854-041
Rev. A | Page 16 of 20
Page 17
AD5680
OUTLINE DIMENSIONS
2.90 BSC
2
1.95
BSC
56
0.65 BSC
2.80 BSC
1.45 MAX
SEATING
PLANE
0.22
0.08
8°
4°
0°
0.60
0.45
0.30
847
1.60 BSC
13
PIN 1
INDICATOR
1.30
1.15
0.90
0.15 MAX
0.38
0.22
COMPLIANT TO JEDEC STANDARDS MO-178-BA
Figure 37. 8-Lead Small Outline Transistor Package [SOT-23]
(RJ-8)
Dimensions shown in millimeters
ORDERING GUIDE
Package
Model Temperature Range
AD5680BRJZ-1500RL7
AD5680BRJZ-1REEL7
AD5680BRJZ-2500RL7
AD5680BRJZ-2REEL7
1
−40°C to +105°C 8-Lead SOT-23 RJ-8 Zero ±64 LSB INL D3C
1
−40°C to +105°C 8-Lead SOT-23 RJ-8 Zero ±64 LSB INL D3C
1
−40°C to +105°C 8-Lead SOT-23 RJ-8 Midscale ±64 LSB INL D3D
1
−40°C to +105°C 8-Lead SOT-23 RJ-8 Midscale ±64 LSB INL D3D
Description
EVAL-AD5680EB Evaluation Board
1
Z = RoHS Compliant Part.
Package
Option
Power-On
Reset to Code
Accuracy Branding
Rev. A | Page 17 of 20
Page 18
AD5680
NOTES
Rev. A | Page 18 of 20
Page 19
AD5680
NOTES
Rev. A | Page 19 of 20
Page 20
AD5680
NOTES
©2006–2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05854-0-3/07(A)
T
Rev. A | Page 20 of 20
TTT
Loading...