Datasheet AD566ATD, AD566ASD, AD566AKD, AD566AJD, AD566A Datasheet (Analog Devices)

High Speed 12-Bit

a

FEATURES
Single Chip Construction
Very High-Speed Settling to 1/2 LSB

AD565A: 250 ns max

AD566A: 350 ns max
Full-Scale Switching Time: 30 ns
Guaranteed for Operation with ⴞ12 V Supplies:

AD565A with –12 V Supply: AD566A
Linearity Guaranteed Over Temperature:

1/2 LSB max (K, T Grades)
Monotonicity Guaranteed Over Temperature
Low Power: AD566A = 180 mW max;

AD565A = 225 mW max

Use with On-Board High-Stability Reference (AD565A)

or with External Reference (AD566A)
Low Cost
MlL-STD-883-Compliant Versions Available

PRODUCT DESCRIPTION

The AD565A and AD566A are fast 12-bit digital-to-analog
converters that incorporate the latest advances in analog circuit
design to achieve high speeds at low cost.

The AD565A and AD566A use 12 precision, high-speed bipolar
current-steering switches, control amplifier and a laser-trimmed
thin-film resistor network to produce a very fast, high accuracy
analog output current. The AD565A also includes a buried
Zener reference that features low-noise, long-term stability and
temperature drift characteristics comparable to the best discrete
reference diodes.

The combination of performance and flexibility in the AD565A
and AD566A has resulted from major innovations in circuit
design, an important new high-speed bipolar process, and con­tinuing advances in laser-wafer-trimming techniques (LWT).
The AD565A and AD566A have a 10–90% full-scale transition
time less than 35 ns and settle to within ±1/2 LSB in 250 ns
max (350 ns for AD566A). Both are laser-trimmed at the wafer
level to ± 1/8 LSB typical linearity and are specified to ± 1/4 LSB
max error (K and T grades) at +25°C. High speed and accuracy
make the AD565A and AD566A the ideal choice for high-speed
display drivers as well as fast analog-to-digital converters.

The laser trimming process which provides the excellent linear­ity is also used to trim both the absolute value and the tempera­ture coefficient of the reference of the AD565A resulting in a
typical full-scale gain TC of 10 ppm/°C. When tighter TC per­formance is required or when a system reference is available, the
AD566A may be used with an external reference.

*Covered by Patent Nos.: 3,803,590; RE 28,633; 4,213,806; 4,136,349;

4,020,486; 3,747,088.

REV. D

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

Monolithic D/A Converters

AD565A*/AD566A*

FUNCTIONAL BLOCK DIAGRAMS

10V

19.95k⍀

20k⍀

–V

EE

–V

EE

V

CC

AD565A

0.5mA

I

REF

I

OUT

4 ⴛ I

CODE INPUT

POWER

GND

AD566A

0.5mA

I

REF

I

OUT

4 ⴛ I

CODE INPUT

POWER

MSB

GND

=

REF

=

REF

BIPOLAR OFF

9.95k⍀

DAC

ⴛ CODE

LSBMSB

BIPOLAR OFF

9.95k⍀

DAC

ⴛ CODE

LSB

20V SPAN

5k⍀

10V SPAN

5k⍀

I

O

I

O

DAC OUT

8k⍀

20V SPAN

5k⍀

10V SPAN

5k⍀

DAC OUT

8k⍀

REF OUT

REF

IN

REF

GND

19.95k⍀

REF

IN

20k⍀

REF

GND

AD565A and AD566A are available in four performance
grades. The J and K are specified for use over the 0°C to +70°C
temperature range while the S and T grades are specified for the
–55°C to +125°C range. The D grades are all packaged in a
24-lead, hermetically sealed, ceramic, dual-in-line package. The
JR grade is packaged in a 28-lead plastic SOIC.

PRODUCT HIGHLIGHTS

1. The wide output compliance range of the AD565A and
AD566A are ideally suited for fast, low noise, accurate volt­age output configurations without an output amplifier.

2. The devices incorporate a newly developed, fully differential,
nonsaturating precision current switching cell structure
which combines the dc accuracy and stability first developed
in the AD562/3 with very fast switching times and an
optimally-damped settling characteristic.

3. The devices also contain SiCr thin film application resistors
which can be used with an external op amp to provide a
precision voltage output or as input resistors for a successive
approximation A/D converter. The resistors are matched to
the internal ladder network to guarantee a low gain tempera­ture coefficient and are laser-trimmed for minimum
full-scale and bipolar offset errors.

4. The AD565A and AD566A are available in versions compli­ant with MIL-STD-883. Refer to the Analog Devices Mili­tary Products Databook or current /883B data sheet for
detailed specifications.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 2000

AD565A–SPECIFICATIONS

(TA = +25ⴗC, VCC = +15 V, VEE = +15 V, unless otherwise noted.)

Model Min Typ Max Min Typ Max Units

AD565AJ AD565AK

DATA INPUTS1 (Pins 13 to 24)
TTL or 5 Volt CMOS

Input Voltage

Bit ON Logic “1” +2.0 +5.5 +2.0 +5.5 V
Bit OFF Logic “0” +0.8 +0.8 V

Logic Current (Each Bit)

Bit ON Logic “1” +120 +300 +120 +300 µA

Bit OFF Logic “0” +35 +100 +35 +100 µA
RESOLUTION 12 12 Bits
OUTPUT

Current

Unipolar (All Bits On) –1.6 –2.0 –2.4 –1.6 –2.0 –2.4 mA

Bipolar (All Bits On or Off) ⴞ0.8 ± 1.0 ⴞ1.2 ⴞ0.8 ± 1.0 ⴞ1.2 mA

Resistance (Exclusive of Span Resistors) 6 8 10 6 8 10 kΩ
Offset

Unipolar 0.01 0.05 0.01 0.05 % of F.S. Range

Bipolar (Figure 3, R2 = 50 Ω Fixed) 0.05 0.15 0.05 0.1 % of F.S. Range

Capacitance 25 25 pF
Compliance Voltage

T

MIN

to T

MAX

–1.5 +10 –1.5 +10 V

ACCURACY (Error Relative to

Full Scale) +25°C ± 1/4 ⴞ1/2 ± 1/8 ⴞ1/4 LSB

(0.006) (0.012) (0.003) (0.006) % of F.S. Range

T

MIN

to T

MAX

± 1/2 ⴞ3/4 ± 1/4 ⴞ1/2 LSB
(0.012) (0.018) (0.006) (0.012) % of F.S. Range

DIFFERENTIAL NONLINEARITY

+25°C ± 1/2 ⴞ3/4 ± 1/4 ⴞ1/2 LSB
T

MIN

to T

MAX

MONOTONICITY GUARANTEED MONOTONICITY GUARANTEED

TEMPERATURE COEFFICIENTS

With Internal Reference

Unipolar Zero 1 2 1 2 ppm/°C

Bipolar Zero 5 10 5 10 ppm/°C

Gain (Full Scale) 15 50 10 20 ppm/°C

Differential Nonlinearity 2 2 ppm/°C
SETTLING TIME TO 1/2 LSB

All Bits ON-to-OFF or OFF-to-ON 250 400 250 400 ns

FULL-SCALE TRANSITION

10% to 90% Delay plus Rise Time 15 30 15 30 ns
90% to 10% Delay plus Fall Time 30 50 30 50 ns

TEMPERATURE RANGE

Operating 0 +70 0 +70 °C
Storage –65 +150 –65 +150 °C

POWER REQUIREMENTS

VCC, +11.4 to +16.5 V de 3 5 3 5 mA
VEE, –11.4 to –16.5 V dc –12 –18 –12 –18 mA

POWER SUPPLY GAIN SENSITIVITY

2

VCC = +11.4 to +16.5 V dc 3 10 3 10 ppm of F.S./%
VEE = –11.4 to –16.5 V dc 15 25 15 25 ppm of F.S./%

PROGRAMMABLE OUTPUT RANGES

(See Figures 2, 3, 4) 0 to +5 0 to +5 V

–2.5 to +2.5 –2.5 to +2.5 V
0 to +10 0 to +10 V
–5 to +5 –5 to +5 V
–10 to +10 –10 to +10 V

EXTERNAL ADJUSTMENTS

Gain Error with Fixed 50 Ω

Resistor for R2 (Figure 2) ± 0.1 ⴞ0.25 ± 0.1 ⴞ0.25 % of F.S. Range

Bipolar Zero Error with Fixed

50 Ω Resistor for R1 (Figure 3) ±0.05 ⴞ0.15 ± 0.05 ± 0.1 % of F.S. Range

Gain Adjustment Range (Figure 2) ±0.25 ±0.25 % of F.S. Range
Bipolar Zero Adjustment Range ± 0.15 ±0.15 % of F.S. Range

REFERENCE INPUT

Input Impedance 15 20 25 15 20 25 kΩ

REFERENCE OUTPUT

Voltage 9.90 10.00 10.10 9.90 10.00 10.10 V
Current (Available for External Loads)31.5 2.5 1.5 2.5 mA

POWER DISSIPATION 225 345 225 345 mW

NOTES

1

The digital inputs are guaranteed but not tested over the operating temperature range.

2

The power supply gain sensitivity is tested in reference to a VCC, V

3

For operation at elevated temperatures the reference cannot supply current for external loads. It, therefore, should be buffered if additional loads are to be supplied.

Specifications subject to change without notice.

of ± 15 V dc.

EE

–2–

REV. D

AD565A/AD566A

Model Min Typ Max Min Typ Max Units

AD565AS AD565AT

DATA INPUTS1 (Pins 13 to 24)

TTL or 5 Volt CMOS

Input Voltage

Bit ON Logic “1” +2.0 +5.5 +2.0 +5.5 V
Bit OFF Logic “0” +0.8 +0.8 V

Logic Current (Each Bit)

Bit ON Logic “1” +120 +300 +120 +300 µA

Bit OFF Logic “0” +35 +100 +35 +100 µA
RESOLUTION 12 12 Bits
OUTPUT

Current

Unipolar (All Bits On) –1.6 –2.0 –2.4 –1.6 –2.0 –2.4 mA

Bipolar (All Bits On or Off) ⴞ0.8 ± 1.0 ⴞ1.2 ⴞ0.8 ± 1.0 ⴞ1.2 mA

Resistance (Exclusive of Span Resistors) 6 8 10 6 8 10 kΩ
Offset

Unipolar 0.01 0.05 0.01 0.05 % of F.S. Range

Bipolar (Figure 3, R2 = 50 Ω Fixed) 0.05 0.15 0.05 0.1 % of F.S. Range

Capacitance 25 25 pF
Compliance Voltage

T

MIN

to T

MAX

–1.5 +10 –1.5 +10 V

ACCURACY (Error Relative to

Full Scale) +25°C ± 1/4 ⴞ1/2 ± 1/8 ⴞ1/4 LSB

(0.006) (0.012) (0.003) (0.006) % of F.S. Range

T

MIN

to T

MAX

± 1/2 ⴞ3/4 ± 1/4 ⴞ1/2 LSB
(0.012) (0.018) (0.006) (0.012) % of F.S. Range

DIFFERENTIAL NONLINEARITY

+25°C ± 1/2 ⴞ3/4 ± 1/4 ⴞ1/2 LSB
T

MIN

to T

MAX

MONOTONICITY GUARANTEED MONOTONICITY GUARANTEED

TEMPERATURE COEFFICIENTS

With Internal Reference

Unipolar Zero 1 2 1 2 ppm/°C

Bipolar Zero 5 10 5 10 ppm/°C

Gain (Full Scale) 15 30 10 15 ppm/°C

Differential Nonlinearity 2 2 ppm/°C
SETTLING TIME TO 1/2 LSB

All Bits ON-to-OFF or OFF-to-ON 250 400 250 400 ns

FULL-SCALE TRANSITION

10% to 90% Delay plus Rise Time 15 30 15 30 ns
90% to 10% Delay plus Fall Time 30 50 30 50 ns

TEMPERATURE RANGE

Operating –55 +125 –55 +125 °C
Storage –65 +150 –65 +150 °C

POWER REQUIREMENTS

VCC, +11.4 to +16.5 V dc 3 5 3 5 mA
VEE, –11.4 to –16.5 V dc –12 –18 –12 –18 mA

POWER SUPPLY GAIN SENSITIVITY

2

VCC = +11.4 to +16.5 V dc 3 10 3 10 ppm of F.S./%
VEE = –11.4 to –16.5 V dc 15 25 15 25 ppm of F.S./%

PROGRAMMABLE OUTPUT RANGES

(See Figures 2, 3, 4) 0 to +5 0 to +5 V

–2.5 to +2.5 –2.5 to +2.5 V
0 to +10 0 to +10 V
–5 to +5 –5 to +5 V
–10 to +10 –10 to +10 V

EXTERNAL ADJUSTMENTS

Gain Error with Fixed 50 Ω

Resistor for R2 (Figure 2) ±0.1 ⴞ0.25 ± 0.1 ⴞ0.25 % of F.S. Range

Bipolar Zero Error with Fixed

50 Ω Resistor for R1 (Figure 3) ± 0.05 ⴞ0.15 ± 0.05 ⴞ0.1 % of F.S. Range

Gain Adjustment Range (Figure 2) ± 0.25 ±0.25 % of F.S. Range
Bipolar Zero Adjustment Range ±0.15 ±0.15 % of F.S. Range

REFERENCE INPUT

Input Impedance 15 20 25 15 20 25 kΩ

REFERENCE OUTPUT

Voltage 9.90 10.00 10.10 9.90 10.00 10.10 V
Current (Available for External Loads)31.5 2.5 1.5 2.5 mA

POWER DISSIPATION 225 345 225 345 mW

Specifications shown in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. All min
and max specifications are guaranteed, although only those shown in boldface are tested on all production units.

Specification subject to change without notice.

REV. D

–3–

AD566A–SPECIFICATIONS

(TA = +25ⴗC, VEE = –15 V, unless otherwise noted)

Model Min Typ Max Min Typ Max Units

DATA INPUTS1 (Pins 13 to 24)
TTL or 5 Volt CMOS

Input Voltage

Bit ON Logic “1” +2.0 +5.5 +2.0 +5.5 V
Bit OFF Logic “0” 0 +0.8 0 +0.8 V

Logic Current (Each Bit)

Bit ON Logic “1” +120 +300 +120 +300 µA
Bit OFF Logic “0” +35 +100 +35 +100 µA

AD566AJ AD566AK

RESOLUTION 12 12 Bits
OUTPUT

Current

Unipolar (All Bits On) –1.6 –2.0 –2.4 –1.6 –2.0 –2.4 mA

Bipolar (All Bits On or Off) ⴞ0.8 ± 1.0 ⴞ1.2 ⴞ0.8 ± 1.0 ⴞ 1.2 mA

Resistance (Exclusive of Span Resistors) 6 8 10 6 8 10 kΩ
Offset

Unipolar (Adjustable to Zero per Figure 3) 0.01 0.05 0.01 0.05 % of F.S. Range
Bipolar (Figure 4, R1 and R2 = 50 Ω Fixed) 0.05 0.15 0.05 0.1 % of F.S. Range

Capacitance 25 25 pF
Compliance Voltage

T

to T

MIN

to T

to T

MAX

MAX

MAX

2

ACCURACY (Error Relative to

Full Scale) +25°C ± 1/4 ⴞ1/2 ± 1/8 ⴞ1/4 LSB

T

MIN

DIFFERENTIAL NONLINEARITY

+25°C ± 1/2 ⴞ3/4 ± 1/4 ⴞ1/2 LSB
T

MIN

TEMPERATURE COEFFICIENTS

Unipolar Zero 1 2 1 2 ppm/°C
Bipolar Zero 5 10 5 10 ppm/°C
Gain (Full Scale) 7 10 3 5 ppm/°C
Differential Nonlinearity 2 2 ppm/°C

SETTLING TIME TO 1/2 LSB

All Bits ON-to-OFF or OFF-to-ON (Figure 8) 250 350 250 350 ns

FULL-SCALE TRANSITION

10% to 90% Delay plus Rise Time 15 30 15 30 ns
90% to 10% Delay plus Fall Time 30 50 30 50 ns

POWER REQUIREMENTS

VEE, –11.4 to –16.5 V dc –12 –18 –12 –18 mA

POWER SUPPLY GAIN SENSITIVITY

VEE = –11.4 to –16.5 V dc 15 25 15 25 ppm of F.S./%

PROGRAMMABLE OUTPUT RANGES

(see Figures 3, 4, 5) 0 to +5 0 to +5 V

EXTERNAL ADJUSTMENTS

Gain Error with Fixed 50 Ω

Resistor for R2 (Figure 3) ± 0.1 ⴞ 0.25 ± 0.1 ⴞ 0.25 % of F.S. Range

Bipolar Zero Error with Fixed

50 Ω Resistor for R1 (Figure 4) ± 0.05 ⴞ0.15 ± 0.05 ⴞ0.1 % of F.S. Range

Gain Adjustment Range (Figure 3) ± 0.25 ±0.25 % of F.S. Range
Bipolar Zero Adjustment Range ± 0.15 ± 0.15 % of F.S. Range

REFERENCE INPUT

Input Impedance 15 20 25 15 20 25 kΩ

–1.5 +10 –1.5 +10 V

(0.006) (0.012) (0.003) (0.006) % of F.S. Range
± 1/2 ⴞ3/4 ± 1/4 ⴞ1/2 LSB
(0.012) (0.018) (0.006) (0.012) % of F.S. Range

MONOTONICITY GUARANTEED MONOTONICITY GUARANTEED

–2.5 to +2.5 –2.5 to +2.5 V
0 to +10 0 to +10 V
–5 to +5 –5 to +5 V
–10 to +10 –10 to +10 V

POWER DISSIPATION 180 300 180 300 mW
MULTIPLYING MODE PERFORMANCE (All Models)

Quadrants Two (2): Bipolar Operation at Digital Input Only
Reference Voltage +1 V to +10 V, Unipolar
Accuracy 10 Bits (± 0.05% of Reduced F.S.) for 1 V dc Reference Voltage
Reference Feedthrough (Unipolar Mode,

All Bits OFF, and 1 V to +10 V [p-p], Sine Wave
Frequency for 1/2 LSB [p-p] Feedthrough) 40 kHz typ

Output Slew Rate 10%–90% 5 mA/µs

Output Settling Time (All Bits ON and a 0 V–10 V

Step Change in Reference Voltage) 1.5 µs to 0.01% F.S.

CONTROL AMPLIFIER

Full Power Bandwidth 300 kHz
Small-Signal Closed-Loop Bandwidth 1.8 MHz

NOTES

1

The digital input levels are guaranteed but not tested over the temperature range.

2

The power supply gain sensitivity is tested in reference to a VEE of –1.5 V dc.

Specifications subject to change without notice.

90%–10% 1 mA/µs

–4–

REV. D

AD565A/AD566A

Model Min Typ Max Min Typ Max Units

DATA INPUTS1 (Pins 13 to 24)
TTL or 5 Volt CMOS

Input Voltage

Bit ON Logic “1” +2.0 +5.5 +2.0 +5.5 V
Bit OFF Logic “0” 0 +0.8 0 +0.8 V

Logic Current (Each Bit)

Bit ON Logic “1” +120 +300 +120 +300 µA
Bit OFF Logic “0” +35 +100 +35 +100 µA

AD566AS AD566AT

RESOLUTION 12 12 Bits
OUTPUT

Current

Unipolar (All Bits On) –1.6 –2.0 –2.4 –1.6 –2.0 –2.4 mA

Bipolar (All Bits On or Off) ⴞ0.8 ± 1.0 ⴞ 1.2 ⴞ0.8 ± 1.0 ⴞ1.2 mA
Resistance (Exclusive of Span Resistors) 6 8 10 6 8 10 kΩ
Offset

Unipolar (Adjustable to Zero per Figure 3) 0.01 0.05 0.01 0.05 % of F.S. Range

Bipolar (Figure 4, R1 and R2 = 50 Ω Fixed) 0.05 0.15 0.05 0.1 % of F.S. Range
Capacitance 25 25 pF
Compliance Voltage

T

to T

MIN

to T

to T

MAX

MAX

MAX

2

ACCURACY (Error Relative to

Full Scale) +25°C ± 1/4 ⴞ1/2 ± 1/8 ⴞ1/4 LSB

T

MIN

DIFFERENTIAL NONLINEARITY

+25°C ± 1/2 ⴞ3/4 ± 1/4 ⴞ1/2 LSB
T

MIN

TEMPERATURE COEFFICIENTS

Unipolar Zero 1 2 1 2 ppm/°C
Bipolar Zero 5 10 5 10 ppm/°C
Gain (Full Scale) 7 10 3 5 ppm/°C
Differential Nonlinearity 2 2 ppm/°C

SETTLING TIME TO 1/2 LSB

All Bits ON-to-OFF or OFF-to-ON (Figure 8) 250 350 250 350 ns

FULL-SCALE TRANSITION

10% to 90% Delay plus Rise Time 15 30 15 30 ns
90% to 10% Delay plus Fall Time 30 50 30 50 ns

POWER REQUIREMENTS

VEE, –11.4 to –16.5 V dc –12 –18 –12 –18 mA

POWER SUPPLY GAIN SENSITIVITY

VEE = –11.4 to –16.5 V dc 15 25 15 25 ppm of F.S./%

PROGRAMMABLE OUTPUT RANGES

(see Figures 3, 4, 5) 0 to +5 0 to +5 V

EXTERNAL ADJUSTMENTS

Gain Error with Fixed 50 Ω

Resistor for R2 (Figure 3) ± 0.1 ⴞ 0.25 ± 0.1 ⴞ 0.25 % of F.S. Range
Bipolar Zero Error with Fixed

50 Ω Resistor for R1 (Figure 4) ± 0.05 ⴞ 0.15 ± 0.05 ⴞ0.1 % of F.S. Range
Gain Adjustment Range (Figure 3) ± 0.25 ±0.25 % of F.S. Range
Bipolar Zero Adjustment Range ± 0.15 ±0.15 % of F.S. Range

REFERENCE INPUT

Input Impedance 15 20 25 15 20 25 kΩ

–1.5 +10 –1.5 +10 V

(0.006) (0.012) (0.003) (0.006) % of F.S. Range
± 1/2 ⴞ3/4 ± 1/4 ⴞ1/2 LSB
(0.012) (0.018) (0.006) (0.012) % of F.S. Range

MONOTONICITY GUARANTEED MONOTONICITY GUARANTEED

–2.5 to +2.5 –2.5 to +2.5 V
0 to +10 0 to +10 V
–5 to +5 –5 to +5 V
–10 to +10 –10 to +10 V

POWER DISSIPATION 180 300 180 300 mW
MULTIPLYING MODE PERFORMANCE (All Models)

Quadrants Two (2): Bipolar Operation at Digital Input Only
Reference Voltage +1 V to +10 V, Unipolar
Accuracy 10 Bits (± 0.05% of Reduced F.S.) for 1 V dc Reference Voltage
Reference Feedthrough (Unipolar Mode,

All Bits OFF, and 1 V to +10 V [p-p], Sine Wave

Frequency for l/2 LSB [p-p] Feedthrough) 40 kHz typ
Output Slew Rate 10%–90% 5 mA/µs

Output Settling Time (All Bits ON and a 0 V–10 V

Step Change in Reference Voltage) 1.5 µs to 0.01% F.S.

CONTROL AMPLIFIER

Full Power Bandwidth 300 kHz
Small-Signal Closed-Loop Bandwidth 1.8 MHz

NOTES
Specifications shown in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. All min and max
specifications are guaranteed, although only those shown in boldface are tested on all production units.

Specification subject to change without notice.

90%–10% 1 mA/µs

REV. D

–5–

AD565A/AD566A

ABSOLUTE MAXIMUM RATINGS

VCC to Power Ground . . . . . . . . . . . . . . . . . . . . . 0 V to +18 V

to Power Ground (AD565A) . . . . . . . . . . . . 0 V to –18 V

V

EE

Voltage on DAC Output (Pin 9) . . . . . . . . . . . . –3 V to +12 V

Digital Inputs (Pins 13 to 24) to

Power Ground . . . . . . . . . . . . . . . . . . . . . . –1.0 V to +7.0 V

REF IN to Reference Ground . . . . . . . . . . . . . . . . . . . . ±12 V

Bipolar Offset to Reference Ground . . . . . . . . . . . . . . . ±12 V

10 V Span R to Reference Ground . . . . . . . . . . . . . . . . ± 12 V

20 V Span R to Reference Ground . . . . . . . . . . . . . . . . ± 24 V

REF OUT (AD565A) . . . . . Indefinite Short to Power Ground

Momentary Short to V

CC

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . 1000 mW

AD565A ORDERING GUIDE

Max Gain Linearity
T.C. (ppm Temperature Error Max Package

1

Model

AD565AJD 50 0°C to +70°C ± 1/2 LSB Ceramic (D-24)
AD565AJR 50 0°C to +70°C ± 1/2 LSB SOIC (R-28)
AD565AKD 20 0°C to +70°C ± 1/4 LSB Ceramic (D-24)
AD565ASD 30 –55°C to +125°C ± 1/2 LSB Ceramic (D-24)
AD565ATD 15 –55°C to +125°C ± 1/4 LSB Ceramic (D-24)

NOTES

1

For details on grade and package offerings screened in accordance with MIL­STD-883, refer to the Analog Devices Military Products Databook or current/
883B data sheet.

2

D = Ceramic DIP, R = SOIC.

of F.S./ⴗC) Range @ +25ⴗC Options

2

AD566A ORDERING GUIDE

Max Gain Linearity
T.C. (ppm Temperature Error Max Package

1

Model

AD566AJD 10 0°C to +70°C ± 1/2 LSB Ceramic (D-24)
AD566AKD 3 0°C to +70°C ± 1/4 LSB Ceramic (D-24)
AD566ASD 10 –55°C to +125°C ± 1/2 LSB Ceramic (D-24)
AD566ATD 3 –55°C to +125°C ± 1/4 LSB Ceramic (D-24)

NOTES

1

For details on grade and package offerings screened in accordance with MIL­STD-883, refer to the Analog Devices Military Products Databook or current/
883B data sheet.

2

D = Ceramic DIP.

of F.S./ⴗC) Range @ +25ⴗC Option

2

GROUNDING RULES

The AD565A and AD566A bring out separate reference and
power grounds to allow optimum connections for low noise and
high-speed performance. These grounds should be tied together
at one point, usually the device power ground. The separate
ground returns are provided to minimize current flow in
low-level signal paths. In this way, logic return currents are not
summed into the same return path with analog signals.

CONNECTING THE AD565A FOR BUFFERED VOLTAGE
OUTPUT

The standard current-to-voltage conversion connections using
an operational amplifier are shown here with the preferred
trimming techniques. If a low offset operational amplifier
(AD510L, AD517L, AD741L, AD301AL, AD OP07) is used,
excellent performance can be obtained in many situations with­out trimming (an op amp with less than 0.5 mV max offset
voltage should be used to keep offset errors below 1/2 LSB). If
a 50 Ω fixed resistor is substituted for the 100 Ω trimmer, uni­polar zero will typically be within ±1/2 LSB (plus op amp off­set), and full-scale accuracy will be within 0.1% (0.25% max).
Substituting a 50 Ω resistor for the 100 Ω bipolar offset trimmer
will give a bipolar zero error typically within ±2 LSB (0.05%).

The AD509 is recommended for buffered voltage-output appli­cations which require a settling time to ±1/2 LSB of one micro­second. The feedback capacitor is shown with the optimum
value for each application; this capacitor is required to compen­sate for the 25 picofarad DAC output capacitance.

–6–

REV. D

PIN DESIGNATIONS

24-Lead DIP

AD565A/AD566A

V

REF OUT (+10V ±1%)

REF GND

REF IN

–V

BIPOLAR OFFSET IN

DAC OUT (–2mA F.S.)

10V SPAN R

20V SPAN R

PWR GND

1

NC

2

NC

3

CC

4

5

AD565A

6

TOP VIEW

(Not to Scale)

7

EE

8

9

10

11

12

NC = NO CONNECT

24

BIT 1 IN (MSB)

23

BIT 2 IN

22

BIT 3 IN

21

BIT 4 IN

20

BIT 5 IN

19

BIT 6 IN

18

BIT 7 IN

17

BIT 8 IN

BIT 9 IN

16

BIT 10 IN

15

BIT 11 IN

14

BIT 12 IN (LSB)

13

REF OUT (10V)

REF GND

REF IN

–V

BIPOLAR OFFSET IN

DAC OUT

10V SPAN R

20V SPAN R

28-Lead SOIC

1

NC

2

NC

3

NC

4

V

CC

5

6

AD565A

7

TOP VIEW

(Not to Scale)

NC

8

9

EE

10

11

NC

12

13

14

NC = NO CONNECT

NC

NC

REF GND

AMP SUMMING JUNCTION

REF V HI IN

–V

–15V IN (20mA)

EE

BIPOLAR OFFSET IN

NC

DAC OUT (–2mA F.S.)

10V SPAN R

20V SPAN R

PWR GND

28

NC

27

BIT 1 (MSB)

26

BIT 2

25

BIT 3

24

BIT 4

23

BIT 5

22

BIT 6

BIT 7

21

BIT 8

20

BIT 9

19

BIT 10

18

BIT 11

17

BIT 12 (LSB)

16

PWR GND

15

1

2

3

4

5

AD566A

6

TOP VIEW

(Not to Scale)

7

8

9

10

11

12

NC = NO CONNECT

24

BIT 1 IN (MSB)

23

BIT 2 IN

22

BIT 3 IN

21

BIT 4 IN

20

BIT 5 IN

19

BIT 6 IN

18

BIT 7 IN

17

BIT 8 IN

BIT 9 IN

16

BIT 10 IN

15

BIT 11 IN

14

BIT 12 IN (LSB)

13

REV. D

–7–

AD565A/AD566A

FIGURE 1. UNIPOLAR CONFIGURATION

This configuration will provide a unipolar 0 volt to +10 volt
output range. In this mode, the bipolar terminal, Pin 8, should
be grounded if not used for trimming.

2.4k⍀

+15V

–15V

10pF

AD509

R1
50k⍀

OUTPUT
0V TO
+10V

100⍀

GND

R2

REF

REF

100k⍀

100⍀

REF

V

OUT

CC

10V

AD565A

19.95k⍀

IN

20k⍀

–V

EE

POWER

GND

0.5mA

I

REF

9.95k⍀

MSB

BIPOLAR OFF

5k⍀

5k⍀

I

O

8k⍀

DAC

I

=

OUT

4 ⴛ I

REF

ⴛ CODE

CODE
INPUT

LSB

20V SPAN

10V SPAN

DAC
OUT

Figure 1. 0 V to +10 V Unipolar Voltage Output

STEP I . . . ZERO ADJUST

Turn all bits OFF and adjust zero trimmer R1, until the output
reads 0.000 volts (1 LSB = 2.44 mV). In most cases this trim is
not needed, but Pin 8 should then be connected to Pin 12.

STEP II . . . GAIN ADJUST

Turn all bits ON and adjust 100 Ω gain trimmer R2, until the
output is 9.9976 volts. (Full scale is adjusted to 1 LSB less than
nominal full scale of 10.000 volts.) If a 10.2375 V full scale is
desired (exactly 2.5 mV/bit), insert a 120 Ω resistor in series
with the gain resistor at Pin 10 to the op amp output.

FIGURE 2. BIPOLAR CONFIGURATION

This configuration will provide a bipolar output voltage from
–5.000 to +4.9976 volts, with positive full scale occurring with
all bits ON (all 1s).

STEP I . . . OFFSET ADJUST

Turn OFF all bits. Adjust 100 Ω trimmer R1 to give –5.000
volts output.

STEP II . . . GAIN ADJUST

Turn ON All bits. Adjust 100 Ω gain trimmer R2 to give a read­ing of +4.9976 volts.

Please note that it is not necessary to trim the op amp to obtain
full accuracy at room temperature. In most bipolar situations,
an op amp trim is unnecessary unless the untrimmed offset drift
of the op amp is excessive.

FIGURE 3. OTHER VOLTAGE RANGES

The AD565A can also be easily configured for a unipolar 0 volt
to +5 volt range or ±2.5 volt and ± 10 volt bipolar ranges by
using the additional 5k application resistor provided at the 20
volt span R terminal, Pin 11. For a 5 volt span (0 to +5 or
± 2.5), the two 5k resistors are used in parallel by shorting Pin
11 to Pin 9 and connecting Pin 10 to the op amp output and the
bipolar offset either to ground for unipolar or to REF OUT for
the bipolar offset either to ground for unipolar or to REF OUT
for the bipolar range. For the ±10 volt range (20 volt span) use
the 5k resistors in series by connecting only Pin 11 to the op
amp output and the bipolar offset connected as shown. The ±10
volt option is shown in Figure 3.

V

CC

AD565A

GND

R1

100⍀

9.95k⍀

0.5mA

I

REF

BIPOLAR OFF

5k⍀

5k⍀

I

O

8k⍀

DAC

I

=

OUT

4 ⴛ I

REF

ⴛ CODE

CODE
INPUT

LSBMSB

20V SPAN

10V SPAN

DAC
OUT

3.0k⍀

10pF

AD509

OUTPUT
–10V TO
+10V

100⍀

GND

R2

REF

REF

REF
OUT

10V

19.95k⍀

IN

20k⍀

POWER

–V

EE

100⍀

GND

R2

REF

V

CC

AD565A

0.5mA

GND

I

REF

R1

100⍀

9.95k⍀

BIPOLAR OFF

5k⍀

5k⍀

I

O

8k⍀

DAC

I

=

OUT

4 ⴛ I

REF

ⴛ CODE

CODE
INPUT

LSBMSB

REF

REF
OUT

10V

19.95k⍀

IN

20k⍀

POWER

–V

EE

Figure 2.±5 V Bipolar Voltage Output

20V SPAN

10V SPAN

DAC
OUT

2.4k⍀

10pF

AD509

OUTPUT
–5V TO
+5V

–8–

Figure 3.±10 V Voltage Output

REV. D

AD565A/AD566A

CONNECTING THE AD566A FOR BUFFERED VOLTAGE
OUTPUT

The standard current-to-voltage conversion connections using
an operational amplifier are shown here with the preferred trim­ming techniques. If a low offset operational amplifier (AD510L,
AD517L, AD741L, AD301AL, AD OP07) is used, excellent
performance can be obtained in many situations without trim­ming (an op amp with less than 0.5 mV max offset voltage
should be used to keep offset errors below 1/2 LSB). If a 50 Ω
fixed resistor is substituted for the 100 Ω trimmer, unipolar zero
will typically be within ±1/2 LSB (plus op amp offset), and full
scale accuracy will be within 0.1% (0.25% max). Substituting a
50 Ω resistor for the 100 Ω bipolar offset trimmer will give a
bipolar zero error typically within ±2 LSB (0.05%).

The AD509 is recommended for buffered voltage-output appli­cations which require a settling time to ±1/2 LSB of one micro­second. The feedback capacitor is shown with the optimum
value for each application; this capacitor is required to compen­sate for the 25 picofarad DAC output capacitance.

FIGURE 4. UNIPOLAR CONFIGURATION

This configuration will provide a unipolar 0 volt to +10 volt
output range. In this mode, the bipolar terminal, Pin 7, should
be grounded if not used for trimming.

100⍀

100k⍀

BIPOLAR OFF

AD566A

9.95k⍀

E

REF

AD561

REF

GND

REF
IN

–V

19.95k⍀

20k⍀

POWER

EE

GND

0.5mA

I

REF

R2

100⍀

10V

+V

5k⍀

5k⍀

I

DAC

I

=

OUT

4 ⴛ I

REF

ⴛ CODE

CODE
INPUT

O

8k⍀

LSBMSB

+15V

–15V

20V SPAN

10V SPAN

DAC
OUT

R1
50k⍀

10pF

AD509

2.4k⍀

FIGURE 5. BIPOLAR CONFIGURATION

This configuration will provide a bipolar output voltage from
–5.000 volts to +4.9976 volts, with positive full scale occurring
with all bits ON (all 1s).

R1

100⍀

AD566A

R2

100⍀

REF
IN

19.95k⍀

E

REF

10V

+V

AD561

REF

GND

–V

20k⍀

EE

POWER

GND

0.5mA

I

REF

9.95k⍀

BIPOLAR OFF

5k⍀

5k⍀

I

O

8k⍀

DAC

I

=

OUT

4 ⴛ I

REF

ⴛ CODE

CODE
INPUT

LSBMSB

20V SPAN

10V SPAN

DAC
OUT

10pF

AD509

2.4k⍀

Figure 5.±5 V Bipolar Voltage Output

STEP I . . . OFFSET ADJUST

Turn OFF all bits. Adjust 100 Ω trimmer R1 to give –5.000
output volts.

STEP II . . . GAIN ADJUST

Turn ON all bits. Adjust 100 Ω gain trimmer R2 to give a read­ing of +4.9976 volts.

Please note that it is not necessary to trim the op amp to obtain
full accuracy at room temperature. In most bipolar situations,
an op amp trim is unnecessary unless the untrimmed offset drift
of the op amp is excessive.

Figure 4. 0 V to +10 V Unipolar Voltage Output

STEP I . . . ZERO ADJUST

Turn all bits OFF and adjust zero trimmer, R1, until the output
reads 0.000 volts (1 LSB = 2.44 mV). In most cases this trim is
not needed, but Pin 7 should then be connected to Pin 12.

STEP II . . . GAIN ADJUST

Turn all bits ON and adjust 100 Ω gain trimmer, R2, until the
output is 9.9976 volts. (Full scale is adjusted to 1 LSB less than
nominal full scale of 10.000 volts.) If a 10.2375 V full scale is
desired (exactly 2.5 mV/bit), insert a 120 Ω resistor in series
with the gain resistor at Pin 10 to the op amp output.

REV. D

–9–

AD565A/AD566A

FIGURE 6. OTHER VOLTAGE RANGES

The AD566A can also be easily configured for a unipolar 0 volt
to +5 volt range or ±2.5 volt and ± 10 volt bipolar ranges by
using the additional 5k application resistor provided at the 20
volt span R terminal, Pin 11. For a 5 volt span (0 V to +5 V or
± 2.5 V), the two 5k resistors are used in parallel by shorting Pin
11 to Pin 9 and connecting Pin 10 to the op amp output and the
bipolar offset resistor either to ground for unipolar or to V

REF

for the bipolar range. For the ±10 volt range (20 volt span) use
the 5k resistors in series by connecting only Pin 11 to the op
amp output and the bipolar offset connected as shown. The
± 10 volt option is shown in Figure 6.

R1

BIPOLAR OFF

5k⍀

8k⍀

20V SPAN

10V SPAN

DAC
OUT

AD509

2.4k⍀

R3

26k⍀*

10pF

AD566A

GND

0.5mA

I

REF

9.95k⍀

14k⍀

R2

5k⍀

REF
IN

19.95k⍀

E

REF

7.5V

–V

AD561

REF

GND

–V

20k⍀

POWER

EE

MSB

5k⍀

5k⍀

DAC

I

=

OUT

4 ⴛ I
ⴛ CODE

CODE
INPUT

I

REF

O

LSB

Table I. Digital Input Codes

DIGITAL INPUT ANALOG OUTPUT

MSB LSB Straight Binary Offset Binary Twos Compl.*

0 0 0 0 0 0 0 0 0 0 0 0 Zero –FS Zero

0 1 1 1 1 1 1 1 1 1 1 1 Mid Scale – 1 LSB Zero – 1 LSB +FS – 1 LSB

1 0 0 0 0 0 0 0 0 0 0 0 +1/2 FS Zero –FS

1 1 1 1 1 1 1 1 1 1 1 1 +FS – l LSB + FS – 1 LSB Zero – 1 LSB

*Inverts the MSB of the offset binary code with an external inverter to obtain

twos complement.

*

THE PARALLEL COMBINATION OF THE BIPOLAR OFFSET RESISTOR
AND R3 ESTABLISHES A CURRENT TO BALANCE THE MSB CURRENT.
THE EFFECT OF TEMPERATURE COEFFICIENT MISMATCH BETWEEN
THE BIPOLAR RESISTOR COMBINATION AND DAC RESISTORS IS
EXPANDED ON PREVIOUS PAGE.

Fgure 6.±10 V Voltage Output

–10–

REV. D

0.098 (2.49) MAX

0.005 (0.13) MIN

SEATING

PLANE

0.0118 (0.30)

0.0040 (0.10)

0.0192 (0.49)

0.0138 (0.35)

0.1043 (2.65)

0.0926 (2.35)

0.0500
(1.27)

BSC

0.0125 (0.32)

0.0091 (0.23)

0.0500 (1.27)

0.0157 (0.40)

8°
0°

0.0291 (0.74)

0.0098 (0.25)

x 45°

0.7125 (18.10)

0.6969 (17.70)

0.4193 (10.65)

0.3937 (10.00)

0.2992 (7.60)

0.2914 (7.40)

PIN 1

28 15

141

0.225 (5.72)
MAX

0.200 (5.08)

0.120 (3.05)

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

Ceramic DIP (D-24)

24

112

PIN 1

1.290 (32.77) MAX

0.023 (0.58)

0.014 (0.36)

0.100 (2.54)
BSC

13

0.070 (1.78)

0.030 (0.76)

0.610 (15.49)

0.500 (12.70)

0.075 (1.91)

0.015 (0.38)

0.150
(3.81)
MIN

SEATING
PLANE

0.620 (15.75)

0.590 (14.99)

0.015 (0.38)

0.008 (0.20)

SOIC (R-28) Package

AD565A/AD566A

C1814a–0–3/00 (rev. D)

REV. D

PRINTED IN U.S.A.

–11–