Datasheet AD5663 Datasheet (ANALOG DEVICES)

2.7 V to 5.5 V, 250 μA, Rail-to-Rail Output,

V

V

FEATURES

Low power, dual 16-bit nanoDAC
Relative accuracy: ±12 LSBs maximum
Guaranteed monotonic by design
10-lead MSOP and 3 mm × 3 mm LFCSP_WD

2.7 V to 5.5 V power supply
Per channel power-down
Power-on reset to zero scale or midscale

Hardware

LDAC

Serial interface; up to 50 MHz

APPLICATIONS

Process control
Data acquisition systems
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators

and

CLR

functions

Dual 16-Bit nanoDAC

FUNCTIONAL BLOCK DIAGRAM

DD

REF

LDAC

STRING

DAC

DAC A

STRING

DAC

DAC B

POWER-ON

RESET

GND

2.7 V to 5.5 V, dual 12-/14-/16-bit
DACs with internal reference

CLR

INPUT

REGISTER

INPUT

REGISTER

AD5663

REGISTER

REGISTER

SCLK

SYNC

INTERFACE

LOGIC

DIN

LDAC

Figure 1.

Table 1. Related Devices

Part No. Description

AD5623R/AD5643R/AD5663R

AD5663

BUFFER

BUFFER

POWER-DOW N

LOGIC

®

V

A

OUT

V

B

OUT

05855-001

GENERAL DESCRIPTION

The AD5663, a member of the nanoDAC family, is a low power,
dual, 16-bit buffered voltage-out DAC that operates from a single

2.7 V to 5.5 V supply and is guaranteed monotonic by design.

The AD5663 requires an external reference voltage to set the
output range of the DAC. The part incorporates a power-on
reset circuit that ensures the DAC output powers up to 0 V or
midscale (AD5663-1) and remains there until a valid write takes
place. The part contains a power-down feature that reduces the
current consumption of the device to 480 nA at 5 V and provides
software-selectable output loads while in power-down mode.

The low power consumption of this part in normal operation
makes it ideally suited to portable, battery-operated equipment.
The power consumption is 1.25 mW at 5 V, going down to

2.4 µW in power-down mode.

The on-chip precision output amplifier of the AD5663 allows
rail-to-rail output swing to be achieved.

The AD5663 uses a versatile, 3-wire serial interface that
operates at clock rates up to 50 MHz and is compatible with
standard SPI®, QSPI™, MICROWIRE™, and DSP interface
standards.

PRODUCT HIGHLIGHTS

1. Dual 16-bit DAC; relative accuracy of ±12 LSBs maximum.

2. Available in 10-lead MSOP and 10-lead, 3 mm × 3 mm

LFCSP_WD packages.

3. Low power; typically consumes 0.6 mW at 3 V and

1.25 mW at 5 V.

4. 7 µs maximum settling time.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2006 Analog Devices, Inc. All rights reserved.

AD5663

TABLE OF CONTENTS

Features .............................................................................................. 1

Output Amplifier........................................................................ 14

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description......................................................................... 1

Product Highlights........................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

AC Characteristics........................................................................ 4

Timing Characteristics ................................................................ 5

Timing Diagram ...........................................................................5

Absolute Maximum Ratings............................................................ 6

ESD Caution.................................................................................. 6

Pin Configuration and Function Description .............................. 7

Typical Performance Characteristics............................................. 8

Te r mi n ol o g y .................................................................................... 12

Theory of Operation ...................................................................... 14

Serial Interface............................................................................ 14

Input Shift Register .................................................................... 14

SYNC

Interrupt .......................................................................... 15

Power-On Reset .......................................................................... 15

Software Reset............................................................................. 15

Power-Down Modes .................................................................. 16

LDAC

Function .......................................................................... 16

Microprocessor Interfacing....................................................... 18

Applications..................................................................................... 19

Choosing a Reference for the AD5663.................................... 19

Using a Reference as a Power Supply for the AD5663 ..........19

Bipolar Operation Using the AD5663..................................... 20

Using the AD5663 with a Galvanically Isolated Interface .... 20

Power Supply Bypassing and Grounding................................ 20

Outline Dimensions .......................................................................21

D/A Section................................................................................. 14

Resistor String............................................................................. 14

REVISION HISTORY

4/06—Revision 0: Initial Version

Ordering Guide .......................................................................... 21

Rev. 0 | Page 2 of 24

AD5663

SPECIFICATIONS

VDD = 2.7 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; V

Table 2.

A Grade

1

Parameter Min Typ Max Min Typ Max Unit Conditions/Comments

STATIC PERFORMANCE

2

AD5663

Resolution 16 16 Bits
Relative Accuracy ±8 ±16 ±6 ±12 LSB
Differential Nonlinearity ±1 ±1 LSB Guaranteed monotonic by design
Zero-Scale Error +2 +10 +2 +10 mV All 0s loaded to DAC register
Offset Error ±1 ±10 ±1 ±10 mV
Full-Scale Error −0.15 ±1 −0.15 ±1 % of FSR All 1s loaded to DAC register
Gain Error ±1.5 ±1.5 % of FSR
Zero-Scale Error Drift

3

±2 ±2 µV/°C

Gain Temperature Coefficient ±2.5 ±2.5 ppm Of FSR/°C

DC Power Supply Rejection Ratio −100 −100 dB DAC code = midscale, VDD ± 10%
DC Crosstalk 10 10 µV

10 10 µV/mA Due to load current change
5 5 µV Due to powering down (per channel)
OUTPUT CHARACTERISTICS

Output Voltage Range 0 V

2

DD

Capacitive Load Stability 2 2 nF RL = ∞
10 10 nF RL = 2 kΩ
DC Output Impedance 0.5 0.5 Ω
Short-Circuit Current 30 30 mA VDD = 5 V
Power-Up Time 4 4 s

REFERENCE INPUTS

Reference Current 170 200 170 200 µA V
Reference Input Range 0.75 V

DD

Reference Input Impedance 26 26 kΩ

LOGIC INPUTS

3

Input Current ±2 ±2 µA All digital inputs
V

, Input Low Voltage 0.8 0.8 V VDD = 5 V, 3 V

INL

V

, Input High Voltage 2 2 V VDD = 5 V, 3 V

INH

Pin Capacitance 3 3 pF
19 19 pF

POWER REQUIREMENTS

V

DD

IDD (Normal Mode)

4

2.7 5.5 2.7 5.5 V

VIH = VDD and VIL = GND
VDD = 4.5 V to 5.5 V 250 450 250 450 µA
VDD = 2.7 V to 3.6 V 200 425 200 425 µA

IDD (All Power-Down

Modes)

5

VIH = VDD, VIL = GND

VDD = 4.5 V to 5.5 V 0.48 1 0.48 1 µA
VDD = 2.7 V to 3.6 V 0.2 1 0.2 1 µA

1

Temperature range: A grade and B grade are both equal to −40°C to +105°C.

2

Linearty calculated using a reduced code range: AD5663 (Code 512 to Code 65024). Output unloaded.

3

Guaranteed by design and characterization, not production tested.

4

Interface inactive. All DACs active. DAC outputs unloaded.

5

Both DACs powered down.

= VDD; all specifications T

REF

B Grade

1

0 V

0.75 V

V

DD

V

DD

MIN

to T

, unless otherwise noted.

MAX

Due to full-scale output change
R

L = 2 kΩ to GND or VDD

Coming out of power-down mode;
V

= 5 V

DD

= VDD = 5.5 V, 3.6 V

REF

DIN, SCLK, and

SYNC

LDAC and CLR

Rev. 0 | Page 3 of 24

AD5663

AC CHARACTERISTICS

VDD = 2.7 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; V

= VDD; all specifications T

REF

MIN

to T

, unless otherwise noted.

MAX

Table 3.

Parameter

2

Min Typ Max Unit Conditions/Comments

Output Voltage Settling Time 4 7 µs 1/4 to 3/4 scale settling to ±2 LSB
Slew Rate 1.8 V/µs
Digital-to-Analog Glitch Impulse 10 nV-s 1 LSB change around major carry
Digital Feedthrough 0.1 nV-s
Reference Feedthrough −90 dBs V

= 2 V ± 0.1 V p-p, frequency 10 Hz to 20 MHz

REF

Digital Crosstalk 0.1 nV-s
Analog Crosstalk 1 nV-s
DAC-to-DAC Crosstalk 1 nV-s
Multiplying Bandwidth 340 kHz V
Total Harmonic Distortion −80 dB V

= 2 V ± 0.1 V p-p

REF

= 2 V ± 0.1 V p-p; frequency = 10 kHz

REF

Output Noise Spectral Density 120 nV/√Hz DAC code = midscale, 1 kHz
100 nV/√Hz DAC code = midscale, 10 kHz
Output Noise 15

1

Guaranteed by design and characterization, not production tested.

2

See the Terminology section.

μV p-p

0.1 Hz to 10 Hz

1

Rev. 0 | Page 4 of 24

AD5663

TIMING CHARACTERISTICS

All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
V

= 2.7 V to 5.5 V; all specifications T

DD

Table 4.

Limit at T

Parameter

2

t

1

VDD = 2.7 V to 5.5 V Unit Conditions/Comments

20 ns min SCLK cycle time

t2 9 ns min SCLK high time
t3 9 ns min SCLK low time
t4 13 ns min
t5 5 ns min Data setup time
t6 5 ns min Data hold time
t7 0 ns min
t8 15 ns min

t9 13 ns min
t10 0 ns min
t

11

t

12

10 ns min

15 ns min
t13 5 ns min
t14 0 ns min
t

15

1

Guaranteed by design and characterization; not production tested.

2

Maximum SCLK frequency is 50 MHz at VDD = 2.7 V to 5.5 V.

300 ns max

MIN

MIN

to T

, T

, unless otherwise noted.1

MAX

MAX

SYNC to SCLK falling edge setup time

SCLK falling edge to
Minimum

SYNC high time

SYNC rising edge

SYNC rising edge to SCLK fall ignore
SCLK falling edge to

SYNC fall ignore
LDAC pulse width low
SCLK falling edge to

LDAC rising edge
CLR pulse width low
SCLK falling edge to

LDAC falling edge
CLR pulse activation time

TIMING DIAGRAM

SCLK

SYNC

DIN

LDAC

LDAC

CLR

V

OUT

1

ASYNCHRONOUS LDAC UPDAT E MODE.

2

SYNCHRONOUS LDAC UPDAT E MODE.

t

10

t

8

1

2

DB23

t

4

t

6

t

5

t

13

t

15

t

1

t

t

3

2

DB0

t

9

t

7

t

11

t

14

t

12

05855-002

Figure 2. Serial Write Operation

Rev. 0 | Page 5 of 24

AD5663

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 5.

Parameter Rating

VDD to GND −0.3 V to +7 V
V

to GND −0.3 V to VDD + 0.3 V

OUT

V

to GND −0.3 V to VDD + 0.3 V

REF

Digital Input Voltage to GND −0.3 V to VDD + 0.3 V
Operating Temperature Range

Industrial −40°C to +105°C
Storage Temperature Range −65°C to +150°C
Junction Temperature (TJ max) 150°C
Power Dissipation (TJ max − TA)/θ
LFCSP_WD Package (4-Layer Board)

θJA Thermal Impedance 61°C/W
MSOP Package (4-Layer Board)

θJA Thermal Impedance 142°C/W

θJC Thermal Impedance 43.7°C/W
Reflow Soldering Peak Temperature

Pb-Free 260(+0/−5)°C

JA

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. 0 | Page 6 of 24

AD5663

PIN CONFIGURATION AND FUNCTION DESCRIPTION

V

OUT

V

OUT

GND

LDAC

CLR

1

A

2

B

3

4

5

AD5663

TOP VIEW

(Not to Scale)

10

V

REF

9

V

DD

8

DIN

7

SCLK

6

SYNC

5855-003

Figure 3. Pin Configuration

Table 6. Pin Function Descriptions

Pin No. Mnemonic Description

1 V
2 V

A Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.

OUT

B Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.

OUT

3 GND Ground Reference Point for All Circuitry on the Part.
4

LDAC Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new data.

This allows simultaneous update of all DAC outputs. Alternatively, this pin can be tied permanently low.

5

CLR Asynchronous Clear Input. The CLR input is falling edge sensitive. While CLR is low, all LDAC pulses are ignored.

CLR is activated, zero scale is loaded to all input and DAC registers. This clears the output to 0 V. The part

When
exits clear code mode on the 24th falling edge of the next write to the part. If

CLR is activated during a write

sequence, the write is aborted.

6

SYNC Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low,

it powers on the SCLK and DIN buffers and enables the input shift register. Data is transferred in on the falling
edges of the next 24 clocks. If SYNC is taken high before the 24th falling edge, the rising edge of SYNC acts as an
interrupt, and the write sequence is ignored by the device.

7 SCLK

Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input.
Data can be transferred at rates up to 50 MHz.

8 DIN

Serial Data Input. This device has a 24-bit shift register. Data is clocked into the register on the falling edge
of the serial clock input.

9 VDD

Power Supply Input. These parts can be operated from 2.7 V to 5.5 V, and the supply should be decoupled with a
10 µF capacitor in parallel with a 0.1 µF capacitor to GND.

10 V

Reference Voltage Input.

REF

Rev. 0 | Page 7 of 24

AD5663

TYPICAL PERFORMANCE CHARACTERISTICS

10

10

VDD = V

8

T

6

4

2

0

–2

INL ERROR (LSB)

–4

–6

–8

–10

0 5k 10k 15k 20k 25k 30k 35k 40k 45k 50k 55k 60k 65k

= 25°C

A

REF

= 5V

CODE

Figure 4. INL

1.0
VDD = V
T

0.8

0.6

0.4

0.2

0

–0.2

DNL ERROR (LSB)

–0.4

–0.6

–0.8

–1.0

0 10k 20k 30k 40k 50k 60k

= 25°C

A

REF

= 5V

CODE

Figure 5. DNL

8

6

= 5V

V

DD

4

T

= 25°C

A

2

0

–2

ERROR (L SB)

–4

–6

–8

–10

05855-004

0.75 1.25 1.75 2.25 4.253. 753.252.75 4.75
V

(V)

REF

Figure 7. INL and DNL Error vs. V

8

6

= 25°C

T

A

4

2

0

ERROR (L SB)

–2

–4

–6

–8

05855-005

2.7 3.2 3.7 4.74.2 5. 2
VDD (V)

Figure 8. INL and DNL Error vs. Supply

MAX INL

MAX DNL

MIN DNL

MIN INL

05855-007

REF

MAX INL

MAX DNL

MIN DNL

MIN INL

05855-008

8

6

V

= V

= 5V

DD

4

2

0

ERROR (LSB)

–2

–4

–6

–8

–40 –20 40200 1008060 120

REF

TEMPERATURE ( °C)

Figure 6. INL Error and DNL Error vs. Temperature

MAX INL

MAX DNL

MIN DNL

MIN INL

05855-006

Rev. 0 | Page 8 of 24

0

VDD = 5V

–0.02

–0.04

–0.06

–0.08

–0.10

–0.12

ERROR (% FSR)

–0.14

–0.16

–0.18

–0.20

–40 –20 40200 1008060

GAIN ERROR

FULL-SCAL E ERROR

TEMPERATURE (°C)

Figure 9. Gain Error and Full-Scale Error vs. Temperature

05855-009

AD5663

1.5

1.0

0.5

0

–0.5

ERROR (mV)

–1.0

–1.5

–2.0

–2.5

–40 –20 40200860 100

ZERO-SCALE ERROR

OFFSET ERROR

TEMPERATURE ( °C)

Figure 10. Zero-Scale and Offset Error vs. Temperature

1.0

0.5

GAIN ERROR

0

–0.5

ERROR (% FSR)

–1.0

–1.5

–2.0

FULL-SCAL E ERROR

2.7 3.2 3.7 4.74.2 5.2
VDD (V)

Figure 11. Gain Error and Full-Scale Error vs. Supply

1.0
= 25°C

T

A

0.5

ZERO-SCALE ERROR

0

05855-010

05855-011

VDD = 5.5V

= 25°C

T

A

8

6

4

NUMBER OF UNITS

2

0

0.230 0.235 0.240 0.245 0.250 0.255
IDD (mA)

Figure 13. IDD Histogram with VDD = 5.5 V

0.20
VDD= V

T

0.15

A

0.10

0.05

0

–0.05

–0.10

ERROR VOLT AGE (V)

–0.15

–0.20

–0.25

–5 –4 –3 –2 –1 0 1 2 435

= 5V, 3V

REF

= 25°C

DAC LOADED WITH
FULL SCALE –
SOURCING CURRENT

DAC LOADED WIT H
ZERO SCALE –
SINKING CURRENT

I (mA)

Figure 14. Headroom at Rails vs. Source and Sink Current

0.30

TA = 25°C

0.25

= V

REFIN

= 5V

V

DD

05858-090

05855-014

0

–0.5

–1.0

ERROR (mV)

–1.5

–2.0

–2.5

2.7 3. 2 4.23.7 5.24.7
VDD (V)

Figure 12. Zero-Scale and Offset Error vs. Supply

OFFSET ERROR

05855-012

Rev. 0 | Page 9 of 24

0.20

0.15

(mA)

DD

I

0.10

0.05

0

–40 –20 0 20 40 60 80 100

V

= V

DD

REFIN

TEMPERATURE ( °C)

= 3V

Figure 15. Supply Current vs. Temperature

05855-044

AD5663

–

2.538

2.537

2.536

2.535

2.534

2.533

VDD = V
T
FULL-SCAL E CODE CHANGE
0x0000 TO 0xFF FF
OUTPUT L OADED WIT H 2kΩ
AND 200pF TO GND

V

= 909mV/DIV

OUT

1

TIME BASE = 4µs/DIV

= 25°C

A

REF

= 5V

05855-019

Figure 16. Full-Scale Settling Time, 5 V

2.532

2.531

(V)

2.530

2.529

OUT

V

2.528

2.527

2.526

2.525

2.524

2.523

2.522

2.521
0 50 100 150 350 400200 250 300 450 512

Figure 19. Digital-to-Analog Glitch Impulse (Negative)

VDD= V
T
5ns/SAMPL E NUMBER
GLITCH IMPULSE = 9.494nV
1LSB CHANGE AROUND
MIDSCALE (0 x8000 TO 0x7FF F)

SAMPLE NUMBER

= 25°C

A

REF

= 5V

05855-058

V

1

2

DD

V

OUT

CH1 2.0V CH2 500mV M100µ s 125MS/s

A CH1 1.28V

Figure 17. Power-On Reset to 0 V

SYNC

1

3

SLCK

VDD = V
T

= 25°C

A

= 5V

REF

MAX(C2)*

420.0mV

8.0ns/p t

2.498

2.497

2.496

2.495

(V)

OUT

V

2.494

2.493

2.492

05855-020

2.491
0 50 100 150 350 400200 250 300 450 512

VDD= V
T
5ns/SAMPL E NUMBER
ANALOG CROSSTALK = 0.424 nV

SAMPLE NUMBER

= 25°C

A

REF

= 5V

05855-059

Figure 20. Analog Crosstalk

20

VDD = 5V
T

= 25°C

A

–30

DAC LOADED WIT H FULL SCAL E
V

= 2V ± 0.3V p -p

REF

–40

–50

–60

(dB)

–70

–80

–90

–100

2k 4k 6k 8k 10k

FREQUENCY (Hz)

Figure 21. Total Harmonic Distortion

05855-025

2

CH1 5.0V
CH3 5.0V

V

OUT

CH2 500mV M400ns A CH1 1.4V

VDD = 5V

Figure 18. Exiting Power-Down to Midscale

05855-021

Rev. 0 | Page 10 of 24

AD5663

16

V

= V

REF

DD

TA = 25°C

14

V

3V

=

12

10

TIME (µs)

8

6

4

012 34 567 981

CAPACITANCE (nF)

DD

V

5V

=

DD

Figure 22. Settling Time vs. Capacitive Load

VDD = V
T
DAC LOADED WIT H MIDSCALE

1

= 25°C

A

REF

= 5V

05855-026

0

5

0

–5

–10

–15

(dB)

–20

–25

–30

–35

–40

10k 100k 1M 10M

FREQUENCY (Hz)

Figure 25. Multiplying Bandwidth

3

V

A

OUT

CLR

VDD = 5V
T

= 25°C

A

05855-029

V

B

OUT

4

4

Y AXIS = 2µV/DIV
X AXIS = 4s/DIV

Figure 23. 0.1 Hz to 10 Hz Output Noise Plot

800

VDD = V
T

700

600

500

400

300

OUTPUT NOISE (nV/ Hz)

200

100

0

10 100k10k1k100 1M

= 25°C

A

REF

= 5V

FREQUENCY (Hz)

05855-027

05855-028

2

CH3 5.0V CH4 1.0V

CH2 1.0V M200ns A CH3 1.10V

Figure 26.

CLR

Pulse Activation Time

05855-050

Figure 24. Noise Spectral Density

Rev. 0 | Page 11 of 24

AD5663

TERMINOLOGY

Relative Accuracy or Integral Nonlinearity (INL)
For the DAC, relative accuracy or integral nonlinearity is a
measurement of the maximum deviation, in LSBs, from a
straight line passing through the endpoints of the DAC transfer
function. A typical INL vs. code plot is shown in

Figure 4.

Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of ±1 LSB maximum
ensures monotonicity. This DAC is guaranteed monotonic by
design. A typical DNL vs. code plot is shown in

Figure 5.

Zero-Scale Error
Zero-scale error is a measurement of the output error when
zero code (0x0000) is loaded to the DAC register. Ideally, the
output should be 0 V. The zero-scale error is always positive in
the AD5663 because the output of the DAC cannot go below
0 V. It is due to a combination of the offset errors in the DAC
and the output amplifier. Zero-scale error is expressed in mV.
A plot of zero-scale error vs. temperature is shown in

Figure 10.

Full-Scale Error
Full-scale error is a measurement of the output error when full­scale code (0xFFFF) is loaded to the DAC register. Ideally, the
output should be V

− 1 LSB. Full-scale error is expressed in

DD

percent of full-scale range. A plot of full-scale error vs. tempera­ture is shown in

Figure 9.

Gain Error
Gain error is a measure of the span error of the DAC. It is the
deviation in slope of the DAC transfer characteristic from ideal
expressed as a percent of the full-scale range.

Zero-Scale Error Drift
Zero-scale error drift is a measurement of the change in zero­scale error with a change in temperature. It is expressed in µV/°C.

Gain Temperature Coefficient
Gain temperature coefficient is a measurement of the change in
gain error with changes in temperature. It is expressed in (ppm
of full-scale range)/°C.

Offset Error

Offset error is a measure of the difference between V
and V

(ideal) expressed in mV in the linear region of the trans-

OUT

(actual)

OUT

fer function. Offset error is measured on the AD5663 with
Code 512 loaded in the DAC register.

positive.

DC Power Supply Rejection Ratio (PSRR)

It can be negative or

PSRR indicates how the output of the DAC is affected by changes
in the supply voltage. PSRR is the ratio of the change in V
a change in V
in dB. V

for full-scale output of the DAC. It is measured

DD

is held at 2 V, and VDD is varied by ±10%.

REF

OUT

to

Output Voltage Settling Time

Output voltage settling time is the amount of time it takes for the
output of a DAC to settle to a specified level for a 1/4 to 3/4 full­scale input change and is measured from the 24th falling edge of
SCLK.

Digital-to-Analog Glitch Impulse
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is normally specified as the area of the glitch in nV-s,
and is measured when the digital input code is changed by
1 LSB at the major carry transition (0x7FFF to 0x8000). See
Figure 19.

Digital Feedthrough
Digital feedthrough is a measure of the impulse injected into
the analog output of the DAC from the digital inputs of the
DAC, but it is measured when the DAC output is not updated.
It is specified in nV-s and measured with a full-scale code change
on the data bus, that is, from all 0s to all 1s and vice versa.

Total Harmonic Distortion (THD)

Total harmonic distortion is the difference between an ideal
sine wave and its attenuated version using the DAC. The sine
wave is used as the reference for the DAC, and the THD is a
measurement of the harmonics present on the DAC output.
It is measured in dB.

Noise Spectral Density

Noise spectral density is a measurement of the internally
generated random noise. Random noise is characterized as a
spectral density (voltage per √Hz). It is measured by loading the
DAC to midscale and measuring noise at the output. It is
measured in nV/√Hz.

Figure 24 shows a plot of noise spectral

density.

DC Crosstalk

DC crosstalk is the dc change in the output level of one DAC in
response to a change in the output of another DAC. It is measured
with a full-scale output change on one DAC (or soft power-down
and power-up) while monitoring another DAC kept at midscale.
It is expressed in V.

DC crosstalk due to load current change is a measure of the
impact that a change in load current on one DAC has to another
DAC kept at midscale. It is expressed in V/mA.

Digital Crosstalk

Digital crosstalk is the glitch impulse transferred to the output
of one DAC at midscale in response to a full-scale code change
(all 0s to all 1s and vice versa) in the input register of another
DAC. It is measured in standalone mode and is expressed
in nV-s.

Rev. 0 | Page 12 of 24

AD5663

Analog Crosstalk

Analog crosstalk is the glitch impulse transferred to the output
of one DAC due to a change in the output of another DAC. It is
measured by loading one of the input registers with a full-scale
code change (all 0s to all 1s and vice versa) while keeping
LDAC

high. Then pulse
the DAC whose digital code was not changed. The area of the
glitch is expressed in nV-s.

DAC-to-DAC Crosstalk

DAC-to-DAC crosstalk is the glitch impulse transferred to the
output of one DAC due to a digital code change and subsequent
output change of another DAC. This includes both digital and
analog crosstalk. It is measured by loading one of the DACs
with a full-scale code change (all 0s to all 1s and vice versa) with
LDAC

low and monitoring the output of another DAC. The
energy of the glitch is expressed in nV-s.

LDAC

low and monitor the output of

Multiplying Bandwidth

The amplifiers within the DAC have a finite bandwidth. The
multiplying bandwidth is a measure of this. A sine wave on the
reference (with full-scale code loaded to the DAC) appears on
the output. The multiplying bandwidth is the frequency at
which the output amplitude falls to 3 dB below the input.

Rev. 0 | Page 13 of 24

AD5663

V

THEORY OF OPERATION

D/A SECTION

The AD5663 DAC is fabricated on a CMOS process. The
architecture consists of a string DAC followed by an output
buffer amplifier.

Figure 27 shows a block diagram of the DAC

architecture.

DAC

REGISTER

DD

REF (+)

RESISTOR

STRING

REF (–)

GND

Figure 27. DAC Architecture

OUTPUT
AMPLIFIER
(GAIN = +2)

V

OUT

05855-032

Because the input coding to the DAC is straight binary, the ideal
output voltage is given by

D

OUT

⎛

×=

VV

⎜

REF

⎝

65,536

⎞
⎟

⎠

where D is the decimal equivalent of the binary code that is
loaded to the DAC register. It can range from 0 to 65,535.

RESISTOR STRING

The resistor string section is shown in Figure 28. It is a string of
resistors, each of Value R. The code loaded to the DAC register
determines at which node on the string the voltage is tapped off
to be fed into the output amplifier. The voltage is tapped off by
closing one of the switches connecting the string to the amplifier.
Because it is a string of resistors, it is guaranteed monotonic.

R

R

R

R

R

Figure 28. Resistor String

TO OUTPUT
AMPLIFIER

5855-033

OUTPUT AMPLIFIER

The output buffer amplifier can generate rail-to-rail voltages on
its output, which gives an output range of 0 V to V

. It can drive

DD

a load of 2 k in parallel with 1000 pF to GND.

The source and sink capabilities of the output amplifier can be

Figure 14. The slew rate is 1.8 V/µs with a 1/4 to 3/4

seen in
full-scale settling time of 10 µs.

SERIAL INTERFACE

The AD5663 has a 3-wire serial interface (
DIN) that is compatible with SPI, QSPI, and MICROWIRE
interface standards, as well as with most DSPs. See
a timing diagram of a typical write sequence.

The write sequence begins by bringing the
from the DIN line is clocked into the 24-bit shift register on the
falling edge of SCLK. The serial clock frequency can be as high
as 50 MHz, making the AD5663 compatible with high speed
DSPs. On the 24th falling clock edge, the last data bit is clocked
in and the programmed function is executed; that is, there is a
change in DAC register contents and/or a change in the mode
of operation. At this stage, the

SYNC
brought high. In either case, it must be brought high for a mini­mum of 15 ns before the next write sequence so that a falling edge

SYNC

of

can initiate the next write sequence. Because the
buffer draws more current when V
V

= 0.10 V,

IN

SYNC

should be idled low between write sequences
for even lower power operation. As mentioned previously,
however, it must be brought high again just before the next
write sequence.

SYNC

, SCLK, and

Figure 2 for

SYNC

line low. Data

line can be kept low or be

SYNC

= 2.0 V than it does when

IN

INPUT SHIFT REGISTER

The input shift register is 24 bits wide (see Figure 29). The first
two bits are don’t cares. The next three are the Command Bit C2
to Command Bit C0 (see
Address A2 to DAC Address A0 (see
16-bit data-word. These are transferred to the DAC register on
the 24th falling edge of SCLK.

Table 7. Command Definition

C2 C1 C0 Command

0 0 0 Write to input register n
0 0 1 Update DAC register n
0 1 0

0 1 1 Write to and update DAC channel n
1 0 0 Power down DAC (power up)
1 0 1 Reset
1 1 0

1 1 1 Reserved

Table 7), followed by the 3-bit DAC

Table 8), and, finally, the

Write to input register n, update all
(software

LDAC)

LDAC register setup

Rev. 0 | Page 14 of 24

AD5663

S

Table 8. Address Command

A2 A1 A0 ADDRESS (n)

0 0 0 DAC A
0 0 1 DAC B
0 1 0 Reserved
0 1 1 Reserved
1 1 1 All DACs

SYNC INTERRUPT

In a normal write sequence, the
least 24 falling edges of SCLK, and the DAC is updated on the
24th falling edge. However, if
24th falling edge, this acts as an interrupt to the write sequence.
The shift register is reset and the write sequence is seen as
invalid. Neither an update of the DAC register contents nor a
change in the operating mode occurs (see

SYNC

line is kept low for at

SYNC

is brought high before the

Figure 30).

POWER-ON RESET

The AD5663 family contains a power-on reset circuit that
controls the output voltage during power-up. The AD5663 DAC
outputs power up to 0 V, the AD5663-1 powers up to midscale,
and the output remains there until a valid write sequence is
made to the DAC. This is useful in applications where it is
important to know the state of the output of the DAC while it is
in the process of powering up. Any events on
during power-on reset are ignored.

LDAC

or

CLR

SOFTWARE RESET

The AD5663 contains a software reset function. Command 101
is reserved for the software reset function (see
software reset command contains two reset modes that are
software-programmable by setting Bit DB0 in the control
register.

Table 9 shows how the state of the bit corresponds to the mode
of operation of the device.

Table 10 shows the contents of the

input shift register during the software reset mode of operation.

Table 9. Software Reset Modes for the AD5663

DB0 Registers Reset to 0

0 DAC register
Input register
1 (Power-On Reset) DAC register
Input register

LDAC register

Power-down register

Table 7). The

Table 10. 24-Bit Input Shift Register Contents for Software Reset Command

MSB LSB
DB23 to DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 to DB1 DB0

x 1 0 1 x x x x 1/0
Don’t care Command bits (C2 to C0) Address bits (A2 to A0) Don’t care Determines software reset mode

DB23 (MSB) DB0 (LSB)

X X C2 C1 C0 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

COMMAND BITS ADDRESS BITS

Figure 29. Input Register Contents

DATA BIT S

05855-034

SCLK

YNC

DIN

DB23 DB23 DB0DB0

INVALID WRITE SEQUENCE:

SYNC HIGH BEFORE 24

TH

FALLING EDGE

Figure 30.

SYNC

Interrupt Facility

VALID WRITE SEQUENCE, OUTPUT UPDATES

ON THE 24

TH

FALLING EDGE

05855-035

Rev. 0 | Page 15 of 24

AD5663

POWER-DOWN MODES

The AD5663 contains four separate modes of operation.
Command 100 is reserved for the power-down function
(see

Table 7). These modes are software-programmable by
setting Bit DB5 and Bit DB4 in the control register.
shows how the state of the bits corresponds to the mode of
operation of the device. Any or all DACs (DAC B and DAC A)
can be powered down to the selected mode by setting the
corresponding two bits (Bit DB1 and Bit DB0) to 1. By
executing the same Command 100, any combination of DACs
can be powered up by setting Bit DB5 and Bit DB4 to normal
operation mode. Again, to select which combination of DAC
channels to power up, set the corresponding two bits (Bit DB1
and Bit DB0) to 1. See

Table 12 for contents of the input shift

register during power-down/power-up operation.

The DAC output powers up to the value in the input register
while

LDAC

is low. If

LDAC

is high, the DAC output powers up

to the value held in the DAC register before power-down.

When both bits are set to 0, the part works normally with its
normal power consumption of 500 µA at 5 V. However, for the
three power-down modes, the supply current falls to 480 nA at
5 V (100 nA at 3 V). Not only does the supply current fall, but
the output stage is also internally switched from the output of
the amplifier to a resistor network of known values. This has the
advantage that the output impedance of the part is known while
the part is in power-down mode. The outputs can either be
connected internally to GND through a 1 kΩ or 100 kΩ register
or left open-circuited (three-state) (see

RESISTOR

STRING DAC

Figure 31. Output Stage During Power-Down

AMPLI FIER

POWER-DOW N

CIRCUITRY

Figure 31).

RESISTOR
NETWORK

The bias generator, the output amplifier, the resistor string, and
other associated linear circuitry are shut down when power­down mode is activated. However, the contents of the DAC
register are unaffected when in power-down.

Table 11

V

OUT

05855-036

The time required to exit power-down is typically 4 µs for
V

= 5 V and for VDD = 3 V (see Figure 18).

DD

Table 11. Power-Down Modes of Operation for the AD5663

DB5 DB4 Operating Mode

0 0 Normal operation

0 1 1 kΩ to GND
1 0 100 kΩ to GND
1 1 Three-state

Power-Down Modes

LDAC FUNCTION

The AD5663 DAC has double-buffered interfaces consisting of
two banks of registers: input registers and DAC registers. The
input registers are connected directly to the input shift register
and the digital code is transferred to the relevant input register
on completion of a valid write sequence. The DAC registers
contain the digital code used by the resistor strings.

LDAC

Access to the DAC registers is controlled by the
When the

LDAC

pin is high, the DAC registers are latched and

the input registers can change state without affecting the

LDAC

contents of the DAC registers. When

is brought low,
however, the DAC registers become transparent and the
contents of the input registers are transferred to them. The
double-buffered interface is useful if the user requires
simultaneous updating of all DAC outputs. The user can write
to one of the input registers individually and then, by bringing
LDAC

low when writing to the other DAC input register, all

outputs update simultaneously.
These parts each contain an extra feature whereby a DAC

register is not updated unless its input register has been
updated since the last time

LDAC

when

is brought low, the DAC registers are filled with

LDAC

was brought low. Normally,

the contents of the input registers. In the case of the AD5663,
the DAC register updates only if the input register has changed
since the last time the DAC register was updated, thereby
removing unnecessary digital crosstalk.

The outputs of all DACs can be updated simultaneously using

LDAC

the hardware

pin.

pin.

Table 12. 24-Bit Input Shift Register Contents of Power-Up/Power-Down Function

MSB
DB23 to

DB22

x 1 0 0 x x x x PD1 PD0 x x DAC B DAC A
Don’t

care

DB21 DB20 DB19 DB18 DB17 DB16

Command bits (C2 to C0) Address bits (A2 to A0);

don’t care

DB15 to
DB6

Don’t
care

LSB

DB5 DB4 DB3 DB2 DB1 DB0

Power- down
mode

Don’t care

Power down/Power up
channel selection;
set bit to 1 to select
channel

Rev. 0 | Page 16 of 24

AD5663

Synchronous

LDAC

: The DAC registers are updated after new

data is read in on the falling edge of the 24th SCLK pulse.
LDAC

can be permanently low or pulsed, as shown in Figure 2.

Asynchronous

time that the input registers are written to. When

LDAC

: The outputs are not updated at the same

LDAC

goes
low, the DAC registers are updated with the contents of the
input register.

LDAC

The
over the hardware

register gives the user full flexibility and control

LDAC

pin. This register allows the user to
select which combination of channels to simultaneously update
when the hardware

LDAC

pin is executed. Setting the

LDAC

bit
register to 0 for a DAC channel means that the update of this
channel is controlled by the

LDAC

pin. If this bit is set to 1, this
channel synchronously updates; that is, the DAC register is
updated after new data is read in, regardless of the state of the
LDAC

pin. It effectively sees the

See

Table 13 for the

LDAC

LDAC

pin as being pulled low.

register mode of operation.

Table 14. 24-Bit Input Shift Register Contents for

MSB
DB23 to DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 to DB2 DB1 DB0

x 1 1 0 x x x x DAC B DAC A
Don’t care Command bits (C2 to C0) Address bits (A3 to A0);

LDAC

Don’t care

Register Setup Command

This flexibility is useful in applications where the user wants to
simultaneously update select channels while the rest of the
channels are synchronously updating

Writing to the DAC using Command 110 loads the 2-bit

LDAC

register [DB1:DB0]. The default for each channel is 0; that is,

LDAC

the
DAC register is updated regardless of the state of the
See
LDAC

Table 13.

LDAC
(DB1 to DB0)

0 1/0

1 x = don’t care

pin works normally. Setting the bits to 1 means the

LDAC

pin.

Table 14 for contents of the input shift register during the

register setup command.

LDAC

Register Mode of Operation

Bits

Don’t care

LDAC

Pin

Set DAC to 0 or 1 for required mode of
operation

Operation

LDAC

Determined by

The DAC registers are updated
after new data is read in on the
falling edge of the 24th SCLK
pulse

LDAC pin

LSB

Rev. 0 | Page 17 of 24

AD5663

MICROPROCESSOR INTERFACING

AD5663 to Blackfin® ADSP BF53x Interface

Figure 32 shows a serial interface between the AD5663 and the

Blackfin ADSP-BF53x microprocessor. The ADSP-BF53x processor

family incorporates two dual-channel synchronous serial ports,
SPORT1 and SPORT0, for serial and multiprocessor
communications. Using SPORT0 to connect to the AD5663, the
setup for the interface is as follows:

• DT0PRI drives the DIN pin of the AD5663.

• TSCLK0 drives the SCLK of the part.

• The

AD5663 to 68HC11/68L11 Interface

Figure 33 shows a serial interface between the AD5663 and the
68HC11/68L11 microcontroller. SCK of the 68HC11/68L11
drives the SCLK of the AD5663, and the MOSI output drives
the serial data line of the DAC.

The
conditions for correct operation of this interface are as follows:

• The 68HC11/68L11 is configured with its CPOL bit as 0.

• The 68HC11/68L11 is configured with its CPHA bit as 1.

When data is being transmitted to the DAC, the
taken low (PC7). When the 68HC11/68L11 is configured as
previously described, data appearing on the MOSI output is
valid on the falling edge of SCK. Serial data from the
68HC11/68L11 is transmitted in 10-bit bytes with only eight
falling clock edges occurring in the transmit cycle. Data is
transmitted MSB first. To load data to the AD5663, PC7 is left
low after the first eight bits are transferred, and a second serial
write operation is performed to the DAC. PC7 is taken high at
the end of this procedure.

SYNC

pin is driven from TFS0.

AD5663

1

TFS0

1

SYNC

DINDTOPRI

SCLKTSCLK0

ADSP-BF53x

1

ADDITIONAL PINS OMITTED FO R CLARITY.

Figure 32. AD5663 to Blackfin ADSP-BF53x Interface

SYNC

signal is derived from a port line (PC7). The setup

05855-037

SYNC

line is

PC7

1

SYNC

SCLKSCK

DINMOSI

68HC11/68L11

1

ADDITIONAL PINS OMI TTED FO R CLARITY.

Figure 33. AD5663 to 68HC11/68L11 Interface

AD5663 to 80C51/80L51 Interface

Figure 34 shows a serial interface between the AD5663 and the
80C51/80L51 microcontroller. The setup for the interface is as
follows:

• TxD of the 80C51/80L51 drives SCLK of the AD5663.

• RxD drives the serial data line of the part.

SYNC

The

signal is again derived from a bit-programmable pin
on the port. In this case, Port Line P3.3 is used. When data is to be
transmitted to the AD5663, P3.3 is taken low. The 80C51/80L51
transmits data in 10-bit bytes only; thus only eight falling clock
edges occur in the transmit cycle. To load data to the DAC, P3.3
is left low after the first eight bits are transmitted, and a second
write cycle is initiated to transmit the second byte of data. P3.3
is taken high following the completion of this cycle. The 80C51/
80L51 outputs the serial data in a format that has the LSB first.
The AD5663 must receive data with the MSB first. The 80C51/
80L51 transmit routine should take this into account.

P3.3

1

SYNC

SCLKTxD

DINRxD

80C51/80L51

1

ADDITIONAL PINS OMI TTED FO R CLARITY.

Figure 34. AD5663 to 80C51/80L51 Interface

AD5663 to MICROWIRE Interface

Figure 35 shows an interface between the AD5663 and any
MICROWIRE-compatible device. Serial data is shifted out on
the falling edge of the serial clock and is clocked into the AD5663
on the rising edge of the SK.

CS

1

SYNC

SCLKSK

DINSO

MICROWIRE

AD5663

AD5663

AD5663

1

05855-038

1

05855-039

1

1

ADDITIONAL PINS OMITTED FOR CLARITY.

Rev. 0 | Page 18 of 24

Figure 35. AD5663 to MICROWIRE Interface

05855-040

AD5663

T

V

APPLICATIONS

CHOOSING A REFERENCE FOR THE AD5663

To achieve the optimum performance from the AD5663,
thought should be given to the choice of a precision voltage
reference. The AD5663 has only one reference input, V
The voltage on the reference input is used to supply the positive
input to the DAC. Therefore, any error in the reference is
reflected in the DAC.

When choosing a voltage reference for high accuracy applica­tions, the sources of error are initial accuracy, ppm drift, long­term drift, and output voltage noise. Initial accuracy on the
output voltage of the DAC leads to a full-scale error in the
DAC. To minimize these errors, a reference with high initial
accuracy is preferred. Also, choosing a reference with an output
trim adjustment, such as the

ADR423, allows a system designer

to trim system errors out by setting a reference voltage to a
voltage other than the nominal. The trim adjustment can also
be used at temperature to trim out any error.

Long-term drift is a measurement of how much the reference
drifts over time. A reference with a tight long-term drift specifi­cation ensures that the overall solution remains relatively stable
during its entire lifetime.

The temperature coefficient of a reference’s output voltage
affects INL, DNL, and TUE. A reference with a tight temperature
coefficient specification should be chosen to reduce temperature
dependence of the DAC output voltage in ambient conditions.

In high accuracy applications, which have a relatively low noise
budget, reference output voltage noise needs to be considered.
It is important to choose a reference with as low an output noise
voltage as practical for the system noise resolution required.
Precision voltage references, such as the

ADR425, produce low

output noise in the 0.1 Hz to 10 Hz range. Examples of recom­mended precision references for use as supplies to the AD5663
are shown in the

Table 1 5.

Table 15. Partial List of Precision References for Use with the AD5663

Part No. Initial Accuracy (mV Max) Temperature Drift (ppmoC Max) 0.1 Hz to 10 Hz Noise (μV p-p Typ) V

ADR425 ±2 3 3.4 5

ADR395 ±6 25 5 5

REF195 ±2 5 50 5

AD780 ±2 3 4 2.5/3

ADR423 ±2 3 3.4 3

REF

.

USING A REFERENCE AS A POWER SUPPLY FOR THE AD5663

Because the supply current required by the AD5663 is extremely
low, an alternative option is to use a voltage reference to supply
the required voltage to the part (see
useful if the power supply is quite noisy, or if the system supply
voltages are at some value other than 5 V or 3 V (for example,
15 V). The voltage reference outputs a steady supply voltage for
the AD5663; see
out

REF195 is used, it must supply 250 µA of current to the

Table 1 5 for a suitable reference. If the low drop-

AD5663, with no load on the output of the DAC. When the
DAC output is loaded, the REF195 also needs to supply the
current to the load. The total current required (with a 5 kΩ
load on the DAC output) is

250 µA + (5 V/5 kΩ) = 1.25 mA

The load regulation of the REF195 is typically 2 ppm/mA,
which results in a 2.5 ppm (12.5 µV) error for the 1.25 mA
current drawn from it. This corresponds to a 0.164 LSB error.

15

REF195

HREE-WIRE

SERIAL

INTERFACE

SYNC

SCLK

DIN

Figure 36. REF195 as Power Supply to the AD5663

Figure 36). This is especially

5V

500µA

V

V

REF

DD

AD5663

V

OUT

= 0V TO 5V

OUT

05855-041

(V)

Rev. 0 | Page 19 of 24

AD5663

BIPOLAR OPERATION USING THE AD5663

The AD5663 has been designed for single-supply operation,
but a bipolar output range is also possible using the circuit in
Figure 37. The circuit gives an output voltage range of ±5 V.
Rail-to-rail operation at the amplifier output is achievable using
an

AD820 or an OP295 as the output amplifier.

The output voltage for any input code can be calculated as

⎡

VV

×=

⎢

O

⎣

⎞

⎛

⎟

⎜

536,65

⎠

⎝

R2R1D

+

R1

⎞

V

⎟

DDDD

⎠

⎛

×

⎜
⎝

⎤

R2

⎞

⎛

×−

⎟

⎜

⎥

R1

⎠

⎝

⎦

where D represents the input code in decimal (0 to 65,535).

With V

= 5 V, R1 = R2 = 10 kΩ

DD

×

D

10

⎛

=

V

⎜

O

⎝

⎞

V5

−

⎟

536,65

⎠

This is an output voltage range of ±5 V, with 0x0000 corre­sponding to a −5 V output, and 0xFFFF corresponding to a
+5 V output.

R2 = 10kΩ

+5V

R1 = 10kΩ

V

DDVOUT

0.1µF10µF

Figure 37. Bipolar Operation with the AD5663

AD5663

THREE-WIRE

SERIAL

INTERFACE

+5V

AD820/

OP295

–5V

±5V

05855-042

USING THE AD5663 WITH A GALVANICALLY ISOLATED INTERFACE

In process control applications in industrial environments, it
is often necessary to use a galvanically isolated interface to
protect and isolate the controlling circuitry from any hazardous
common-mode voltages that can occur in the area where the
DAC is functioning. iCoupler® provides isolation in excess of

2.5 kV. The AD5663 use a 3-wire serial logic interface, so the

ADuM1300 three-channel digital isolator provides the required

isolation (see
needs to be isolated, which is done by using a transformer. On
the DAC side of the transformer, a 5 V regulator provides the
5 V supply required for the AD5663.

Figure 38). The power supply to the part also

POWER

SCLK

DATA

V

IA

ADuM1300

SDI

V

IB

V

IC

Figure 38. AD5663 with a Galvanically Isolated Interface

V

OA

V

OB

V

OC

POWER SUPPLY BYPASSING AND GROUNDING

When accuracy is important in a circuit, it is helpful to carefully
consider the power supply and ground return layout on the
board. The printed circuit board containing the AD5663 should
have separate analog and digital sections, each having its own
area of the board. If the AD5663 is in a system where other
devices require an AGND-to-DGND connection, the connection
should be made at one point only. This ground point should be
as close as possible to the AD5663.

The power supply to the AD5663 should be bypassed with 10 µF
and 0.1 µF capacitors. The capacitors should be located as close
as possible to the device, with the 0.1 µF capacitor ideally right
up against the device. The 10 µF capacitors are of the tantalum
bead type. It is important that the 0.1 µF capacitor have low
effective series resistance (ESR) and effective series inductance
(ESI) as in, for example, common ceramic types of capacitors.
This 0.1 µF capacitor provides a low impedance path to ground
for high frequencies caused by transient currents due to internal
logic switching.

The power supply line itself should have as large a trace as
possible to provide a low impedance path and to reduce glitch
effects on the supply line. Clocks and other fast switching
digital signals should be shielded from other parts of the board
by digital ground. Avoid crossover of digital and analog signals
if possible. When traces cross on opposite sides of the board,
ensure that they run at right angles to each other to reduce
feedthrough effects through the board. The best board layout
technique is the microstrip technique, where the component
side of the board is dedicated to the ground plane only, and the
signal traces are placed on the solder side. However, this is not
always possible with a 2-layer board.

5V

REGULATOR

SCLK

SYNC

DIN

V

DD

AD5663

GND

V

10µF

OUT

0.1µF

05855-043

Rev. 0 | Page 20 of 24

AD5663

S

OUTLINE DIMENSIONS

INDEX

ORDERING GUIDE

Model

AD5663ARMZ
AD5663ARMZ-REEL7

AD5663BRMZ
AD5663BRMZ-REEL7
AD5663BRMZ-1
AD5663BRMZ-1REEL7
AD5663BCPZ-250RL7
AD5663BCPZ-REEL7

1

Z = Pb-free part.

1

1

1

1

1

1

1.50

BCS SQ

0.80

0.75

0.70

EATING

PLANE

AREA

3.00

BSC SQ

TOP VIEW

SIDE VIEW

0.30

0.23

0.18

0.80 MAX

0.55 TYP

0.50
BSC

0.50

0.40

0.30

0.05 MAX

0.02 NOM

0.20 REF

Figure 39. 10-Lead Lead Frame Chip Scale Package [LFCSP_WD]

3 mm x 3 mm Body, Very Very Thin, Dual Lead

(CP-10-9)

Dimensions shown in millimeters

3.10

3.00

2.90

6

0.95

0.85

0.75

3.10

3.00

2.90

0.15

0.05

PIN 1

10

1

0.50 BSC

0.33

0.17

COPLANARITY

0.10

COMPLIANT TO JEDEC STANDARDS MO-187-BA

5.15

4.90

4.65

5

1.10 MAX

SEATING
PLANE

0.23

0.08

Figure 40. 10-Lead Mini Small Outline Package [MSOP]

(RM-10)

Dimensions shown in millimeters

Temperature
Range

Power-On
Reset Code

Accuracy

−40°C to +105°C Zero ±16 LSB INL 10-lead MSOP RM-10 D80

−40°C to +105°C Zero ±16 LSB INL 10-lead MSOP RM-10 D80

−40°C to +105°C Zero ±12 LSB INL 10-lead MSOP RM-10 D8C

−40°C to +105°C Zero ±12 LSB INL 10-lead MSOP RM-10 D8C

−40°C to +105°C Midscale ±12 LSB INL 10-lead MSOP RM-10 D7J

1

−40°C to +105°C Midscale ±12 LSB INL 10-lead MSOP RM-10 D7J

1

−40°C to +105°C Zero ±12 LSB INL 10-lead LFCSP_WD CP-10-9 D8C

−40°C to +105°C Zero ±12 LSB INL 10-lead LFCSP_WD CP-10-9 D8C

10

EXPOSED

PAD

(BOTTOM VIEW)

6

1.74

1.64

1.49

8°
0°

Package
Description

PIN 1
INDICATOR

1

5

0.80

0.60

0.40

2.48

2.38

2.23

Package
Option

Branding

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AD5663

NOTES

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AD5663

NOTES

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AD5663

NOTES

©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05855-0-4/06(0)

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