Datasheet AD5662 Datasheet (Analog Devices)

2.7 V to 5.5 V, 250 µA, Rail-to-Rail Output

FEATURES

Low power (250 µA @ 5 V) single 16-bit nanoDAC
12-bit accuracy guaranteed
Tiny 8-lead SOT-23/MSOP package
Power-down to 480 nA @ 5 V, 100 nA @ 3 V
Power-on reset to zero scale/midscale

2.7 V to 5.5 V power supply
Guaranteed 16-bit monotonic by design
3 power-down functions
Serial interface with Schmitt-triggered inputs
Rail-to-rail operation
SYNC interrupt facility
Temperature range −40°C to +125°C

APPLICATIONS

Process control
Data acquisition systems
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators

GENERAL DESCRIPTION

The AD5662, a member of the nanoDAC family, is a low power,
single, 16-bit buffered voltage-out DAC that operates from a
single 2.7 V to 5.5 V supply and is guaranteed monotonic by
design.

16-Bit

nano

DACTM in a SOT-23

AD5662

FUNCTIONAL BLOCK DIAGRAM

V

REF

POWER-ON

RESET

DAC

REGISTER

INPUT

CONTROL

LOGIC

SYNC SCLK DIN

REF(+)

16-BIT

DAC

The AD5662 uses a versatile 3-wire serial interface that operates
at clock rates up to 30 MHz, and is compatible with standard
SPI®, QSPI™, MICROWIRE™, and DSP interface standards.

V

DD

GND

OUTPUT
BUFFER

POWER-DOWN

CONTROL LOGIC

Figure 1.

AD5662

RESISTOR
NETWORK

V

FB

V

OUT

04777-001

The AD5662 requires an external reference voltage to set the
output range of the DAC. The part incorporates a power-on
reset circuit that ensures the DAC output powers up to 0 V
(AD5662x-1) or to midscale (AD5662x-2), and remains there
until a valid write takes place. The part contains a power-down
feature that reduces the current consumption of the device to
480 nA at 5 V and provides software-selectable output loads
while in power-down mode.

The low power consumption of this part in normal operation
makes it ideally suited to portable battery-operated equipment.
The power consumption is 0.75 mW at 5 V, going down to

2.4 µW in power-down mode.

The AD5662’s on-chip precision output amplifier allows rail-to­rail output swing to be achieved. For remote sensing applications,
the output amplifier’s inverting input is available to the user.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

PRODUCT HIGHLIGHTS

1. 16-bit DAC—12-bit accuracy guaranteed.

2. Available in 8-lead SOT-23 and 8-lead MSOP packages.

3. Low power. Typically consumes 0.42 mW at 3 V and

0.75 mW at 5 V.

4. Power-on reset to zero scale or to midscale.

5. 10 µs max settling time.

RELATED DEVICES

Part No. Description

AD5620/AD5640/AD5660

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]
Fax: [phone] © 2005 Analog Devices, Inc. All rights reserved.

www.analog.com

3 V/5 V 12-/14-/16-bit DAC with
internal reference in SOT-23

AD5662

TABLE OF CONTENTS

Specifications..................................................................................... 3

Timing Characteristics..................................................................... 5

Absolute Maximum Ratings............................................................ 6

ESD Caution.................................................................................. 6

Pin Configuration and Function Description .............................. 7

Typical Performance Characteristics ............................................. 8

Te r mi n ol o g y .................................................................................... 13

Theory of Operation ...................................................................... 14

DAC Section ................................................................................ 14

Resistor String............................................................................. 14

Output Amplifier........................................................................ 14

Serial Interface............................................................................ 14

Input Shift Register..................................................................... 15

Interrupt........................................................................... 15

SYNC

Power-On Reset .......................................................................... 15

Power-Down Modes .................................................................. 16

Microprocessor Interfacing....................................................... 16

Applications..................................................................................... 18

Choosing a Reference for the AD5662.................................... 18

Using a Reference as a Power Supply for the AD5662 .......... 18

Bipolar Operation Using the AD5662..................................... 19

Using the AD5662 as an Isolated, Programmable, 4-20 mA
Process Controller

Using AD5662 with a Galvanically Isolated Interface........... 20

Power Supply Bypassing and Grounding................................ 20

Outline Dimensions ....................................................................... 21

Ordering Guide .......................................................................... 22

...................................................................... 19

REVISION HISTORY

1/05—Revision 0: Initial Version

Rev. 0 | Page 2 of 24

AD5662

SPECIFICATIONS

VDD = 2.7 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; V

Table 1.

A Grade B Grade Y Version
Parameter Min Typ Max Min Typ Max Unit Conditions/Comments

STATIC PERFORMANCE

2

Resolution 16 16 Bits
Relative Accuracy ±8 ±32 ±8 ±16 LSB See Figure 4
Differential Nonlinearity ±1 ±1 LSB

Zero Code Error 2 10 2 10 mV All 0s loaded to DAC register
Full-Scale Error −0.2 −1 −0.2 −1 % FSR All 1s loaded to DAC register
Offset Error ±10 ±10 mV
Gain Error ±1.5 ±1.5 % FSR
Zero Code Error Drift
Gain Temperature Coefficient

3

±2 ±2 µV/°C

3

±2.5 ±2.5 ppm Of FSR/°C

DC Power Supply Rejection Ratio3 −100 −100 dB DAC code = midscale; VDD = 5 V/3 V ±10%

OUTPUT CHARACTERISTICS

Output Voltage Range 0 V

3

DD

Output Voltage Settling Time 8 10 8 10 µs

Slew Rate 1.5 1.5 V/µs ¼ to ¾ scale
Capacitive Load Stability 2 2 nF RL = ∞
10 10 nF RL = 2 kΩ
Output Noise Spectral Density
Output Noise (0.1 Hz to 10 Hz)

4

100 100 nV/√Hz DAC code = midscale,10 kHz

4

10 10 µV p-p DAC code = midscale
Total Harmonic Distortion (THD)4 −80 −80 dB V
Digital-to-Analog Glitch Impulse 5 5 nV-s 1 LSB change around major carry
Digital Feedthrough 0.1 0.1 nV-s
DC Output Impedance 0.5 0.5 Ω
Short-Circuit Current

4

30 30 mA VDD = 5 V, 3 V
Power-Up Time 4 4 µs

REFERENCE INPUT

3

Reference Current 40 75 40 75 µA V
30 50 30 50 µA V
Reference Input Range

5

0.75 V

DD

Reference Input Impedance 125 125 kΩ

LOGIC INPUTS3

Input Current ±2 ±2 µA All digital inputs
V

, Input Low Voltage 0.8 0.8 V VDD = 5 V, 3 V

INL

V

, Input High Voltage 2 2 V VDD = 5 V, 3 V

INH

Pin Capacitance 3 3 pF

= VDD; all specifications T

REF

0 V

0.75 V

DD

DD

to T

MIN

MAX

Guaranteed monotonic by design
See Figure 5

V

¼ to ¾ scale change settling to ±2 LSB

= 2 kΩ; 0 pF < CL < 200 pF

R

L

= 2 V ± 300 mV p-p, f = 5 kHz

REF

Coming out of power-down mode

= 5 V, 3 V

V

DD

= VDD = 5 V

REF

= VDD = 3.6 V

REF

V

, unless otherwise noted.

1

Rev. 0 | Page 3 of 24

AD5662

A Grade B Grade Y Version

1

Parameter Min Typ Max Min Typ Max Unit Conditions/Comments

POWER REQUIREMENTS

VDD 2.7 5.5 2.7 5.5 V All digital inputs at 0 V or V

DD

IDD (Normal Mode) DAC active and excluding load current
VDD = 4.5 V to 5.5 V 150 250 150 250 µA VIH = VDD and VIL = GND
VDD = 2.7 V to 3.6 V 140 225 140 225 µA VIH = VDD and VIL = GND

IDD (All Power-Down Modes)

VDD = 4.5 V to 5.5 V 0.48 1 0.48 1 µA VIH = VDD and VIL = GND
VDD = 2.7 V to 3.6 V 0.1 0.375 0.1 0.375 µA VIH = VDD and VIL = GND

POWER EFFICIENCY

I

OUT/IDD

1

Temperature range is as follows: Y version: −40°C to +125°C, typical at +25°C.

2

DC specifications tested with the outputs unloaded, unless otherwise stated. Linearity calculated using a reduced code range of 512 to 65024.

3

Guaranteed by design and characterization; not production tested.

4

Output unloaded.

5

Reference input range at ambient where ±1 LSB max DNL specification is achievable.

90 90 % I

= 2 mA. VDD = 5 V

LOAD

Rev. 0 | Page 4 of 24

AD5662

TIMING CHARACTERISTICS

All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 2.

= 2.7 V to 5.5 V; all specifications T

V

DD

Table 2.

Limit at T
Parameter VDD = 2.7 V to 3.6 V VDD = 3.6 V to 5.5 V Unit Conditions/Comments

1

t

1

t

2

t

3

t

4

t

5

t

6

t

7

t

8

t

9

t

10

1

Maximum SCLK frequency is 30 MHz at VDD = 3.6 V to 5.5 V, and 20 MHz at VDD = 2.7 V to 3.6 V.

50 33 ns min SCLK cycle time
13 13 ns min SCLK high time
13 13 ns min SCLK low time
13 13 ns min

5 5 ns min Data setup time

4.5 4.5 ns min Data hold time
0 0 ns min

50 33 ns min
13 13 ns min
0 0 ns min

MIN

to T

, unless otherwise noted.

MAX

, T

MIN

MAX

SYNC to SCLK falling edge setup time

SCLK falling edge to
Minimum

SYNC high time
SYNC rising edge to SCLK fall ignore
SCLK falling edge to

SYNC rising edge

SYNC fall ignore

t

SCLK

SYNC

DIN

10

t

8

DB23

t

4

t

6

t

5

t

1

t

t

3

2

t

DB0

t

9

7

04777-002

Figure 2. Serial Write Operation

Rev. 0 | Page 5 of 24

AD5662

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 3.

Parameter Rating

VDD to GND −0.3 V to +7 V
V

to GND −0.3 V to VDD + 0.3 V

OUT

VFB to GND −0.3 V to VDD + 0.3 V
V

to GND −0.3 V to VDD + 0.3 V

REF

Digital Input Voltage to GND −0.3 V to VDD + 0.3 V
Operating Temperature Range

Industrial (Y Version) −40°C to +125°C
Storage Temperature Range −65°C to +150°C
Junction Temperature (TJ max) 150°C

Power Dissipation (TJ max − TA)/θ
SOT-23 Package (4-Layer Board)

θJA Thermal Impedance 119°C/W
MSOP Package (4-Layer Board)

θJA Thermal Impedance 141°C/W

θJC Thermal Impedance 44°C/W
Reflow Soldering Peak Temperature

SnPb 240°C

Pb-free 260°C
ESD 2 kV

JA

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. 0 | Page 6 of 24

AD5662

V

PIN CONFIGURATION AND FUNCTION DESCRIPTION

V

V

REF

V

OUT

DD

FB

1

AD5662

2

TOP VIEW

3

(Not to Scale)

4

8

7

6

5

GND
DIN
SCLK
SYNC

04777-003

Figure 3. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Function

1 VDD Power Supply Input. These parts can be operated from 2.7 V to 5.5 V. VDD should be decoupled to GND.
2 V
3 VFB Feedback Connection for the Output Amplifier. VFB should be connected to V
4 V
5

6 SCLK

Reference Voltage Input.

REF

for normal operation.

OUT

Analog Output Voltage from DAC. The output amplifier has rail-to-rail operation.

OUT

SYNC Level-Triggered Control Input (Active Low). This is the frame synchronization signal for the input data. When SYNC

goes low, it enables the input shift register, and data is transferred in on the falling edges of the following clocks.
The DAC is updated following the 24
rising edge of

SYNC acts as an interrupt and the write sequence is ignored by the DAC.

th

clock cycle unless SYNC is taken high before this edge, in which case the

Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can
be transferred at rates up to 30 MHz.

7 DIN

Serial Data Input. This device has a 24-bit shift register. Data is clocked into the register on the falling edge of the
serial clock input.

8 GND Ground Reference Point for All Circuitry on the Part.

Rev. 0 | Page 7 of 24

AD5662

TYPICAL PERFORMANCE CHARACTERISTICS

10

VDD = V

8

T

6
4
2

0

–2

INL ERROR (LSB)

–4

–6
–8

–10

0 5k 10k 15k 20k 25k 30k 35k 40k 45k 50k 55k 60k 65k

90

VDD = V
T

80

70

60

50

40

ERROR (LSB)

30

20

10

0

511 2051110511 30511 5051140511 60511

= 5V

REF

= 25°C

A

CODE

Figure 4. Typical INL Plot

Figure 5. Typical DNL Plot

= 5V

REF

= 25°C

A

CODES

Figure 6. Typical Total Unadjusted Error Plot

04777-011

04777-019

8

6

V

= V

= 5V

DD

4

2

0

ERROR (LSB)

–2

–4

–6

–8

–40 –20 40200 1008060 120

REF

MAX DNL

MIN DNL

TEMPERATURE (°C)

Figure 7. INL Error and DNL Error vs. Temperature

10

8

6

V

= 5V

DD

4

= 25°C

T

A

2

0

–2

ERROR (LSB)

–4

–6

–8

–10

0.75 1.25 1.75 2.25 4.253.753.252.75 4.75
V

(V)

REF

Figure 8. INL and DNL Error vs. V

MAX DNL

MIN DNL

REF

8

6

= 25°C

T

A

4

2

0

ERROR (LSB)

–2

–4

–6

–8

2.7 3.2 3.7 4.74.2 5.2
VDD (V)

MAX DNL

MIN DNL

Figure 9. INL and DNL Error vs. Supply

MAX INL

MIN INL

04777-036

MAX INL

MIN INL

04777-045

MAX INL

MIN INL

04777-041

Rev. 0 | Page 8 of 24

AD5662

0

VDD = 5V

–0.22

–0.04

–0.06

–0.08

–0.01
–0.12

ERROR (% FSR)

–0.14
–0.16

–0.18
–0.20

–40 –20 40200 1008060 120

GAIN ERROR

FULL-SCALE ERROR

TEMPERATURE (°C)

Figure 10. Gain Error and Full-Scale Error vs. Temperature

1.5

1.0

0.5

0

–0.5

ERROR (mV)

–1.0

–1.5

–2.0

–2.5

–40 –20 40200 1008060 120

ZERO-SCALE ERROR

OFFSET ERROR

TEMPERATURE (°C)

Figure 11. Zero-Scale and Offset Error vs. Temperature

1.0

0.5

GAIN ERROR

0

–0.5

ERROR (% FSR)

–1.0

–1.5

–2.0

FULL-SCALE ERROR

2.7 3.2 3.7 4.74.2 5.2
VDD (V)

Figure 12. Gain Error and Full-Scale Error vs. Supply

04777-038

04777-035

04777-042

1.0
= 25°C

T

A

0.5

0

–0.5

–1.0

ERROR (mV)

–1.5

–2.0

–2.5

2.7 3.2 4.23.7 5.24.7

ZERO-SCALE ERROR

OFFSET ERROR

VDD (V)

Figure 13. Zero-Scale and Offset Error vs. Supply

20

VDD = V

18

T
16

14

12

10

8

6

NUMBER OF DEVICES

4

2
0

215

REF

= 25°C

A

216

217

Figure 14. I

= 5.5V

218

222

221

220

219

DD

223

IDD (µA)

Histogram with VDD = 5.5 V

224

225

226

227

228

229

230

231

232

0.20
VDD= V

T

0.15

0.10

0.05

0

–0.05

–0.10

ERROR VOLTAGE (V)

–0.15

–0.20

–0.25

–5 –4 –3 –2 –1 0 1 2 435

= 5V, 3V

REF

= 25°C

A

DAC LOADED WITH
FULL SCALE –
SOURCING CURRENT

DAC LOADED WITH
ZERO SCALE –
SINKING CURRENT

I (mA)

Figure 15. Headroom at Rails vs. Source and Sink Current

MORE

04777-039

04777-046

04777-013

Rev. 0 | Page 9 of 24

AD5662

250

TA = 25°C

200

150

(µA)

DD

I

100

50

0

512 10512 3051220512 50512 6051240512

Figure 16. Supply Current vs. Code

160

V

=5V

DD

140

120

VDD = 3V

100

(µA)

80

DD

I

60

CODE

VDD = V

VDD = V

REF

REF

= 5V

= 3V

04777-043

1000

TA = 25°C

900

800
700

600

A)

µ

500

(

DD

I

400
300

200
100

0

012 43

VDD = 5V

VDD = 3V

V

LOGIC

(V)

Figure 19. Supply Current vs. Logic Input Voltage

VDD = V

= 25°C

T

A

FULL-SCALE CODE CHANGE
0x0000 TO 0xFFFF
OUTPUT LOADED WITH 2kΩ
AND 200pF TO GND

V

= 455mV/DIV

OUT

REF

= 3V

04777-044

5

40

20

0

–40 –20 40200 1008060 120

TEMPERATURE (°C)

Figure 17. Supply Current vs. Temperature

160

TA = 25°C

140

120

100

A)

µ

(

80

DD

I

60

40

20

0

2.7 3.2 4.23.7 5.24.7
VDD (V)

Figure 18. Supply Current vs. Supply Voltage

04777-037

04777-040

TIME BASE = 4µs/DIV

04777-014

Figure 20. Full-Scale Settling Time, 3 V

VDD = V
T
FULL-SCALE CODE CHANGE
0x0000 TO 0xFFFF
OUTPUT LOADED WITH 2kΩ
AND 200pF TO GND

V

= 909mV/DIV

OUT

1

TIME BASE = 4µs/DIV

= 25°C

A

REF

= 5V

04777-015

Figure 21. Full-Scale Settling Time, 5 V

Rev. 0 | Page 10 of 24

AD5662

VDD = V
T

V

1

2

DD

V

OUT

CH1 2.0V CH2 500mV M100µs 125MS/s

A CH1 1.28V

Figure 22. Power-On Reset to 0 V

VDD = V
T

V

1

2

DD

V

OUT

CH1 2.0V CH2 1.0V M100µs 125MS/s

A CH1 1.28V

Figure 23. Power-On Reset to Midscale

1

2

SCLK

V

OUT

CH1 2.0V CH2 1.0V M1.0µs 5.0gS/s

A CH2 2.16V

Figure 24. Exiting Power-Down to Midscale

= 25°C

A

= 25°C

A

= 5V

REF

MAX(C2)*

420.0mV

8.0ns/pt

= 5V

REF

8.0ns/pt

200ps/pt

04777-016

04777-017

04777-018

2.502500

2.502250

2.502000

2.501750

2.501500

2.501250

2.501000

2.500750

2.500500

2.500250

AMPLITUDE

2.500000

2.499750

2.499500

2.499250

2.499000

2.498750
0 150 200 25050 100 300 350 400 450 500 550

Figure 25. Digital-to-Analog Glitch Impulse (Negative)

2.500400

2.500300

2.500200

2.500100

2.500000

2.499900

2.499800

2.499700

AMPLITUDE

2.499600

2.499500

2.499400

2.499300

2.499200

2.499100
0 150 200 25050 100 300 350 400 450 500 550

Figure 26. Digital-to-Analog Glitch Impulse (Positive)

2.500250

2.500200

2.500150

2.500100

2.500050

2.500000

2.499950

2.499900

AMPLITUDE

2.499850

2.499800

2.499750

2.499700

2.499650

2.499600
0 150 200 25050 100 300 350 400 450 500 550

Figure 27. Digital Feedthrough

VDD = V
T
13nS/SAMPLE NUMBER
1 LSB CHANGE AROUND

GLITCH IMPULSE = 2.723nV.s

SAMPLE NUMBER

= 5V

REF

= 25°C

A

MIDSCALE (0x8000 TO 0x7FFF)

VDD = V
T
13nS/SAMPLE NUMBER
1 LSB CHANGE AROUND

GLITCH IMPULSE = 1.271nV.s

SAMPLE NUMBER

= 5V

REF

= 25°C

A

MIDSCALE (0x7FFF TO 0x8000)

VDD = V
T
20nS/SAMPLE NUMBER
DAC LOADED WITH MIDSCALE
DIGITAL FEEDTHROUGH = 0.06nV.s

SAMPLE NUMBER

= 25°C

A

REF

= 5V

04777-005

04777-006

04777-007

Rev. 0 | Page 11 of 24

AD5662

–20

VDD = 5V

= 25°C

T

A

–30

DAC LOADED WITH FULL SCALE

= 2V ± 0.3Vp-p

V

REF

–40

–50

–60

dB

–70

–80

–90

–100

2k 4k 6k 8k 10k

Hz

Figure 28. Total Harmonic Distortion

16

V

= V

REF

DD

TA = 25°C

14

V

3V

=

12

s)

µ

10

TIME (

8

6

4

01234567 981

CAPACITANCE (nF)

DD

V

5V

=

DD

Figure 29. Settling Time vs. Capacitive Load

04777-008

04777-009

0

VDD = V
T
DAC LOADED WITH MIDSCALE

1

Y AXIS = 2µV/DIV
X AXIS = 4s/DIV

= 25°C

A

REF

= 5V

Figure 30. 0.1 Hz to 10 Hz Output Noise Plot

800

VDD = V
T

700

600

500

400

300

OUTPUT NOISE (nV/√Hz)

200

100

0

10 100k10k1k100 1M

= 25°C

A

REF

= 5V

Figure 31. Noise Spectral Density

FREQUENCY (Hz)

04777-010

04777-020

Rev. 0 | Page 12 of 24

AD5662

TERMINOLOGY

Relative Accuracy or Integral Nonlinearity (INL)
For the DAC, relative accuracy or integral nonlinearity is a
measurement of the maximum deviation, in LSBs, from a
straight line passing through the endpoints of the DAC transfer
function. A typical INL vs. code plot can be seen in Figure 4.

Offset Error

Offset error is a measure of the difference between V
and V

(ideal) expressed in mV in the linear region of the

OUT

(actual)

OUT

transfer function. Offset error is measured on the AD5662 with
Code 512 loaded in the DAC register.

It can be negative or positive.

Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of ±1 LSB maximum
ensures monotonicity. This DAC is guaranteed monotonic by
design. A typical DNL vs. code plot can be seen in Figure 5.

Zero-Code Error
Zero-code error is a measurement of the output error when
zero code (0x0000) is loaded to the DAC register. Ideally, the
output should be 0 V. The zero-code error is always positive in
the AD5662 because the output of the DAC cannot go below
0 V. It is due to a combination of the offset errors in the DAC
and the output amplifier. Zero-code error is expressed in mV. A
plot of zero-code error vs. temperature can be seen in Figure 11.

Full-Scale Error
Full-scale error is a measurement of the output error when full­scale code (0xFFFF) is loaded to the DAC register. Ideally, the
output should be V

− 1 LSB. Full-scale error is expressed in

DD

percent of full-scale range. A plot of full-scale error vs.
temperature can be seen in Figure 10.

Gain Error
This is a measure of the span error of the DAC. It is the deviation
in slope of the DAC transfer characteristic from ideal expressed
as a percent of the full-scale range.

Tota l Una d ju s te d Er ro r ( TU E)
Total unadjusted error is a measurement of the output error,
taking all the various errors into account. A typical TUE vs.
code plot can be seen in Figure 6.

Zero-Code Error Drift
This is a measurement of the change in zero-code error with a
change in temperature. It is expressed in µV/°C.

Gain Temperature Coefficient
This is a measurement of the change in gain error with changes
in temperature. It is expressed in (ppm of full-scale range)/°C.

DC Power Supply Rejection Ratio (PSRR)

This indicates how the output of the DAC is affected by changes
in the supply voltage. PSRR is the ratio of the change in V
change in V
dB. V

REF

Output Voltage Settling Time

This is the amount of time it takes for the output of a DAC to settle
to a specified level for a ¼ to ¾ full-scale input change and is
measured from the 24

for full-scale output of the DAC. It is measured in

DD

is held at 2 V, and VDD is varied by ±10%.

th

falling edge of SCLK.

OUT

to a

Digital-to-Analog Glitch Impulse
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is normally specified as the area of the glitch in nV-s,
and is measured when the digital input code is changed by
1 LSB at the major carry transition (0x7FFF to 0x8000). See
Figure 25 and Figure 26.

Digital Feedthrough
Digital feedthrough is a measure of the impulse injected into
the analog output of the DAC from the digital inputs of the
DAC, but is measured when the DAC output is not updated. It
is specified in nV-s, and measured with a full-scale code change
on the data bus, that is, from all 0s to all 1s and vice versa.

Total Harmonic Distortion (THD)

This is the difference between an ideal sine wave and its attenuated
version using the DAC. The sine wave is used as the reference for
the DAC, and the THD is a measurement of the harmonics present
on the DAC output. It is measured in dB.

Noise Spectral Density

This is a measurement of the internally generated random noise.
Random noise is characterized as a spectral density (voltage per
√Hz). It is measured by loading the DAC to m

idscale and meas-

uring noise at the output. It is measured in nV/√Hz. A plot of
noise spectral density can be seen in Figure 31.

Rev. 0 | Page 13 of 24

AD5662

THEORY OF OPERATION

DAC SECTION

The AD5662 DAC is fabricated on a CMOS process. The
architecture consists of a string DAC followed by an output
buffer amplifier. Figure 32 shows a block diagram of the DAC
architecture.

V

DD

R

DAC REGISTER

REF (+)

RESISTOR

STRING

REF (–)

ٛ

GND

Figure 32. DAC Architecture

Since the input coding to the DAC is straight binary, the ideal
output voltage is given by

OUT

⎛

VV

×=

⎜

REF

⎝

65,536

⎟
⎠

D

⎞

where D is the decimal equivalent of the binary code that is
loaded to the DAC register. It can range from 0 to 65,535.

RESISTOR STRING

The resistor string section is shown in Figure 33. It is simply a
string of resistors, each of value R. The code loaded to the DAC
register determines at which node on the string the voltage is
tapped off to be fed into the output amplifier. The voltage is
tapped off by closing one of the switches connecting the string
to the amplifier. Because it is a string of resistors, it is guaranteed
monotonic.

R

R

OUTPUT

AMPLIFIER

V

FB

V

OUT

04777-022

OUTPUT AMPLIFIER

The output buffer amplifier can generate rail-to-rail voltages on
its output, which gives an output range of 0 V to V
buffer amplifier has a gain of 2 derived from a 50 kΩ resistor
divider network in the feedback path. The output amplifier’s
inverting input is available to the user, allowing for remote
sensing. This V

pin must be connected to V

FB

operation. It can drive a load of 2 kΩ in parallel with 1000 pF to
GND. The source and sink capabilities of the output amplifier can
be seen in Figure 15. The slew rate is 1.5 V/µs with a ¼ to ¾
full-scale settling time of 10 µs.

SERIAL INTERFACE

The AD5662 has a 3-wire serial interface (

SYNC
DIN) that is compatible with SPI, QSPI, and MICROWIRE
interface standards as well as with most DSPs. See Figure 2 for

a timing diagram of a typical write sequence.

The write sequence begins by bringing the

SYNC

from the DIN line is clocked into the 24-bit shift register on the
falling edge of SCLK. The serial clock frequency can be as high
as 30 MHz, making the AD5662 compatible with high speed

th

DSPs. On the 24

falling clock edge, the last data bit is clocked
in and the programmed function is executed, that is, a change
in DAC register contents and/or a change in the mode of opera­tion. At this stage, the

line can be kept low or be brought

SYNC

high. In either case, it must be brought high for a minimum of
33 ns before the next write sequence so that a falling edge of

can initiate the next write sequence. Since the

SYNC
buffer draws more current when V

= 0.8 V,

V

IN

should be idled low between write sequences

SYNC

= 2.4 V than it does when

IN

for even lower power operation. As mentioned previously it
must, however, be brought high again just before the next write
sequence.

. This output

DD

for normal

OUT

, SCLK, and

line low. Data

SYNC

R

R

R

R

Figure 33. Resistor String

TO OUTPUT
AMPLIFIER

04777-023

Rev. 0 | Page 14 of 24

AD5662

INPUT SHIFT REGISTER

The input shift register is 24 bits wide (see Figure 34). The first
six bits are don’t cares. The next two are control bits that control
the part’s mode of operation (normal mode or any one of three
power-down modes). See the Power-Down Modes section for a
more complete description of the various modes. The next 16
bits are the data bits. These are transferred to the DAC register
on the 24

SYNC

In a normal write sequence, the

least 24 falling edges of SCLK, and the DAC is updated on the
24

th

falling edge of SCLK.

INTERRUPT

th

falling edge. However, if

DB23 (MSB)

SCLK

line is kept low for at

SYNC

is brought high before the

SYNC

PD1 PD0 D15 D14 D13 D12X X X X X X D11 D10 D9 D8 D7 D6 D5 D4 D3 D2

0
0
1
1

NORMAL OPERATION

0
1

1 kΩ TO GND
100 kΩ TO GND

0

THREE-STATE

1

Figure 34. Input Register Contents

th

falling edge, this acts as an interrupt to the write sequence.

24
The shift register is reset and the write sequence is seen as
invalid. Neither an update of the DAC register contents nor a
change in the operating mode occurs (see Figure 35).

POWER-ON RESET

The AD5662 family contains a power-on reset circuit that
controls the output voltage during power-up. The AD5662x-1
DAC output powers up to 0 V, and the AD5662x-2 DAC output
powers up to midscale. The output remains there until a valid
write sequence is made to the DAC. This is useful in
applications where it is important to know the state of the
output of the DAC while it is in the process of powering up.

DBO (LSB)

D1 D0

DATA BITS

POWER-DOWN MODES

04777-024

SYNC

DIN

DB23 DB23 DB0DB0

INVALID WRITE SEQUENCE:

SYNC HIGH BEFORE 24

TH

FALLING EDGE

Figure 35.

SYNC

Interrupt Facility

VALID WRITE SEQUENCE, OUTPUT UPDATES

ON THE 24TH FALLING EDGE

04777-025

Rev. 0 | Page 15 of 24

AD5662

POWER-DOWN MODES

The AD5662 contains four separate modes of operation. These
modes are software-programmable by setting two bits (DB17
and DB16) in the control register. Table 5 shows how the state
of the bits corresponds to the device’s mode of operation.

Table 5. Modes of Operation for the AD5662

DB17 DB16 Operating Mode

0 0 Normal Operation
Power-Down Modes
0 1 1 kΩ to GND
1 0 100 kΩ to GND
1 1 Three-State

When both bits are set to 0, the part works normally with its
normal power consumption of 250 µA at 5 V. However, for the
three power-down modes, the supply current falls to 480 nA at
5 V (100 nA at 3 V). Not only does the supply current fall, but
the output stage is also internally switched from the output of
the amplifier to a resistor network of known values. This has the
advantage that the output impedance of the part is known while
the part is in power-down mode. The outputs can either be
connected internally to GND through a 1 kΩ or 100 kΩ
resistor, or left open-circuited (three-state) (see Figure 36).

RESISTOR

STRING DAC

AMPLIFIER

V

OUT

MICROPROCESSOR INTERFACING

AD5662 to Blackfin® ADSP-BF53x Interface

Figure 37 shows a serial interface between the AD5662 and
the Blackfin ADSP-BF53x microprocessor. The ADSP-BF53x
processor family incorporates two dual-channel synchronous
serial ports, SPORT1 and SPORT0, for serial and multiprocessor
communications. Using SPORT0 to connect to the AD5662, the
setup for the interface is as follows. DT0PRI drives the DIN pin
of the AD5662, while TSCLK0 drives the SCLK of the part. The

is driven from TFS0.

SYNC

ADSP-BF53x*

TFS0

DTOPRI

TSCLK0

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 37. AD5662 to Blackfin ADSP-BF53x Interface

AD5662 to 68HC11/68L11 Interface

Figure 38 shows a serial interface between the AD5662 and the
68HC11/68L11 microcontroller. SCK of the 68HC11/68L11
drives the SCLK of the AD5662, while the MOSI output drives
the serial data line of the DAC.

AD5662*

SYNC
DIN
SCLK

04777-027

POWER-DOWN

CIRCUITRY

Figure 36. Output Stage During Power-Down

RESISTOR

NETWORK

04777-026

The bias generator, the output amplifier, the resistor string, and
other associated linear circuitry are shut down when power­down mode is activated. However, the contents of the DAC
register are unaffected when in power-down. The time to exit
power-down is typically 4 µs for V

= 5 V and for VDD = 3 V

DD

(see Figure 24).

The

signal is derived from a port line (PC7). The setup

SYNC

conditions for correct operation of this interface are as follows.
The 68HC11/68L11 is configured with its CPOL bit as a 0 and
its CPHA bit as a 1. When data is being transmitted to the DAC,
the

line is taken low (PC7). When the 68HC11/ 68L11 is

SYNC

configured as described above, data appearing on the MOSI
output is valid on the falling edge of SCK. Serial data from the
68HC11/68L11 is transmitted in 8-bit bytes with only eight
falling clock edges occurring in the transmit cycle. Data is
transmitted MSB first. In order to load data to the AD5662, PC7
is left low after the first eight bits are transferred, and a second
serial write operation is performed to the DAC; PC7 is taken
high at the end of this procedure.

68HC11/68L11*

PC7

SCK

MOSI

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 38. AD5662 to 68HC11/68L11 Interface

AD5662*

SYNC
SCLK
DIN

04777-028

Rev. 0 | Page 16 of 24

AD5662

AD5662 to 80C51/80L51 Interface

Figure 39 shows a serial interface between the AD5662 and the
80C51/80L51 microcontroller. The setup for the interface is as
follows. TxD of the 80C51/80L51 drives SCLK of the AD5662,
while RxD drives the serial data line of the part. The

SYNC

signal is again derived from a bit-programmable pin on the port.
In this case, port line P3.3 is used. When data is to be transmitted
to the AD5662, P3.3 is taken low. The 80C51/80L51 transmits
data in 8-bit bytes only; thus only eight falling clock edges occur
in the transmit cycle. To load data to the DAC, P3.3 is left low
after the first eight bits are transmitted, and a second write cycle
is initiated to transmit the second byte of data. P3.3 is taken
high following the completion of this cycle. The 80C51/80L51
outputs the serial data in a format that has the LSB first. The
AD5662 must receive data with the MSB first. The 80C51/80L51
transmit routine should take this into account.

AD5662 to MICROWIRE Interface

Figure 40 shows an interface between the AD5662 and any
MICROWIRE-compatible device. Serial data is shifted out on
the falling edge of the serial clock and is clocked into the AD5662
on the rising edge of the SK.

MICROWIRE*

CS
SK

SO

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 40. AD5662 to MICROWIRE Interface

AD5662*

SYNC
SCLK
DIN

04777-030

80C51/80L51*

P3.3

TxD
RxD

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 39. AD5662 to 80C51/80L51 Interface

AD5662*

SYNC
SCLK
DIN

04777-029

Rev. 0 | Page 17 of 24

AD5662

APPLICATIONS

CHOOSING A REFERENCE FOR THE AD5662

To achieve the optimum performance from the AD5662,
thought should be given to the choice of a precision voltage
reference. The AD5662 has only one reference input, V
voltage on the reference input is used to supply the positive
input to the DAC. Therefore any error in the reference is
reflected in the DAC.

When choosing a voltage reference for high accuracy applica­tions, the sources of error are initial accuracy, ppm drift, long­term drift, and output voltage noise. Initial accuracy on the
output voltage of the DAC leads to a full-scale error in the
DAC. To minimize these errors, a reference with high initial
accuracy is preferred. Also, choosing a reference with an output
trim adjustment, such as the ADR423, allows a system designer
to trim system errors out by setting a reference voltage to a
voltage other than the nominal. The trim adjustment can also
be used at temperature to trim out any error.

Long-term drift is a measurement of how much the reference
drifts over time. A reference with a tight long-term drift
specification ensures that the overall solution remains relatively
stable during its entire lifetime.

The temperature coefficient of a reference’s output voltage
effect INL, DNL, and TUE. A reference with a tight temperature
coefficient specification should be chosen to reduce temperature
dependence of the DAC output voltage in ambient conditions.

In high accuracy applications, which have a relatively low noise
budget, reference output voltage noise needs to be considered. It
is important to choose a reference with as low an output noise
voltage as practical for the system noise resolution required.
Precision voltage references such as the ADR425 produce low
output noise in the 0.1 Hz to10 Hz range. Examples of recom­mended precision references for use as supply to the AD5662
are shown in the Table 6.

REF

. The

USING A REFERENCE AS A POWER SUPPLY FOR THE AD5662

Because the supply current required by the AD5662 is extremely
low, an alternative option is to use a voltage reference to supply
the required voltage to the part (see Figure 41). This is especially
useful if the power supply is quite noisy, or if the system supply
voltages are at some value other than 5 V or 3 V, for example,
15 V. The voltage reference outputs a steady supply voltage for
the AD5662; see Table 6 for a suitable reference. If the low drop­out REF195 is used, it must supply 250 µA of current to the
AD5662, with no load on the output of the DAC. When the
DAC output is loaded, the REF195 also needs to supply the
current to the load. The total current required (with a 5 kΩ
load on the DAC output) is

250 µA + (5 V/5 kΩ) = 1.25 mA

The load regulation of the REF195 is typically 2 ppm/mA,
which results in a 2.5 ppm (12.5 µV) error for the 1.25 mA
current drawn from it. This corresponds to a 0.164 LSB error.

+15V

+5V

V

DD

AD5662

250µA

V

REF

V

OUT

= 0V TO 5V

04777-031

INTERFACE

REF195

3-WIRE

SERIAL

SYNC
SCLK

DIN

Figure 41. REF195 as Power Supply to the AD5662

Table 6. Partial List of Precision References for Use with the AD5662

Part No. Initial Accuracy (mV max) Temp Drift (ppmoC max) 0.1 Hz to 10 Hz Noise (µV p-p typ) V

OUT

(V)

ADR425 ±2 3 3.4 5
ADR395 ±6 25 5 5
REF195 ±2 5 50 5
AD780 ±2 3 4 2.5/3
ADR423 ±2 3 3.4 3

Rev. 0 | Page 18 of 24

AD5662

L

BIPOLAR OPERATION USING THE AD5662

The AD5662 has been designed for single-supply operation,
but a bipolar output range is also possible using the circuit in
Figure 42. The circuit gives an output voltage range of ±5 V.
Rail-to-rail operation at the amplifier output is achievable using
an AD820 or an OP295 as the output amplifier.

The output voltage for any input code can be calculated as
follows:

⎡

⎛

VV

×=

⎜

⎢

O

⎝

⎣

⎞
⎟

536,65

⎠

R2R1D

+

R1

⎞

V

⎟

DDDD

⎠

⎛

×

⎜
⎝

⎤

R2

⎞

⎛

×−

⎟

⎜

⎥

R1

⎠

⎝

⎦

USING THE AD5662 AS AN ISOLATED,
PROGRAMMABLE, 4-20 mA PROCESS
CONTROLLER

In many process control system applications, 2-wire current
transmitters are used to transmit analog signals through noisy
environments. These current transmitters use a zero-scale
signal current of 4 mA that can power the transmitter’s signal
conditioning circuitry. The full-scale output signal in these
transmitters is 20 mA. The converse approach to process
control can also be used; a low-power, programmable current
source can be used to control remotely located sensors or
devices in the loop.

where D represents the input code in decimal (0 to 65,535).
With V

= 5 V, R1 = R2 = 10 kΩ,

DD

10

×=D

⎞

⎛

V

⎜

O

536,65

⎝

V5

−

⎟
⎠

This is an output voltage range of ±5 V, with 0x0000 corre­sponding to a −5 V output, and 0xFFFF corresponding to a
+5 V output.

R2 = 10kΩ

+5V

R1 = 10kΩ

V

FB

AD5662

SERIAL

INTERFACE

V

OUT

V

REF

0.1µF10µF

THREE-WIRE

Figure 42. Bipolar Operation with the AD5662

+5V

AD820/
OP295

–5V

±5V

04777-032

A circuit that performs this function is shown in Figure 43.
Using the AD5662 as the controller, the circuit provides a
programmable output current of 4 mA to 20 mA, proportional
to the DAC’s digital code. Biasing for the controller is provided
by the ADR02 and requires no external trim for two reasons:
(1) the ADR02’s tight initial output voltage tolerance and (2)
the low supply current consumption of both the AD8627 and
the AD5662. The entire circuit, including opto-couplers,
consumes less than 3 mA from the total budget of 4 mA. The
AD8627 regulates the output current to satisfy the current
summation at the noninverting node of the AD8627.

= 1/R7 (V

I

OUT

× R3/R1 + V

DAC

× R3/R2)

REF

For the values shown in Figure 43,

= 0.2435 µA × D + 4 mA

I

OUT

where D = 0 ≤ D ≤ 65535, giving a full-scale output current of
20 mA when the AD5662’s digital code equals 0xFFFF. Offset
trim at 4 mA is provided by P2, and P1 provides the circuit’s
gain trim at 20 mA. These two trims do not interact because
the noninverting input of the AD8627 is at virtual ground. The
Schottky diode, D1, is required in this circuit to prevent loop
supply power-on transients from pulling the noninverting input
of the AD8627 more than 300 mV below its inverting input.
Without this diode, such transients could cause phase reversal
of the AD8627 and possible latch-up of the controller. The loop
supply voltage compliance of the circuit is limited by the maxi­mum applied input voltage to the ADR02 and is from 12 V to
40 V.

AD8627

ADR02

3.3kΩ

R6

100Ω

Q1
2N3904

D1

4mA TO 20mA

R7

R2

18.5kΩ
P2

4mA

ADJUST

SERIA

LOAD

AD5662

R1

P1

4.7kΩ

20mA

ADJUST

R3

1.5kΩ

Figure 43. Programmable 4–20 mA Process Controller

Rev. 0 | Page 19 of 24

V

LOOP

12V TO 36V

RL

04777-034

AD5662

USING AD5662 WITH A GALVANICALLY ISOLATED INTERFACE

In process-control applications in industrial environments, it is
often necessary to use a galvanically isolated interface to protect
and isolate the controlling circuitry from any hazardous
common-mode voltages that might occur in the area where the
DAC is functioning. Isocouplers provide isolation in excess of
3 kV. The AD5662 uses a 3-wire serial logic interface, so the
ADuM130x 3-channel digital isolator provides the required
isolation (see Figure 44). The power supply to the part also
needs to be isolated, which is done by using a transformer. On
the DAC side of the transformer, a 5 V regulator provides the
5 V supply required for the AD5662.

+5V

POWER

SCLK

DATA

V1A

ADMu103x

V1B

SDI

V1C

Figure 44. AD5662 with a Galvanically Isolated Interface

REGULATOR

VOB

VOC

V

SCLK

AD5662

SYNC

DIN

GND

DD

V

10µF

OUT

0.1µF

04777-033

POWER SUPPLY BYPASSING AND GROUNDING

When accuracy is important in a circuit, it is helpful to carefully
consider the power supply and ground return layout on the
board. The printed circuit board containing the AD5662 should
have separate analog and digital sections, each having its own
area of the board. If the AD5662 is in a system where other
devices require an AGND-to-DGND connection, the connection
should be made at one point only. This ground point should be
as close as possible to the AD5662.

The power supply to the AD5662 should be bypassed with 10 µF
and 0.1 µF capacitors. The capacitors should be located as close
as possible to the device, with the 0.1 µF capacitor ideally right
up against the device. The 10 µF capacitors are the tantalum
bead type. It is important that the 0.1 µF capacitor has low
effective series resistance (ESR) and effective series inductance
(ESI), for example, common ceramic types of capacitors. This

0.1 µF capacitor provides a low impedance path to ground for
high frequencies caused by transient currents due to internal
logic switching.

The power supply line itself should have as large a trace as
possible to provide a low impedance path and to reduce glitch
effects on the supply line. Clocks and other fast switching
digital signals should be shielded from other parts of the board
by digital ground. Avoid crossover of digital and analog signals
if possible. When traces cross on opposite sides of the board,
ensure that they run at right angles to each other to reduce
feedthrough effects through the board. The best board layout
technique is the microstrip technique where the component
side of the board is dedicated to the ground plane only and the
signal traces are placed on the solder side. However, this is not
always possible with a 2-layer board.

Rev. 0 | Page 20 of 24

AD5662

R

OUTLINE DIMENSIONS

2.90 BSC

847

1.60 BSC

PIN 1

INDICATO

1.30

1.15

0.90

0.15 MAX

1 3562

1.95
BSC

0.38

0.22

COMPLIANT TO JEDEC STANDARDS MO-178BA

Dimensions shown in millimeters

3.00
BSC

2.80 BSC

0.65 BSC

1.45 MAX

SEATING
PLANE

0.22

0.08

Figure 45. 8-Lead SOT-23

(RJ-8)

8°
4°
0°

0.60

0.45

0.30

85

3.00

BSC

PIN 1

0.65 BSC

0.15

0.00

0.38

0.22

COPLANARITY

0.10
COMPLIANT TO JEDEC STANDARDS MO-187AA

4

SEATING
PLANE

4.90
BSC

1.10 MAX

0.23

0.08

8°
0°

Figure 46. 8-Lead Mini Small Outline Package [MSOP]

(RM-8)

Dimensions shown in millimeters

0.80

0.60

0.40

Rev. 0 | Page 21 of 24

AD5662

ORDERING GUIDE

Package

Model Temperature Range

AD5662ARJ-1500RL7 −40°C to +125°C 8-lead SOT-23 RJ-8 D38 Zero ±32 LSB INL
AD5662ARJ-1REEL7 −40°C to +125°C 8-lead SOT-23 RJ-8 D38 Zero ±32 LSB INL
AD5662ARJ-2500RL7 −40°C to +125°C 8-lead SOT-23 RJ-8 D39 Midscale ±32 LSB INL
AD5662ARJ-2REEL7 −40°C to +125°C 8-lead SOT-23 RJ-8 D39 Midscale ±32 LSB INL
AD5662ARM-1 −40°C to +125°C 8-lead MSOP RM-8 D38 Zero ±32 LSB INL
AD5662ARM-1REEL7 −40°C to +125°C 8-lead MSOP RM-8 D38 Zero ±32 LSB INL
AD5662BRJ-1500RL7 −40°C to +125°C 8-lead SOT-23 RJ-8 D36 Zero ±16 LSB INL
AD5662BRJ-1REEL7 −40°C to +125°C 8-lead SOT-23 RJ-8 D36 Zero ±16 LSB INL
AD5662BRJ-2500RL7 −40°C to +125°C 8-lead SOT-23 RJ-8 D37 Midscale ±16 LSB INL
AD5662BRJ-2REEL7 −40°C to +125°C 8-lead SOT-23 RJ-8 D37 Midscale ±16 LSB INL
AD5662BRM-1 −40°C to +125°C 8-lead MSOP RM-8 D36 Zero ±16 LSB INL
AD5662BRM-1REEL7 −40°C to +125°C 8-lead MSOP RM-8 D36 Zero ±16 LSB INL

Description

Package
Option

Branding

Power-On
Reset to Code

Acurracy

Rev. 0 | Page 22 of 24

AD5662

NOTES

Rev. 0 | Page 23 of 24

AD5662

NOTES

© 2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04777–0–1/05(0)

Rev. 0 | Page 24 of 24