Page 1
3 V/5 V, 16-Bit
J
10 ppm/°C Max On-Chip Reference in SOT-23
nano
DACTM D/A with
Preliminary Technical Data
FEATURES
Low power single 16-bit nanoDAC
12-bit accuracy guaranteed
On-chip 1.25/2.5 V, 10 ppm/°c reference
Tiny 8-lead SOT-23/MSOP package
Power-down to 200 nA @ 5 V, 50 nA @ 3 V
3 V/5 V single power supply
Guaranteed 16-bit monotonic by design
Power-on-reset to zero/midscale
Three power-down functions
Serial interface with Schmitt-triggered inputs
Rail-to-rail operation
SYNC interrupt facility
APPLICATIONS
Processcontrol
Data acquisition systems
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators
GENERAL DESCRIPTION
The AD5660 parts are a member of the nanoDAC family of
devices. They are low power, single, 16-bit buffered voltage-out
DACs, guaranteed monotonic by design.
The AD5660x-1 operate from a 3 V single supply featuring an
internal reference of 1.25 V and an internal gain of 2. The
AD5660x-2/3 operate from a 5 V single supply featuring an
internal reference of 2.5 V and an internal gain of 2. Each
reference has a 10 ppm/°C max temperature coefficient. The
reference associated with each part is available at the REFOUT
pin.
The part incorporates a power-on reset circuit that ensures that
the DAC output powers up to 0 V (AD5660x-1/2) or midscale
(AD5660x-3) and remains there until a valid write takes place.
The part contains a power-down feature that reduces the current
consumption of the device to 200 nA at 5 V and provides
software selectable output loads while in power-down mode.
The AD5660 uses a versatile three-wire serial interface that
operates at clock rates up to 30 MHz and is compatible with
standard SPI™, QSPI™, MICROWIRE™ and DSP interface
AD5660
Figure 1.
standards. Its on-chip precision output amplifier allows rail-torail output swing to be achieved.
The low power consumption of this part in normal operation
makes it ideally suited to portable battery operated equipment.
The power consumption is 0.7 mW at 5 V reducing to 1 µW in
power-down mode.
The AD5660 is designed with new technology and is the next
generation to the AD53xx family.
PRODUCT HIGHLIGHTS
1. 16-Bit DAC; 12-Bit Accuracy Guaranteed.
2. On-chip 1.25/2.5 V, 10 ppm/°C max Reference.
3. Available in 8-lead SOT-23 and 8-lead MSOP package.
4. Power-On Reset to 0 V or Midscale.
5. Power-down capability. When powered down, the DAC
typically consumes 50 nA at 3 V and 200n A at 5 V.
6. 10 µS Settling Time.
RELATED DEVICES
Part No. Description
AD5620/AD5640
AD5662
3 V/5 V 12-/14-bit DAC with internal ref in
SOT-23
2.7V to 5.5 V, 16-bit DAC in SOT-23,
external reference
Rev. Pr
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.
www.analog.com
Page 2
AD5660 Preliminary Technical Data
TABLE OF CONTENTS
AD5660X-2/3–Specifications ......................................................... 3
AD5660x-1–Specifications.............................................................. 5
Timing Characteristics..................................................................... 7
Pin Configuration and Function Descriptions............................. 8
Absolute Maximum Ratings............................................................ 9
ESD Caution.................................................................................. 9
Terminology .................................................................................... 10
Typical Performance Characteristics ........................................... 11
Theory of Operation ...................................................................... 14
D/A Section................................................................................. 14
Resistor String............................................................................. 14
Output Amplifier........................................................................ 14
REVISION HISTORY
Revision PrJ: Preliminary
Serial Interface............................................................................ 14
SYNC
Interrupt .......................................................................... 15
Power-On Reset .......................................................................... 15
Power-Down Modes .................................................................. 15
Microprocessor Interfacing....................................................... 15
Applications..................................................................................... 17
Using REF19x as a Power Supply for AD5660 ....................... 17
Bipolar Operation Using the AD5660 ..................................... 17
Using AD5660 with an Opto-Isolated Interface..................... 17
Power Supply Bypassing and Grounding................................ 18
Outline Dimensions....................................................................... 19
Ordering Guide .......................................................................... 19
Rev. PrJ Page 2 of 20
Page 3
Preliminary Technical Data AD5660
AD5660X-2/3–SPECIFICATIONS
VDD = 4.5 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications T
Table 1.
Parameter A Grade B Grade C Grade Unit
STATIC PERFORMANCE2
Resolution 16 16 16 Bits min
Relative Accuracy ±32 ±16 ±16 LSB max See Figure 4
Differential Nonlinearity ±1 ±1 ±1 LSB max Guaranteed Monotonic by Design. See Figure 5.
Zero Code Error +5 +5 +5 mV typ All Zeroes Loaded to DAC
+20 +20 +20 mV max Register. See Figure 8.
Full-Scale Error −0.15 −0.15 −0.15 % of FSR typ All Ones Loaded to DAC
−1.25 −1.25 −1.25 % of FSR max Register. See Figure 8
Gain Error ±1.25 ±1.25 ±1.25 % of FSR max
Zero Code Error Drift3 ±20 ±20 ±20 µV/°C typ
Gain Temperature Coefficient ±5 ±5 ±5 ppm typ f FSR/°C
OUTPUT CHARACTERISTICS3
Output Voltage Range 0 0 V min
V
V
DD
V
DD
V max
DD
Output Voltage Settling Time 8 8 8 µs typ To ±0.003% FSR 0200H to FD00H
10 10 10 µs max RL = 2 kΩ; 0 pF <CL < 200 pF See Figure 18.
12 12 12 µs typ RL = 2 kΩ; CL = 500 pF
Slew Rate 1 1 1 V/µs typ
Capacitive Load Stability 470 470 470 pF typ RL = ∞
1000 1000 1000 pF typ RL = 2 kΩ
Output Noise 100 100 100 nV/√Hz typ DAC code = 8400H, 10 kHz
Output Drift ppm/°C typ
Digital-to-Analog Glitch Impulse 10 10 10 nV-s typ 1 LSB Change Around Major Carry. See Figure 21.
Digital Feedthrough 0.5 0.5 0.5 nV-s typ
DC Output Impedance 1 1 1 Ω typ
Short Circuit Current 50 50 50 mA typ VDD = 5 V
Power-Up Time 10 10 10 ms typ Coming Out of Power-Down Mode. VDD = 5 V
REFERENCE OUTPUT
Output Voltage
AD5660x-2/3 2.495 2.495 2.495 V min
2.505 2.505 2.505 V max
Reference TC ±25 ±25 ±10 ppm/°C max
LOGIC INPUTS3
Input Current ±1 ±1 ±1 µA max
V
, Input Low Voltage 0.8 0.8 0.8 V max VDD = 5 V
INL
V
, Input High Voltage 2 2 2 V min VDD = 5 V
INH
Pin Capacitance 3 3 3 pF max
MIN
to T
, unless other wise noted.
MAX
B Version
Conditions/Comments
1
Rev. PrJ | Page 3 of 20
Page 4
AD5660 Preliminary Technical Data
Parameter A Grade B Grade C Grade Unit
B Version
Conditions/Comments
1
POWER REQUIREMENTS
VDD 4.5 4.5 4.5 V min All Digital Inputs at 0 V or VDD
5.5 5.5 5.5 V max DAC Active and Excluding
IDD (Normal Mode) Load Current
VDD = 4.5 V to +5.5 V 0.5 0.5 0.5 mA typ VIH = VDD and VIL = GND
VDD = 4.5 V to +5.5 V 1 1 1 mA max VIH = VDD and VIL = GND
IDD (All Power-Down Modes)
VDD = 4.5 V to +5.5 V 0.2 0.2 0.2 µA typ VIH = VDD and VIL = GND
VDD = 4.5 V to +5.5 V 1 1 1 µA max VIH = VDD and VIL = GND
POWER EFFICIENCY
I
89 89 89 % I
OUT/IDD
= 2 mA, VDD = 5 V
LOAD
1
Temperature ranges are as follows: B Version: -40°C to +105°C, typical at 25°C.
2
Linearity calculated using a reduced code range of 485 to 64714. Output unloaded.
3
Guaranteed by design and characterization, not production tested.
Rev. PrJ Page 4 of 20
Page 5
Preliminary Technical Data AD5660
AD5660X-1–SPECIFICATIONS
VDD = 2.7 V to 3.6 V; RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications T
Table 2.
Parameter A Grade B Grade C Grade Unit
STATIC PERFORMANCE5
Resolution 16 16 16 Bits min
Relative Accuracy ±32 ±16 ±16 LSB max See Figure 4
Differential Nonlinearity ±1 ±1 ±1 LSB max Guaranteed Monotonic by Design. See Figure 5.
Zero Code Error +5 +5 +5 mV typ All Zeroes Loaded to DAC
+20 +20 +20 mV max Register. See Figure 8.
Full-Scale Error −0.15 −0.15 −0.15 % of FSR typ All Ones Loaded to DAC
−1.25 −1.25 −1.25 % of FSR max Register. See Figure 8.
Gain Error ±1.25 ±1.25 ±1.25 % of FSR max
Zero Code Error Drift6 ±20 ±20 ±20 µV/°C typ
Gain Temperature Coefficient ±5 ±5 ±5 ppm typ of FSR/°C
OUTPUT CHARACTERISTICS3
Output Voltage Range 0 0 V min
V
V
DD
V
DD
V max
DD
Output Voltage Settling Time 8 8 8 µs typ To ±0.003% FSR 0200H to FD00H
10 10 10 µs max RL = 2 kΩ; 0 pF<CL<200 pF See Figure 18.
12 12 12 µs typ RL = 2 kΩ; CL = 500 pF
Slew Rate 1 1 1 V/µs typ
Capacitive Load Stability 470 470 470 pF typ RL = ∞
1000 1000 1000 pF typ RL = 2 kΩ
Output Noise 100 100 100 nV/√Hz typ DAC code = 8400H, 10 kHz
Output Drift tbd ppm/°C typ
Digital-to-Analog Glitch Impulse 10 10 10 nV-s typ 1 LSB Change Around Major Carry. See Figure 21.
Digital Feedthrough 0.5 0.5 0.5 nV-s typ
DC Output Impedance 1 1 1 Ω typ
Short Circuit Current 20 20 20 mA typ VDD = 3 V
Power-Up Time 10 10 10 ms typ Coming Out of Power-Down Mode. VDD = 3 V
REFERENCE OUTPUT
Output Voltage
AD5660x-1 1.248 1.248 1.248 V min
1.252 1.252 1.252 V max
Reference TC ±25 ±25 ±10 ppm/°C max
LOGIC INPUTS3
Input Current ±1 ±1 ±1 µA max
V
, Input Low Voltage 0.8 0.8 0.8 V max VDD = 3 V
INL
V
, Input High Voltage 2 2 2 V min VDD = 3 V
INH
Pin Capacitance 3 3 3 pF max
MIN
to T
, unless other wise noted.
MAX
B Version
Conditions/Comments
4
Rev. PrJ | Page 5 of 20
Page 6
AD5660 Preliminary Technical Data
Parameter A Grade B Grade C Grade Unit
B Version
Conditions/Comments
4
POWER REQUIREMENTS
VDD 2.7 2.7 2.7 V min All Digital Inputs at 0 V or VDD
3.6 3.6 3.6 V max DAC Active and Excluding
IDD (Normal Mode) Load Current
VDD = 2.7 V to 3.6 V 0.5 0.5 0.5 mA typ VIH = VDD and VIL = GND
VDD = 2.7 V to 3.6 V 1 1 1 mA max VIH = VDD and VIL = GND
IDD (All Power-Down Modes)
VDD = 2.7 V to 3.6 V 0.2 0.2 0.2 µA typ VIH = VDD and VIL = GND
VDD = 2.7 V to 3.6 V 1 1 1 µA max VIH = VDD and VIL = GND
POWER EFFICIENCY
I
I
OUT/IDD
= 2 mA, VDD = 3 V
LOAD
4
Temperature ranges are as follows: B Version: -40°C to +105°C, typical at 25°C.
5
Linearity calculated using a reduced code range of 485 to 64714. Output unloaded.
6
Guaranteed by design and characterization, not production tested.
Rev. PrJ Page 6 of 20
Page 7
Preliminary Technical Data AD5660
TIMING CHARACTERISTICS
All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 2.
= 2.7 V to 5.5 V; all specifications T
V
DD
Limit at T
MIN
to T
, unless otherwise noted.
MAX
, T
MIN
MAX
Parameter VDD = 2.7 V to 3.6 V VDD = 3.6 V to 5.5 V Unit Conditions/Comments
t1 1 50 33 ns min SCLK Cycle Time
t2 13 13 ns min SCLK High Time
t3 13 13 ns min SCLK Low Time
t4 13 13 ns min
SYNC
to SCLK Falling Edge Setup Time
t5 5 5 ns min Data Setup Time
t6 4.5 4.5 ns min Data Hold Time
t7 0 0 ns min
t8 50 33 ns min
t9 13 13 ns min
t10 0 0 ns min
SCLK Falling Edge to
Minimum
SYNC
SYNC
Rising Edge to SCLK Fall Ignore
SCLK Falling Edge to
SYNC
High Time
SYNC
1
Maximum SCLK frequency is 30 MHz at VDD = 3.6 V to 5.5 V and 20 MHz at VDD = 2.7 V to 3.6 V.
Rising Edge
Fall Ignore
Figure 2. Serial Write Operation
Rev. PrJ | Page 7 of 20
Page 8
AD5660 Preliminary Technical Data
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 3. Pin Configuration
Table 3. Pin Function Descriptions
Pin No. Mnemonic Function
1 VDD Power Supply Input. These parts can be operated from 2.5 V to 5.5 V and VDD should be decoupled to GND.
2 V
3 VFB Feedback connection for the output amplifier.
4 V
5
6 SCLK
7 DIN
8 GND Ground reference point for all circuitry on the part.
Reference Voltage Output.
REFOUT
Analog output voltage from DAC. The output amplifier has rail to rail operation.
OUT
SYNC Level triggered control input (active low). This is the frame synchronization signal for the input data. When
SYNC
goes low, it enables the input shift register and data is transferred in on the falling edges of the following
SYNC
clocks. The DAC is updated following the 24th clock cycle unless
SYNC
case the rising edge of
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data
can be transferred at rates up to 30 MHz.
Serial Data Input. This device has a 24-bit shift register. Data is clocked into the register on the falling edge of
the serial clock input.
acts as an interrupt and the write sequence is ignored by the DAC.
is taken high before this edge in which
Rev. PrJ Page 8 of 20
Page 9
Preliminary Technical Data AD5660
ABSOLUTE MAXIMUM RATINGS
TA = +25°C unless otherwise noted.
Table 4.
Parameter Rating
VDD to GND −0.3 V to +7 V
Digital Input Voltage to GND −0.3 V to VDD + 0.3 V
V
to GND −0.3 V to VDD + 0.3 V
OUT
Operating Temperature Range
Industrial (B Version) −40°C to +105°C
Storage Temperature Range −65°C to +150°C
Junction Temperature (TJ max) 150°C
SOT-23 Package
Power Dissipation (TJ max − TA)/θJA
θJA Thermal Impedance 240°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) 215°C
Infrared (15 sec) 220°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. PrJ | Page 9 of 20
Page 10
AD5660 Preliminary Technical Data
TERMINOLOGY
Relative Accuracy
This is a measure of the span error of the DAC. It is the
deviation in slope of the DAC transfer characteristic from ideal
expressed as a percent of the full-scale range.
For the DAC, relative accuracy or Integral Nonlinearity (INL) is
a measure of the maximum deviation, in LSBs, from a straight
line passing through the endpoints of the DAC transfer
function. A typical INL vs. code plot can be seen in Figure 4.
Differential Nonlinearity
Differential Nonlinearity (DNL) is the difference between the
measured change and the ideal 1 LSB change between any two
adjacent codes. A specified differential nonlinearity of ±1 LSB
maximum ensures monotonicity. This DAC is guaranteed
monotonic by design. A typical DNL vs. code plot can be seen in
Figure 5.
Zero-Code Error
Zero-code error is a measure of the output error when zero
code (0000Hex) is loaded to the DAC register. Ideally the output
should be 0 V. The zero-code error is always positive in the
AD5660 because the output of the DAC cannot go below 0 V. It
is due to a combination of the offset errors in the DAC and
output amplifier. Zero-code error is expressed in mV. A plot of
zero-code error vs. temperature can be seen in Figure 8.
Full-Scale Error
Tot a l U n ad ju s te d E rr o r
Total Unadjusted Error (TUE) is a measure of the output error
taking all the various errors into account. A typical TUE vs.
code plot can be seen in Figure 6.
Zero-Code Error Drift
This is a measure of the change in zero-code error with a
change in temperature. It is expressed in µV/°C.
Gain Error Drift
This is a measure of the change in gain error with changes in
temperature. It is expressed in ( ppm of full-scale range)/°C.
Digital-to-Analog Glitch Impulse
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is normally specified as the area of the glitch in nV secs
and is measured when the digital input code is changed by 1
LSB at the major carry transition (7FFF Hex to 8000 Hex). See
Figure 21.
Digital Feedthrough
Full-scale error is a measure of the output error when full-scale
code (FFFF Hex) is loaded to the DAC register. Ideally the
output should be V
percent of full-scale range. A plot of full-scale error vs.
temperature can be seen in Figure 8.
Gain Error
– 1 LSB. Full-scale error is expressed in
DD
Digital feedthrough is a measure of the impulse injected into
the analog output of the DAC from the digital inputs of the
DAC but is measured when the DAC output is not updated. It is
specified in nV secs and measured with a full-scale code change
on the data bus, i.e., from all 0s to all 1s and vice versa.
Rev. PrJ Page 10 of 20
Page 11
Preliminary Technical Data AD5660
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 4. Typical INL Plot
Figure 5. Typical DNL Plot
Figure 7. INL Error and DNL Error vs. Temperature
Figure 8. Zero-Scale Error and Full-Scale Error vs. Temperature
Figure 6. Typical Total Unadjusted Error Plot
Rev. PrJ | Page 11 of 20
Figure 9. I
Histogram with VDD = 3 V and VDD = 5 V
DD
Page 12
AD5660 Preliminary Technical Data
Figure 10. Source and Sink Current Capability with V
Figure 11. Source and Sink Current Capability with V
DD
DD
= 3 V
= 5 V
Figure 13. Supply Current vs. Temperature
Figure 14. Supply Current vs. Supply Voltage
Figure 12. Supply Current vs. Code
Rev. PrJ Page 12 of 20
Figure 15. Power-Down Current vs. Supply Voltage
Page 13
Preliminary Technical Data AD5660
Figure 16. Supply Current vs. Logic Input Voltage
Figure 17. Full-Scale Settling Time
Figure 19. Power-On Reset to 0V
Figure 20. Exiting Power-Down (800 Hex Loaded)
Figure 18. Half-Scale Settling Time
Figure 21. Digital-to-Analog Glitch Impulse
Rev. PrJ | Page 13 of 20
Page 14
AD5660 Preliminary Technical Data
THEORY OF OPERATION
D/A SECTION
The AD5660 DAC is fabricated on a CMOS process. The
architecture consists of a string DAC followed by an output
buffer amplifier. The parts include an internal 1.25 V/2.5 V,
10 ppm/°C reference with an internal gain of two. Figure 22
shows a block diagram of the DAC architecture.
Figure 22. DAC Architecture
Since the input coding to the DAC is straight binary, the ideal
output voltage is given by:
⎛
2DxVREFV
OUT
where D = the decimal equivalent of the binary code that is
loaded to the DAC register; it can range from 0 to 65535.
×=
⎜
⎝
65536
⎞
⎟
⎠
RESISTOR STRING
The resistor string section is shown in Figure 23. It is simply a
string of resistors, each of value R. The code loaded to the DAC
register determines at which node on the string the voltage is
tapped off to be fed into the output amplifier. The voltage is
tapped off by closing one of the switches connecting the string
to the amplifier. Because it is a string of resistors, it is
guaranteed monotonic.
OUTPUT AMPLIFIER
The output buffer amplifier is capable of generating rail-to-rail
voltages on its output which gives an output range of 0 V to V
It is capable of driving a load of 2 kΩ in parallel with 1000 pF to
GND. The source and sink capabilities of the output amplifier
can be seen in Figure 10 and Figure 11. The slew rate is 1 V/µs
with a half-scale settling time of 8 µs with the output unloaded.
SERIAL INTERFACE
The AD5660 has a 3-wire serial interface (
DIN), which is compatible with SPI, QSPI and MICROWIRE
interface standards as well as most DSPs. See Figure 2 for a
timing diagram of a typical write sequence.
The write sequence begins by bringing the
from the DIN line is clocked into the 24-bit shift register on the
falling edge of SCLK. The serial clock frequency can be as high
as 30 MHz, making the AD5660compatible with high speed
DSPs. On the 24th falling clock edge, the last data bit is clocked
in and the programmed function is executed, that is, a change in
DAC register contents and/or a change in the mode of
SYNC
operation. At this stage, the
brought high. In either case, it must be brought high for a
minimum of 33 ns before the next write sequence so that a
falling edge of
SYNC
the
does when V
sequences for even lower power operation of the part. As is
mentioned above, however, it must be brought high again just
before the next write sequence.
SYNC
can initiate the next write sequence. Since
buffer draws more current when VIN = 2.4 V than it
= 0.8 V,
IN
SYNC
line may be kept low or be
should be idled low between write
SYNC
SYNC
, SCLK and
line low. Data
DD
.
INPUT SHIFT REGISTER
The input shift register is 24 bits wide (see Figure 24). The first
six bits are “don’t cares.” The next two are control bits that
control which mode of operation the part is in (normal mode
or any one of three power-down modes). There is a more
Figure 23. Resistor String
Rev. PrJ Page 14 of 20
complete description of the various modes in the Power-Down
Modes section. The next sixteen bits are the data bits. These are
transferred to the DAC register on the24th falling edge of
SCLK.
Page 15
Preliminary Technical Data AD5660
Figure 24. Input Register Contents
SYNC INTERRUPT
In a normal write sequence, the
least 24 falling edges of SCLK and the DAC is updated on the
24th falling edge. However, if
24th falling edge this acts as an interrupt to the write sequence.
The shift register is reset and the write sequence is seen as
invalid. Neither an update of the DAC register contents or a
change in the operating mode occurs—see Figure 27.
SYNC
line is kept low for at
SYNC
is brought high before the
POWER-ON RESET
The AD5660 family contains a power-on reset circuit that
controls the output voltage during power-up. The AD5660x-1/2
DAC output powers up to zero volts and the AD5660x-3 DAC
output powers up to midscale. The output remains there until a
valid write sequence is made to the DAC. This is useful in
applications where it is important to know the state of the
output of the DAC while it is in the process of powering up.
POWER-DOWN MODES
The AD5660 contains four separate modes of operation. These
modes are software-programmable by setting two bits (DB17
and DB16) in the control register. Table 5 shows how the state of
the bits corresponds to the mode of operation of the device.
Table 5. Modes of Operation for the AD5660
DB17 DB16 Operating Mode
0 0 Normal Operation
Power Down Modes
0 1 1 kΩ to GND
1 0 100 kΩ to GND
1 1 Three State
When both bits are set to 0, the part works normally with its
normal power consumption of 250 µA at 5 V. However, for the
three power-down modes, the supply current falls to 200 nA at
5 V (50 nA at 3 V). Not only does the supply current fall but the
output stage is also internally switched from the output of the
amplifier to a resistor network of known values. This has the
advantage that the output impedance of the part is known while
the part is in power-down mode. There are three different
options. The output is connected internally to GND through a
1 kΩ resistor, a 100 kΩ resistor or it is left open-circuited
(Three-State). The output stage is illustrated in Figure 25.
Figure 25. Output Stage During Power-Down
The bias generator, the output amplifier, the resistor string and
other associated linear circuitry are all shut down when the
power-down mode is activated. However, the contents of the
DAC register are unaffected when in power-down. The time to
exit power-down is typically 2.5 µs for V
= 3 V. See Figure 20 for a plot.
V
DD
= 5 V and 5 µs for
DD
MICROPROCESSOR INTERFACING
AD5660 to ADSP-2101/ADSP-2103 Interface
Figure 26 shows a serial interface between the AD5660 and the
ADSP-2101/ADSP-2103. The ADSP-2101/ADSP-2103 should
be set up to operate in the SPORT transmit alternate framing
mode. The ADSP-2101/ADSP-2103 SPORT is programmed
through the SPORT control register and should be configured
as follows: internal clock operation, active low framing, 24-bit
word length. Transmission is initiated by writing a word to the
Tx register after the SPORT has been enabled.
Figure 26. AD5660 to ADSP-2101/ADSP-2103 Interface
Rev. PrJ | Page 15 of 20
Page 16
AD5660 Preliminary Technical Data
Figure 27. SYNC Interrupt Facility
AD5660 to 68HC11/68L11 Interface
Figure 28 shows a serial interface between the AD5660 and the
68HC11/68L11 microcontroller. SCK of the 68HC11/68L11
drives the SCLK of the AD5660, while the MOSI output drives
the serial data line of the DAC. The
SYNC
signal is derived
from a port line (PC7). The setup conditions for correct
operation of this interface are as follows: the 68HC11/68L11
should be configured so that its CPOL bit is a 0 and its CPHA
bit is a 1. When data is being transmitted to the DAC, the
SYNC
line is taken low (PC7). When the 68HC11/68L11 is configured
as above, data appearing on the MOSI output is valid on the
falling edge of SCK. Serial data from the 68HC11/ 68L11 is
transmitted in 8-bit bytes with only eight falling clock edges
occurring in the transmit cycle. Data is transmitted MSB first.
In order to load data to the AD5660, PC7 is left low after the
first eight bits are transferred, and a second serial write
operation is performed to the DAC and PC7 is taken high at the
end of this procedure.
80C51/80L51 outputs the serial data in a format which has the
LSB first. The AD5660 requires its data with the MSB as the first
bit received. The 80C51/80L51 transmit routine should take this
into account.
Figure 29. AD5660 to 80C51 Interface
AD5660 to MICROWIRE Interface
Figure 30 shows an interface between the AD5320 and any
MICROWIRE compatible device. Serial data is shifted out on
the falling edge of the serial clock and is clocked into the
AD5320 on the rising edge of the SK.
Figure 28. AD5660 to 68HC11/68L11 Interface
AD5660 to 80C51/80L51 Interface
Figure 29 shows a serial interface between the AD5660 and the
80C51/80L51 microcontroller. The setup for the interface is as
follows: TXD of the 80C51/80L51 drives SCLK of the AD5660,
while RXD drives the serial data line of the part. The
SYNC
signal is again derived from a bit programmable pin on the port.
In this case port line P3.3 is used. When data is to be
transmitted to the AD5660, P3.3 is taken low. The 80C51/80L51
transmits data only in 8-bit bytes; thus only eight falling clock
edges occur in the transmit cycle. To load data to the DAC, P3.3
is left low after the first eight bits are transmitted, and a second
write cycle is initiated to transmit the second byte of data. P3.3
is taken high following the completion of this cycle. The
Rev. PrJ Page 16 of 20
Figure 30. AD5660 to MICROWIRE Interface
Page 17
Preliminary Technical Data AD5660
(
)
κ
µ
APPLICATIONS
USING REF19X AS A POWER SUPPLY FOR AD5660
Because the supply current required by the AD5660 is extremely
low, an alternative option is to use a REF19x voltage reference
(REF195 for 5 V or REF193 for 3 V) to supply the required
voltage to the part—see Figure 31. This is especially useful if the
power supply is quite noisy or if the system supply voltages are
at some value other than 5 V or 3 V, for example, 15 V. The
REF19x will output a steady supply voltage for the AD5660. If
the low dropout REF195 is used, the current it needs to supply
to the AD5660 is 250 µA. This is with no load on the output of
the DAC. When the DAC output is loaded, the REF195 also
needs to supply the current to the load. The total current
required (with a 5 kΩ load on the DAC output) is
mAVA 25.15/5250 =Ω+
The load regulation of the REF195 is typically 2 ppm/mA,
which results in an error of 2.5 ppm (12.5 µV) for the 1.25 mA
current drawn from it. This corresponds to a 0.164 LSB error.
This is an output voltage range of ±5 V with 0000Hex
corresponding to a −5 V output and FFFF Hex corresponding
to a +5 V output.
Figure 32. Bipolar Operation with the AD5660
USING AD5660 WITH AN OPTO-ISOLATED INTERFACE
In process-control applications in industrial environments it is
often necessary to use an opto-isolated interface to protect and
isolate the controlling circuitry from any hazardous commonmode voltages that may occur in the area where the DAC is
functioning. Opto-isolators provide isolation in excess of 3 kV.
Because the AD5660 uses a three-wire serial logic interface, it
requires only three opto-isolators to provide the required
isolation (see Figure 33). The power supply to the part also
needs to be isolated. This is done by using a transformer. On the
DAC side of the transformer, a 5 V regulator provides the 5 V
supply required for the AD5660.
Figure 31. REF195 as Power Supply to AD5660
BIPOLAR OPERATION USING THE AD5660
The AD5660 has been designed for single-supply operation but
a bipolar output range is also possible using the circuit in Figure
32. The circuit below will give an output voltage range of ±5 V.
Rail-to-rail operation at the amplifier output is achievable using
an AD820 or an OP295 as the output amplifier.
The output voltage for any input code can be calculated as
follows:
+
21
⎡
⎛
×=
VV
⎢
⎣
10
⎛
⎜
65536
⎝
⎜
⎝
×
D
O
where D represents the input code in decimal (0–65535). With
= 5 V, R1 = R2 = 10 kΩ:
V
DD
=
V
O
⎞
×
⎟
65536 R
⎠
⎞
V
5
−
⎟
⎠
RRD
⎛
⎜
⎝
⎞
V
⎟
1
R
⎠
2
R
⎤
⎞
⎛
×−
DDDD
⎟
⎜
⎥
1
⎠
⎝
⎦
Figure 33. AD5660 with an Opto-Isolated Interface
Rev. PrJ | Page 17 of 20
Page 18
AD5660 Preliminary Technical Data
POWER SUPPLY BYPASSING AND GROUNDING
When accuracy is important in a circuit it is helpful to carefully
consider the power supply and ground return layout on the
board. The printed circuit board containing the AD5660 should
have separate analog and digital sections, each having its own
area of the board. If the AD5660 is in a system where other
devices require an AGND to DGND connection, the connection
should be made at one point only. This ground point should be
as close as possible to the AD5660.
The power supply to the AD5660 should be bypassed with
10 µF and 0.1 µF capacitors. The capacitors should be physically
as close as possible to the device with the 0.1 µF capacitor
ideally right up against the device. The 10 µF capacitors are the
tantalum bead type. It is important that the 0.1 µF capacitor has
low effective series resistance (ESR) and effective series
inductance (ESI), for example, common ceramic types of
capacitors. This 0.1 µF capacitor provides a low impedance path
to ground for high frequencies caused by transient currents due
to internal logic switching.
The power supply line itself should have as large a trace as
possible to provide a low impedance path and reduce glitch
effects on the supply line. Clocks and other fast switching digital
signals should be shielded from other parts of the board by
digital ground. Avoid crossover of digital and analog signals if
possible. When traces cross on opposite sides of the board,
ensure that they run at right angles to each other to reduce
feedthrough effects through the board. The best board layout
technique is the microstrip technique where the component
side of the board is dedicated to the ground plane only and the
signal traces are placed on the solder side. However, this is not
always possible with a 2-layer board.
Rev. PrJ Page 18 of 20
Page 19
Preliminary Technical Data AD5660
OUTLINE DIMENSIONS
Figure 34. 8-Lead SOT-23
(RJ-8)
ORDERING GUIDE
Internal
Model Grade Power-On-Reset to
AD5660ARJ-1 A Zero 1.25 V TBD RJ-8 ±32 LSB INL, 25 ppm/°C Ref, 3 V
AD5660ARJ-2 A Zero 2.5 V TBD RJ-8 ±32 LSB INL, 25 ppm/°C Ref, 5 V
AD5660ARJ-3 A Midscale 2.5 V TBD RJ-8 ±32 LSB INL, 25 ppm/°C Ref, 5 V
AD5660BRJ-1 B Zero 1.25 V TBD RJ-8 ±16 LSB INL, 25 ppm/°C Ref, 3 V
AD5660BRJ-2 B Zero 2.5 V TBD RJ-8 ±16 LSB INL, 25 ppm/°C Ref, 5 V
AD5660BRJ-3 B Midscale 2.5 V TBD RJ-8 ±16 LSB INL, 25 ppm/°C Ref, 5 V
AD5660CRM-1 C Zero 1.25 V TBD RM-8 ±16 LSB INL, 10 ppm/°C Ref, 3 V
AD5660CRM-2 C Zero 2.5 V TBD RM-8 ±16 LSB INL, 10 ppm/°C Ref, 5 V
AD5660CRM-3 C Midscale 2.5 V TBD RM-8 ±16 LSB INL, 10 ppm/°C Ref, 5 V
1
RJ = SOT-23
RM = MSOP
Reference Branding Package Options1 Description
Figure 35. 8-Lead MSOP
(RJ-8)
Rev. PrJ | Page 19 of 20
Page 20
AD5660 Preliminary Technical Data
NOTES
© 2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
PR04539-0-5/04(PrJ)
Rev. PrJ Page 20 of 20
Loading...