Page 1
2.7 V to 5.5 V, <100 µA, 14-Bit
nano
DAC™, SPI® Interface in SC70 Package
FEATURES
6-lead SC70 package
Micropower operation: 100 µA max at 5 V
Power-down to typically 0.2 µA at 3 V
Single 14-bit DAC
A version: ±16 LSB INL
2.7 V to 5.5 V power supply
Guaranteed monotonic by design
Power-on reset to 0 V with brownout detection
3 power-down functions
Low power serial interface with Schmitt-triggered inputs
On-chip output buffer amplifier, rail-to-rail operation
SYNC
interrupt facility
APPLICATIONS
Voltage level setting
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators
GENERAL DESCRIPTION
The AD5641, a member of the nanoDAC fam ily, is a single,
14-bit, buffered, voltage-out DAC that operates from a single
2.7 V to 5.5 V supply, typically consuming 75 µA at 5 V. The
part comes in a tiny SC70 package. Its on-chip precision output
amplifier allows rail-to-rail output swing to be achieved. The
AD5641 utilizes a versatile 3-wire serial interface that operates
at clock rates up to 30 MHz and is compatible with SPI, QSPI™,
MICROWIRE™, and DSP interface standards. The reference for
AD5641 is derived from the power supply inputs and, therefore,
gives the widest dynamic output range. The part incorporates a
power-on reset circuit, which ensures that the DAC output
powers up to 0 V and remains there until a valid write to the
device takes place.
The AD5641 contains a power-down feature that reduces
current consumption typically 0.2 µA at 3 V, and provides
software-selectable output loads while in power-down mode.
The part is put into power-down mode over the serial interface.
The low power consumption of the part in normal operation
makes it ideally suited to portable battery-operated equipment.
The combination of small package and low power makes this
nanoDAC device ideal for level-setting requirements such as
generating bias or control voltages in space-constrained and
power-sensitive applications.
AD5641
FUNCTIONAL BLOCK DIAGRAM
V
DD
GND
POWER-ON
RESET
REF(+)
14-BIT
DAC
POWER-DOWN
CONTROL LOGIC
Figure 1.
OUTPUT
BUFFER
SYNC
DAC
REGISTER
INPUT
CONTROL
LOGIC
SCLK SDIN
Table 1. Related Devices
Part Number Description
AD5601/AD5611/AD5621 2.7 V to 5.5 V, <100 µA, 8-/10-/12-Bit
nanoDAC, SPI Interface in SC70 Package
PRODUCT HIGHLIGHTS
1. Available in a space-saving, 6-lead SC70 package.
2. Low power, single-supply operation. The AD5641 operates
from a single 2.7 V to 5.5 V supply and with a maximum
current consumption of 100 µA, making it ideal for
battery-powered applications.
3. The on-chip output buffer amplifier allows the output of
the DAC to swing rail-to-rail with a typical slew rate of
0.5 V/µs.
4. Reference derived from the power supply.
5. High speed serial interface with clock speeds up to
30 MHz. Designed for very low power consumption. The
interface powers up only during a write cycle.
6. Power-down capability. When powered down, the DAC
typically consumes 0.2 µA at 3 V.
7. Power-on reset with brownout detection.
AD5641
RESISTOR
NETWORK
V
OUT
04611-001
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.3113 © 2005 Analog Devices, Inc. All rights reserved.
www.analog.com
Page 2
AD5641
TABLE OF CONTENTS
Specifications..................................................................................... 3
Timing Characteristics ................................................................ 4
Absolute Maximum Ratings............................................................ 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
Te r m in o l o g y ...................................................................................... 7
Typical Performance Characteristics ............................................. 8
Theory of Operation ...................................................................... 13
D/A Section................................................................................. 13
Resistor String............................................................................. 13
Output Amplifier........................................................................ 13
Serial Interface............................................................................ 13
REVISION HISTORY
3/05—Rev. 0 to Rev. A
Changes to Timing Characteristics................................................ 4
Changes to Absolute Maximum Ratings ....................................... 5
Changes to Full-Scale Error Section .............................................. 7
Changes to Figures 28 and 30 ....................................................... 12
Change to Resistor String Section................................................ 13
Changes to Power-Down Mode Section...................................... 14
1/05—Revision 0: Initial Version
Input Shift Register .................................................................... 13
SYNC
Interrupt .......................................................................... 13
Power-On Reset.......................................................................... 14
Power-Down Modes .................................................................. 14
Microprocessor Interfacing ...................................................... 15
Applications..................................................................................... 17
Choosing a Reference as Power Supply for the AD5641 ...... 17
Bipolar Operation Using the AD5641..................................... 17
Using the AD5641 with an Opto-Isolated Interface.............. 18
Power Supply Bypassing and Grounding................................ 18
Outline Dimensions....................................................................... 19
Ordering Guide .......................................................................... 19
Rev. A | Page 2 of 20
Page 3
AD5641
SPECIFICATIONS
VDD = 2.7 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications T
Table 2.
A Grade
1
Parameter Min Typ Max Unit Test Conditions/Comments
STATIC PERFORMANCE
Resolution 14 Bits
Relative Accuracy
2
±16 LSB A grade
Differential Nonlinearity2 ±1 LSB Guaranteed monotonic by design
Zero-Code Error 0.5 10 mV All 0s loaded to DAC register
Offset Error ±0.063 ±10 mV
Full-Scale Error ±0.5 mV All 1s loaded to DAC register
Gain Error ±0.0004 ±0.037 % of FSR
Zero-Code Error Drift 5.0 µV/°C
Gain Temperature Coefficient 2.0 ppm of FSR/°C
OUTPUT CHARACTERISTICS
Output Voltage Range 0 V
3
DD
V
Output Voltage Settling Time 6 10 µs Code ¼ scale to ¾ scale
Slew Rate 0.5 V/µs
Capacitive Load Stability 470 pF RL = ∞
1000 pF RL = 2 kΩ
Output Noise Spectral Density 120
nV/√Hz
Noise 2 µV DAC code = midscale, 0.1 Hz to 10 Hz bandwidth
Digital-to-Analog Glitch Impulse 5 nV-s 1 LSB change around major carry
Digital Feedthrough 0.2 nV-s
DC Output Impedance 0.5 Ω
Short-Circuit Current 15 mA VDD = 3 V/5 V
LOGIC INPUTS
Input Current
V
, Input Low Voltage 0.8 V VDD = 4.5 V to 5.5 V
INL
4
± 2 µA
0.6 V VDD = 2.7 V to 3.6 V
V
, Input High Voltage 1.8 V VDD = 4.5 V to 5.5 V
INH
1.4 V VDD = 2.7 V to 3.6 V
Pin Capacitance 3 pF
POWER REQUIREMENTS
V
DD
2.7 5.5 V All digital inputs at 0 V or V
IDD (Normal Mode) DAC active and excluding load current
VDD = 4.5 V to 5.5 V 75 100 µA VIH = VDD and VIL = GND
VDD = 2.7 V to 3.6 V 60 90 µA VIH = VDD and VIL = GND
IDD (All Power-Down Modes)
VDD = 4.5 V to 5.5 V 0.5 µA VIH = VDD and VIL = GND
VDD = 2.7 V to 3.6 V 0.2 µA VIH = VDD and VIL = GND
POWER EFFICIENCY
I
OUT/IDD
1
Temperature range for A grade: −40°C to +125°C; typical at +25°C.
2
Linearity calculated using a reduced code range (Code 256 to Code 16128).
3
Guaranteed by design and characterization, not production tested.
4
Total current flowing into all pins.
96 % I
MIN
to T
, unless other wise noted.
MAX
DAC code = midscale, 1 kHz
= 2 mA and VDD = ±5 V, full scale loaded
LOAD
DD
Rev. A | Page 3 of 20
Page 4
AD5641
TIMING CHARACTERISTICS
VDD = 2.7 V to 5.5 V; all specifications T
Table 3.
Parameter Limit
2
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
1
All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
2
Maximum SCLK frequency is 30 MHz.
1
33 ns min SCLK cycle time
5 ns min SCLK high time
5 ns min SCLK low time
10 ns min
5 ns min Data setup time
4.5 ns min Data hold time
0 ns min
20 ns min
13 ns min
MIN
to T
, unless otherwise noted. See Figure 2.
MAX
Unit Test Conditions/Comments
SYNC to SCLK falling edge setup time
SCLK falling edge to
Minimum
SYNC high time
SYNC rising edge
SYNC rising edge to next SCLK falling edge ignored
SCLK
SYNC
SDIN
t
4
t
8
t
t
2
1
t
3
t
6
t
5
t
9
t
7
D0D1D2D14D15
D15 D14
04611-002
Figure 2. Timing Diagram
Rev. A | Page 4 of 20
Page 5
AD5641
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 4.
Parameter Rating
VDD to GND −0.3 V to +7.0 V
Digital Input Voltage to GND –0.3 V to VDD + 0.3 V
V
to GND –0.3 V to VDD + 0.3 V
OUT
Operating Temperature Range
Industrial (A Grade) –40°C to +125°C
Storage Temperature Range –65°C to +160°C
Maximum Junction Temperature 150°C
SC70 Package
θJA Thermal Impedance 433.34°C/W
θJC Thermal Impedance 149.47°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) 215°C
Infrared (15 sec) 220°C
ESD 2.0 kV
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. A | Page 5 of 20
Page 6
AD5641
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
16
SYNC
SDIN
AD5641
TOP VIEW
25
(Not to Scale)
34
V
OUT
GNDSCLK
V
DD
Figure 3. 6-Lead SC70 Pin Configuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic Function
1
2 SCLK
SYNC Level-Triggered Control Input (Active Low). This is the frame synchronization signal for the input data. When SYNC
goes low, it enables the input shift register, and data is transferred in on the falling edges of the clocks that follow.
The DAC is updated following the 16
rising edge of
SYNC acts as an interrupt and the write sequence is ignored by the DAC.
th
clock cycle unless SYNC is taken high before this edge, in which case the
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can
be transferred at rates up to 30 MHz.
3 SDIN
Serial Data Input. This device has a 16-bit shift register. Data is clocked into the register on the falling edge of the
serial clock input.
4 V
DD
Power Supply Input. The AD5641 can be operated from 2.7 V to 5.5 V. VDD should be decoupled to GND.
5 GND Ground Reference Point for All Circuitry on the AD5641.
6 V
OUT
Analog Output Voltage from the DAC. The output amplifier has rail-to-rail operation.
04611-003
Rev. A | Page 6 of 20
Page 7
AD5641
TERMINOLOGY
Relative Accuracy
For the DAC, relative accuracy or integral nonlinearity (INL) is
a measure of the maximum deviation, in LSBs, from a straight
line passing through the endpoints of the DAC transfer
funct ion. See Figure 4 for a plot of typical INL vs. code.
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of ±1 LSB maximum
ensures monotonicity. This DAC is guaranteed monotonic by
design. See Figure 12 for a plot of typical DNL vs. code.
Zero-Code Error
Zero-code error is a measure of the output error when zero
code (0x0000) is loaded to the DAC register. Ideally, the output
should be 0 V. The zero-code error is always positive in the
AD5641, because the output of the DAC cannot go below 0 V.
Zero-code error is due to a combination of the offset errors in
the DAC and output amplifier. Zero-code error is expressed in
mV. See Figure 10 for a plot of zero-code error vs. temperature.
Full-Scale Error
Full-scale error is a measure of the output error when full-scale
code (0xFFFF) is loaded to the DAC register. Ideally, the output
should be V
Figure 10 for a plot of full-scale error vs. temperature.
Gain Error
Gain error is a measure of the span error of the DAC. It is the
deviation in slope of the DAC transfer characteristic from ideal,
expressed as a percent of the full-scale range.
− 1 LSB. Full-scale error is expressed in mV. See
DD
Tot a l U n ad ju s te d E rr o r ( TU E )
Total unadjusted error is a measure of the output error taking
the various errors into account. See Figure 7 for a plot of typical
TUE vs. code.
Zero-Code Error Drift
Zero-code error drift is a measure of the change in zero-code
error with a change in temperature. It is expressed in µV/°C.
Gain Error Drift
Gain error drift is a measure of the change in gain error with
changes in temperature. It is expressed in (ppm of full-scale
range)/°C.
Digital-to-Analog Glitch Impulse
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is normally specified as the area of the glitch in nV-s
and is measured when the digital input code is changed by
1 LSB at the major carry transition (0x2000 to 0x1FFF). See
Figure 26.
Digital Feedthrough
Digital feedthrough is a measure of the impulse injected into
the analog output of the DAC from the digital inputs of the
DAC, but is measured when the DAC output is not updated. It is
specified in nV-s and is measured with a full-scale code change
on the data bus, that is, from all 0s to all 1s and vice versa.
Rev. A | Page 7 of 20
Page 8
AD5641
TYPICAL PERFORMANCE CHARACTERISTICS
16
VDD = 5V
14
= 25°C
T
A
12
10
8
6
4
2
0
–2
–4
INL ERROR (LSB)
–6
–8
–10
–12
–14
–16
256 2256 4256 6256 8256 10256 12256 14256
6
4
MAX INL @ V
2
0
–2
–4
INL ERROR (LSB)
–6
MIN INL @ VDD = 3V
–8
–10
–40 –20 0 20 40 60 80 100 120 140
DD
Figure 5. INL Error vs. Temperature (3 V/5 V Supply )
20
TA = 25°C
15
10
5
0
–5
INL ERROR (LSB)
–10
–15
–20
2.7 3.2 3.7 4.2 4.7
Figure 6. INL Error vs. Supply at 25°C
DAC CODE
Figure 4. Typical I NL
= 3V
TEMPERATURE (°C)
MAX INL @ V
MIN INL @ V
MAX INL ERROR
MIN INL ERROR
SUPPLY (V)
04611-004
= 5V
DD
= 5V
DD
04611-005
5.2
04611-006
16
VDD = 5V
14
°c
T
= 25°C
A
12
10
8
6
4
2
0
–2
–4
TUE ERROR (LSB)
–6
–8
–10
–12
–14
–16
256 2256 4256 6256 8256 10256 12256 14256
DAC CODE
04611-007
Figure 7. Typical Total Unadjusted Error ( TUE)
15
10
5
0
MIN TUE ERROR @ V
–5
TUE ERROR (LSB)
–10
–15
–40 –20 0 20 40 60 80 100 120 140
MIN TUE ERROR @ V
TEMPERATURE (°C)
MAX TUE ERROR @ VDD = 3V
MAX TUE ERROR @ V
= 5V
DD
DD
DD
= 3V
= 5V
04611-008
Figure 8. Total Unadjusted Error (TUE) vs. Temperature (3 V/5 V Supply )
10
TA = 25°C
8
6
4
2
0
–2
TUE ERROR (LSB)
–4
–6
–8
–10
2.7 3.2 3.7 4.2 4.7 5.2
SUPPLY (V)
MAX TUE ERROR
MIN TUE ERROR
04611-009
Figure 9. Total Unadjusted Error (TUE) vs. Supply at 25°C
Rev. A | Page 8 of 20
Page 9
AD5641
0.0025
0.0020
0.0015
0.0010
0.0005
–0.0005
ERROR (LSB)
–0.0010
–0.0015
–0.0020
–0.0025
ZERO-SCALE ERROR @ VDD = 5V
ZERO-SCALE ERROR @ VDD = 3V
0
FULL-SCALE ERROR @ VDD = 3V
–40 –20 0 20 40 60 80 100 120 140
FULL-SCALE ERROR @ VDD = 5V
TEMPERATURE (°C)
Figure 10. Zero-Code/Full-Scale Error vs. Temperature (3 V/5 V)
0.0020
TA = 25°C
0.0015
0.0010
0.0005
ERROR (LSB)
–0.0005
–0.0010
–0.0015
–0.0020
ZERO-CODE ERROR
0
FULL-SCALE ERROR
2.7 3.2 3.7 4.2 4.7 5.2
SUPPLY (V)
Figure 11. Zero-Code/Full-Scale Error vs. Supply at 25°C
0.5
VDD = 5V
T
= 25°C
A
0.4
0.3
0.2
0.1
0
–0.1
DNL ERROR (LSB)
–0.2
–0.3
–0.4
–0.5
256 2256 4256 6256 8256 10256 12256 14256
DAC CODE
Figure 12. Typical DNL
04611-012
04611-010
04611-011
0.6
0.5
DNL ERROR (LSB)
0.4
0.3
0.2
0.1
–0.1
–0.2
–0.3
–0.4
MAX DNL @ V
0
MIN DNL @ V
MIN DNL @ V
–40 –20 0 20 40 60 80 100 120 140
= 3V
DD
MAX DNL @ VDD = 5V
= 3V
DD
= 5V
DD
TEMPERATURE (°C)
Figure 13. DNL Error vs. Temperature (3 V/5 V)
1.0
TA = 25°C
0.8
0.6
0.4
0.2
0
–0.2
DNL ERROR (LSB)
–0.4
–0.6
–0.8
–1.0
2.7 3.2 3.7 4.2 4.7 5.2
SUPPLY (V)
MAX DNL ERROR
MIN DNL ERROR
Figure 14. DNL Error vs. Supply at 25°C
12
V
10
NUMBER OF DEVICES
8
6
4
2
0
= 3V
DD
= DV
V
IH
VIL = GND
TA = 25°C
0.05456
0.05527
DD
0.05599
0.05671
Figure 15. I
0.05742
0.05814
0.05885
0.06648
IDD (mA)
Histogram (3 V/5 V)
DD
0.06710
0.06773
0.06835
0.06897
VDD = 5V
V
IH
VIL = GND
T
A
0.06960
0.07022
= 25°C
0.07084
= DV
0.07147
DD
0.07209
0.07271
04611-013
04611-014
0.07334
04611-015
Rev. A | Page 9 of 20
Page 10
AD5641
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
OFFSET ERROR (mV)
0.5
0.4
0.3
0.2
0.1
–40 –20 0 20 40 60 80 100 120 140
Figure 16. Offset Error vs. Temperature (3 V/5 V Supply)
0
–0.002
–0.004
–0.006
–0.008
–0.010
GAIN ERROR (%FSR)
–0.012
–0.014
–0.016
–40 –20 0 20 40 60 80 100 120 140
VDD = 3V
Figure 17. Gain Error vs. Temperature (3 V/5 V)
0.10
0.09
0.08
0.07
0.06
0.05
(mA)
DD
I
0.04
0.03
0.02
0.01
0
–40 –20 0 20 40 60 80 100 120 140
V
= 5V
DD
Figure 18. Supply Current vs. Temperature (3 V/5 V Supply)
VDD = 5V
VDD = 3V
TEMPERATURE (°C)
V
= 5V
DD
TEMPERATURE (°C)
VDD = 3V
TEMPERATURE (°C)
04611-016
04611-017
04611-018
0.10
TA = 25°C
0.09
0.08
0.07
0.06
0.05
(mA)
DD
I
0.04
0.03
0.02
0.01
0
2.7 3.2 3.7 4.2 4.7 5.2
SUPPLY VOLTAGE (V)
Figure 19. Supply Current vs. Supply Voltage at 25°C
0.8
VDD = 5V
= 25°C
T
A
0.6
0.4
0.2
(V)
O
∆V
0.0
–0.2
–0.4
–0.6
DAC LOADED WITH ZERO-SCALE CODE
DAC LOADED WITH FULL-SCALE CODE
–15 –10 –5 0 5 10 15
I(mA)
Figure 20. Sink and Source Capability
70
VDD = 5V
60
50
VDD = 3V
40
(mA)
DD
I
30
20
10
0
0 2000 4000 6000 8000 10000 12000 14000 16000
DIGITAL INPUT CODE
Figure 21. Supply Current vs. Digital Input Code
04611-019
04611-020
04611-021
Rev. A | Page 10 of 20
Page 11
AD5641
CH1 = SCLK
TA = 25°C
V
DD
CH2 = V
CH1
= 5V
CH2
OUT
V
DD
V
OUT
VDD = 5V
T
= 25°C
A
CH1 = 5V/DIV CH2 = 1V/DIV TIME BASE = 2µs/DIV
Figure 22. Full-Scale Settling Time
TA = 25°C
V
CH1 = SCLK
CH2 = V
OUT
CH1 = 5V/DIV CH2 = 1V/DIV TIME BASE = 2µs/DIV
DD
Figure 23. Half-Scale Settling Time
V
VDD = 5V
T
= 25°C
A
DD
= 5V
04611-022
04611-023
CH1 1V, CH2 5V, TIME BASE = 50µs/DIV
Figure 25. V
DD
vs. V
OUT
2.458
2.456
2.454
2.452
2.450
2.448
2.446
AMPLITUDE (V)
2.444
2.442
2.440
2.438
2.436
0 100 200 300 400 500
SAMPLE NUMBER
TA = 25°C
V
= 5V
DD
LOAD = 2kΩ AND 220pF
CODE 0x2000 TO 0x1FFF
10ns/SAMPLE NUMBER
Figure 26. Digital-to-Analog Glitch Energy
= 5V
V
DD
T
= 25°C
A
MIDSCALE LOADED
04611-025
04611-026
CH1
CH2
V
= 70mV
OUT
CH1 1V, CH2 20mV, TIME BASE = 20µs/DIV
Figure 24. Power-On Reset to 0 V
04611-024
Rev. A | Page 11 of 20
CH1
CH1 5µV/DIV
Figure 27. 1/f Noise, 0.1 Hz to 10 Hz Bandwidth
04611-027
Page 12
AD5641
CH1
VDD = 5V
= 25°C
T
A
700
VDD = 5V
= 25°C
T
A
600
UNLOADED OUTPUT
500
V
OUT
CH2
CH1 5V, CH2 1V, TIME BASE = 2µs/DIV
Figure 28. Exiting Power-Down Mode
140
120
100
80
(µA)
60
DD
I
40
20
0
0 5 10 15 20 25
FULL SCALE
FREQUENCY (MHz)
Figure 29. I
1/4 SCALE
ZERO SCALE
vs. SCLK vs. Code
DD
3/4 SCALE
MIDSCALE
04783-028
04611-029
400
300
200
100
OUTPUT NO ISE SPECT RAL DENSITY (nV/ Hz)
ZERO SCALE
MIDSCALE
0
100 1000 10000 100000
FREQUENCY (Hz)
FULL SCALE
Figure 30. Noise Spectral Density
450
TA = 25°C
400
350
300
250
(µA)
200
DD
I
150
100
50
SCLK/SDIN DECREASING V
0
0
SCLK/SDIN
INCREASING
V
= 5V
DD
DD
V
LOGIC
= 3V
(V)
SCLK/SDIN
DECREASING
V
= 5V
DD
SCLK/SDIN
INCREASING
V
= 3V
DD
Figure 31. SCLK/SDIN vs. Logic Voltage
645321
04611-030
04611-044
Rev. A | Page 12 of 20
Page 13
AD5641
THEORY OF OPERATION
D/A SECTION
The AD5641 DAC is fabricated on a CMOS process. The
architecture consists of a string DAC followed by an output
buffer amplifier. Figure 32 is a block diagram of the DAC
architecture.
V
DD
REF (+)
DAC REGISTER
RESISTOR
NETWORK
REF (–)
ٛ
GND
Figure 32. DAC Architecture
OUTPUT AMPLIFIER
V
OUT
Because the input coding to the DAC is straight binary, the ideal
output voltage is given by
OUT
VV
⎜
DD
16384
⎝
⎟
⎠
D
⎞
⎛
×=
where D is the decimal equivalent of the binary code that is
loaded to the DAC register; it can range from 0 to 16,384.
RESISTOR STRING
The resistor string structure is shown in Figure 33. It is simply a
string of resistors, each of value R. The code loaded to the DAC
register determines at which node on the string the voltage is
tapped off to be fed into the output amplifier. The voltage is
tapped off by closing one of the switches connecting the string
to the amplifier. Because it is a string of resistors, it is guaranteed monotonic.
R
R
R
TO OUTPUT
AMPLIFIER
04611-031
OUTPUT AMPLIFIER
The output buffer amplifier is capable of generating rail-to-rail
voltages on its output, giving an output range of 0 V to V
DD
. It is
capable of driving a load of 2 kΩ in parallel with 1000 pF to
GND. The source and sink capabilities of the output amplifier
can be seen in Figure 20. The slew rate is 0.5 V/µs, with a halfscale settling time of 8 µs with the output loaded.
SERIAL INTERFACE
The AD5641 has a 3-wire serial interface (
SDIN) that is compatible with SPI, QSPI, and MICROWIRE
interface standards, as well as most DSPs. See Figure 2 for a
timing diagram of a typical write sequence.
The write sequence begins by bringing the
from the SDIN line is clocked into the 16-bit shift register on
the falling edge of SCLK. The serial clock frequency can be as
high as 30 MHz, making the AD5641compatible with high
th
speed DSPs. On the 16
falling clock edge, the last data bit is
clocked in and the programmed function is executed (a change
in DAC register contents and/or a change in the mode of
operation). At this stage, the
SYNC
brought high. In either case, it must be brought high for a
minimum of 33 ns before the next write sequence, so that a
falling edge of
Because the
than it does when V
SYNC
can initiate the next write sequence.
SYNC
buffer draws more current when VIN = 1.8 V
= 0.8 V,
IN
SYNC
between write sequences for even lower power operation of the
part, as mentioned previously. However, it must be brought high
again just before the next write sequence.
SYNC
, SCLK, and
SYNC
line low. Data
line can be kept low or
should be idled low
INPUT SHIFT REGISTER
The input shift register is 16 bits wide (see Figure 34). The first
two bits are control bits, which determine the part’s mode of
operation (normal mode or any one of three power-down
modes). For a complete description of the various modes, see
the Power-Down Modes section. The next 16 bits are the data
bits, which are transferred to the DAC register on the 16
edge of SCLK.
th
falling
SYNC INTERRUPT
In a normal write sequence, the
least 16 falling edges of SCLK and the DAC is updated on the
th
16
R
R
04611-032
Figure 33. Resistor String Structure
falling edge. However, if
th
16
falling edge, this acts as an interrupt to the write sequence.
The shift register is reset and the write sequence is seen as
invalid. Neither an update of the DAC register contents nor a
change in the operating mode occurs (see Figure 35).
Rev. A | Page 13 of 20
SYNC
line is kept low for at
SYNC
is brought high before the
Page 14
AD5641
DB15 (MSB) DB0 (LSB)
PD1 PD0 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
DATA BITS
0
0
1
1
NORMAL OPERATION
0
1
1 kΩ TO GND
100 kΩ TO GND
0
THREE-STATE
1
POWER-DOWN MODES
04611-033
Figure 34. Input Register Contents
SCLK
SYNC
SDIN
DB15 DB16 DB0DB0
INVALID WRITE SEQUENCE:
SYNC HIGH BEFORE 16
TH
FALLING EDGE
Figure 35.
SYNC
Interrupt Facility
VALID WRITE SEQUENCE, OUTPUT UPDATES
ON THE 16TH FALLING EDGE
04611-034
POWER-ON RESET
The AD5641 contains a power-on reset circuit that controls the
output voltage during power-up. The DAC register is filled with
0s and the output voltage is 0 V. It remains there until a valid
write sequence is made to the DAC. This is useful in applications in which it is important to know the state of the DAC’s
output while it is in the process of powering up.
POWER-DOWN MODES
The AD5641 has four separate modes of operation. These
modes are software-programmable by setting two bits (DB15
and DB14) in the control register. Table 6 shows how the state of
the bits corresponds to the mode of operation of the device.
Table 6. Modes of Operation for the AD5641
DB15 DB14 Operating Mode
0 0 Normal operation
Power-down mode:
0 1 1 kΩ to GND
1 0 100 kΩ to GND
1 1 Three-state
When both bits are set to 0, the part works normally with its
normal power consumption of 100 µA maximum at 5 V.
However, for the three power-down modes, the supply current
falls to typically 0.2 µA at 3 V.
Not only does the supply current fall, but the output stage is also
internally switched from the output of the amplifier to a resistor
network of known values. This has the advantage that the output impedance of the part is known while the part is in powerdown mode. There are three different options: the output is
connected internally to GND through either a 1 kΩ resistor or a
100 kΩ resistor, or the output is left open-circuited (three-state).
Figure 36 shows the output stage.
RESISTOR
STRING DAC
Figure 36. Output Stage During Power-Down
AMPLIFIER
POWER-DOWN
CIRCUITRY
RESISTOR
NETWORK
V
OUT
04611-035
The bias generator, output amplifier, resistor string, and other
associated linear circuitry are all shut down when power-down
mode is activated. However, the contents of the DAC register
are unaffected when in power-down. The time to exit powerdown is typically 13 µs for V
= 5 V and 16 µs for VDD = 3 V.
DD
See Figure 28 for a plot.
Rev. A | Page 14 of 20
Page 15
AD5641
MICROPROCESSOR INTERFACING
AD5641 to ADSP-2101/ADSP-2103 Interface
Figure 37 shows a serial interface between the AD5641 and the
ADSP-2101/ADSP-2103. The ADSP-2101/ADSP-2103 should
be set up to operate in SPORT transmit alternate framing mode.
The ADSP-2101/ADSP-2103 SPORT is programmed through
the SPORT control register and should be configured as follows:
internal clock operation, active low framing, and 16-bit word
length. Transmission is initiated by writing a word to the Tx
register after the SPORT is enabled.
AD5641 to Blackfin® ADSP-BF53X Interface
Figure 39 shows a serial interface between the AD5641 and the
Blackfin ADSP-BF53x microprocessor. The ADSP-BF53x processor family incorporates two dual-channel synchronous serial
ports, SPORT1 and SPORT0, for serial and multiprocessor
communications. Using SPORT0 to connect to the AD5641, the
setup for the interface is as follows: DT0PRI drives the SDIN
pin of the AD5641, while TSCLK0 drives the SCLK of the part.
SYNC
The
is driven from TFS0.
ADSP-2101/
ADSP-2103*
TFS
DT
SCLK
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 37. AD5641 to ADSP-2101/ADSP-2103 Interface
AD5641*
SYNC
SDIN
SCLK
AD5641 to 68HC11/68L11 Interface
Figure 38 shows a serial interface between the AD5641 and the
68HC11/68L11 microcontroller. SCK of the 68HC11/68L11
drives the SCLK of the AD5641, while the MOSI output drives
SYNC
the serial data line of the DAC. The
signal is derived
from a port line (PC7). The setup conditions for correct
operation of this interface are as follows: the 68HC11/68L11
should be configured so that the CPOL bit is 0 and the CPHA
bit is 1. When data is being transmitted to the DAC, the
SYNC
line is taken low (PC7). When the 68HC11/68L11 are
configured as above, data appearing on the MOSI output is valid
on the falling edge of SCK. Serial data from the 68HC11/68L11
is transmitted in 8-bit bytes with only eight falling clock edges
occurring in the transmit cycle. Data is transmitted MSB first.
To load data to the AD5641, PC7 is left low after the first eight
bits are transferred and a second serial write operation is
performed to the DAC. PC7 is taken high at the end of this
procedure.
04611-036
ADSP-BF53x*
DT0PRI
TSCLK0
TFS0
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 39. AD5641 to Blackfin ADSP-BF53x Interface
AD5641*
SDIN
SCLK
SYNC
AD5641 to 80C51/80L51 Interface
Figure 40 shows a serial interface between the AD5641 and the
80C51/80L51 microcontroller. The setup for the interface is as
follows: TxD of the 80C51/80L51 drives SCLK of the AD5641,
while RxD drives the serial data line of the part. The
SYNC
signal is again derived from a bit programmable pin on the port.
In this case, Port Line P3.3 is used. When data is to be
transmitted to the AD5641, P3.3 is taken low.
The 80C51/80L51 transmits data only in 8-bit bytes; therefore,
only eight falling clock edges occur in the transmit cycle. To
load data to the DAC, P3.3 is left low after the first eight bits are
transmitted, and a second write cycle is initiated to transmit the
second byte of data. P3.3 is taken high following the completion
of this cycle. The 80C51/80L51 outputs the serial data LSB first.
The AD5641 requires its data with the MSB as the first bit
received. The 80C51/80L51 transmit routine should take this
into account.
04611-038
68HC11/
68L11*
PC7
SCK
MOSI
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 38. AD5641 to 68HC11/68L11 Interface
AD5641*
SYNC
SCLK
SDIN
04611-037
Rev. A | Page 15 of 20
*ADDITIONAL PINS OMITTED FOR CLARITY
80C51/80L51*
P3.3
TXD
RXD
Figure 40. AD5641 to 80C51/80L51 Interface
AD5641*
SYNC
SCLK
SDIN
04611-039
Page 16
AD5641
AD5641 to MICROWIRE Interface
Figure 41 shows an interface between the AD5641 and any
MICROWIRE-compatible device. Serial data is shifted out on
the falling edge of the serial clock and is clocked into the
AD5641 on the rising edge of the SK.
MICROWIRE*
CS
SK
SO
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 41. AD5641 to MICROWIRE Interface
AD5641*
SYNC
SCLK
SDIN
04611-040
Rev. A | Page 16 of 20
Page 17
AD5641
APPLICATIONS
CHOOSING A REFERENCE AS POWER SUPPLY FOR THE AD5641
The AD5641 comes in a tiny SC70 package with less than
100 µA supply current. Because of this, the choice of reference
depends on the application requirement. For space-saving
applications, the ADR02 is available in an SC70 package and has
excellent drift at 9 ppm/°C (3 ppm/°C in the R-8 package). It
also provides very good noise performance at 3.4 µV p-p in the
0.1 Hz to 10 Hz range.
Because the supply current required by the AD5641 is extremely
low, the parts are ideal for low supply applications. The ADR395
voltage reference is recommended in this case. It requires less
than 100 µA of quiescent current and can, therefore, drive
multiple DACs in one system, if required. It also provides very
good noise performance at 8 µV p-p in the 0.1 Hz to 10 Hz
range.
7V
ADR395
5V
BIPOLAR OPERATION USING THE AD5641
The AD5641 has been designed for single-supply operation, but
a bipolar output range is also possible using the circuit in
Figure 43. The circuit in Figure 43 gives an output voltage range
of ±5 V. Rail-to-rail operation at the amplifier output is
achievable using an AD820 or OP295 as the output amplifier.
R2 = 10k
Ω
+5V
10µF
0.1µF
Figure 43. Bipolar Operation with the AD5641
R1 = 10kΩ
V
DD
AD5641
INTERFACE
3-WIRE
SERIAL
V
OUT
The output voltage for any input code can be calculated as
follows:
+5V
AD820/
OP295
–5V
+5V
04611-042
3-WIRE
SERIAL
INTERFACE
SYNC
SCLK
SDIN
Figure 42. ADR395 as Power Supply to AD5641
AD5641
V
OUT
= 0V TO 5V
04611-041
Table 7 lists some recommended precision references for use as
supplies to the AD5641.
Table 7. Precision References for Use with AD5641
Part
No.
Initial
Accuracy
(mV max)
Temperature
Drift
(ppm/°C max)
0.1 Hz to 10 Hz
Noise (µV p-p typ)
ADR435 ±2 3 (R-8) 8
ADR425 ±2 3 (R-8) 3.4
ADR02 ±3 3 (R-8) 10
ADR02 ±3 3 (SC70) 10
ADR395 ±5 9 (TSOT-23) 8
+
⎡
⎛
×=
VV
O
⎜
⎢
⎝
⎣
16384
⎞
⎟
⎠
R2R1D
⎛
×
⎜
⎝
R1
⎞
V
⎟
⎠
R2
⎤
⎛
⎞
×−
DDDD
⎜
⎟
⎥
R1
⎝
⎠
⎦
where D represents the input code in decimal (0 – 16384). With
V
= 5 V, R1 = R2 = 10 kΩ,
DD
10
×=D
16384
⎞
V5
−
⎟
⎠
⎛
V
⎜
O
⎝
This is an output voltage range of ±5 V with 0x0000 corresponding to a –5 V output, and 0x3FFF corresponding to a
+5 V output.
Rev. A | Page 17 of 20
Page 18
AD5641
USING THE AD5641 WITH AN OPTO-ISOLATED INTERFACE
In process-control applications in industrial environments, it is
often necessary to use an opto-isolated interface to protect and
isolate the controlling circuitry from any hazardous commonmode voltages that might occur in the area where the DAC is
functioning. Opto-isolators provide isolation in excess of 3 kV.
Because the AD5641 uses a 3-wire serial logic interface, it
requires only three opto-isolators to provide the required
isolation (see Figure 44). The power supply to the part must also
be isolated using a transformer. On the DAC side of the transformer, a 5 V regulator provides the 5 V supply required for
the AD5641.
+5V
POWER
SCLK
REGULATOR
V
DD
10kΩ
V
SCLK
10µF
0.1µF
DD
POWER SUPPLY BYPASSING AND GROUNDING
When accuracy is important in a circuit, it is helpful to carefully
consider the power supply and ground return layout on the
board. The printed circuit board containing the AD5641 should
have separate analog and digital sections, each having its own
area of the board. If the AD5641 is in a system where other
devices require an AGND-to-DGND connection, the connection
should be made at one point only. This ground point should be
as close as possible to the AD5641.
The power supply to the AD5641 should be bypassed with
10 µF and 0.1 µF capacitors. The capacitors should be physically
as close as possible to the device, with the 0.1 µF capacitor
ideally right up against the device. The 10 µF capacitors are the
tantalum bead type. It is important that the 0.1 µF capacitor
have low effective series resistance (ESR) and effective series
inductance (ESI),
This 0.1 µF capacitor provides a low impedance path to ground
for high frequencies caused by transient currents due to internal
logic switching.
such as in common ceramic types of capacitors.
SYNC
10kΩ
SYNC
AD5641
V
OUT
V
DD
The power supply line itself should have as large a trace as
possible to provide a low impedance path and reduce glitch
effects on the supply line. Clocks and other fast switching digital
signals should be shielded from other parts of the board by
digital ground. Avoid crossover of digital and analog signals, if
V
DD
10kΩ
DATA
Figure 44. AD5641 with an Opto-Isolated Interface
SDIN
GND
04611-043
possible. When traces cross on opposite sides of the board,
ensure that they run at right angles to each other to reduce
feedthrough effects through the board. The best board layout
technique is the microstrip technique, where the component
side of the board is dedicated to the ground plane only and the
signal traces are placed on the solder side. However, this is not
always possible with a 2-layer board.
Rev. A | Page 18 of 20
Page 19
AD5641
OUTLINE DIMENSIONS
2.20
2.00
1.80
2.40
1.35
1.25
1.15
PIN 1
1.30 BSC
1.00
0.90
0.70
0.10 MAX
0.10 COPLANARITY
COMPLIANT TO JEDEC STANDARDS MO-203-AB
Figure 45. 6-Lead Thin Shrink Small Outline Transistor Package [SC70]
ORDERING GUIDE
Temperature
Model
AD5641AKSZ-REEL7
AD5641AKSZ-500RL71 –40°C to +125°C ±16 LSB INL
1
Z = Pb-free part.
Range Description Package Description
1
–40°C to +125°C ±16 LSB INL
4 5 6
2.10
3 2 1
1.80
0.65 BSC
0.40
0.10
0.22
0.08
0.30
0.15
1.10
0.80
SEATING
PLANE
(KS-6)
Dimensions shown in millimeters
6-Lead Thin Shrink Small Outline Transistor Package
(SC70)
6-Lead Thin Shrink Small Outline Transistor Package
(SC70)
0.30
0.10
Package
Option Branding
KS-6 D3Q
KS-6 D3Q
Rev. A | Page 19 of 20
Page 20
AD5641
NOTES
© 2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04611–0–3/05(A)
Rev. A | Page 20 of 20
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