Datasheet AD5623R, AD5643R, AD5663R Datasheet (ANALOG DEVICES)

5 ppm/°C On-Chip Reference

AD5623R/AD5643R/AD5663R

Rev. E

Trademarks and registered trademarks are the property of their respective owners.

Fax: [phone] ©2006–2012 Analog Devices, Inc. All rights reserved.

INTERFACE

LOGIC

SCLK

SYNC

DIN

CLR

INPUT

REGISTER

INPUT

REGISTER

DAC

REGISTER

DAC

REGISTER

V

DD

GND

POWER-ON

RESET

STRING

DAC A

STRING

DAC B

BUFFER

BUFFER

V

REFIN/VREFOUT

POWER-DOWN

LOGIC

V

OUT

A

V

OUT

B

AD5623R/AD5643R/AD5663R

LDAC

LDAC

05858-001

1.25V/2.5V

REFERENCE

Data Sheet

FEATURES

Low power, smallest pin-compatible, dual nanoDAC

AD5663R: 16 bits
AD5643R: 14 bits
AD5623R: 12 bits

User-selectable external or internal reference

External reference default
On-chip 1.25 V/2.5 V, 5 ppm/°C reference

10-lead MSOP and 3 mm × 3 mm LFCSP

2.7 V to 5.5 V power supply
Guaranteed monotonic by design
Power-on reset to zero scale
Per channel power-down
Serial interface up to 50 MHz
Hardware

LDAC

APPLICATIONS

Process control
Data acquisition systems
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators

and

CLR

functions

Dual 12-/14-/16-Bit nanoDAC® with

FUNCTIONAL BLOCK DIAGRAM

Figure 1.

Table 1. Related Devices

Part No. Description

AD5663 2.7 V to 5.5 V, dual 16-bit nanoDAC, with external

reference

GENERAL DESCRIPTION

The AD5623R/AD5643R/AD5663R, members of the nanoDAC
family, are low power, dual 12-, 14-, and 16-bit buffered voltage­out digital-to-analog converters (DAC) that operate from a single

2.7 V to 5.5 V supply and are guaranteed monotonic by design.

The AD5623R/AD5643R/AD5663R have an on-chip reference.
The AD5623R-3/AD5643R-3/AD5663R-3 have a 1.25 V, 5 ppm/°C
reference, giving a full-scale output of 2.5 V; and the AD5623R-5/
AD5643R-5/AD5663R-5 have a 2.5 V, 5 ppm/°C reference,
giving a full-scale output of 5 V. The on-chip reference is off at
power-up, allowing the use of an external reference; and all
devices can be operated from a single 2.7 V to 5.5 V supply.
The internal reference is turned on by writing to the DAC.

The parts incorporate a power-on reset circuit that ensures the
DAC output powers up to 0 V and remains there until a valid
write takes place. The part contains a power-down feature that
reduces the current consumption of the device to 480 nA at 5 V
and provides software-selectable output loads while in power­down mode.

Information furnishe d by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

The low power consumption of this part in normal operation
makes it ideally suited to portable, battery-operated equipment.

The AD5623R/AD5643R/AD5663R use a versatile, 3-wire serial
interface that operates at clock rates up to 50 MHz, and they are
compatible with standard SPI®, QSPI™, MICROWIRE™, and
DSP interface standards. The on-chip precision output amplifier
enables rail-to-rail output swing to be achieved.

PRODUCT HIGHLIGHTS

1. Dual 12-, 14-, and 16-bit DAC.

2. On-chip 1.25 V/2.5 V, 5 ppm/°C reference.

3. Available in 10-lead MSOP and 10-lead, 3 mm ×

3 mm LFCSP.

4. Low power; typically consumes 0.6 mW at 3 V and

1.25 mW at 5 V.

5. 4.5 µs maximum settling time for the AD5623R.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]

www.analog.com

AD5623R/AD5643R/AD5663R Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Output Amplifier ........................................................................ 20

Applications ....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

AD5623R-5/AD5643R-5/AD5663R-5 ....................................... 3

AD5623R-3/AD5643R-3/AD5663R-3 ....................................... 5

AC Characteristics ........................................................................ 6

Timing Characteristics ................................................................ 7

Timing Diagram ........................................................................... 7

Absolute Maximum Ratings ............................................................ 8

ESD Caution .................................................................................. 8

Pin Configuration and Function Descriptions ............................. 9

Typical Performance Characteristics ........................................... 10

Internal Reference ...................................................................... 20

External Reference ..................................................................... 20

Serial Interface ............................................................................ 20

Input Shift Register .................................................................... 21

SYNC

Interrupt .......................................................................... 21

Power-On Reset .......................................................................... 22

Software Reset ............................................................................. 22

Power-Down Modes .................................................................. 22

LDAC

Function .......................................................................... 23

Internal Reference Setup ........................................................... 24

Microprocessor Interfacing ....................................................... 25

Applications Information .............................................................. 26

Using a Reference as a Power Supply ....................................... 26

Bipolar Operation Using the AD5663R .................................. 26

Using the AD5663R with a Galvanically Isolated Interface . 26

Terminology .................................................................................... 18

Theory of Operation ...................................................................... 20

Digital-to-Analog Section ......................................................... 20

Resistor String ............................................................................. 20

REVISION HISTORY

4/12—Rev. D to Rev. C

Changes to Table 2 ............................................................................ 3

Updated Outline Dimensions ....................................................... 28

Changes to Ordering Guide .......................................................... 29

4/11—Rev. C to Rev. D

Changes to Ordering Guide .......................................................... 29

6/10—Rev. B to Rev. C

Changes to Ordering Guide .......................................................... 28

Power Supply Bypassing and Grounding ................................ 27

Outline Dimensions ....................................................................... 28

Ordering Guide .......................................................................... 29

4/10—Rev. A to Rev. B

Updated Outline Dimensions ....................................................... 28

12/06—Rev. 0 to Rev. A

Changes to Table 2 ............................................................................. 3

Changes to Table 3 ............................................................................. 5

Changes to Figure 3 ........................................................................... 9

Changes to Ordering Guide .......................................................... 28

4/06—Revision 0: Initial Version

Rev. E | Page 2 of 32

Data Sheet AD5623R/AD5643R/AD5663R

AD5663R

DC Crosstalk (External Reference)

10

10 µV

Due to full-scale output change;

Power-Up Time

4 4 μs

Coming out of power-down mode;

Reference Input Range

0.75 VDD

0.75 VDD

V

SPECIFICATIONS

AD5623R-5/AD5643R-5/AD5663R-5

VDD = 4.5 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; V

Table 2.

A Grade1 B Grade1
Parameter Min Typ Max Min Typ Max Unit Conditions/Comments

STATIC PERFORMANCE2

Resolution 16 Bits
Relative Accuracy ±8 ±16 LSB
Differential Nonlinearity ±1 LSB Guaranteed monotonic by design

AD5643R

Resolution 14 Bits
Relative Accuracy ±2 ±4 LSB
Differential Nonlinearity ±0.5 LSB Guaranteed monotonic by design

AD5623R

Resolution 12 Bits
Relative Accuracy ±1 ±2 ±0.5 ±1 LSB

Differential Nonlinearity ±1 ±0.25 LSB Guaranteed monotonic by design
Zero-Scale Error +2 +10 +2 +10 mV All 0s loaded to DAC register
Offset Error ±1 ±10 ±1 ±10 mV
Full-Scale Error −0.1 ±1 −0.1 ±1 % of

Gain Error ±1.5 ±1.5 % of

Zero-Scale Error Drift ±2 ±2 µV/°C
Gain Temperature Coefficient ±2.5 ±2.5 ppm Of FSR/°C
DC Power Supply Rejection Ratio −100 −100 dB DAC code = midscale ; VDD = 5 V ±

= VDD; all specifications T

REFIN

FSR

FSR

MIN

to T

unless otherwise noted.

MAX,

All 1s loaded to DAC register

10%

RL = 2 kΩ to GND or V

DD

10 10 µV/mA Due to load current change
5 5 µV Due to powering down (per channel)

DC Crosstalk (Internal Reference) 25 25 µV

Due to full-scale output change;
R

= 2 kΩ to GND or V

L

DD

20 20 µV/mA Due to load current change
10 10 µV Due to powering down (per channel)
OUTPUT CHARACTERISTICS3

Output Voltage Range 0 VDD 0 VDD V
Capacitive Load Stability 2 2 nF RL = ∞
10 10 nF RL = 2 kΩ
DC Output Impedance 0.5 0.5 Ω
Short-Circuit Current 30 30 mA VDD = 5 V

VDD = 5 V

REFERENCE INPUTS

Reference Current 170 200 170 200 µA V

= VDD = 5.5 V

REF

Reference Input Impedance 26 26 kΩ

Rev. E | Page 3 of 32

AD5623R/AD5643R/AD5663R Data Sheet

VDD = 4.5 V to 5.5 V

0.25

0.45 0.25

0.45

mA

Internal reference off

A Grade1 B Grade1
Parameter Min Typ Max Min Typ Max Unit Conditions/Comments

REFERENCE OUTPUT

Output Voltage 2.495 2.505 2.495 2.505 V At ambient
Reference Temperature Coefficient3 ±10 ±5 ±10 ppm/°C MSOP package models
±10 ±10 ppm/°C LFCSP package models
Output Impedance 7.5 7.5 kΩ

LOGIC INPUTS3

Input Current ±2 ±2 µA All digital inputs
Input Low Voltage (V
Input High Voltage (V
Pin Capacitance 3 3 pF DIN, SCLK, and

19 19 pF

POWER REQUIREMENTS

VDD 4.5 5.5 4.5 5.5 V

IDD (Normal Mode)4 VIH = VDD and VIL = GND

VDD = 4.5 V to 5.5 V 0.8 1 0.8 1 mA Internal reference on
IDD (All Power-Down Modes)5
VDD = 4.5 V to 5.5 V 0.48 1 0.48 1 µA VIH = VDD and VIL = GND

1

Temperature range: A, B grade = −40°C to +105°C.

2

Linearity calculated using a reduced code range: AD5663R (Code 512 to Code 65,024), AD5643R (Code 128 to Code 16,256), and AD5623R (Code 32 to Code 4064).

Output unloaded.

3

Guaranteed by design and characterization, not production tested.

4

Interface inactive. All DACs active. DAC outputs unloaded.

5

Both DACs powered down.

) 0.8 0.8 V VDD = 5 V

INL

) 2 2 V VDD = 5 V

INH

LDAC

and

CLR

SYNC

Rev. E | Page 4 of 32

Data Sheet AD5623R/AD5643R/AD5663R

Relative Accuracy

±8

±16

LSB

DC Crosstalk (External Reference)

10 µV

Due to full-scale output change;

Reference Input Range

0.75 VDD

V

AD5623R-3/AD5643R-3/AD5663R-3

VDD = 2.7 V to 3.6 V; RL = 2 kΩ to GND; CL = 200 pF to GND; V

Table 3.

B Grade1
Parameter Min Typ Max Unit Conditions/Comments

STATIC PERFORMANCE2

AD5663R

Resolution 16 Bits

Differential Nonlinearity ±1 LSB Guaranteed monotonic by design
AD5643R

Resolution 14 Bits

Relative Accuracy ±2 ±4 LSB

Differential Nonlinearity ±0.5 LSB Guaranteed monotonic by design
AD5623R

Resolution 12 Bits

Relative Accuracy ±0.5 ±1 LSB

Differential Nonlinearity ±0.25 LSB Guaranteed monotonic by design
Zero-Scale Error +2 +10 mV All 0s loaded to DAC register
Offset Error ±1 ±10 mV
Full-Scale Error −0.1 ±1 % of FSR All 1s loaded to DAC register
Gain Error ±1.5 % of FSR
Zero-Scale Error Drift ±2 µV/°C
Gain Temperature Coefficient ±2.5 ppm Of FSR/°C
DC Power Supply Rejection Ratio −100 dB DAC code = midscale; VDD = 3 V ± 10%

= VDD; all specifications T

REFIN

MIN

to T

, unless otherwise noted.

MAX

RL = 2 kΩ to GND or V

DD

10 µV/mA Due to load current change
5 µV Due to powering down (per channel)

DC Crosstalk (Internal Reference) 25 µV

Due to full-scale output change;

= 2 kΩ to GND or V

R

L

DD

20 µV/mA Due to load current change
10 µV Due to powering down (per channel)
OUTPUT CHARACTERISTICS3

Output Voltage Range 0 VDD V
Capacitive Load Stability 2 nF RL = ∞
10 nF RL = 2 kΩ
DC Output Impedance 0.5 Ω
Short Circuit Current 30 mA VDD = 3 V
Power-Up Time 4 µs Coming out of power-down mode; VDD = 3 V

REFERENCE INPUTS

Reference Current 170 200 µA V

= VDD = 3.6 V

REF

Reference Input Impedance 26 kΩ

REFERENCE OUTPUT

Output Voltage 1.247 1.253 V At ambient
Reference Temperature Coefficient3 ±5 ±15 ppm/°C MSOP package models
±10 ppm/°C LFCSP package models
Output Impedance 7.5 kΩ

Rev. E | Page 5 of 32

AD5623R/AD5643R/AD5663R Data Sheet

Digital Crosstalk

0.1 nV-s

Multiplying Bandwidth

340 kHz

V

= 2 V ± 0.1 V p-p

B Grade1
Parameter Min Typ Max Unit Conditions/Comments

LOGIC INPUTS3

Input Current ±2 µA All digital inputs
V

, Input Low Voltage 0.8 V VDD = 3 V

INL

V

, Input High Voltage 2 V VDD = 3 V

INH

Pin Capacitance 3 pF DIN, SCLK, and
19 pF

LDAC

and

CLR

POWER REQUIREMENTS

VDD 2.7 3.6 V

IDD (Normal Mode)4 VIH = VDD and VIL = GND
VDD = 2.7 V to 3.6 V 200 425 µA Internal reference off
VDD = 2.7 V to 3.6 V 800 900 µA Internal reference on
IDD (All Power-Down Modes)5
VDD = 2.7 V to 3.6 V 0.2 1 µA VIH = VDD and VIL = GND

1

Temperature range: B grade = −40°C to +105°C.

2

Linearity calculated using a reduced code range: AD5663R (Code 512 to Code 65,024), AD5643R (Code 128 to Code 16,256), and AD5623R (Code 32 to Code 4064).

Output unloaded.

3

Guaranteed by design and characterization, not production tested.

4

Interface inactive. All DACs active. DAC outputs unloaded.

5

Both DACs powered down.

SYNC

AC CHARACTERISTICS

VDD = 2.7 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; V

Table 4.

Parameter

1, 2

Min Ty p Max Unit Conditions/Comments3

Output Voltage Settling Time

AD5623R 3 4.5 µs ¼ to ¾ scale settling to ±0.5 LSB
AD5643R 3.5 5 µs ¼ to ¾ scale settling to ±0.5 LSB

AD5663R 4 7 µs ¼ to ¾ scale settling to ±2 LSB
Slew Rate 1.8 V/µs
Digital-to-Analog Glitch Impulse 10 nV-s 1 LSB change around major carry
Digital Feedthrough 0.1 nV-s
Reference Feedthrough −90 dB V

Analog Crosstalk 1 nV-s External reference
4 nV-s Internal reference
DAC-to-DAC Crosstalk 1 nV-s External reference
4 nV-s Internal reference

Total Harmonic Distortion −80 dB V
Output Noise Spectral Density 120 nV/√Hz DAC code = midscale, 1 kHz
100 nV/√Hz DAC code = midscale, 10 kHz
Output Noise 15 μV p-p 0.1 Hz to 10 Hz

1

Guaranteed by design and characterization, not production tested.

2

See the Terminology section.

3

Temperature range: A, B grade = −40°C to +105°C, typical at +25°C.

= VDD; all specifications T

REFIN

to T

MIN

= 2 V ± 0.1 V p-p, frequency 10 Hz to 20 MHz

REF

REF

= 2 V ± 0.1 V p-p, frequency = 10 kHz

REF

, unless otherwise noted.

MAX

Rev. E | Page 6 of 32

Data Sheet AD5623R/AD5643R/AD5663R

05858-002

t

4

t

3

SCLK

SYNC

DIN

t

1

t

2

t

5

t

6

t

7

t

8

DB23

t

9

t

10

t

11

t

12

LDAC

1

LDAC

2

t

14

1

ASYNCHRONOUS LDAC UPDATE MODE .

2

SYNCHRONOUS LDAC UPDATE MODE .

CLR

t

13

t

15

V

OUT

DB0

TIMING CHARACTERISTICS

All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
V

= 2.7 V to 5.5 V; all specifications T

DD

Table 5.

Limit at T
Parameter

2

t

20 ns min SCLK cycle time

1

VDD = 2.7 V to 5.5 V Unit Conditions/Comments

MIN

t2 9 ns min SCLK high time
t3 9 ns min SCLK low time
t4 13 ns min
t5 5 ns min Data setup time
t6 5 ns min Data hold time
t7 0 ns min
t8 15 ns min
t9 13 ns min

t10 0 ns min
t11 10 ns min
t12 15 ns min
t13 5 ns min
t14 0 ns min
t15 300 ns max

1

Guaranteed by design and characterization, not production tested.

2

Maximum SCLK frequency is 50 MHz at VDD = 2.7 V to 5.5 V.

to T

MIN

, T

MAX

, unless otherwise noted.1

MAX

to SCLK falling edge setup time

SYNC

SCLK falling edge to
Minimum
SYNC

SYNC

rising edge to SCLK fall ignore

SCLK falling edge to

pulse width low

LDAC

SCLK falling edge to

pulse width low

CLR
SCLK falling edge to

pulse activation time

CLR

SYNC

high time

SYNC

LDAC

LDAC

rising edge

fall ignore

rising edge

falling edge

TIMING DIAGRAM

Figure 2. Serial Write Operation

Rev. E | Page 7 of 32

AD5623R/AD5643R/AD5663R Data Sheet

θJA Thermal Impedance

142°C/W

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 6.

Parameter Rating

VDD to GND −0.3 V to +7 V
V

to GND −0.3 V to VDD + 0.3 V

OUT

V

REFIN/VREFOUT

Digital Input Voltage to GND −0.3 V to VDD + 0.3 V
Operating Temperature Range

Industrial −40°C to +105°C
Storage Temperature Range −65°C to +150°C
Junction Temperature (TJ max) 150°C

Power Dissipation (TJ max − TA)/θJA
LFCSP Package (4-Layer Board)

θJA Thermal Impedance 61°C/W
MSOP Package (4-Layer Board)

θJC Thermal Impedance 43.7°C/W
Reflow Soldering Peak Temperature

Pb-Free 260(+0/−5)°C

to GND −0.3 V to VDD + 0.3 V

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

Rev. E | Page 8 of 32

Data Sheet AD5623R/AD5643R/AD5663R

05858-003

1

V

OUT

A

10

V

REFIN

/V

REFOUT

2

V

OUT

B

9

V

DD

3

GND

8

DIN

4

LDAC

7

SCLK

5

CLR

6

SYNC

AD5623R/
AD5643R/

AD5663R

TOP VIEW

(Not to Scale)

NOTE:
EXPOSED PAD TIED TO GND ON
LFCSP PACKAG E .

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Figure 3. Pin Configuration

Table 7. Pin Function Descriptions

Pin No. Mnemonic Description

1 V
2 V

A Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.

OUT

B Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.

OUT

3 GND Ground. Reference point for all circuitry on the part.
4

Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new data.

LDAC

This allows simultaneous update of all DAC outputs. Alternatively, this pin can be tied permanently low.

5

CLR

Asynchronous Clear Input. The
ignored. When

is activated, zero scale is loaded to all input and DAC registers. This clears the output to 0 V.

CLR

input is falling edge sensitive. While

CLR

CLR

is low, all

The part exits clear code mode on the 24th falling edge of the next write to the part. If

pulses are

LDAC

is activated during

CLR

a write sequence, the write is aborted.

6

Level-Triggered Control Input (Active Low). This is the frame synchronization signal for the input data.

SYNC

When
following clocks. The DAC is updated following the 24th clock cycle unless
in which case the rising edge of

goes low, it enables the input shift register, and data is transferred in on the falling edges of the

SYNC

is taken high before this edge,

SYNC

acts as an interrupt and the write sequence is ignored by the DAC.

SYNC

7 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input.

Data can be transferred at rates up to 50 MHz.

8 DIN Serial Data Input. This device has a 24-bit shift register. Data is clocked into the register on the falling edge

of the serial clock input.

9 VDD Power Supply Input. These parts can be operated from 2.7 V to 5.5 V, and the supply should be decoupled with

a 10 μF capacitor in parallel with a 0.1 μF capacitor to GND.

10 V

REFIN/VREFOUT

Common Reference Input/Reference Output. When the internal reference is selected, this is the reference output

pin. When using an external reference, this is the reference input pin. The default for this pin is a reference input.

Rev. E | Page 9 of 32

AD5623R/AD5643R/AD5663R Data Sheet

CODE

INL ERROR ( LSB)

10

4

6

8

0

2

–6

–10

–8

–2
–4

0 5k 10k 15k 20k 25k 30k 35k 40k 45k 50k 55k 60k 65k

V

DD

= V

REF

= 5V

TA = 25°C

05858-005

CODE

INL ERROR ( LSB)

4

–4

0 2.5k 5.0k 7.5k 10.0k 12.5k 15.0k

–3

–2

–1

0

1

2

3

V

DD

= V

REF

= 5V

T

A

= 25°C

05858-006

CODE

INL ERROR ( LSB)

1.0

–1.0

0 0.5k 1.0k 1.5k 2.0k 2.5k 3.0k 3.5k 4.0k

–0.8

–0.6

–0.4

0

0.4

0.2

–0.2

0.6

0.8

V

DD

= V

REF

= 5V

T

A

= 25°C

05858-007

CODE

DNL ERROR (L S B)

1.0

0.6

0.4

0.2

0.8

0

–0.4

–0.2

–0.6

–1.0

–0.8

0 10k 20k 30k 40k 50k 60k

VDD = V

REF

= 5V

T

A

= 25°C

05858-008

DNL ERROR (L S B)

0.5

0.3

0.2

0.1

0.4

0

–0.2

–0.1

–0.3

–0.5

–0.4

VDD = V

REF

= 5V

T

A

= 25°C

CODE

0 2.5k 5.0k 7.5k 10.0k 12.5k 15.0k

05858-009

DNL ERROR (L S B)

0.20

0.10

0.05

0.15

0

–0.05

–0.10

–0.20

–0.15

CODE

0 0.5k 1.0k 1.5k 2.0k 2.5k 3.0k 3.5k 4.0k

VDD = V

REF

= 5V

T

A

= 25°C

05858-010

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 4. INL—AD5663R, External Reference

Figure 5. INL—AD5643R, External Reference

Figure 7. DNL—AD5663R, External Reference

Figure 8. DNL—AD5643R, External Reference

Figure 6. INL—AD5623R, External Reference

Figure 9. DNL—AD5623R, External Reference

Rev. E | Page 10 of 32

Data Sheet AD5623R/AD5643R/AD5663R

CODE

INL ERROR ( LSB)

10

8

0

–10

–6

–8

–4

6

–2

4

2

V

DD

= 5V

V

REFOUT

= 2.5V

T

A

= 25°C

05858-011

0 5k 10k 15k 20k 25k 30k 35k 40k 45k 50k 55k 60k 65k

CODE

INL ERROR ( LSB)

4

3

–4

–3

–2

2

–1

1

0

16250

15000

13750

12500

11250

10000

8750

7500

6250

5000

3750

2500

1250

0

VDD = 5V
V

REFOUT

= 2.5V

T

A

= 25°C

05858-012

CODE

INL ERROR ( LSB)

1.0

0.8

0

–1.0

–0.8

–0.6

0.6

–0.4

–0.2

0.4

0.2

0 1.0k0.5k 2.0k1.5k 3.5k3.0k2.5k 4.0k

VDD = 5V
V

REFOUT

= 2.5V

T

A

= 25°C

05858-013

CODE

DNL ERROR (L S B)

1.0

0.8

0

–1.0

–0.6

–0.8

–0.4

0.6

–0.2

0.4

0.2

65k60k55k50k45k40k35k30k25k20k15k10k5k0

V

DD

= 5V

V

REFOUT

= 2.5V

T

A

= 25°C

05858-014

CODE

DNL ERROR (L S B)

0.5

0.4

0

–0.5

–0.3

–0.4

–0.2

0.3

–0.1

0.2

0.1

16250

15000

13750

12500

11250

10000

8750

7500

6250

5000

3750

2500

1250

0

VDD = 5V
V

REFOUT

= 2.5V

T

A

= 25°C

05858-015

CODE

DNL ERROR (L S B)

0.20

0.15

0

–0.20

–0.15

–0.10

0.10

–0.05

0.05

0 1.0k0.5k 2.0k1.5k 3.5k3.0k2.5k 4.0k

VDD = 5V
V

REFOUT

= 2.5V

T

A

= 25°C

05858-016

Figure 10. INL—AD5663R-5

Figure 11. INL—AD5643R-5

Figure 13. DNL—AD5663R-5

Figure 14. DNL—AD5643R-5

Figure 12. INL—AD5623R-5

Figure 15. DNL—AD5623R-5

Rev. E | Page 11 of 32

AD5623R/AD5643R/AD5663R Data Sheet

CODE

INL ERROR ( LSB)

10

8

4

6

2

0

–4

–2

–6

–8

–10

05858-017

V

DD

= 3V

V

REFOUT

= 1.25V

T

A

= 25°C

0 5k 10k 15k 20k

25k 30k 35k 40k 45k 50k 55k 60k 65k

CODE

INL ERROR ( LSB)

4

–4

16250

15000

13750

12500

11250

10000

8750

7500

6250

5000

3750

2500

1250

0

3

2

1

0

–1

–2

–3

05858-018

VDD = 3V
V

REFOUT

= 1.25V

T

A

= 25°C

CODE

INL ERROR ( LSB)

1.0

–1.0

0 0.5k 1.0k 1.5k 2.0k 2.5k 3.0k 3.5k 4.0k

0

0.8

0.6

0.4

0.2

–0.2

–0.4

–0.6

–0.8

05858-019

VDD = 3V
V

REFOUT

= 1.25V

T

A

= 25°C

CODE

DNL ERROR (L S B)

1.0

0.8

0.4

0.6

0.2

0

–0.4

–0.2

–0.6

–0.8
–1.0

05858-020

V

DD

= 3V

V

REFOUT

= 1.25V

T

A

= 25°C

0 5k 10k 15k 20k 25k 30k

35k 40k 45k 50k 55k 60k

65k

CODE

DNL ERROR (L S B)

0.5

–0.5

16250

15000

13750

12500

11250

10000

8750

7500

6250

5000

3750

2500

1250

0

0

0.4

0.3

0.2

0.1

–0.1

–0.2

–0.3

–0.4

05858-021

VDD = 3V
V

REFOUT

= 1.25V

T

A

= 25°C

CODE

DNL ERROR (L S B)

0.20

–0.20

0 0.5k 1.0k 1.5k 2.0k 2.5k 3.0k 3.5k 4.0k

0

0.15

0.10

0.05

–0.05

–0.10

–0.15

05858-022

V

DD

= 3V

V

REFOUT

= 1.25V

T

A

= 25°C

Figure 16. INL—AD5663R-3

Figure 17. INL—AD5643R-3

Figure 19. DNL—AD5663R-3

Figure 20. DNL—AD5643R-3

Figure 18. INL—AD5623R-3

Figure 21. DNL—AD5623R-3

Rev. E | Page 12 of 32

Data Sheet AD5623R/AD5643R/AD5663R

TEMPERATURE (°C)

ERROR (LSB)

8

6

4

2

–6

–4

–2

0

–8

–40 –20 40200 1008060 120

05858-080

MIN DNL

MAX DNL

MAX INL

MIN INL

V

DD

= V

REF

= 5V

V

REF

(V)

ERROR (LSB)

10

4

6

8

2

0

–8

–6

–4

–2

–10

0.75 1.25 1.75 2.25 4.25

3.753.252.75 4.75

05858-081

MIN DNL

MAX DNL

MAX INL

MIN INL

V

DD

= 5V

T

A

= 25°C

VDD (V)

ERROR (LSB)

8

6

4

2

–6

–4

–2

0

–8

2.7 3.2 3.7 4.74.2 5.2

05858-082

MIN DNL

MAX DNL

MAX INL

MIN INL

T

A

= 25°C

TEMPERATURE (°C)

ERROR (% FSR)

0

–0.04

–0.02

–0.06

–0.08

–0.10

–0.18

–0.16

–0.14

–0.12

–0.20

–40 –20 40200 1008060

VDD = 5V

GAIN ERROR

FULL-S CALE ERROR

05858-023

TEMPERATURE (°C)

ERROR (mV)

1.5

1.0

0.5

0

–2.0

–1.5

–1.0

–0.5

–2.5

–40 –20

40200 8060 100

OFFSET ERROR

ZERO-SCALE ERROR

05858-024

VDD (V)

ERROR (% FSR)

1.0

–1.5

–1.0

–0.5

0

0.5

–2.0

2.7 3.2 3.7 4.74.2 5.2

GAIN ERROR

FULL-S CALE ERROR

05858-025

Figure 22. INL Error and DNL Error vs. Temperature

Figure 23. INL Error and DNL Error vs. V

REF

Figure 25. Gain Error and Full-Scale Error vs. Temperature

Figure 26. Zero-Scale Error and Offset Error vs. Temperature

Figure 24. INL Error and DNL Error vs. Supply

Figure 27. Gain Error and Full-Scale Error vs. Supply

Rev. E | Page 13 of 32

AD5623R/AD5643R/AD5663R Data Sheet

V

DD

(V)

ERROR (mV)

1.0

0.5

0

–2.0

–1.5

–1.0

–0.5

–2.5

2.7 3.2 4.23.7 5.24.7

ZERO-SCALE ERROR

OFFSET ERROR

T

A

= 25°C

05858-026

IDD (mA)

NUMBER OF UNI TS

8

6

4

2

0

0.230 0.235 0.240

0.245 0.250 0.255

VDD = 5.5V
T

A

= 25°C

05858-090

I

DD

(mA)

NUMBER OF UNI TS

4

5

3

2

1

0

0.78 0.80

0.82 0.84

V

DD

= 5.5V

T

A

= 25°C

05858-091

CURRENT (mA)

ERROR VOLTAGE (V)

0.5

0.4

–0.5

–0.4

–0.3

–0.2

–0.1

0

0.1

0.2

0.3

–10 –8 –6 –4 –2 0 2 4 86 10

V

DD

= 3V

V

REFOUT

= 1.25V

V

DD

= 5V

V

REFOUT

= 2.5V

DAC LOADED WITH
ZERO-SCALE
SINKING CURRE NT

DAC LOADED WITH
FULL-SCALE
SOURCING CURRE NT

05858-029

CURRENT (mA)

V

OUT

(V)

6

5

4

3

2

1

–1

0

–30 –20 –10 0 10 20 30

V

DD

= 5V

V

REFOUT

= 2.5V

T

A

= 25°C

ZERO SCAL E

FULL SCALE

MIDSCALE

1/4 SCALE

3/4 SCALE

05858-030

CURRENT (mA)

V

OUT

(V)

4

–1

0

1

2

3

–30 –20 –10 0 10 20 30

VDD= 3V
V

REFOUT

= 1.25V

T

A

= 25°C

ZERO SCAL E

FULL SCALE

MIDSCALE

1/4 SCALE

3/4 SCALE

05858-031

Figure 28. Zero-Scale Error and Offset Error vs. Supply

Figure 29. IDD Histogram with External Reference

Figure 31. Headroom at Rails vs. Source and Sink

Figure 32. AD56x3R-5 Source and Sink Capability

Figure 30. IDD Histogram with Internal Reference

Figure 33. AD56x3R-3 Source and Sink Capability

Rev. E | Page 14 of 32

Data Sheet AD5623R/AD5643R/AD5663R

TEMPERATURE (°C)

I

DD

(mA)

0.30

0.05

0.10

0.15

0.20

0.25

0

–40 –20 0 20 40 60 80 100

05858-044

T

A

= 25°C

V

DD

= V

REFIN

= 5V

V

DD

= V

REFIN

= 3V

TIME BASE = 4µs/DIV

V

DD

= V

REF

= 5V

T

A

= 25°C
FULL-S CALE CODE CHANGE
0x0000 TO 0xFF FF
OUTPUT LOADED WITH 2kΩ
AND 200pF TO GND

V

OUT

= 909mV/DIV

1

05858-060

CH1 2.0V CH2 500mV M100µs 125MS/s

A CH1 1.28V

8.0ns/pt

VDD = V

REF

= 5V

T

A

= 25°C

V

OUT

V

DD

1

2

MAX(C2)*

420.0mV

05858-061

VDD = 5V

SYNC

SLCK

V

OUT

1
3

CH1 5.0V
CH3 5.0V

CH2 500mV M400n s A CH1 1.4V

2

05858-062

SAMPLE NUMBER

V

OUT

(V)

2.521

2.522

2.523

2.524

2.525

2.526

2.527

2.528

2.529

2.530

2.531

2.532

2.533

2.534

2.535

2.536

2.537

2.538

0 50 100 150 350 400200 250 300 450 512

05858-058

V

DD

= V

REF

= 5V

T

A

= 25°C
5ns/SAMPLE NUMBER
GLITCH IMPULSE = 9.494nV
1LSB CHANGE ARO UND
MIDSCALE ( 0x8000 TO 0x7FFF )

SAMPLE NUMBER

V

OUT

(V)

2.491

2.492

2.493

2.494

2.495

2.496

2.497

2.498

0 50 100 150 350 400200 250 300 450 512

05858-059

VDD= V

REF

= 5V

T

A

= 25°C
5ns/SAMPLE NUMBER
ANALOG CRO S S TALK = 0.424nV

Figure 34. Supply Current vs. Temperature

Figure 35. Full-Scale Settling Time, 5 V

Figure 37. Exiting Power-Down to Midscale

Figure 38. Digital-to-Analog Glitch Impulse (Negative)

Figure 36. Power-On Reset to 0 V

Figure 39. Analog Crosstalk, External Reference

Rev. E | Page 15 of 32

AD5623R/AD5643R/AD5663R Data Sheet

SAMPLE NUMBER

V

OUT

(V)

2.456

2.458

2.460

2.462

2.464

2.466

2.468

2.470

2.472

2.474

2.476

2.478

2.480

2.482

2.484

2.486

2.488

2.490

2.492

2.494

2.496

0 50 100 150 350 400200 250 300 450 512

05858-057

V

DD

= 5V

V

REFOUT

= 2.5V

T

A

= 25°C
5ns/SAMPLE NUMBER
ANALOG CRO S S TALK = 4.462nV

1

Y AXIS = 2µV/DIV
X AXIS = 4s/DIV

VDD = V

REF

= 5V

T

A

= 25°C

DAC LOADED WITH MIDSCAL E

05858-063

5s/DIV

10µV/DIV

1

VDD = 5V
V

REFOUT

= 2.5V

T

A

= 25°C

DAC LOADED WITH MIDSCAL E

05858-064

4s/DIV

5µV/DIV

1

VDD = 3V
V

REFOUT

= 1.25V

T

A

= 25°C

DAC LOADED WITH MIDSCAL E

05858-065

FREQUENCY ( Hz )

OUTPUT NOISE (nV/√Hz)

800

0

100

200

300

400

500

600

700

100 10k1k 1M 10M

VDD= 3V
V

REFOUT

= 1.25V

V

DD

= 5V

V

REFOUT

= 2.5V

TA = 25°C
MIDSCALE LOADED

05858-066

FREQUENCY ( Hz )

(dB)

–20

–50

–80

–30

–40

–60

–70

–90

–100

2k 4k 6k 8k 10k

V

DD

= 5V

T

A

= 25°C
DAC LOADED WITH FULL S CALE
V

REF

= 2V ± 0.3V p- p

05858-067

Figure 40. Analog Crosstalk, Internal Reference

Figure 41. 0.1 Hz to 10 Hz Output Noise Plot, External Reference

Figure 43. 0.1 Hz to 10 Hz Output Noise Plot, Internal Reference

Figure 44. Noise Spectral Density, Internal Reference

Figure 42. 0.1 Hz to 10 Hz Output Noise Plot, Internal Reference

Figure 45. Total Harmonic Distortion

Rev. E | Page 16 of 32

Data Sheet AD5623R/AD5643R/AD5663R

CAPACITANCE (nF)

TIME (µs)

16

14

12

10

8

6

4

0 1 2 3 4 5 6 7 98 10

V

REF

= V

DD

T

A

= 25°C

V

DD

=

5V

V

DD

=

3V

05858-068

FREQUENCY ( Hz )

(dB)

5

–40

10k 100k 1M 10M

–35

–30

–25

–20

–15

–10

–5

0

05858-069

V

DD

= 5V

T

A

= 25°C

05858-050

V

OUT

A

V

OUT

B

3

CH3 5.0V CH4 1.0V

CH2 1.0V M200ns A CH3 1.10V

2

4

4

CLR

Figure 46. Settling Time vs. Capacitive Load

Figure 48.

CLR

Pulse Activation Time

Figure 47. Multiplying Bandwidth

Rev. E | Page 17 of 32

AD5623R/AD5643R/AD5663R Data Sheet

TERMINOLOGY

Relative Accuracy or Integral Nonlinearity (INL)

For the DAC, relative accuracy or integral nonlinearity is a
measurement of the maximum deviation, in LSBs, from a
straight line passing through the endpoints of the DAC transfer
function. A typical INL vs. code plot is shown in Figure 5.

Differential Nonlinearity (DNL)

Differential nonlinearity (DNL) is the difference between the
measured change and the ideal 1 LSB change between any two
adjacent codes. A specified differential nonlinearity of ±1 LSB
maximum ensures monotonicity. This DAC is guaranteed
monotonic by design. A typical DNL vs. code plot is shown in
Figure 9.

Zero-Scale Error

Zero-scale error is the measurement of the output error when
zero code (0x0000) is loaded to the DAC register. Ideally, the
output should be 0 V. The zero-scale error is always positive in
the AD56x3R because the output of the DAC cannot go below
0 V. It is due to a combination of the offset errors in the DAC
and the output amplifier. Zero-scale error is expressed in mV.
A plot of zero-scale error vs. temperature is shown in Figure 26.

Full-Scale Error

Full-scale error is the measurement of the output error when
full-scale code (0xFFFF) is loaded into the DAC register. Ideally,
the output should be V

− 1 LSB. Full-scale error is expressed

DD

in percent of full-scale range. A plot of full-scale error vs.
temperature is shown in Figure 25.

Gain Error

Gain error is a measure of the span error of the DAC. It is the
deviation in slope of the DAC transfer characteristic from ideal,
expressed as a percent of the full-scale range.

Zero-Scale Error Drift

Zero-scale error drift is the measurement of the change in zero­scale error with a change in temperature. It is expressed in
microvolts/°C (µV/°C).

DC Power Supply Rejection Ratio (PSRR)

PSRR indicates how the output of the DAC is affected by
changes in the supply voltage. PSRR is the ratio of the change in
VOUT to a change in VDD for full-scale output of the DAC. It
is measured in dB. VREF is held at 2 V, and VDD is varied by
±10%.

Output Voltage Settling Time

Output voltage settling time is the amount of time it takes for
the output of a DAC to settle to a specified level for a 1/4 to 3/4
full-scale input change and is measured from the 24th falling
edge of SCLK.

Digital-to-Analog Glitch Impulse

The impulse injected into the analog output when the input
code in the DAC register changes state. It is normally specified
as the area of the glitch in nV-s and is measured when the
digital input code is changed by 1 LSB at the major carry
transition (0x7FFF to 0x8000). See Figure 38.

Digital Feedthrough

A measure of the impulse injected into the analog output of the
DAC from the digital inputs of the DAC, digital feedthrough is
measured when the DAC output is not updated. It is specified
in nV-s, and it is measured with a full-scale code change on the
data bus, that is, from all 0s to all 1s and vice versa.

Reference Feedthrough

Reference feedthrough is the ratio of the amplitude of the signal
at the DAC output to the reference input when the DAC output
is not being updated (that is,

LDAC

is high). It is expressed in

decibels (dB).

Noise Spectral Density

Noise spectral density is a measurement of the internally
generated random noise. Random noise is characterized as a
spectral density (nV/√Hz). It is measured by loading the DAC
to midscale and measuring noise at the output. A plot of noise
spectral density is shown in Figure 44.

Gain Temperature Coefficient

Gain temperature coefficient is a measurement of the change in
gain error with changes in temperature. It is expressed in (ppm
of full-scale range)/°C.

Offset Error

Offset error is a measure of the difference between V
and V

(ideal) expressed in mV in the linear region of the

OUT

(actual)

OUT

transfer function. Offset error is measured on the AD56x3R
with code 512 loaded in the DAC register. It can be negative or
positive.

Rev. E | Page 18 of 32

DC Crosstalk

DC crosstalk is the dc change in the output level of one DAC in
response to a change in the output of another DAC. It is
measured with a full-scale output change on one DAC (or soft
power-down and power-up) while monitoring another DAC
kept at midscale. It is expressed in microvolts (μV).

DC crosstalk due to load current change is a measure of the
impact that a change in load current on one DAC has to
another DAC kept at midscale. It is expressed in microvolts/
milliamps (μV/mA).

Data Sheet AD5623R/AD5643R/AD5663R

Digital Crosstalk

Digital crosstalk is the glitch impulse transferred to the output
of one DAC at midscale in response to a full-scale code change
(all 0s to all 1s and vice versa) in the input register of another
DAC. It is measured in standalone mode and is expressed
in nanovolts-second (nV-s).

Analog Crosstalk

Analog crosstalk is the glitch impulse transferred to the output
of one DAC due to a change in the output of another DAC. It is
measured by loading one of the input registers with a full-scale
code change (all 0s to all 1s and vice versa) while keeping LDAC
high. Then pulse
whose digital code was not changed. The area of the glitch is
expressed in nanovolts-second (nV-s).

DAC-to-DAC Crosstalk

DAC-to-DAC crosstalk is the glitch impulse transferred to the
output of one DAC due to a digital code change and subsequent
output change of another DAC. This includes both digital and
analog crosstalk. It is measured by loading one of the DACs
with a full-scale code change (all 0s to all 1s and vice versa) with
LDAC

low and monitoring the output of another DAC. The

energy of the glitch is expressed in nanovolts-second (nV-s).

LDAC

low and monitor the output of the DAC

Multiplying Bandwidth

The amplifiers within the DAC have a finite bandwidth. The
multiplying bandwidth is a measure of this. A sine wave on the
reference (with full-scale code loaded to the DAC) appears on
the output. The multiplying bandwidth is the frequency at
which the output amplitude falls to 3 dB below the input.

Total Harmonic Distortion (THD)

Total harmonic distortion is the difference between an ideal
sine wave and its attenuated version using the DAC. The sine
wave is used as the reference for the DAC, and the THD is a
measurement of the harmonics present on the DAC output.
It is measured in decibels (dB).

Rev. E | Page 19 of 32

AD5623R/AD5643R/AD5663R Data Sheet

V

THEORY OF OPERATION

DIGITAL-TO-ANALOG SECTION

The AD5623R/AD5643R/AD5663R DAC is fabricated on
a CMOS process. The architecture consists of a string DAC
followed by an output buffer amplifier. Figure 49 shows a block
diagram of the DAC architecture.

DD

DAC

REGISTER

REF (+)

RESISTOR

STRING

REF (–)

GND

Figure 49. DAC Architecture

Because the input coding to the DAC is straight binary, the ideal
output voltage when using an external reference is given by

VV

REFIN

OUT

The ideal output voltage when using the internal reference is
given by

OUTPUT
AMPLIFIER
(GAIN = +2)

V

OUT

05858-032

D











N

2





INTERNAL REFERENCE

The AD5623R/AD5643R/AD5663R on-chip reference is off at
power-up and is enabled via a write to a control register. See the
Internal Reference Setup section for details.

R

R

R

R

R

Figure 50. Resistor String

TO OUTPUT
AMPLIFIER

5858-033

D





VV

2



REFOUTOUT





N

2





where:

D is the decimal equivalent of the binary code that is loaded to

the DAC register:

0 to 4095 for AD5623R (12-bit)
0 to 16,383 for AD5643R (14-bit)
0 to 65,535 for AD5663R (16-bit)

N is the DAC resolution.

RESISTOR STRING

The resistor string section is shown in Figure 50. It is simply a
string of resistors, each of Value R. The code loaded to the DAC
register determines at which node on the string the voltage is
tapped off to be fed into the output amplifier. The voltage is
tapped off by closing one of the switches connecting the string
to the amplifier. Because it is a string of resistors, it is guaranteed
monotonic.

OUTPUT AMPLIFIER

The output buffer amplifier can generate rail-to-rail voltages on
its output, which gives an output range of 0 V to V
a load of 2 kΩ in parallel with 1000 pF to GND. The source and
sink capabilities of the output amplifier can be seen in Figure 31.
The slew rate is 1.8 V/μs with a 1/4 to 3/4 full-scale settling time
of 10 μs.

. It can drive

DD

The AD56x3R-3 has a 1.25 V, 5 ppm/°C reference, giving a full­scale output of 2.5 V. The AD56x3R-5 has a 2.5 V, 5 ppm/°C
reference, giving a full-scale output of 5 V. The internal refer­ence associated with each part is available at the V

REFOUT

pin.
A buffer is required if the reference output is used to drive
external loads. When using the internal reference, it is
recommended that a 100 nF capacitor be placed between
reference output and GND for reference stability.

EXTERNAL REFERENCE

The V
the use of an external reference if the application requires it.
The on-chip reference is off at power-up, and this is the default
condition. The AD56x3R-3 and the AD56x3R-5 can be operated
from a single 2.7 V to 5.5 V supply.

pins on the AD56x3R-3 and the AD56x3R-5 allows

REFIN

SERIAL INTERFACE

The AD5623R/AD5643R/AD5663R have a 3-wire serial interface

SYNC

, SCLK, and DIN) that is compatible with SPI, QSPI, and

(
MICROWIRE interface standards, as well as with most DSPs.
See Figure 2 for a timing diagram of a typical write sequence.

The write sequence begins by bringing the
from the DIN line is clocked into the 24-bit shift register on the
falling edge of SCLK. The serial clock frequency can be as high
as 50 MHz, making the AD5623R/AD5643R/AD5663R compatible
with high speed DSPs. On the 24th falling clock edge, the last
data bit is clocked in and the programmed function is executed,
for example, a change in DAC register contents and/or a change
in the mode of operation.

SYNC

line low. Data

Rev. E | Page 20 of 32

Data Sheet AD5623R/AD5643R/AD5663R

X X C2 C1 C0 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

DB23 (MSB) DB0 (LSB)

COMMAND BITS ADDRESS BITS

DATA BITS

05858-034

X X C2 C1 C0 A2 A1 A0 X XD11 D10D13 D12 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

DB23 (MSB) DB0 (LSB)

COMMAND BITS

ADDRESS BITS

DATA BITS

05858-071

X X C2 C1 C0 A2 A1 A0 X X X XD11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

DB23 (MSB) DB0 (LSB)

COMMAND BITS ADDRESS BITS

DATA BITS

05858-072

DIN

DB23 DB23 DB0DB0

VALID WRI TE SEQUENCE , OUTPUT UP DATES

ON THE 24

TH

FALLING EDGE

SYNC

SCLK

INVALID W RITE SEQ UE NCE :

SYNC HIGH BEF ORE 24

TH

FALLING EDGE

05858-035

At this stage, the
In either case, it must be brought high for a minimum of 15 ns
before the next write sequence, so that a falling edge of
can initiate the next write sequence.

Because the
than it does when V
write sequences for even lower power operation. As mentioned
previously, it must, however, be brought high again just before

the next write sequence.

INPUT SHIFT REGISTER

The input shift register is 24 bits wide (see Figure 52). The first
two bits are don’t cares. The next three are Command Bit C2 to
Command Bit C0 (see Table 8), followed by the 3-bit DAC
Address A2 to DAC Address A0 (see Table 9), and, finally, the
16-, 14-, and 12-bit data-word.

The data-word comprises the 16-, 14-, and 12-bit input codes,
followed by zero, two, or four don’t care bits, for the AD5663R,
AD5643R, and AD5623R, respectively (see Figure 51, Figure 52,
and Figure 53). The data bits are transferred to the DAC register
on the 24th falling edge of SCLK.

SYNC

line can be kept low or be brought high.

SYNC

buffer draws more current when VIN = 2 V

= 0.8 V,

IN

SYNC

should be idled low between

SYNC

Table 8. Command Definition

C2 C1 C0 Command

0 0 0 Write to Input Register n
0 0 1 Update DAC Register n
0 1 0 Write to Input Register n, update all

(software

LDAC

)
0 1 1 Write to and update DAC Channel n
1 0 0 Power down DAC (power up)
1 0 1 Reset
1 1 0

register setup

LDAC

1 1 1 Internal reference setup (on/off)

Table 9. Address Command

A2 A1 A0 ADDRESS (n)

0 0 0 DAC A
0 0 1 DAC B
0 1 0 Reserved
0 1 1 Reserved
1 1 1 All DACs

SYNC

INTERRUPT

In a normal write sequence, the

SYNC

line is kept low for at
least 24 falling edges of SCLK, and the DAC is updated on the
24th falling edge. However, if

SYNC

is brought high before the
24th falling edge, this acts as an interrupt to the write sequence.
The shift register is reset, and the write sequence is seen as
invalid. Neither an update of the DAC register contents nor a
change in the operating mode occurs (see

Figure 54).

Figure 51. AD5663R Input Shift Register Contents

Figure 52. AD5643R Input Shift Register Contents

Figure 53. AD5623R Input Shift Register Contents

Figure 54.

SYNC

Interrupt Facility

Rev. E | Page 21 of 32

AD5623R/AD5643R/AD5663R Data Sheet

1 (Power-on Reset)

DAC register

RESISTOR
NETWORK

V

OUT

RESISTOR

STRING DAC

POWER-DOWN

CIRCUITRY

AMPLIFIER

05858-036

POWER-ON RESET

The AD5623R/AD5643R/AD5663R contain a power-on reset
circuit that controls the output voltage during power-up. The
AD5623R/AD5643R/AD5663R DACs output power up to 0 V,
and the output remains there until a valid write sequence is
made to the DACs. This is useful in applications where it is
important to know the state of the output of the DACs while
they are in the process of powering up. Any events on
CLR

during power-on reset are ignored.

LDAC

or

SOFTWARE RESET

The AD5623R/AD5643R/AD5663R contain a software reset
function. Command 101 is reserved for the software reset
function (see Table 8). The software reset command contains
two reset modes that are software-programmable by setting bit
DB0 in the control register. Table 10 shows how the state of the
bit corresponds to the mode of operation of the device. Table 12
shows the contents of the input shift register during the
software reset mode of operation.

Table 10. Software Reset Modes

DB0 Registers Reset to Zero

0 DAC register
Input register

Input register

Power-down register
Internal reference setup register

LDAC

register

Again, to select which combination of DAC channels to power
up, set the corresponding bits (Bit DB1 and Bit DB0) to 1. See
Tabl e 13 for contents of the input shift register during power­down/power-up operation.

The DAC output powers up to the value in the input register
while

LDAC

is low. If

LDAC

is high, the DAC ouput powers up

to the value held in the DAC register before power-down.

Table 11. Modes of Operation

DB5 DB4 Operating Mode

0 0 Normal operation
Power-down modes
0 1 1 kΩ to GND
1 0 100 kΩ to GND
1 1 Three-state

When both Bit DB1 and Bit DB2 are set to 0, the part works
normally, with its normal power consumption of 250 µA at 5 V.
However, for the three power-down modes, the supply current
falls to 480 nA at 5 V (200 nA at 3 V). Not only does the supply
current fall, but the output stage is also internally switched from
the output of the amplifier to a resistor network of known values.
This has the advantage that the output impedance of the part is
known while the part is in power-down mode. The outputs can
either be connected internally to GND through a 1 kΩ or 100 kΩ
resistor or left open-circuited (three-state) (see Figure 55).

POWER-DOWN MODES

The AD5623R/AD5643R/AD5663R contain four separate
modes of operation. Command 100 is reserved for the power­down function (see Tabl e 8). These modes are software­programmable by setting Bit DB5 and Bit DB4 in the control
register. Tabl e 11 shows how the state of the bits corresponds to
the mode of operation of the device. Any or all DACs (DAC B
and DAC A) can be powered down to the selected mode by
setting the corresponding two bits (Bit DB1 and Bit DB0) to 1.

By executing the same Command 100, any combination of DACs
can be powered up by setting Bit DB5 and Bit DB4 to normal

The bias generator, the output amplifier, the resistor string,
and other associated linear circuitry are shut down when
power-down mode is activated. However, the contents of the
DAC register are unaffected when in power-down. The time
to exit power-down is typically 4 µs for both VDD = 5 V and
VDD = 3 V (see Figure 37).

Figure 55. Output Stage During Power-Down

operation mode.

Table 12. 24-Bit Input Shift Register Contents for Software Reset Command

MSB LSB
DB23 to DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 to DB1 DB0

x 1 0 1 x x x x 1/0
Don’t care Command bits (C2 to C0) Address bits (A2 to A0) Don’t care Determines software reset mode

Rev. E | Page 22 of 32

Data Sheet AD5623R/AD5643R/AD5663R

x 1 1 0 x x x x DAC B

DAC A

Table 13. 24-Bit Input Shift Register Contents of Power Up/Down Function

MSB
DB23 to

DB22 DB21 DB20 DB19 DB18 DB17 DB16

x 1 0 0 x x x x PD1 PD0 x x DAC B DAC A
Don’t

care

Command bits (C2 to C0) Address bits (A2 to A0)

Don’t care

DB15 to
DB6 DB5 DB4 DB3 DB2 DB1 DB0

Don’t
care

Power-down
mode

Don’t care Power down/Power up

channel selection;
set bit to 1 to select
channel

LSB

Table 14. 24-Bit Input Shift Register Contents for

MSB LSB
DB23 to

DB22

Don’t care Command bits (C2 to C0) Address bits (A3 to A0)

DB21 DB20 DB19 DB110 DB17 DB16 DB15 to DB2 DB1 DB0

LDAC

Don’t care

Setup Command

Don’t care Set DAC to 0 or 1 for required

mode of operation

FUNCTION

LDAC

The AD5623R/AD5643R/AD5663R DACs have double­buffered interfaces consisting of two banks of registers: input
registers and DAC registers. The input registers are connected
directly to the input shift register, and the digital code is
transferred to the relevant input register on completion of a
valid write sequence. The DAC registers contain the digital code
used by the resistor strings.

Access to the DAC registers is controlled by the
When the

LDAC

pin is high, the DAC registers are latched and

LDAC

pin.

the input registers can change state without affecting the

LDAC

contents of the DAC registers. When

is brought low,
however, the DAC registers become transparent and the
contents of the input registers are transferred to them. The
double-buffered interface is useful if the user requires
simultaneous updating of all DAC outputs. The user can write
to one of the input registers individually and then, by bringing
LDAC

low when writing to the other DAC input register, all

outputs will update simultaneously.

These parts each contain an extra feature whereby a DAC
register is not updated unless its input register has been updated
since the last time

LDAC

was brought low. Normally, when

LDAC
is brought low, the DAC registers are filled with the contents of
the input registers. In the case of the AD5623R/AD5643R/

Asynchronous

The outputs are not updated at the same time that the input
registers are written to. When
registers are updated with the contents of the input register.

LDAC

The
the hardware
which combination of channels to simultaneously update when
the hardware
register to 0 for a DAC channel means that the update of this
channel is controlled by the
channel synchronously updates; that is, the DAC register is
updated after new data is read in, regardless of the state of the
LDAC

pin. It effectively sees the
See Table 15 for the
flexibility is useful in applications where the user wants to

simultaneously update select channels while the rest of the
channels are synchronously updating.

Writing to the DAC using Command 110 loads the 2-bit
register [DB1:DB0]. The default for each channel is 0; that is,

LDAC

the
DAC register is updated, regardless of the state of the
pin. See Table 14 for contents of the input shift register during

LDAC

the

LDAC

LDAC

goes low, the DAC

register gives the user full flexibility and control over

LDAC

pin. This register allows the user to select

LDAC

pin is executed. Setting the

LDAC

LDAC

LDAC

register mode of operation. This

pin. If this bit is set to 1, this

pin as being pulled low.

LDAC

bit

LDAC

pin works normally. Setting the bits to 1 means the

LDAC

register setup command.
AD5663R, the DAC register updates only if the input register
has changed since the last time the DAC register was updated,
thereby removing unnecessary digital crosstalk.

The outputs of all DACs can be simultaneously updated, using

LDAC

LDAC

pin.

the hardware

Synchronous

The DAC registers are updated after new data is read in on the

LDAC

falling edge of the 24th SCLK pulse.

can be permanently

low or pulsed as shown in Figure 2.

Table 15.

LDAC
(DB1 to DB0)

0 1/0 Determined by

1 x = don’t care The DAC registers are updated

Bits

LDAC

Register Mode of Operation

Pin

LDAC

Operation

LDAC

pin

LDAC

after new data is read in on the
falling edge of the 24th SCLK
pulse.

Rev. E | Page 23 of 32

AD5623R/AD5643R/AD5663R Data Sheet

Don’t care

Command bits (C2 to C0)

Address bits (A2 to A0)

Don’t care

Reference

INTERNAL REFERENCE SETUP

The on-chip reference is off at power-up by default. This
reference can be turned on or off by setting a software
programmable bit, DB0, in the control register. Table 16 shows
how the state of the bit corresponds to the mode of operation.
Command 111 is reserved for setting up the internal reference
(see Tabl e 8). See Table 16 for the contents of the input shift
register during the internal reference setup command.

Table 17. 32-Bit Input Shift Register Contents for Reference Setup Function

MSB
DB23 to DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 to DB1 DB0

x 1 1 1 x x x x 1/0

Table 16. Reference Setup Register

Internal Reference
Setup Register (DB0)

0 Reference off (default)
1 Reference on

Action

setup register

LSB

Rev. E | Page 24 of 32

Data Sheet AD5623R/AD5643R/AD5663R

AD5643R/
AD5663R

1

ADSP-BF53x

1

SYNC

TFS0

DIN

DTOPRI

SCLK

TSCLK0

1

ADDITIONAL PINS OMITTED FOR CLARITY.

05858-037

AD5643R/

AD5663R

1

68HC11/68L11

1

SYNC

PC7

SCLK

SCK

DINMOSI

1

ADDITIONAL PINS OMITTED FOR CLARITY.

05858-038

AD5643R/
AD5663R

1

80C51/80L51

1

SYNC

P3.3

SCLK

TxD

DIN

RxD

1

ADDITIONAL PINS OMITTED FOR CLARITY.

05858-039

AD5643R/
AD5663R

1

MICROWIRE

1

SYNC

CS

SCLKSK

DINSO

1

ADDITIONAL PINS OMITTED FOR CLARITY.

05858-040

MICROPROCESSOR INTERFACING

AD5623R/AD5643R/AD5663R to Blackfin® ADSP-BF53X Interface

Figure 56 shows a serial interface between the AD5623R/
AD5643R/AD5663R and the Blackfin ADSP-BF53X micro-
processor. The ADSP-BF53X processor family incorporates two
dual-channel synchronous serial ports, SPORT1 and SPORT0,
for serial and multiprocessor communications. Using SPORT0
to connect to the AD5623R/AD5643R/AD5663R, the setup for
the interface is as follows: DT0PRI drives the DIN pin of the
AD5623R/AD5643R/AD5663R, while TSCLK0 drives the
SCLK of the parts. The

Figure 56. AD5623R/AD5643R/AD5663R to Blackfin ADSP-BF53X Interface

SYNC

is driven from TFS0.

transferred, and a second serial write operation is performed to
the DAC. PC7 is taken high at the end of this procedure.

AD5623R/AD5643R/AD5663R to 80C51/80L51 Interface

Figure 58 shows a serial interface between the AD5623R/
AD5643R/AD5663R and the 80C51/80L51 microcontroller.
The setup for the interface is as follows: TxD of the 80C51/
80L51 drives SCLK of the AD5623R/AD5643R/AD5663R,
and RxD drives the serial data line of the part. The

SYNC

signal
is again derived from a bit-programmable pin on the port. In this
case, Port Line P3.3 is used. When data is to be transmitted to the
AD5623R/AD5643R/AD5663R, P3.3 is taken low. The 80C51/
80L51 transmit data in 8-bit bytes only; thus, only eight falling
clock edges occur in the transmit cycle. To load data to the
DAC, P3.3 is left low after the first eight bits are transmitted,
and a second write cycle is initiated to transmit the second byte
of data. P3.3 is taken high following the completion of this cycle.

The 80C51/80L51 output the serial data in a format that has the
LSB first. The AD5623R/AD5643R/AD5663R must receive data
with the MSB first. The 80C51/80L51 transmit routine should
take this into account.

AD5623R/AD5643R/AD5663R to 68HC11/68L11 Interface

Figure 57 shows a serial interface between the AD5623R/
AD5643R/AD5663R and the 68HC11/68L11 microcontroller.
SCK of the 68HC11/68L11 drives the SCLK of the AD5623R/
AD5643R/AD5663R, and the MOSI output drives the serial
data line of the DAC.

Figure 57. AD5623R/AD5643R/AD5663R to 68HC11/68L11 Interface

SYNC

The

signal is derived from a port line (PC7). The setup
conditions for correct operation of this interface are as follows:
the 68HC11/68L11 is configured with its CPOL bit as 0, and its
CPHA bit as 1. When data is being transmitted to the DAC, the
SYNC

line is taken low (PC7). When the 68HC11/68L11 is
configured as described previously, data appearing on the MOSI
output is valid on the falling edge of SCK. Serial data from the
68HC11/68L11 is transmitted in 8-bit bytes with only eight
falling clock edges occurring in the transmit cycle.

Data is transmitted MSB first. To load data to the AD5623R/
AD5643R/AD5663R, PC7 is left low after the first eight bits are

Figure 58. AD5623R/AD5643R/AD5663R to 80C512/80L51 Interface

AD5623R/AD5643R/AD5663R to MICROWIRE Interface

Figure 59 shows an interface between the AD5623R/AD5643R/
AD5663R and any MICROWIRE-compatible device. Serial data is
shifted out on the falling edge of the serial clock and is clocked into
the AD5623R/AD5643R/AD5663R on the rising edge of the SK.

Figure 59. AD5623R/AD5643R/AD5663R to MICROWIRE Interface

Rev. E | Page 25 of 32

AD5623R/AD5643R/AD5663R Data Sheet

AD5623R/
AD5643R/

AD5663R

THREE-WIRE

SERIAL

INTERFACE

SYNC

SCLK

DIN

15V

5V

V

OUT

= 0V TO 5V

V

DD

REF195

05858-041




















×−










+

×











×=

R1

R2

V

R1

R2R1D

VV

DDDD

O

536,65

V5

536,65

10

−











×=D

V

O

THREE-WIRE

SERIAL

INTERFACE

R2 = 10kΩ

+5V

–5V

AD820/

OP295

+5V

AD5663R

V

DD

V

OUT

R1 = 10kΩ

±5V

0.1µF10µF

05858-042

0.1µF

5V

REGULATOR

GND

DIN

SYNC

SCLK

POWER

10µF

SDI

SCLK

DATA

AD5663R

V

OUT

V

OB

V

OA

V

OC

V

DD

V

IC

V

IB

V

IA

ADuM1300

05858-043

APPLICATIONS INFORMATION

USING A REFERENCE AS A POWER SUPPLY

Because the supply current required by the AD5623R/AD5643R/
AD5663R is extremely low, an alternative option is to use a
voltage reference to supply the required voltage to the parts (see
Figure 60). This is especially useful if the power supply is quite
noisy or if the system supply voltages are at some value other
than 5 V or 3 V, for example, 15 V. The voltage reference outputs
a steady supply voltage for the AD5623R/AD5643R/ AD5663R.
If the low dropout REF195 is used, it must supply 500 µA of
current to the AD5623R/AD5643R/AD5663R, with no load on
the output of the DAC. When the DAC output is loaded, the
REF195 also needs to supply the current to the load. The total
current required (with a 5 kΩ load on the DAC output) is

500 µA + (5 V/5 kΩ) = 1.25 mA

The load regulation of the REF195 is typically 2 ppm/mA,
which results in a 3 ppm (15 µV) error for the 1.5 mA current
drawn from it. This corresponds to a 0.196 LSB error.

Figure 60. REF195 as Power Supply to the AD5623R/AD5643R/AD5663R

This is an output voltage range of ±5 V, with 0x0000 corre­sponding to a −5 V output, and 0xFFFF corresponding to a
+5 V output.

Figure 61. Bipolar Operation with the AD5663R

USING THE AD5663R WITH A GALVANICALLY ISOLATED INTERFACE

In process control applications in industrial environments,
it is often necessary to use a galvanically isolated interface to
protect and isolate the controlling circuitry from any hazardous
common-mode voltages that can occur in the area where
the DAC is functioning. iCoupler® provides isolation in excess
of 2.5 kV. The AD5663R uses a 3-wire serial logic interface, so
the ADuM1300 3-channel digital isolator provides the required
isolation (see Figure 62). The power supply to the part also
needs to be isolated, which is done by using a transformer. On
the DAC side of the transformer, a 5 V regulator provides the
5 V supply required for the AD5663R.

BIPOLAR OPERATION USING THE AD5663R

The AD5663R has been designed for single-supply operation,
but a bipolar output range is also possible using the circuit in
Figure 61. The circuit gives an output voltage range of ±5 V.
Rail-to-rail operation at the amplifier output is achievable using
an AD820 or an OP295 as the output amplifier.

The output voltage for any input code can be calculated as
follows:

where D represents the input code in decimal (0 to 65,535).
With V

= 5 V, R1 = R2 = 10 kΩ,

DD

Rev. E | Page 26 of 32

Figure 62. AD5663R with a Galvanically Isolated Interface

Data Sheet AD5623R/AD5643R/AD5663R

POWER SUPPLY BYPASSING AND GROUNDING

When accuracy is important in a circuit, it is helpful to carefully
consider the power supply and ground return layout on the
board. The printed circuit board containing the AD5663R
should have separate analog and digital sections, each having its
own area of the board.

If the AD5663R is in a system where other devices require an
AGND-to-DGND connection, the connection should be made at
one point only. This ground point should be as close as possible
to the AD5663R.

The power supply to the AD5663R should be bypassed with
10 µF and 0.1 µF capacitors. The capacitors should be located as
close as possible to the device, with the 0.1 µF capacitor ideally
right up against the device. The 10 µF capacitors are the
tantalum bead type. It is important that the 0.1 µF capacitor
have low effective series resistance (ESR) and effective series
inductance (ESI), which is found, for example, in common
ceramic types of capacitors.

This 0.1 µF capacitor provides a low impedance path to ground
for high frequencies caused by transient currents due to internal
logic switching.

The power supply line itself should have as large a trace as
possible to provide a low impedance path and to reduce glitch
effects on the supply line. Clocks and other fast switching
digital signals should be shielded from other parts of the board
by digital ground. Avoid crossover of digital and analog signals,
if possible. When traces cross on opposite sides of the board,
ensure that they run at right angles to each other to reduce
feedthrough effects through the board. The best board layout
technique is the microstrip technique, where the component
side of the board is dedicated to the ground plane only and the
signal traces are placed on the solder side. However, this is not
always possible with a 2-layer board.

Rev. E | Page 27 of 32

AD5623R/AD5643R/AD5663R Data Sheet

2.48

2.38

2.23

0.50

0.40

0.30

TOP VIEW

10

1

6

5

0.30

0.25

0.20

BOTTOM VIEW

PIN 1 INDEX

AREA

SEATING

PLANE

0.80

0.75

0.70

1.74

1.64

1.49

0.20 REF

0.05 MAX

0.02 NOM

0.50 BSC

EXPOSED

PAD

3.10

3.00 SQ

2.90

PIN 1
INDICATOR
(R 0.15)

FOR PROP E R CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CO NFIGURATI ON AND
FUNCTIO N DE S CRIPTIONS
SECTION OF THIS DATA SHEET.

COPLANARITY

0.08

02-27-2012-B

COMPLIANT TO JEDEC STANDARDS MO-187-BA

091709-A

6°
0°

0.70

0.55

0.40

5

10

1

6

0.50 BSC

0.30

0.15

1.10 MAX

3.10

3.00

2.90

CO

PLANARITY

0.10

0.23

0.13

3.10

3.00

2.90

5.

15

4.90

4.65

PIN 1

IDENTIFIER

15° MAX

0.95

0.85

0.75

0.15

0.05

OUTLINE DIMENSIONS

Figure 63. 10-Lead Lead Frame Chip Scale Package [LFCSP_WD]

3 mm x 3 mm Body, Very Very Thin, Dual Lead

(CP-10-9)

Dimensions shown in millimeters

Figure 64. 10-Lead Mini Small Outline Package [MSOP]

(RM-10)

Dimensions shown in millimeters

Rev. E | Page 28 of 32

Data Sheet AD5623R/AD5643R/AD5663R

Internal

Package

AD5623RARMZ-5

−40°C to +105°C

±2 LSB INL

2.5V

10-Lead MSOP

RM-10

DKP

AD5663RBCPZ-5REEL7

−40°C to +105°C

±16 LSB INL

2.5 V

10-Lead LFCSP_WD

CP-10-9

D7H

ORDERING GUIDE

Model1 Temperature Range Accuracy

AD5623RBCPZ-3R2 −40°C to +105°C ±1 LSB INL 1.25 V 10-Lead LFCSP_WD CP-10-9 D85
AD5623RBCPZ-3REEL7 −40°C to +105°C ±1 LSB INL 1.25 V 10-Lead LFCSP_WD CP-10-9 D85
AD5623RBCPZ-5REEL7 −40°C to +105°C ±1 LSB INL 2.5 V 10-Lead LFCSP_WD CP-10-9 D86
AD5623RBRMZ-3 −40°C to +105°C ±1 LSB INL 1.25 V 10-Lead MSOP RM-10 D85
AD5623RBRMZ-3REEL7 −40°C to +105°C ±1 LSB INL 1.25 V 10-Lead MSOP RM-10 D85
AD5623RBRMZ-5 −40°C to +105°C ±1 LSB INL 2.5 V 10-Lead MSOP RM-10 D86
AD5623RBRMZ-5REEL7 −40°C to +105°C ±1 LSB INL 2.5 V 10-Lead MSOP RM-10 D86
AD5623RACPZ-5REEL7 −40°C to +105°C ±2 LSB INL 2.5 V 10-Lead LFCSP_WD CP-10-9 DKB
AD5623RARMZ-5REEL7 −40°C to +105°C ±2 LSB INL 2.5V 10-Lead MSOP RM-10 DKP

AD5643RBRMZ-3 −40°C to +105°C ±4 LSB INL 1.25 V 10-Lead MSOP RM-10 D81
AD5643RBRMZ-3REEL7 −40°C to +105°C ±4 LSB INL 1.25 V 10-Lead MSOP RM-10 D81
AD5643RBRMZ-5 −40°C to +105°C ±4 LSB INL 2.5 V 10-Lead MSOP RM-10 D7Q
AD5643RBRMZ-5REEL7 −40°C to +105°C ±4 LSB INL 2.5 V 10-Lead MSOP RM-10 D7Q
AD5663RBCPZ-3R2 −40°C to +105°C ±16 LSB INL 1.25 V 10-Lead LFCSP_WD CP-10-9 D7S
AD5663RBCPZ-3REEL7 −40°C to +105°C ±16 LSB INL 1.25 V 10-Lead LFCSP_WD CP-10-9 D7S

AD5663RBRMZ-3 −40°C to +105°C ±16 LSB INL 1.25 V 10-Lead MSOP RM-10 D7S
AD5663RBRMZ-3REEL7 −40°C to +105°C ±16 LSB INL 1.25 V 10-Lead MSOP RM-10 D7S
AD5663RBRMZ-5 −40°C to +105°C ±16 LSB INL 2.5 V 10-Lead MSOP RM-10 D7H
AD5663RBRMZ-5REEL7 −40°C to +105°C ±16 LSB INL 2.5 V 10-Lead MSOP RM-10 D7H
EVAL-AD5663REBZ Evaluation Board

1

Z = RoHS Compliant Part.

Reference

Package Description

Option

Branding

Rev. E | Page 29 of 32

AD5623R/AD5643R/AD5663R Data Sheet

NOTES

Rev. E | Page 30 of 32

Data Sheet AD5623R/AD5643R/AD5663R

NOTES

Rev. E | Page 31 of 32

AD5623R/AD5643R/AD5663R Data Sheet

©2006–2012 Analog Devices, Inc. All rights reserved. Trademarks and

NOTES

registered trademarks are the property of their respective owners.
D05858-0-4/12(E)

Rev. E | Page 32 of 32