Datasheet AD5620 Datasheet (Analog Devices)

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Page 1

3 V/5 V, 12/14-Bit

10 ppm/°C Max On-Chip Reference in SOT-23

nano

DACTM D/A with

Preliminary Technical Data

FEATURES

AD5620: low power single 12-bit nanoDAC AD5640: low power single 16-bit nanoDAC

12-bit accuracy guaranteed On-chip 1.25 V/2.5 V, 10 ppm/°C reference Tiny 8-lead SOT-23/MSOP package Power-down to 200 nA @ 5 V, 50 nA @ 3 V 3 V/5 V single power supply Guaranteed 16-bit monotonic by design Power-on reset to zero/midscale 3 power-down functions Serial interface with Schmitt-triggered inputs Rail-to-rail operation SYNC interrupt facility

APPLICATIONS

Process control Data acquisition systems Portable battery-powered instruments Digital gain and offset adjustment Programmable voltage and current sources Programmable attenuators

GENERAL DESCRIPTION

The AD5620/40 parts are a member of the nanoDAC family of devices. They are low power, single, 12-/14-bit buffered voltageout DACs, guaranteed monotonic by design. The AD5620/40x-1 operate from a 3 V single supply featuring an internal reference of 1.25 V and an internal gain of 2. The AD5620/40x-2/3 operate from a 5 V single supply featuring an internal reference of 2.5 V and an internal gain of 2. Each reference has a 10 ppm/°C max temperature coefficient. The reference associated with each part is available at the REFOUT pin.

The part incorporates a power-on reset circuit, which ensures that the DAC output powers up to 0 V (AD5620/40x-1/2) or to midscale (AD5620/40x-3) and remains there until a valid write takes place. The part contains a power-down feature that reduces the current consumption of the device to 200 nA at 5 V and provides software selectable output loads while in power-down mode.

The AD5620/40 uses a versatile 3-wire serial interface that operates at clock rates up to 30 MHz and is compatible with standard SPI™, QSPI™, MICROWIRE™, and DSP interface standards. Its on-chip precision output amplifier allows rail-torail output swing to be achieved.

Rev. PrA

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

AD5620/AD5640

FUNCTIONAL BLOCK DIAGRAM

REFOUT

POWER-ON

RESET

DAC

INPUT

CONTROL

LOGIC

SYNC SCLK DIN

1.25/2.5V REF

REF(+)

DAC

POWER-DOWN

CONTROL LOGIC

The low power consumption of this part in normal operation makes it ideally suited to portable battery-operated equipment. The power consumption is 0.7 mW at 5 V, reducing to 1 µW in power-down mode.

The AD5620/40 is designed with new technology and is the next generation to the AD53xx family.

RELATED DEVICES

Part No. Description

AD5660 3 V/5 V 16-bit DAC in SOT-23, internal reference AD5662 2.7 V to 5.5 V 16-bit DAC in SOT-23, external reference

PRODUCT HIGHLIGHTS

1. 16-bit DAC; 12-bit accuracy guaranteed.

2. On-chip 1.25 V/2.5 V, 10 ppm/°C max reference.

3. Available in 8-lead SOT-23 and 8-lead MSOP packages.

4. Power-on reset to 0 V or midscale.

5. Power-down capability. When powered down, the DAC

typically consumes 50 nA at 3 V and 200 nA at 5 V.

6. 10 µS settling time.

www.analog.com

GND

Figure 1.

AD5620/AD5640

OUTPUT BUFFER

RESISTOR NETWORK

OUT

04781-0-001

Page 2

AD5620/AD5640 Preliminary Technical Data

TABLE OF CONTENTS

AD5620/40x-2/3–Specifications..................................................... 3

Typical Perfor m a n c e C haracter i st ics ........................................... 11

AD5620/40x-1–Specifications ........................................................ 5

Timing Characteristics..................................................................... 7

Pin Configuration and Function Descriptions............................. 8

Absolute Maximum Ratings............................................................ 9

ESD Caution.................................................................................. 9

Te r mi n ol o g y .................................................................................... 10

REVISION HISTORY

10/04—Revision 0: PrA

Theory of Operation ...................................................................... 14

Serial Interface............................................................................ 14

Microprocessor Interfacing....................................................... 16

Outline Dimensions ....................................................................... 17

Ordering Guide .......................................................................... 17

Rev. PrA | Page 2 of 20

Page 3

Preliminary Technical Data AD5620/AD5640

AD5620/40X-2/3–SPECIFICATIONS

VDD = +4.5 V to +5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications T

Table 1.

Parameter A Grade B Grade C Grade Unit

STATIC PERFORMANCE

AD5620

Resolution 12 12 12 Bits min Relative Accuracy ±6 ±1 ±1 LSB max See Figure 4. Differential Nonlinearity ±1 ±1 ±1 LSB max Guaranteed monotonic by design. See Figure 5.

AD5640

Resolution 14 14 14 Bits min Relative Accuracy ±8 ±4 ±4 LSB max See Figure 4.

Differential Nonlinearity ±1 ±1 ±1 LSB max Guaranteed monotonic by design. See Figure 5. Zero Code Error +5 +5 +5 mV typ All 0s loaded to DAC register. +20 +20 +20 mV max Offset Error ±10 ±10 ±10 mV typ Full-Scale Error −0.15 −0.15 −0.15 % of FSR typ All 1s loaded to DAC register.

−1.25 −1.25 −1.25 % of FSR max Gain Error ±1.25 ±1.25 ±1.25 % of FSR max Zero Code Error Drift

±2 ±2 ±2 µV/°C typ Gain Temperature Coefficient ±2.5 ±2.5 ±2.5 ppm typ Of FSR/°C DC Power Supply Rejection Ratio −100 −100 −100 dB typ DAC code = midscale; VDD = 5 V ±10%

OUTPUT CHARACTERISTICS3

Output Voltage Range 0 0 V min V

V max Output Voltage Settling Time 8 8 8 µs typ To ±0.003% FSR 0x0200 to 0xFD00 10 10 10 µs max RL = 2 kΩ; 0 pF < CL < 200 pF 12 12 12 µs typ RL = 2 kΩ; CL = 500 pF Slew Rate 1 1 1 V/µs typ Capacitive Load Stability 2 2 2 nF typ RL = ∞ 10 10 10 nF typ RL = 2 kΩ Output Noise Spectral Density 80 80 80 nV/√Hz typ DAC code = midscale, 10kHz Output Noise (0.1 Hz to 10 Hz) 10 10 10 µVp-p typ DAC code = midscale THD, Total Harmonic Distortion −80 −80 −80 dB typ V Output Drift ppm/°C typ Digital-to-Analog Glitch Impulse 5 5 5 nV-s typ 1 LSB change around major carry. Digital Feedthrough 0.1 0.1 0.1 nV-s typ DC Output Impedance 0.5 0.5 0.5 Ω typ Short Circuit Current 30 30 30 mA typ VDD = 5 V Power-Up Time 4 4 4

µs typ

REFERENCE OUTPUT

Output Voltage AD5620/40x-2/3 2.495 2.495 2.495 V min

2.505 2.505 2.505 V max Reference TC ±25 ±25 ±10 ppm/°C max

LOGIC INPUTS3

Input Current ±1 ±1 ±1 µA max

Temperature ranges are as follows: B Version: -40°C to +105°C, typical at 25°C.

Linearity calculated using a reduced code range of 512 to 65024. Output unloaded.

Guaranteed by design and characterization, not production tested.

MIN

to T

, unless otherwise noted.

MAX

B Version

Conditions/Comments

= 2 V ± 300 mV p-p, f = 5 kHz

REF

Coming out of power-down mode. VDD = 5 V

Rev. PrA | Page 3 of 20

Page 4

AD5620/AD5640 Preliminary Technical Data

Parameter A Grade B Grade C Grade Unit

, Input Low Voltage 0.8 0.8 0.8 V max VDD = 5 V

INL

, Input High Voltage 2 2 2 V min VDD = 5 V

INH

B Version Conditions/Comments

Pin Capacitance 3 3 3 pF max

POWER REQUIREMENTS

4.5 4.5 4.5 V min All digital inputs at 0 V or V

IDD (Normal Mode) 5.5 5.5 5.5 V max DAC active and excluding load current VDD = 4.5 V to 5.5 V 0.5 0.5 0.5 mA typ VIH = VDD and VIL = GND VDD = 4.5 V to 5.5 V 1 1 1 mA max VIH = VDD and VIL = GND IDD (All Power-Down Modes) VDD = 4.5 V to 5.5 V 0.2 0.2 0.2 µA typ VIH = VDD and VIL = GND VDD = 4.5 V to 5.5 V 1 1 1 µA max VIH = VDD and VIL = GND

POWER EFFICIENCY

OUT/IDD

89 89 89 % I

= 2 mA, VDD = 5 V

LOAD

Rev. PrA | Page 4 of 20

Page 5

Preliminary Technical Data AD5620/AD5640

AD5620/40X-1–SPECIFICATIONS

VDD = 2.7 V to 3.6 V; RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications T

Table 2.

Parameter A Grade B Grade C Grade Unit

STATIC PERFORMANCE

AD5620

Resolution 12 12 12 Bits min Relative Accuracy ±6 ±1 ±1 LSB max See Figure 4. Differential Nonlinearity ±1 ±1 ±1 LSB max Guaranteed monotonic by design. See Figure 5.

AD5640

Resolution 14 14 14 Bits min Relative Accuracy ±8 ±4 ±4 LSB max See Figure 4.

Differential Nonlinearity ±1 ±1 ±1 LSB max Guaranteed monotonic by design. See Figure 5. Zero Code Error +5 +5 +5 mV typ All 0s loaded to DAC register +20 +20 +20 mV max Offset Error ±10 ±10 ±10 mV typ Full-Scale Error −0.15 −0.15 −0.15 % of FSR typ All 1s loaded to DAC register.

−1.25 −1.25 −1.25 % of FSR max Gain Error ±1.25 ±1.25 ±1.25 % of FSR max Zero Code Error Drift

±20 ±20 ±20 µV/°C typ Gain Temperature Coefficient ±5 ±5 ±5 ppm typ Of FSR/°C DC Power Supply Rejection Ratio −100 −100 −100 dB typ DAC code = midscale; VDD = 3 V ±10%

OUTPUT CHARACTERISTICS3

Output Voltage Range 0 0 V min V

V max Output Voltage Settling Time 8 8 8 µs typ To ±0.003% FSR 0200H to FD00 10 10 10 µs max RL = 2 kΩ; 0 pF < CL < 200 pF. 12 12 12 µs typ RL = 2 kΩ; CL = 500 pF Slew Rate 1 1 1 V/µs typ Capacitive Load Stability 2 2 2 nF typ RL = ∞ 10 10 10 nF typ RL = 2 kΩ Output Noise Spectral Density 80 80 80 nV/√Hz typ DAC code = midscale, 10 kHz Output Noise (0.1 Hz to 10 Hz) 10 10 10 µVp-p typ DAC code = midscale THD, Total Harmonic Distortion −80 −80 −80 dB typ V Output Drift tbd ppm/°C typ Digital-to-Analog Glitch Impulse 5 5 5 nV-s typ 1 LSB change around major carry. Digital Feedthrough 0.1 0.1 0.1 nV-s typ DC Output Impedance 0.5 0.5 0.5

Ω typ Short Circuit Current 30 30 30 mA typ VDD = 3 V Power-Up Time 10 10 10

µs typ

REFERENCE OUTPUT

Output Voltage AD5620/40x-1 1.248 1.248 1.248 V min

1.252 1.252 1.252 V max Reference TC ±25 ±25 ±10 ppm/°C max

Temperature ranges are as follows: B Version: -40°C to +105°C, typical at 25°C.

Linearity calculated using a reduced code range of 485 to 64714. Output unloaded.

Guaranteed by design and characterization, not production tested.

MIN

to T

, unless otherwise noted.

MAX

B Version

Conditions/Comments

= 2 V ± 300 mV p-p, f = 5 kHz

REF

Coming out of power-down mode. VDD = 3 V

Rev. PrA | Page 5 of 20

Page 6

AD5620/AD5640 Preliminary Technical Data

Parameter A Grade B Grade C Grade Unit

B Version Conditions/Comments

LOGIC INPUTS3 Input Current ±1 ±1 ±1 µA max V

, Input Low Voltage 0.8 0.8 0.8 V max VDD = 3 V

INL

, Input High Voltage 2 2 2 V min VDD = 3 V

INH

Pin Capacitance 3 3 3 pF max

POWER REQUIREMENTS

2.7 2.7 2.7 V min All digital inputs at 0 V or V

IDD (Normal Mode) 3.6 3.6 3.6 V max DAC active and excluding load current VDD = 2.7 V to 3.6 V 0.5 0.5 0.5 mA typ VIH = VDD and VIL = GND VDD = 2.7 V to 3.6 V 1 1 1 mA max VIH = VDD and VIL = GND IDD (All Power-Down Modes) VDD = 2.7 V to 3.6 V 0.2 0.2 0.2 µA typ VIH = VDD and VIL = GND VDD = 2.7 V to 3.6 V 1 1 1 µA max VIH = VDD and VIL = GND

POWER EFFICIENCY

OUT/IDD

= 2 mA, VDD = 3 V

LOAD

Rev. PrA | Page 6 of 20

Page 7

Preliminary Technical Data AD5620/AD5640

TIMING CHARACTERISTICS

All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 2. V

= 2.7 V to 5.5 V; all specifications T

Table 3.

Limit at T

Parameter V

= 2.7 V to 3.6 V VDD = 3.6 V to 5.5 V Unit Conditions/Comments

t1 7 50 33 ns min SCLK cycle time t2 13 13 ns min SCLK high time

t3 13 13 ns min SCLK low time t4 0 0 ns min t5 5 5 ns min Data setup time t6 4.5 4.5 ns min Data hold time t7 0 0 ns min t8 50 33 ns min t9 13 13 ns min t10 0 0 ns min

MIN

to T

, unless otherwise noted.

MAX

, T

MIN

MAX

SYNC

to SCLK falling edge setup time

SCLK falling edge to Minimum SYNC

SYNC

rising edge to SCLK fall ignore

SCLK falling edge to

SYNC

high time

SYNC

rising edge

fall ignore

Maximum SCLK frequency is 30 MHz at VDD = 3.6 V to 5.5 V and 20 MHz at VDD = 2.7 V to 3.6 V.

SCLK

SYNC

DIN

DB15

DB0

Figure 2. Serial Write Operation

04781-0-002

Rev. PrA | Page 7 of 20

Page 8

AD5620/AD5640 Preliminary Technical Data

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

AD5620/

REFOUT

OUT

AD5640

TOP VIEW

(Not to Scale)

Figure 3. 8-Lead S0T-23/MSOP Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Function

1 VDD Power Supply Input. These parts can be operated from 2.5 V to 5.5 V, and VDD should be de-coupled to GND. 2 V

Reference Voltage Output.

REFOUT

3 VFB Feedback Connection for the Output Amplifier. 4 V 5

Analog Output Voltage from DAC. The output amplifier has rail-to-rail operation.

OUT

SYNC

Level Triggered Control Input (Active Low). This is the frame synchronization signal for the input data. When SYNC

goes low, it enables the input shift register and data is transferred in on the falling edges of the following

clocks. The DAC is updated following the 16th clock cycle, unless

SYNC

acts as an interrupt, and the write sequence is ignored by the DAC.

6 SCLK

case, the rising edge of Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data

can be transferred at rates up to 30 MHz.

7 DIN

Serial Data Input. This device has a 16-bit shift register. Data is clocked into the register on the falling edge of the serial clock input.

8 GND Ground Reference Point for All Circuitry on the Part.

GND DIN SCLK SYNC

04781-0-003

SYNC

is taken high before this edge; in which

Rev. PrA | Page 8 of 20

Page 9

Preliminary Technical Data AD5620/AD5640

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 5.

Parameter Rating

VDD to GND −0.3 V to +7 V Digital Input Voltage to GND −0.3 V to VDD + 0.3 V V

to GND −0.3 V to VDD + 0.3 V

OUT

Operating Temperature Range

Industrial (B Version) −40°C to +105°C Storage Temperature Range −65°C to +150°C Junction Temperature (TJ max) 150°C SOT-23 Package

Power Dissipation (TJ max − TA)/θ

θJA Thermal Impedance 240°C/W Lead Temperature, Soldering

Vapor Phase (60 s) 215°C

Infrared (15 s) 220°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Rev. PrA | Page 9 of 20

Page 10

AD5620/AD5640 Preliminary Technical Data

TERMINOLOGY

Relative Accuracy

For the DAC, relative accuracy or integral nonlinearity (INL) is a measure of the maximum deviation, in LSBs, from a straight line passing through the endpoints of the DAC transfer function. A typical INL vs. code plot can be seen in Figure 4.

Differential Nonlinearity

Differential nonlinearity (DNL) is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ±1 LSB maximum ensures monotonicity. This DAC is guaranteed monotonic by design. A typical DNL vs. code plot can be seen in Figure 5.

Zero-Code Error

It is a measure of the output error when zero code (0x000) is loaded to the DAC register. Ideally, the output should be 0 V. The zero-code error is always positive in the AD5620/AD5640 because the output of the DAC cannot go below 0 V. It is due to a combination of the offset errors in the DAC and output amplifier. Zero-code error is expressed in mV. A plot of the zero-code error vs. temperature can be seen in Figure 8.

Full-Scale Error It is a measure of the output error when full-scale code (0xFFF) is loaded to the DAC register. Ideally, the output should be

− 1 LSB. Full-scale error is expressed in percent of full-scale

range. A plot of the full-scale error vs. temperature can be seen in Figure 8.

Gain Error

This is a measure of the span error of the DAC. It is the deviation in slope of the DAC transfer characteristic from ideal expressed as a percent of the full-scale range.

Tot a l U n ad ju s te d E rr o r ( TU E )

TUE is a measure of the output error taking all the various errors into account. A typical TUE vs. code plot can be seen in Figure 6.

Zero-Code Error Drift This is a measure of the change in zero-code error with a change in temperature. It is expressed in µV/°C.

Gain Error Drift

This is a measure of the change in gain error with changes in temperature. It is expressed in (ppm of full-scale range)/°C.

Digital-to-Analog Glitch Impulse It is the impulse injected into the analog output when the input code in the DAC register changes state. It is normally specified as the area of the glitch in nV-secs and is measured when the digital input code is changed by 1 LSB at the major carry transition (0x7FF to 0x800). See Figure 21.

Digital Feedthrough

It is a measure of the impulse injected into the analog output of the DAC from the digital inputs of the DAC but is measured when the DAC output is not updated. It is specified in nV-secs and measured with a full-scale code change on the data bus, i.e., from all 0s to all 1s and vice versa.

Rev. PrA | Page 10 of 20

Page 11

Preliminary Technical Data AD5620/AD5640

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 4. AD5620 Typical INL Plot

Figure 5. AD5620 Typical DNL Plot

Figure 7. INL Error and DNL Error vs. Temperature

Figure 8. Zero-Scale Error and Full-Scale Error vs. Temperature

Figure 6. AD5620 Typical Total Unadjusted Error (TUE) Plot

Rev. PrA | Page 11 of 20

Figure 9. I

Histogram with VDD = 3 V and VDD = 5 V

Page 12

AD5620/AD5640 Preliminary Technical Data

Figure 10. Source and Sink Current Capability with V

Figure 11. Source and Sink Current Capability with V

= 3 V

= 5 V

Figure 13. Supply Current vs. Temperature

Figure 14. Supply Current vs. Supply Voltage

Figure 12. Supply Current vs. Code

Rev. PrA | Page 12 of 20

Figure 15. Power-Down Current vs. Supply Voltage

Page 13

Preliminary Technical Data AD5620/AD5640

Figure 16. Supply Current vs. Logic Input Voltage

Figure 17. Full-Scale Settling Time

Figure 19. Power-On Reset to 0 V

Figure 20. Exiting Power-Down (0x800 Loaded)

Figure 18. Half-Scale Settling Time

Figure 21. Digital-to-Analog Glitch Impulse

Rev. PrA | Page 13 of 20

Page 14

AD5620/AD5640 Preliminary Technical Data

THEORY OF OPERATION

D/A Section

The AD5620/AD5640 DAC is fabricated on a CMOS process. The architecture consists of a string DAC followed by an output buffer amplifier. The parts include an internal 1.25 V/2.5 V, 10 ppm/°C reference with an internal gain of 2. Figure 22 shows a block diagram of the DAC architecture.

DAC REGISTER

REF (+)

RESISTOR

STRING

REF (–)

GND

Figure 22. DAC Architecture

OUTPUT

AMPLIFIER

OUT

Since the input coding to the DAC is straight binary, the ideal output voltage is given by

OUT

2DVREFV

××=

⎜

65536

⎝

⎟ ⎠

⎞

⎛

where: D equals the decimal equivalent of the binary code that is loaded to the DAC register; 0 − 4095 for AD5620 (12 bit) and 0 − 16383 for AD5640 (14 bit). N equals the DAC resolution.

Figure 23. Resistor String

TO OUTPUT AMPLIFIER

04781-0-023

04781-0-022

Resistor String

The resistor string section is shown in Figure 23. It is simply a string of resistors, each of value R. The code loaded to the DAC register determines at which node on the string the voltage is tapped off to be fed into the output amplifier. The voltage is tapped off by closing one of the switches connecting the string to the amplifier. Because it is a string of resistors, it is guaranteed monotonic.

Output Amplifier

The output buffer amplifier is capable of generating rail-to-rail voltages on its output, which gives an output range of 0 V to

. It is capable of driving a load of 2 kΩ in parallel with

1000 pF to GND. The source and sink capabilities of the output amplifier can be seen in Figure 10 and Figure 11. The slew rate is 1 V/µs with a half-scale settling time of 8 µs with the output unloaded.

SERIAL INTERFACE

The AD5620/AD5640 has a 3-wire serial interface ( SCLK, and DIN), which is compatible with SPI, QSPI, and MICROWIRE interface standards as well as most DSPs. See Figure 2 for a timing diagram of a typical write sequence.

The write sequence begins by bringing the

SYNC from the DIN line is clocked into the 24-bit shift register on the falling edge of SCLK. The serial clock frequency can be as high as 30 MHz, making the AD5620/AD5640 compatible with high speed DSPs. On the 24th falling clock edge, the last data bit is clocked in and the programmed function is executed, i.e., a change in DAC register contents and/or a change in the mode

SYNC

of operation. At this stage, the

line can be kept low or can be brought high. In either case, it must be brought high for a minimum of 33 ns before the next write sequence so that a falling edge of

SYNC

the does when V

SYNC

can initiate the next write sequence. Since

buffer draws more current when VIN = 2.4 V than it

= 0.8 V,

SYNC

should be idled low between write sequences for even lower power operation of the part. As is mentioned previously, however, it must be brought high again just before the next write sequence.

Input Shift Register

The input shift register is 16 bits wide (see Figure 24 and Figure 25). The first two bits are control bits, which control the mode of operation that the part is in (normal mode or any one of the three power-down modes). For a more complete description of the various modes, see the Power-Down Modes section. The next 14/12 bits are the data bits. These are transferred to the DAC register on the 16th falling edge of SCLK.

SYNC

line low. Data

Rev. PrA | Page 14 of 20

Page 15

Preliminary Technical Data AD5620/AD5640

DB15 (MSB) DBO (LSB)

PD1 PD0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X

DATA BITS

Figure 24. AD5620 Input Register Contents

DB15 (MSB) DBO (LSB)

PD1 PD0 D11 D10D13 D12 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Figure 25. AD5640 Input Register Contents

SCLK

SYNC

DIN

DB15 DB15 DB0DB0

INVALID WRITE SEQUENCE:

SYNC HIGH BEFORE 16

FALLING EDGE

Figure 26.

SYNC

Interrupt

In a normal write sequence, the

SYNC

line is kept low for at least 16 falling edges of SCLK, and the DAC is updated on the 16th falling edge. However, if

SYNC

is brought high before the 16th falling edge, this acts as an interrupt to the write sequence. The shift register is reset and the write sequence is seen as invalid. Neither an update of the DAC register contents or a change in the operating mode occurs (see Figure 26).

Power-On Reset

The AD5620/AD5640 family contains a power-on-reset circuit, which controls the output voltage during power-up. The AD5620/AD5640x-1/AD5620/AD5640x-2 DAC output powers up to 0 V, and the AD5620/AD5640x-3 DAC output powers up to midscale. The output remains there until a valid write sequence is made to the DAC. This is useful in applications where it is important to know the state of the output of the DAC while it is in the process of powering up.

Power-Down Modes

The AD5620/AD5640 family contains four separate modes of operation. These modes are software-programmable by setting two bits, DB15 and DB14, in the control register. Table 6 shows how the state of the bits corresponds to the mode of operation of the device.

DATA BITS

SYNC

Interrupt Facility

04781-0-024

04781-0-025

VALID WRITE SEQUENCE, OUTPUT UPDATES

ON THE 16TH FALLING EDGE

04781-0-026

Table 6. Modes of Operation for the AD5620/AD5640

Operating Mode DB15 DB14

Normal Operation 0 0 Power-Down Modes

1 kΩ to GND 0 1 100 kΩ to GND 1 0 Three-State 1 1

When both bits are set to 0, the part works normally with its normal power consumption of 250 µA at 5 V. However, for the three power-down modes, the supply current falls to 200 nA at 5 V and to 0 nA at 3 V. Not only does the supply current fall, but the output stage is internally switched from the output of the amplifier to a resistor network of known values. This has the advantage that the output impedance of the part is known while the part is in power-down mode. There are three different options. The output is connected internally to GND through a 1 kΩ resistor, a 100 kΩ resistor, or left open-circuited (threestate). The output stage is illustrated in Figure 27.

RESISTOR

STRING DAC

AMPLIFIER

POWER-DOWN

CIRCUITRY

Figure 27. Output Stage During Power-Down

RESISTOR NETWORK

OUT

04781-0-027

Rev. PrA | Page 15 of 20

Page 16

AD5620/AD5640 Preliminary Technical Data

The bias generator, the output amplifier, the resistor string, and the other associated linear circuitry are shut down when powerdown mode is activated. However, the contents of the DAC register are unaffected when in power-down. The time to exit power-down is typically 2.5 µs for V

= 5 V and 5 µs for VDD =

3 V. See Figure 20.

MICROPROCESSOR INTERFACING

AD5620/AD5640 to ADSP-2101/ADSP-2103 Interface

Figure 28 shows a serial interface between the AD5620/AD5640 and the ADSP-2101/ADSP-2103. The ADSP-2101/ADSP-2103 should be set up to operate in the SPORT transmit alternate framing mode. The ADSP-2101/ADSP-2103 SPORT is programmed through the SPORT control register and should be configured as follows: internal clock operation, active low framing, and 16-bit word length. Transmission is initiated by writing a word to the Tx register after SPORT is enabled.

ADSP-2101/

ADSP-2103*

TFS

SCLK

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 28. AD5620/AD5640 to ADSP-2101/ADSP-2103 Interface

AD5620/AD5640 to 68HC11/68L11 Interface

Figure 29 shows a serial interface between the AD5620/AD5640 and the 68HC11/68L11 microcontroller. SCK of the 68HC11/68L11 drives the SCLK of the AD5620/AD5640, while the MOSI output drives the serial data line of the DAC. The SYNC

signal is derived from a port line (PC7). The set-up conditions for correct operation of this interface are as follows: the 68HC11/68L11 should be configured so that its CPOL bit is 0 and its CPHA bit is 1. When data transmits to the DAC, the SYNC

line is taken low (PC7). When the 68HC11/68L11 is configured as above, data appearing on the MOSI output is valid on the falling edge of SCK. Serial data from the 68HC11/68L11 transmits in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. Data transmits MSB first. In order to load data to the AD5620/AD5640, PC7 is left low after the first eight bits are transferred, and a second serial write operation is performed to the DAC and PC7 is taken high at the end of this procedure.

AD5620/ AD5640*

SYNC DIN SCLK

04781-0-028

68HC11/68L11*

PC7

SCK

MOSI

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 29. AD5620/AD5640 to 68HC11/68L11 Interface

AD5620/AD5640 to 80C51/80L51 Interface

Figure 30 shows a serial interface between the AD5620/AD5640 and the 80C51/80L51 microcontroller. The setup for the interface is as follows: TXD of the 80C51/80L51 drives SCLK of the AD5620/AD5640, while RXD drives the serial data line of

SYNC

the part. The

signal is again derived from a bitprogrammable pin on the port. In this case, Port Line P3.3 is used. When data transmits to the AD5620/AD5640, P3.3 is taken low. The 80C51/80L51 transmits data only in 8-bit bytes; thus only eight falling clock edges occur in the transmit cycle. To load data to the DAC, P3.3 is left low after the first eight bits are transmitted, and a second write cycle is initiated to transmit the second byte of data. P3.3 is taken high following the completion of this cycle. The 80C51/80L51 outputs the serial data in a format that has the LSB first. The AD5620/AD5640 requires its data with MSBfirst. The 80C51/80L51 transmit routine should take this into account.

80C51/80L51*

P3.3 TXD

RXD

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 30. AD5620/AD5640 to 80C51/80L51 Interface

AD5620/AD5640 to MICROWIRE Interface

Figure 31 shows an interface between the AD5320 and any MICROWIRE-compatible device. Serial data is shifted out on the falling edge of the serial clock and is clocked into the AD5320 on the rising edge of the SK.

MICROWIRE*

CS SK

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 31. AD5620/AD5640 to MICROWIRE Interface

AD5620/ AD5640*

SYNC SCLK DIN

04781-0-029

AD5620/ AD5640*

SYNC SCLK DIN

04781-0-030

AD5620/ AD5640*

SYNC SCLK DIN

04781-0-031

Rev. PrA | Page 16 of 20

Page 17

Preliminary Technical Data AD5620/AD5640

OUTLINE DIMENSIONS

2.90 BSC

3.00 BSC

847

1.60 BSC

PIN 1

INDICATO

1.30

1.15

0.90

0.15 MAX

1 3562

1.95 BSC

0.38

0.22

COMPLIANT TO JEDEC STANDARDS MO-178BA

2.80 BSC

0.65 BSC

1.45 MAX

SEATING PLANE

0.22

0.08

Figure 32. 8-Lead Small Outline Transistor Package [SOT-23]

(RJ-8)

0.15

0.00

8° 4° 0°

0.60

0.45

0.30

3.00

BSC

PIN 1

0.65 BSC

0.38

0.22

COPLANARITY

0.10 COMPLIANT TO JEDEC STANDARDS MO-187AA

SEATING PLANE

4.90 BSC

1.10 MAX

0.23

0.08

8° 0°

Figure 33. 8-Lead Mini Small Outline Package [MSOP]

(RM-8)

Dimensions shown in millimeters

0.80

0.60

0.40

Dimension shown in millimeters

ORDERING GUIDE

Power-On

Model Grade

Reset to

AD5620ARJ-1 A Zero 1.25 V SOT-23 RJ-8 D2K ±2 LSB INL, 25 ppm/°C Ref AD5620ARJ-2 A Zero 2.5 V SOT-23 RJ-8 D2L ±2 LSB INL, 25 ppm/°C Ref AD5620BRJ-1 B Zero 1.25 V SOT-23 RJ-8 D2H ±1 LSB INL, 25 ppm/°C Ref AD5620BRJ-2 B Zero 2.5 V SOT-23 RJ-8 D2J ±1 LSB INL, 25 ppm/°C Ref AD5620CRJ-1 C Zero 1.25 V SOT-23 RJ-8 D2M ±1 LSB INL, 25 ppm/°C Ref AD5620CRJ-2 C Zero 2.5 V SOT-23 RJ-8 D2N ±1 LSB INL, 10 ppm/°C Ref AD5620CRJ-3 C Midscale 2.5 V SOT-23 RJ-8 D2P ±1 LSB INL, 10 ppm/°C Ref AD5620CRM-1 C Zero 1.25 V MSOP RM-8 D2M ±1 LSB INL, 10 ppm/°C Ref AD5620CRM-2 C Zero 2.5 V MSOP RM-8 D2N ±1 LSB INL, 10 ppm/°C Ref AD5620CRM-3 C Midscale 2.5 V MSOP RM-8 D2P ±1 LSB INL, 10 ppm/°C Ref AD5640ARJ-1 A Zero 1.25 V SOT-23 RJ-8 D2S ±8 LSB INL, 25 ppm/°C Ref AD5640ARJ-2 A Zero 2.5 V SOT-23 RJ-8 D2T ±8 LSB INL, 25 ppm/°C Ref AD5640BRJ-1 B Zero 1.25 V SOT-23 RJ-8 D2Q ±4 LSB INL, 25 ppm/°C Ref AD5640BRJ-2 B Zero 2.5 V SOT-23 RJ-8 D2R ±4 LSB INL, 25 ppm/°C Ref AD5640CRJ-1 C Zero 1.25 V SOT-23 RJ-8 D2U ±4 LSB INL, 25 ppm/°C Ref AD5640CRJ-2 C Zero 2.5 V SOT-23 RJ-8 D2V ±4 LSB INL, 10 ppm/°C Ref AD5640CRJ-3 C Midscale 2.5 V SOT-23 RJ-8 D2W ±4 LSB INL, 10 ppm/°C Ref AD5640CRM-1 C Zero 1.25 V MSOP RM-8 D2U ±4 LSB INL, 10 ppm/°C Ref AD5640CRM-2 C Zero 2.5 V MSOP RM-8 D2V ±4 LSB INL, 10 ppm/°C Ref AD5640CRM-3 C Midscale 2.5 V MSOP RM-8 D2W ±4 LSB INL, 10 ppm/°C Ref

Internal Reference

Package Description

Package Options

Branding Description

Rev. PrA | Page 17 of 20

Page 18

AD5620/AD5640 Preliminary Technical Data

NOTES

Rev. PrA | Page 18 of 20

Page 19

Preliminary Technical Data AD5620/AD5640

NOTES

Rev. PrA | Page 19 of 20

Page 20

AD5620/AD5640 Preliminary Technical Data

NOTES

PR04781–0–10/04(PrA)

Rev. PrA | Page 20 of 20