Datasheet AD5601, AD5611, AD5621 Datasheet (ANALOG DEVICES)

2.7 V to 5.5 V, <100 μA, 8-/10-/12-Bit

nano

AD5601/AD5611/AD5621

Rev. F

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

Trademarks and registered trademarks are the property of their respective owners.

Fax: [phone] ©2005–2012 Analog Devices, Inc. All rights reserved.

AD5601/AD5611/AD5621

V

DD

V

OUT

GND

POWER-ON

RESET

DAC

REGISTER

12-/10-/8-BIT

DAC

INPUT

CONTROL

LOGIC

POWER-DOWN

CONTROL LOGIC

OUTPUT
BUFFER

RESISTOR
NETWORK

REF(+)

SCLK SDIN

06853-001

SYNC

Data Sheet

FEATURES

6-lead SC70 and LFCSP packages
Micropower operation: 100 µA maximum at 5 V
Power-down typically to 0.2 µA at 3 V

2.7 V to 5.5 V power supply
Guaranteed monotonic by design
Power-on reset to 0 V with brownout detection
3 power-down functions
Low power serial interface with Schmitt-triggered inputs
On-chip output buffer amplifier, rail-to-rail operation

interrupt facility

SYNC
Minimized zero-code error
AD5601 buffered 8-bit DAC

B version: ±0.5 LSB INL

AD5611 buffered 10-bit DAC

B version: ±0.5 LSB INL
A version: ±4 LSB INL

AD5621 buffered 12-bit DAC

B version: ±1 LSB INL
A version: ±6 LSB INL

APPLICATIONS

Voltage level setting
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators

GENERAL DESCRIPTION

The AD5601/AD5611/AD5621, members of the nanoDAC®
family, are single, 8-/10-/12-bit, buffered voltage output DACs
that operate from a single 2.7 V to 5.5 V supply, consuming
typically 75 µA at 5 V. The parts come in tiny LFCSP and SC70
packages. Their on-chip precision output amplifier allows rail­to-rail output swing to be achieved. The AD5601/AD5611/
AD5621 utilize a versatile 3-wire serial interface that operates at
clock rates up to 30 MHz and is compatible with SPI, QSPI™,
MICROWIRE™, and DSP interface standards.

The reference for the AD5601/AD5611/AD5621 is derived
from the power supply inputs and, therefore, gives the widest
dynamic output range. The parts incorporate a power-on reset
circuit, which ensures that the DAC output powers up to 0 V
and remains there until a valid write to the device takes place.

The AD5601/AD5611/AD5621 contain a power-down feature
that reduces current consumption to typically 0.2 µA at 3 V.

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without n otice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

DAC, SPI Interface in LFCSP and SC70

FUNCTIONAL BLOCK DIAGRAM

Figure 1.

Table 1. Related Devices

Part Number Description

AD5641 2.7 V to 5.5 V, <100 µA, 14-bit nanoDAC in

SC70 and LFCSP packages

They also provide software-selectable output loads while in
power-down mode. The parts are put into power-down mode
over the serial interface.

The low power consumption of these parts in normal operation
makes them ideally suited to portable battery-operated equip­ment. The combination of small package and low power makes
these nanoDAC devices ideal for level-setting requirements,
such as generating bias or control voltages in space-constrained
and power-sensitive applications.

PRODUCT HIGHLIGHTS

1. Available in 6-lead LFCSP and SC70 packages.

2. Low power, single-supply operation. The AD5601/

AD5611/AD5621 operate from a single 2.7 V to 5.5 V
supply with a maximum current consumption of 100 µA,
making them ideal for battery-powered applications.

3. The on-chip output buffer amplifier allows the output of

the DAC to swing rail-to-rail with a typical slew rate of

0.5 V/µs.

4. Reference is derived from the power supply.

5. High speed serial interface with clock speeds up to

30 MHz. Designed for very low power consumption.
The interface powers up only during a write cycle.

6. Power-down capability. When powered down, the DAC

typically consumes 0.2 µA at 3 V. Power-on reset with
brownout detection.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]

www.analog.com

AD5601/AD5611/AD5621 Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Timing Characteristics ................................................................ 4

Absolute Maximum Ratings ............................................................ 5

ESD Caution .................................................................................. 5

Pin Configuration and Function Descriptions ............................. 6

Typical Performance Characteristics ............................................. 7

Terminology .................................................................................... 13

Theory of Operation ...................................................................... 14

DAC Section ................................................................................ 14

Resistor String ............................................................................. 14

Output Amplifier ........................................................................ 14

Serial Interface ............................................................................ 14

Input Shift Register .................................................................... 14

SYNC

Interrupt .......................................................................... 14

Power-On Reset .......................................................................... 16

Power-Down Modes .................................................................. 16

Microprocessor Interfacing ....................................................... 16

Applications ..................................................................................... 18

Choosing a Reference as Power Supply for the

AD5601/AD5611/AD5621 ....................................................... 18

Bipolar Operation Using the AD5601/AD5611/AD5621 ..... 18

Using the AD5601/AD5611/AD5621 with a Galvanically

Isolated Interface ........................................................................ 19

Power Supply Bypassing and Grounding ................................ 19

Outline Dimensions ....................................................................... 20

Ordering Guide .......................................................................... 21

REVISION HISTORY

2/12—Rev. E to Rev. F

Added 6-Lead LFCSP ......................................................... Universal

Changes to Features Section, General Description Section,

Table 1, and Product Highlights Section ....................................... 1

Changes to Table 4 ............................................................................ 5

Added Figure 4; Renumbered Sequentially .................................. 6

Changes to Table 5 ............................................................................ 6

Changes to Choosing a Reference as Power Supply for the

AD5601/AD5611/AD5621 Section .............................................. 18

Updated Outline Dimensions ....................................................... 20

Changes to Ordering Guide .......................................................... 21

7/10—Rev. D to Rev. E

Changes to Figure 1 .......................................................................... 1

5/08—Rev. C to Rev. D

Changes to General Description Section ...................................... 1

Changes to Table 2 ............................................................................ 3

Changes to Choosing a Reference as Power Supply for the

AD5601/AD5611/AD5621 Section .............................................. 18

Changes to Ordering Guide .......................................................... 20

12/07—Rev. B to Rev. C

Changes to Features .......................................................................... 1

Changes to Table 2 ............................................................................. 3

Changes to AD5601/AD5611/AD5621 to ADSP-2101

Interface Section ............................................................................. 16

Updated Outline Dimensions ....................................................... 20

Changes to Ordering Guide .......................................................... 20

7/05—Rev. A to Rev. B

Changes to Figure 48...................................................................... 17

Changes to Galvanically Isolated Interface Section ................... 19

Changes to Figure 52...................................................................... 19

3/05—Rev. 0 to Rev. A

Changes to Timing Characteristics ................................................. 4

Changes to Absolute Maximum Ratings ........................................ 5

Changes to Full Scale Error Section ................................................ 7

Changes to Figure 20...................................................................... 10

Changes to Theory of Operation .................................................. 14

Changes to Power Down Modes .................................................. 15

1/05—Revision 0: Initial Version

Rev. F | Page 2 of 24

Data Sheet AD5601/AD5611/AD5621

AD5621

Short-Circuit Current

15

15 mA

VDD = 3 V/5 V

DC Output Impedance

0.5

0.5 Ω

SPECIFICATIONS

VDD = 2.7 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications T
for A/B grades is −40°C to +125°C, typical at 25°C.

Table 2.

A Grade B Grade
Parameter Min Ty p Max Min Typ Max Unit Test Conditions/Comments

STATIC PERFORMANCE

AD5601

Resolution 8 Bits
Relative Accuracy1 (INL) ±0.5 LSB
Differential Nonlinearity (DNL) ±0.5 LSB Guaranteed monotonic by design

AD5611

Resolution 10 Bits
Relative Accuracy1 (INL) ±4 ±0.5 LSB
Differential Nonlinearity (DNL) ±0.5 ±0.5 LSB Guaranteed monotonic by design

Resolution 12 Bits
Relative Accuracy1 (INL) ±6 ±1 LSB

Differential Nonlinearity (DNL) ±0.5 ±0.5 LSB Guaranteed monotonic by design
Zero-Code Error 0.5 10 0.5 10 mV All 0s loaded to DAC register
Full-Scale Error ±0.5 ±0.5 mV All 1s loaded to DAC register
Offset Error ±0.063 ±10 ±0.063 ±10 mV
Gain Error ±0.0004 ±0.037 ±0.0004 ±0.037 %FSR
Zero-Code Error Drift 5.0 5.0 µV/°C

Gain Temperature Coefficient 2.0 2.0 ppm

OUTPUT CHARACTERISTICS2

Output Voltage Range 0 V

DD

0 VDD V
Output Voltage Settling Time 6 10 6 10 µs Code ¼ scale to ¾ scale
Slew Rate 0.5 0.5 V/µs
Capacitive Load Stability 470 470 pF RL = ∞
1000 1000 pF RL = 2 kΩ
Output Noise Spectral Density 120 120

Noise 2 2 µV DAC code = midscale,

Digital-to-Analog Glitch Impulse 5 5 nV-s 1 LSB change around major carry
Digital Feedthrough 0.2 0.2 nV-s

MIN

to T

, unless otherwise noted. Temperature range

MAX

FSR/°C

nV/√Hz

DAC code = midscale,1 kHz

0.1 Hz to 10 kHz bandwidth

LOGIC INPUTS

Input Current
Input High Voltage, V

1.4 1.4 V VDD = 2.7 V to 3.6 V
Input Low Voltage, V

0.6 0.6 V VDD = 2.7 V to 3.6 V
Pin Input Capacitance 3 3 pF

3

1.8 1.8 V VDD = 4.7 V to 5.5 V

INH

0.8 0.8 V VDD = 4.7 V to 5.5 V

INL

±2 ±2 µA

Rev. F | Page 3 of 24

AD5601/AD5611/AD5621 Data Sheet

VDD = ±2.7 V to ±3.6 V

0.2

0.2 µA

VIH = VDD and VIL = GND

t2 5 ns min

SCLK high time

t8

20

ns min

Minimum

high time

t

4

t

3

t

2

t

5

t

7

t

6

D0D1

D2D14D15

SYNC

SCLK

06853-002

t

9

t

1

t

8

D15 D14

SDIN

A Grade B Grade
Parameter Min Ty p Max Min Typ Max Unit Test Conditions/Comments

POWER REQUIREMENTS

VDD 2.7 5.5 2.7 5.5 V All digital inputs at 0 V or VDD
IDD for Normal Mode DAC active and excluding load

current
VDD = ±4.5 V to ±5.5 V 75 100 75 100 µA VIH = VDD and VIL = GND
VDD = ±2.7 V to ±3.6 V 60 90 60 90 µA VIH = VDD and VIL = GND

IDD for All Power-Down Modes VIH = VDD and VIL = GND

VDD = ±4.5 V to ±5.5 V 0.5 0.5 µA VIH = VDD and VIL = GND

POWER EFFICIENCY

I

96 96 % I

OUT/IDD

1

Linearity calculated using a reduced code range: AD5621 from Code 64 to Code 4032; AD5611 from Code 16 to Code 1008; AD5601 from Code 4 to Code 252.

2

Guaranteed by design and characterization, not production tested.

3

Total current flowing into all pins.

= 2 mA and VDD = ±5 V

LOAD

TIMING CHARACTERISTICS

VDD = 2.7 V to 5.5 V; all specifications T

Table 3.

Parameter Limit1 Unit Test Conditions/Comments

2

t

33 ns min SCLK cycle time

1

MIN

to T

, unless otherwise noted. See Figure 2.

MAX

t3 5 ns min SCLK low time
t4 10 ns min

to SCLK falling edge setup time

SYNC
t5 5 ns min Data setup time
t6 4.5 ns min Data hold time
t7 0 ns min SCLK falling edge to

SYNC

rising edge

SYNC

t9 13 ns min

1

All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.

2

Maximum SCLK frequency is 30 MHz.

rising edge to next SCLK falling edge ignored

SYNC

Figure 2. Timing Diagram

Rev. F | Page 4 of 24

Data Sheet AD5601/AD5611/AD5621

Maximum Junction Temperature

150°C

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 4.

Parameter Rating

VDD to GND −0.3 V to +7.0 V
Digital Input Voltage to GND −0.3 V to VDD + 0.3 V
V

to GND −0.3 V to VDD + 0.3 V

OUT

Operating Temperature Range

Industrial (A/B Grades) −40°C to +125°C

Storage Temperature Range −65°C to +160°C

SC70 Package

θJA Thermal Impedance 433.34°C/W
θJC Thermal Impedance 149.47°C/W

LFCSP Package

θJA Thermal Impedance 95°C/W

Lead Temperature, Soldering

Vapor Phase (60 sec) 215°C
Infrared (15 sec) 220°C

ESD (Human Body Model) 2.0 kV

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

Rev. F | Page 5 of 24

AD5601/AD5611/AD5621 Data Sheet

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

16

SYNC

SDIN

AD5601/
AD5611/

25

AD5621

TOP VIEW

34

(Not to Scale)

V

OUT

GNDSCLK

V

DD

06853-003

Figure 3. 6-Lead SC70 Pin Configuration

1V

DD

2SCLK

3SDIN

NOTES:

1. CONNECT THE EXPOSED PAD TO GND.

Figure 4. 6-Lead LFCSP Pin Configuration

AD5601/
AD5611/
AD5621

TOP VIEW

(Not to Scale)

6V

5GND

4SYNC

Table 5. Pin Function Descriptions

SC70
Pin No.

1 4

LFCSP
Pin No.

Mnemonic Description

Level-Triggered Control Input (Active Low). This is the frame synchronization signal for the input

SYNC

data. When SYNC

goes low, it enables the input shift register, and data is transferred in on the falling
edges of the clocks that follow. The DAC is updated following the 16th clock cycle, unless SYNC is
taken high before this edge, in which case the rising edge of SYNC acts as an interrupt and the write
sequence is ignored by the DAC.

2 2 SCLK

Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock
input. Data can be transferred at rates up to 30 MHz.

3 3 SDIN

Serial Data Input. This device has a 16-bit shift register. Data is clocked into the register on the falling
edge of the serial clock input.

4 1 VDD

Power Supply Input. The AD5601/AD5611/AD5621 can be operated from 2.7 V to 5.5 V. V
decoupled to GND.

5 5 GND Ground. Ground reference point for all circuitry on the AD5601/AD5611/AD5621.
6 6 V

Analog Output Voltage from the DAC. The output amplifier has rail-to-rail operation.

OUT

EP Exposed Pad. Connect to GND.

OUT

DD

06853-053

should be

Rev. F | Page 6 of 24

Data Sheet AD5601/AD5611/AD5621

–1.0

–0.5

0

0.5

1.0

DAC CODE

INL ERROR (LSB)

06853-004

64 564 1064 1564 2064 2564 3064 3564 4064

VDD = V

REF

= 5V

T

A

= 25°C

0

16 116 216 316 416 516 616 716 816 916

DAC CODE

INL ERROR (LSB)

V

DD

= V

REF

= 5V

T

A

=

25°C

06853-005

–0.5

–0.4

–0.3

–0.2

–0.1

0.1

0.2

0.3

0.4

0.5

0

4 54 104 154 204

DAC CODE

INL ERROR (LSB)

VDD = V

REF

= 5V

T

A

= 25°C

06853-006

–0.100

–0.075

–0.050

–0.025

0.025

0.050

0.075

0.100

–2.5

–1.5

–0.5

0.5

1.5

2.5

64 564 1064 1564 2064 2564 3064 3564

DAC CODE

TOTAL UNADJUS TED ERROR (LS B)

06853-007

0

1.0

2.0

–2.0

–1.0

V

DD

= V

REF

= 5V

T

A

= 25°C

4064

–0.6

–0.4

–0.2

0

0.2

0.4

0.6

16 116 216 316 416 516 616 716 816 916

DAC CODE

TOTAL UNADJUS TED ERROR (LS B)

06853-008

V

DD

= V

REF

= 5V

T

A

= 25°C

–0.20

–0.15

–0.10

–0.05

0.05

0.10

0.15

0.20

4 54 104 154 204

DAC CODE

TOTAL UNADJUS TED ERROR (LS B)

0

VDD = V

REF

= 5V

T

A

= 25°C

06853-009

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 5. Typical AD5621 INL

Figure 6. Typical AD5611 INL

Figure 8. AD5621 Total Unadjusted Error (TUE)

Figure 9. AD5611 Total Unadjusted Error (TUE)

Figure 7. Typical AD5601 INL

Figure 10. AD5601 Total Unadjusted Error (TUE)

Rev. F | Page 7 of 24

AD5601/AD5611/AD5621 Data Sheet

–0.20

–0.15

–0.10

–0.05

0

0.05

0.10

0.15

0.20

64 564 1064 1564 2064 2564 3064 3564

DAC CODE

DNL ERROR (LS B)

VDD = 5V
T

A

= 25°C

0

06853-010

–0.05

–0.04

–0.03

–0.02

–0.01

0

0.01

0.02

0.03

0.04

0.05

16 116 216 316 416 516 616 716 816 916

DAC CODE

DNL ERROR (LSB)

V

DD

= 5V

T

A

= 25°C

06853-011

–0.010

–0.008

–0.006

–0.004

–0.002

0

0.002

0.004

0.006

0.008

0.010

4 54 104 154 204

DAC CODE

DNL ERROR (LSB)

06853-012

V

DD

= 5V

T

A

= 25°C

0

2

4

6

8

10

12

0.05456

0.05527

0.05599

0.05671

0.05742

0.05814

0.05885

0.06648

0.06710

0.06773

0.06835

0.06897

0.06960

0.07022

0.07084

0.07147

0.07209

0.07271

0.07334

IDD (mA)

NUMBER OF DEV ICES

06853-013

VDD = 5V
V

IH

= DV

DD

VIL = GND
T

A

= 25°C

V

DD

= 3V

V

IH

= DV

DD

V

IL

= GND

T

A

= 25°C

CH1 = 5V/DIV CH2 = 1V /DIV TI M E BAS E = 2µs/DIV

CH1 = SCLK

CH2 = V

OUT

06853-014

TA = 25°C
V

DD

= 5V

CH1 = 5V/DIV CH2 = 1V /DIV TI M E BAS E = 2µs/DIV

CH1 = SCLK

CH2 = V

OUT

TA = 25°C
V

DD

= 5V

06853-015

Figure 11. Typical AD5621 DNL

Figure 12. Typical AD5611 DNL

Figure 14. IDD Histogram (3 V/5 V)

Figure 15. Full-Scale Settling Time

Figure 13. Typical AD5601 DNL

Figure 16. Half-Scale Settling Time

Rev. F | Page 8 of 24

Data Sheet AD5601/AD5611/AD5621

VDD = 5V
T

= 25°C

A

V

DD

VDD = 5V
T

= 25°C

A

MIDSCALE LOADED

CH1

CH2

CH1

CH2

V

= 70mV

OUT

CH1 1V, CH2 20mV, TIME BASE = 20µs/DIV

Figure 17. Power-On Reset to 0 V

V

DD

V

OUT

CH1 1V, CH2 5V, T IME BASE = 50µ s/DIV

Figure 18. V

DD

vs. V

OUT

VDD = 5V
T

= 25°C

A

CH1

06853-016

CH1 5µV/DIV

06853-019

Figure 20. 1/f Noise, 0.1 Hz to 10 Hz Bandwidth

VDD = 5V

= 25°C

CH1

V

OUT

CH2

06853-017

CH1 5V, CH2 1V, TI ME BASE = 2µ s/DIV

T

A

06853-020

Figure 21. Exiting Power-Down Mode

2.458

2.456

2.454

2.452

2.450

2.448

2.446

AMPLI TUDE (V)

2.444

2.442

2.440

2.438

2.436
0 100 200 300 400 500

SAMPLE NUMBER

TA = 25°C
V

= 5V

DD

LOAD = 2kΩ AND 220pF
CODE 0x2000 TO 0x1FFF
10ns/SAMPLE NUMBER

Figure 19. Digital-to-Analog Glitch Energy

06853-018

Rev. F | Page 9 of 24

140

120

100

80

(µA)

60

DD

I

40

20

0

0 5 10 15 20 25

FULL SCALE

Figure 22. I

1/4 SCALE

ZERO SCALE

FREQUE NCY (MHz )

vs. SCLK vs. Code

DD

3/4 SCALE

MIDSCALE

06853-021

AD5601/AD5611/AD5621 Data Sheet

0

100

200

300

400

500

600

700

100 1k 10k 100k

FREQUENCY ( Hz )

OUTPUT NOISE SPECTRAL DENSITY (nV/ Hz)

VDD = 5V
T

A

= 25°C

UNLOADED OUTPUT

MIDSCALE

ZERO SCAL E

FULL SCALE

06853-022

0

10

20

30

40

50

60

70

0 2000 4000 6000 8000 10000 12000 14000 16000

DIGITAL INPUT CODE

I

DD

(µA)

V

DD

= 5V

V

DD

= 3V

06853-023

T

A

= 25°C

–0.6

–0.4

–0.2

0.0

0.2

0.4

0.6

0.8

–15 –10 –5 0 5 10 15

I (mA)

ΔV

OUT

(V)

06853-024

DAC LOADED WITH ZERO- S CALE CODE

VDD = 5V
T

A

= 25°C

DAC LOADED WITH FULL - S CALE CODE

–0.6

–0.5

–0.4

–0.3

–0.2

–0.1

0

0.1

0.2

0.3

–40 –20 0 4020 60 80 100 120

TEMPERATURE (°C)

INL ERROR ( LSB)

06853-025

AD5611 MIN INL E RROR

AD5621 MIN INL E RROR

AD5621 MAX INL ERROR

V

DD

= 5V

AD5611 MAX INL ERROR

AD5601 MAX INL ERROR

AD5601 MIN INL E RROR

–0.08

–0.07

–0.06

–0.05

–0.04

–0.03

–0.02

–0.01

0

0.01

0.02

0.03

0.04

0.05

0.06

0.07

0.08

–40 10 60 110 160

TEMPERATURE (°C)

DNL ERROR (L S B)

VDD = 5V

06853-026

AD5611 MIN DNL ERRO R

AD5621 MAX DNL ERROR

AD5611 MAX DNL ERROR

AD5601 MAX DNL ERROR
AD5601 MIN DNL ERRO R

AD5621 MIN DNL ERRO R

–40 40 60 80 100

–20 0 –20 120 140

TEMPERATURE (°C)

ERROR (LSB)

AD5621 ZERO-CO DE E RROR

AD5611 FULL-S CALE ERROR
AD5621 FULL-S CALE ERROR

VDD = 5V

06853-027

0.00149

0.00099

0.00049

–0.00001

–0.00051

AD5611 ZERO-CO DE E RROR
AD5601 ZERO-CO DE E RROR

AD5601 FULL-S CALE ERROR

Figure 23. Noise Spectral Density

Figure 26. INL vs. Temperature (5 V)

Figure 24. Supply Current vs. Digital Input Code

Figure 25. Sink and Source Capability

Figure 27. DNL vs. Temperature (5 V)

Figure 28. Zero-Code Error and Full-Scale Error vs. Temperature

Rev. F | Page 10 of 24

Data Sheet AD5601/AD5611/AD5621

–0.5

–0.3

–0.1

0.1

0.3

0.5

1.5

–40 –20

TEMPERATURE (°C)

TOTAL UNADJUSTED ERROR

(LSB)

AD5601 MIN TUE
AD5611 MIN TUE
AD5621 MIN TUE

06853-028

0.7

0.9

1.1

1.3

0 20 40 60 80 100 120 140

AD5621 MAX TUE

AD5601 MAX TUE
AD5611 MAX TUE

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.1

1.2

1.3

1.4

1.5

–40 –20 0 20 100 120 140

TEMPERATURE (°C)

OFFSET ERROR (mV)

40 60 80

1.0

VDD = 5V

VDD = 3V

06853-029

–0.016

–0.014

–0.012

–0.010

–0.008

–0.006

–0.004

–0.002

0

–40 –20 0 20 40 60 80 100 120 140

TEMPERATURE (°C)

GAIN ERROR ( %FSR)

VDD = 3V

V

DD

= 5V

06853-030

0

0.01

0.02

0.03

0.04

0.05

0.06

0.07

0.08

0.09

0.10

–40 –20 0 20 40 60 80 100 120 140

TEMPERATURE (°C)

I

DD

(mA)

VDD = 3V

V

DD

= 5V

06853-031

2.7 3.2 3.7 4.2 4.7 5.2
SUPPLY VOLTAGE (V)

INL ERROR ( LSB)

T

A

= 25°C

06853-032

AD5621 MAX INL ERROR

AD5611 MIN INL E RROR

AD5621 MIN INL E RROR

AD5611 MAX INL ERROR

AD5601 MIN INL E RROR

AD5601 MAX INL ERROR

–0.6

–0.4

–0.2

0

0.2

0.4

–0.10

–0.09

–0.08

–0.07

–0.06

–0.05

–0.04

–0.03

–0.02

–0.01

0.01

0.02

0.03

0.04

0.05

0.06

0.07

0.08

0.09

0.10

2.7 3.2 3.7 4.2 4.7 5.2 5.7 6.2 6.7
SUPPLY VOLTAGE (V)

DNL ERROR (L S B)

0

TA = 25°C

AD5621 MAX DNL ERROR

AD5601 MAX DNL ERROR
AD5601 MIN DNL ERRO R

AD5621 MIN DNL ERRO R

06853-033

AD5611 MAX DNL ERROR

AD5611 MIN DNL ERRO R

Figure 29. Total Unadjusted Error (TUE) vs. Temperature (5 V)

Figure 30. Offset Error vs. Temperature (3 V/5 V Supply)

Figure 32. Supply Current vs. Temperature (3 V/5 V Supply)

Figure 33. INL vs. Supply Voltage at 25°C

Figure 31. Gain Error vs. Temperature ( 3 V/5 V Supply)

Figure 34. DNL vs. Supply Voltage at 25°C

Rev. F | Page 11 of 24

AD5601/AD5611/AD5621 Data Sheet

2.7 3.2 3.7 4.2 4.7 5.2

SUPPLY VOLTAGE (V)

TOTAL UNADJUS TED ERROR (LS B)

T

A

= 25°C

AD5621 MAX TUE

AD5601 MAX TUE
AD5611 MIN TUE
AD5601 MIN TUE

AD5621 MIN TUE

06853-034

–0.3

–0.1

0.1

0.3

0.5

0.7

0.9

1.1

1.3

1.5

AD5611 MAX TUE

2.7 3.2 3.7 4.2 4.7 5.2 5.7 6.2 6.7
SUPPLY VOLTAGE (V)

ERROR (LSB)

TA = 25°C

AD5621 ZERO-CO DE E RROR

AD5611 ZERO-CO DE E RROR

AD5621 FULL-S CALE ERROR

AD5611 FULL-S CALE ERROR

AD5601 ZERO-CO DE E RROR

AD5601 FULL-S CALE ERROR

06853-035

–0.0004

–0.0002

0

0.0002

0.0004

0.0006

0.0008

0.0010

0

0.01

0.02

0.03

0.04

0.05

0.06

0.07

0.08

0.09

0.10

2.7 3.2 3.7 4.2 4.7 5.2
SUPPLY VOLTAGE (V)

I

DD

(

m

A)

TA = 25°C

06853-036

0

50

100

150

200

250

300

350

400

450

0

V

LOGIC

(V)

I

DD

(µA)

SCLK/SDIN
INCREASING
V

DD

= 3V

SCLK/SDI N DE CRE AS ING V

DD

= 3V

SCLK/SDIN
DECREASING
V

DD

= 5V

SCLK/SDIN
INCREASING
V

DD

= 5V

64 5321

TA = 25°C

06853-037

Figure 35. Total Unadjusted Error (TUE) vs. Supply Voltage at 25°C

Figure 37. Supply Current vs. Supply Voltage at 25°C

Figure 36. Zero-Code Error and Full-Scale Error vs. Supply Voltage at 25°C

Figure 38. SCLK/SDIN vs. Logic Voltage

Rev. F | Page 12 of 24

Data Sheet AD5601/AD5611/AD5621

TERMINOLOGY

Relative Accuracy

For the DAC, relative accuracy or integral nonlinearity (INL) is
a measure of the maximum deviation, in LSBs, from a straight
line passing through the endpoints of the DAC transfer func­tion. See Figure 5 to Figure 7 for plots of typical INL vs. code.

Differential Nonlinearity

Differential nonlinearity (DNL) is the difference between the
measured change and the ideal 1 LSB change between any two
adjacent codes. A specified differential nonlinearity of ±1 LSB
maximum ensures monotonicity. This DAC is guaranteed
monotonic by design. See Figure 11 to Figure 13 for plots of
typical DNL vs. code.

Zero-Code Error

Zero-code error is a measure of the output error when zero
code (0x0000) is loaded to the DAC register. Ideally, the output
should be 0 V. The zero-code error is always positive in the
AD5601/AD5611/AD5621 because the output of the DAC cannot
go below 0 V. Ze ro -code error is due to a combination of the
offset errors in the DAC and output amplifier. Zero-code error
is expressed in mV. See Figure 28 for a plot of zero-code error
vs. temperature.

Full-Scale Error

Full-scale error is a measure of the output error when full-scale
code (0xFFFF) is loaded to the DAC register. Ideally, the output
should be V
Figure 28 for a plot of full-scale error vs. temperature.

Gain Error

Gain error is a measure of the span error of the DAC. It is the
deviation in slope of the DAC transfer characteristic from the
ideal, expressed as a percent of the full-scale range.

− 1 LSB. Full-scale error is expressed in mV. See

DD

Total Unadjusted Error

Total unadjusted error (TUE) is a measure of the output error,
taking all the various errors into account. See Figure 8 to
Figure 10 for plots of typical TUE vs. code.

Zero-Code Error Drift

Zero-code error drift is a measure of the change in zero-code
error with a change in temperature. It is expressed in µV/°C.

Gain Temperature Coefficient

Gain temperature coefficient is a measure of the change in gain
error with changes in temperature. It is expressed in (ppm of
full-scale range)/°C.

Digital-to-Analog Glitch Impulse

Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is normally specified as the area of the glitch in nV-s
and is measured when the digital input code is changed by
1 LSB at the major carry transition (0x2000 to 0x1FFF). See
Figure 19.

Digital Feedthrough

Digital feedthrough is a measure of the impulse injected into
the analog output of the DAC from the digital inputs of the
DAC, but is measured when the DAC output is not updated.
It is specified in nV-s and is measured with a full-scale code
change on the data bus—from all 0s to all 1s and vice versa.

Rev. F | Page 13 of 24











×=

n

DD

OUT

D

VV

2

V

DD

V

OUT

GND

RESISTOR
NETWORK

REF (+)

REF (–)

OUTPUT AMPLIFIER

DAC REGISTER

06853-038

R

R

R

R

R

TO OUTPUT
AMPLIFIER

06853-039

AD5601/AD5611/AD5621 Data Sheet

THEORY OF OPERATION

DAC SECTION

The AD5601/AD5611/AD5621 DACs are fabricated on a
CMOS process. The architecture consists of a string DAC
followed by an output buffer amplifier. Figure 39 is a block
diagram of the DAC architecture.

Figure 39. DAC Architecture

Because the input coding to the DAC is straight binary, the ideal
output voltage is given by

where:
D is the decimal equivalent of the binary code that is loaded to
the DAC register.
n is the bit resolution of the DAC.

RESISTOR STRING

The resistor string structure is shown in Figure 40. It is simply a
string of resistors, each of Value R. The code loaded to the DAC
register determines at which node on the string the voltage is
tapped off to be fed into the output amplifier. The voltage is
tapped off by closing one of the switches connecting the string
to the amplifier. Because it is a string of resistors, it is guaran­teed monotonic.

Figure 40. Resistor String Structure

Rev. F | Page 14 of 24

OUTPUT AMPLIFIER

The output buffer amplifier is capable of generating rail-to-rail
voltages on its output, giving an output range of 0 V to V

DD

. It is
capable of driving a load of 2 kΩ in parallel with 1000 pF to
GND. The source and sink capabilities of the output amplifier
are shown in Figure 25. The slew rate is 0.5 V/µs, with a half­scale settling time of 8 µs with the output loaded.

SERIAL INTERFACE

The AD5601/AD5611/AD5621 have a 3-wire serial interface

SYNC

(

, SCLK, and SDIN) that is compatible with SPI, QSPI,
and MICROWIRE interface standards as well as most DSPs. See
Figure 2 for a timing diagram of a typical write sequence.

The write sequence begins by bringing the

SYNC

line low. Data
from the SDIN line is clocked into the 16-bit shift register on
the falling edge of SCLK. The serial clock frequency can be as
high as 30 MHz, making the AD5601/AD5611/AD5621 com­patible with high speed DSPs. On the 16

th

falling clock edge,
the last data bit is clocked in and the programmed function is
executed (a change in DAC register contents and/or a change
in the mode of operation). At this stage, the

SYNC

line may be
kept low or brought high. In either case, it must be brought high
for a minimum of 33 ns before the next write sequence so that a
falling edge of

Because the
than it does when V

SYNC

can initiate the next write sequence.

SYNC

buffer draws more current when VIN = 1.8 V

= 0.8 V,

IN

SYNC

should be idled low
between write sequences for even lower power operation of the
part, as mentioned previously. However, it must be brought
high again just before the next write sequence.

INPUT SHIFT REGISTER

The input shift register is 16 bits wide (see Figure 41). The first
two bits are control bits, which control the operating mode of
the part (normal mode or any one of three power-down
modes). For a complete description of the various modes, see
the Power-Down Modes section. For the AD5621, the next
12 bits are the data bits, which are transferred to the DAC
register on the 16
the last two bits is ignored by the AD5621. See Figure 42 and
Figure 43 for the AD5611 and AD5601 input shift register map.

INTERRUPT

SYNC

In a normal write sequence, the
least 16 falling edges of SCLK and the DAC is updated on the

th

falling edge. However, if

16

th

16

falling edge, this acts as an interrupt to the write sequence.
The shift register is reset and the write sequence is seen as
invalid. Neither an update of the DAC register contents nor a
change in the operating mode occurs (see

th

falling edge of SCLK. The information in

SYNC

line is kept low for at

SYNC

is brought high before the

Figure 44).

Data Sheet AD5601/AD5611/AD5621

DB15 (MSB)

PD1 PD0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X

X

DB0 (LSB)

DATA BITS

POWER-DOWN MODES

0
1
0
1

0
0
1
1

NORMAL OPERATION

1kΩ TO GND

100kΩ TO G ND

THREE-STATE

06853-040

DB15 (MSB)

PD1 PD0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X

X

DB0 (LSB)

DATA BITS

POWER-DOWN MODES

0
1
0
1

0
0
1
1

NORMAL OPERATION

1kΩ TO GND

100kΩ TO G ND

THREE-STATE

06853-041

DB15 (MSB)

PD1 PD0 D8 D7 D6 D5 D4 D3 D2 D1 X X X X X

X

DB0 (LSB)

DATA BITS

POWER-DOWN MODES

0
1
0
1

0
0
1
1

NORMAL OPERATION

1kΩ TO GND

100kΩ TO G ND

THREE-STATE

06853-042

06853-043

DB15 DB15 DB0DB0

INVALID W RITE SEQ UE NCE :

SYNC HIGH BEF ORE 16

TH

FALLING EDGE

VALID WRI TE SEQUENCE , OUTPUT UP DATES

ON THE 16TH FALLING EDGE

SYNC

SCLK

SDIN

Figure 41. AD5621 Input Register Contents

Figure 42. AD5611 Input Register Contents

Figure 43. AD5601 Input Register Contents

Figure 44.

Rev. F | Page 15 of 24

SYNC

Interrupt Facility

AD5601/AD5611/AD5621 Data Sheet

POWER-DOWN

CIRCUITRY

RESISTOR

NETWORK

V

OUT

RESISTOR

STRING DAC

AMPLIFIER

06853-044

AD5601/AD5611/
AD5621*

*ADDITIONAL PINS OMITTED FOR CLARITY

TFS

DT

SCLK

SYNC
SDIN
SCLK

06853-045

ADSP-2101*

68HC11/

68L11*

AD5601/AD5611/
AD5621*

*ADDITIONAL PINS OMITTED FOR CLARITY

PC7

SCK

MOSI

SYNC
SCLK
SDIN

06853-046

POWER-ON RESET

The AD5601/AD5611/AD5621 contain a power-on reset circuit
that controls the output voltage during power-up. The DAC
register is filled with 0s and the output voltage is 0 V. It remains
there until a valid write sequence is made to the DAC. This is
useful in applications in which it is important to know the state
of the DAC output while it is in the process of powering up.

POWER-DOWN MODES

The AD5601/AD5611/AD5621 have four separate modes of
operation. These modes are software-programmable by setting
two bits (DB15 and DB14) in the control register. Table 6 shows
how the state of the bits corresponds to the operating mode of
the device.

Table 6. Operating Modes of the AD5601/AD5611/AD5621

DB15 DB14 Operating Mode

0 0 Normal operation
Power-down modes:
0 1 1 kΩ to GND
1 0 100 kΩ to GND
1 1 Three-state

When both bits are set to 0, the part has normal power
consumption of 100 µA maximum at 5 V. However, for the
three power-down modes, the supply current falls to typically

0.2 µA at 3 V.

Not only does the supply current fall, but the output stage is
also internally switched from the output of the amplifier to a
resistor network of known values. This has the advantage that
the output impedance of the part is known while the part is in
power-down mode.

There are three different options: the output is connected
internally to GND through a 1 kΩ resistor or a 100 kΩ resistor,
or the output is left open-circuited (three-stated). Figure 45
shows the output stage.

MICROPROCESSOR INTERFACING

AD5601/AD5611/AD5621 to ADSP-2101 Interface

Figure 46 shows a serial interface between the AD5601/
AD5611/AD5621 and the ADSP-2101. The ADSP-2101 should
be set up to operate in SPORT transmit alternate framing mode.
The ADSP-2101 SPORT is programmed through the SPORT
control register and should be configured as follows: internal
clock operation, active low framing, and 16-bit word length.
Transmission is initiated by writing a word to the Tx register
after the SPORT is enabled.

Figure 46. AD5601/AD5611/AD5621 to ADSP-2101 Interface

AD5601/AD5611/AD5621 to 68HC11/68L11 Interface

Figure 47 shows a serial interface between the AD5601/AD5611/
AD5621 and the 68HC11/68L11 microcontroller. SCK of the
68HC11/68L11 drives the SCLK of the AD5601/AD5611/
AD5621, while the MOSI output drives the serial data line of
the DAC. The
The setup conditions for correct operation of this interface are
as follows: the 68HC11/68L11 should be configured so that the
CPOL bit is 0 and the CPHA bit is 1. When data is being trans­mitted to the DAC, the
68HC11/68L11 are configured as indicated, data appearing on
the MOSI output is valid on the falling edge of SCK. Serial data
from the 68HC11/68L11 is transmitted in 8-bit bytes with only
eight falling clock edges occurring in the transmit cycle. Data is
transmitted MSB first. To load data to the AD5601/AD5611/
AD5621, PC7 is left low after the first eight bits are transferred
and a second serial write operation is performed to the DAC.
PC7 is taken high at the end of this procedure.

SYNC

signal is derived from a port line (PC7).

SYNC

line is taken low (PC7). When the

Figure 45. Output Stage During Power-Down

The bias generator, output amplifier, resistor string, and other
associated linear circuitry are all shut down when power-down
mode is activated. However, the contents of the DAC register
are unaffected when in power-down. The time to exit power­down is typically 13 µs for V
See Figure 21 for a plot.

= 5 V and 16 µs for VDD = 3 V.

DD

Figure 47. AD5601/AD5611/AD5621 to 68HC11/68L11 Interface

Rev. F | Page 16 of 24

Data Sheet AD5601/AD5611/AD5621

ADSP-BF53x*

AD5601/AD5611/
AD5621*

*ADDITIONAL PINS OMITTED FOR CLARITY

DT0PRI

TSCLK0

TFS0

SDIN
SCLK
SYNC

06853-047

80C51/80L51*

AD5601/AD5611/
AD5621*

*ADDITIONAL PINS OMITTED FOR CLARITY

P3.3

TxD

RxD

SYNC
SCLK
SDIN

06853-048

MICROWIRE*

AD5601/AD5611/
AD5621*

*ADDITIONAL PINS OMITTED FOR CLARITY

CS
SK
SO

SYNC
SCLK
SDIN

06853-049

AD5601/AD5611/AD5621 to Blackfin® ADSP-BF53x Interface

Figure 48 shows a serial interface between the AD5601/AD5611/
AD5621 and the Blackfin ADSP-BF53x microprocess or. The
ADSP-BF53x processor family incorporates two dual-channel
synchronous serial ports, SPORT1 and SPORT0, for serial and
multiprocessor communications. Using SPORT0 to connect to
the AD5601/AD5611/AD5621, the setup for the interface is as
follows: DT0PRI drives the SDIN pin of the AD5601/AD5611/
AD5621, while TSCLK0 drives the SCLK of the part. The

SYNC

is driven from TFS0.

and a second write cycle is initiated to transmit the second byte
of data. P3.3 is taken high following the completion of this
cycle. The 80C51/80L51 output the serial data LSB first. The
AD5601/AD5611/AD5621 require data with the MSB as the
first bit received. The 80C51/80L51 transmit routine should
take this into account.

Figure 48. AD5601/AD5611/AD5621 to Blackfin ADSP-BF53x Interface

AD5601/AD5611/AD5621 to 80C51/80L51 Interface

Figure 49 shows a serial interface between the AD5601/
AD5611/AD5621 and the 80C51/80L51 microcontroller. The
setup for the interface is as follows: TxD of the 80C51/80L51
drives SCLK of the AD5601/AD5611/AD5621, while RxD
drives the serial data line of the part. The

SYNC

signal is again
derived from a bit programmable pin on the port. In this case,
Port Line P3.3 is used. When data is to be transmitted to the
AD5601/AD5611/AD5621, P3.3 is taken low. The 80C51/80L51
transmit data only in 8-bit bytes; therefore, only eight falling
clock edges occur in the transmit cycle. To load data to the
DAC, P3.3 is left low after the first eight bits are transmitted,

Figure 49. AD5601/AD5611/AD5621 to 80C51/80L51 Interface

AD5601/AD5611/AD5621 to MICROWIRE Interface

Figure 50 shows an interface between the AD5601/AD5611/
AD5621 and any MICROWIRE-compatible device. Serial data
is shifted out on the falling edge of the serial clock and is
clocked into the AD5601/AD5611/AD5621 on the rising edge
of the SK.

Figure 50. AD5601/AD5611/AD5621 to MICROWIRE Interface

Rev. F | Page 17 of 24

AD5601/AD5611/AD5621 Data Sheet




















×−










+

×










×=

R1

R2

V

R1

R2R1D

VV

DD

N

DD

OUT

2

V5

2

10

−











×

=

N

OUT

D

V

3-WIRE

SERIAL

INTERFACE

SYNC

SCLK

SDIN

7V

5V

V

OUT

= 0V TO 5V

ADR395

06853-050

AD5601/AD5611/

AD5621

R2 = 10kΩ

06853-051

+5V

–5V

AD820/
OP295

3-WIRE
SERIAL

INTERFACE

+5V

AD5601/AD5611/

AD5621

10µF

0.1µF

V

DD

V

OUT

R1 = 10kΩ

+5V

APPLICATIONS

CHOOSING A REFERENCE AS POWER SUPPLY FOR THE AD5601/AD5611/AD5621

The AD5601/AD5611/AD5621 come in tiny LFCSP and SC70
packages with less than a 100 µA supply current. Because of
this, the choice of reference depends on the application
requirements. For applications with space-saving requirements,
the ADR02 is recommended. It is available in an SC70 package
and has excellent drift at 9 ppm/°C (3 ppm/°C in the R-8 package)
and provides very good noise performance at 3.4 µV p-p in the 0.1
Hz to 10 Hz range.

Because the supply current required by the AD5601/AD5611/
AD5621 is extremely low, the parts are ideal for low supply
applications. The ADR395 voltage reference is recommended in
this case. It requires less than 100 µA of quiescent current and
can, therefore, drive multiple DACs in one system, if required. It
also provides very good noise performance at 8 µV p-p in the

0.1 Hz to 10 Hz range.

BIPOLAR OPERATION USING THE AD5601/AD5611/AD5621

The AD5601/AD5611/AD5621 have been designed for single­supply operation, but a bipolar output range is also possible
using the circuit shown in Figure 52. The circuit in Figure 52
gives an output voltage range of ±5 V. Rail-to-rail operation at
the amplifier output is achievable using an AD820 or OP295 as
the output amplifier.

Figure 51. ADR395 as Power Supply to the AD5601/AD5611/AD5621

Some recommended precision references for use as supplies to
the AD5601/AD5611/AD5621 are listed in Tabl e 7.

Table 7. Precision References for the AD5601/AD5611/AD5621

Initial

Part No.

Accuracy
(mV max)

Temp Drift
(ppm/°C max)

0.1 Hz to 10 Hz
Noise (µV p-p typ)

ADR435 ±2 3 (R-8) 8
ADR425 ±2 3 (R-8) 3.4
ADR02 ±3 3 (R-8) 10
ADR02 ±3 3 (SC70) 10
ADR395 ±5 9 (TSOT-23) 8

Figure 52. Bipolar Operation with the AD5601/AD5611/AD5621

The output voltage for any input code can be calculated as

where D represents the input code in decimal (0 – 2

With V

= 5 V, R1 = R2 = 10 kΩ

DD

N

).

This is an output voltage range of ±5 V, with 0x0000 corre­sponding to a −5 V output and 0x3FFF corresponding to a
+5 V output.

Rev. F | Page 18 of 24

Data Sheet AD5601/AD5611/AD5621

06853-052

V

DD

AD5601/
AD5611/
AD5621

ADuM1300

POWER 10µF 0.1µF

GND

5V

REGULATOR

SCLKV

OA

V

OUT

V

OB

SYNC

V

OC

V

IA

V

IB

V

IC

SCLK

SDI

DATA SDIN

USING THE AD5601/AD5611/AD5621 WITH A GALVANICALLY ISOLATED INTERFACE

In process control applications in industrial environments,
it is often necessary to use a galvanically isolated interface to
protect and isolate the controlling circuitry from any hazardous
common-mode voltages that might occur in the area where the
DAC is functioning. iCoupler® provides isolation in excess of

2.5 kV. Because the AD5601/AD5611/AD5621 use a 3-wire serial
logic interface, the ADuM1300 3-channel digital isolator
provides the required isolation (see Figure 53). The power
supply to the part also needs to be isolated, which is done by
using a transformer. On the DAC side of the transformer, a 5 V
regulator provides the 5 V supply required for the AD5601/
AD5611/AD5621.

Figure 53. AD5601/AD5611/AD5621 with a Galvanically Isolated Interface

POWER SUPPLY BYPASSING AND GROUNDING

When accuracy is important in a circuit, it is helpful to carefully
consider the power supply and ground return layout on the
board. The PCB containing the AD5601/AD5611/AD5621
should have separate analog and digital sections, each having its
own area of the board. If the AD5601/AD5611/AD5621 are in a
system where other devices require an AGND-to-DGND
connection, the connection should be made at one point only.
This ground point should be as close as possible to the
AD5601/AD5611/AD5621.

The power supply to the AD5601/AD5611/AD5621 should be
bypassed with 10 µF and 0.1 µF capacitors. The capacitors
should be physically as close as possible to the device, with the

0.1 µF capacitor ideally right up against the device. The 10 µF
capacitors are the tantalum bead type. It is important that the

0.1 µF capacitor have low effective series resistance (ESR) and
effective series inductance (ESI), such as in common ceramic
types of capacitors. This 0.1 µF capacitor provides a low imped­ance path to ground for high frequencies caused by transient
currents due to internal logic switching.

The power supply line itself should have as large a trace as
possible to provide a low impedance path and reduce glitch
effects on the supply line. Clocks and other fast switching
digital signals should be shielded from other parts of the board
by digital ground. Avoid crossover of digital and analog signals,
if possible. When traces cross on opposite sides of the board,
ensure that they run at right angles to each other to reduce
feedthrough effects on the board. The best board layout tech­nique is the microstrip technique, where the component side of
the board is dedicated to the ground plane only and the signal
traces are placed on the solder side. However, this is not always
possible with a two-layer board.

Rev. F | Page 19 of 24

AD5601/AD5611/AD5621 Data Sheet

1.30BSC

COMPLIANT TO JEDEC STANDARDS MO-203-AB

1.00

0.90

0.70

0.46

0.36

0.26

2.20

2.00

1.80

2.40

2.10

1.80

1.35

1.25

1.15

072809-A

0.10 MAX

1.10

0.80

0.40

0.10

0.22

0.08

3

1 2

46

5

0.65BSC

COPLANARITY

0.10

SEATING
PLANE

0.30

0.15

1.50

1.40

1.30

0.45

0.40

0.35

TOP VIEW

6

1

4

3

BOTTOM VIEW

PIN 1 INDEX

AREA

SEATING

PLANE

0.80

0.75

0.70

1.70

1.60

1.50

0.203 REF

0.05 MAX

0.00 MIN

0.65 REF

EXPOSED

PAD

PIN 1
INDICATOR
(R 0.15)

FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.

10-18-2010-A

2.10

2.00

1.90

3.10

3.00

2.90

COMPLIANT

TO

JEDEC STANDARDS MO-229

COPLANARITY

0.08

0.20 MIN

0.35

0.30

0.25

OUTLINE DIMENSIONS

Figure 54. 6-Lead Thin Shrink Small Outline Transistor Package [SC70]

(KS-6)

Dimensions shown in millimeters

Figure 55. 6-Lead Lead Frame Chip Scale Package [LFCSP_WD]

2.00 × 3.00 mm Body, Very Very Thin, Dual Lead
(CP-6-5)

Dimensions shown in millimeters

Rev. F | Page 20 of 24

Data Sheet AD5601/AD5611/AD5621

Temperature

Package

ORDERING GUIDE

Model1

AD5601BKSZ-500RL7 –40°C to +125°C ±0.5 LSB 6-Lead Thin Shrink Small Outline Transistor Package [SC70] KS-6 D3V
AD5601BKSZ-REEL7 –40°C to +125°C ±0.5 LSB 6-Lead Thin Shrink Small Outline Transistor Package [SC70] KS-6 D3V
AD5601BCPZ-RL7 –40°C to +125°C ±0.5 LSB 6-Lead Lead Frame Chip Scale Package [LFCSP_WD] CP-6-5 89
AD5611AKSZ-500RL7 –40°C to +125°C ±4.0 LSB 6-Lead Thin Shrink Small Outline Transistor Package [SC70] KS-6 D3U
AD5611AKSZ-REEL7 –40°C to +125°C ±4.0 LSB 6-Lead Thin Shrink Small Outline Transistor Package [SC70] KS-6 D3U
AD5611ACPZ-RL7 –40°C to +125°C ±4.0 LSB 6-Lead Lead Frame Chip Scale Package[LFCSP_WD] CP-6-5 8B
AD5611BKSZ-500RL7 –40°C to +125°C ±0.5 LSB 6-Lead Thin Shrink Small Outline Transistor Package [SC70] KS-6 D3T
AD5611BKSZ-REEL7 –40°C to +125°C ±0.5 LSB 6-Lead Thin Shrink Small Outline Transistor Package [SC70] KS-6 D3T
AD5621AKSZ-500RL7 –40°C to +125°C ±6.0 LSB 6-Lead Thin Shrink Small Outline Transistor Package [SC70] KS-6 D3S
AD5621AKSZ-REEL7 –40°C to +125°C ±6.0 LSB 6-Lead Thin Shrink Small Outline Transistor Package [SC70] KS-6 D3S
AD5621ACPZ-RL7 –40°C to +125°C ±6.0 LSB 6-Lead Lead Frame Chip Scale Package[LFCSP_WD] CP-6-5 88
AD5621BKSZ-500RL7 –40°C to +125°C ±1.0 LSB 6-Lead Thin Shrink Small Outline Transistor Package [SC70] KS-6 D3R
AD5621BKSZ-REEL7 –40°C to +125°C ±1.0 LSB 6-Lead Thin Shrink Small Outline Transistor Package [SC70] KS-6 D3R
EVAL-AD5621EBZ Evaluation Board

1

Z = RoHS Compliant Part.

Range

INL Package Description

Option

Branding

Rev. F | Page 21 of 24

AD5601/AD5611/AD5621 Data Sheet

NOTES

Rev. F | Page 22 of 24

Data Sheet AD5601/AD5611/AD5621

NOTES

Rev. F | Page 23 of 24

AD5601/AD5611/AD5621 Data Sheet

©2005–2012 Analog Devices, Inc. All rights reserved. Trademarks and

NOTES

registered trademarks are the property of their respective owners.
D06853-0-2/12(F)

Rev. F | Page 24 of 24