Datasheet AD5601 Datasheet (Analog Devices)

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2.7 V to 5.5 V, <100 µA, 8-/10-/12-Bit

nano

DAC™, SPI® Interface in SC70 Package

FEATURES

6-lead SC70 package Micropower operation: 100 µA max at 5 V Power-down typically to 0.2 µA at 3 V

2.7 V to 5.5 V power supply Guaranteed monotonic by design Power-on reset to 0 V with brownout detection 3 power-down functions Low power serial interface with Schmitt-triggered inputs On-chip output buffer amplifier, rail-to-rail operation SYNC

interrupt facility Minimized zero-code error AD5601 buffered 8-bit DAC in SC70:

B Version: ±0.5 LSB INL

AD5611 buffered 10-bit DAC in SC70:

A Version: ±4 LSB INL

AD5621 buffered 12-bit DAC in SC70:

A Version: ±6 LSB INL

APPLICATIONS

Voltage level setting Portable battery-powered instruments Digital gain and offset adjustment Programmable voltage and current sources Programmable attenuators

GENERAL DESCRIPTION

The AD5601/AD5611/AD5621, members of the nanoDAC family, are single, 8-/10-/12-bit, buffere d, voltage-out DACs that operate from a single 2.7 V to 5.5 V supply, consuming typically 75 µA at 5 V. The parts come in a tiny SC70 package. Their onchip precision output amplifier allows rail-to-rail output swing to be achieved. The AD5601/AD5611/AD5621 utilize a versatile 3-wire serial interface that operates at clock rates up to 30 MHz and is compatible with SPI, QSPI™, MICROWIRE™, and DSP interface standards.

The reference for the AD5601/AD5611/AD5621 is derived from the power supply inputs and, therefore, gives the widest dynamic output range. The parts incorporate a power-on reset circuit, which ensures that the DAC output powers up to 0 V and remains there until a valid write to the device takes place.

The AD5601/AD5611/AD5621 contain a power-down feature that reduces current consumption to typically 0.2 µA at 3 V, and provides software-selectable output loads while in power-down mode. The parts are put into power-down mode over the serial interface.

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

AD5601/AD5611/AD5621

FUNCTIONAL BLOCK DIAGRAM

GND

POWER-ON

RESET

REF(+)

14-BIT

SYNC

DAC

INPUT

CONTROL

LOGIC

SCLK SDIN

Table 1. Related Devices

Part Number Description

AD5641 2.7 V to 5.5 V, <100 µA, 14-Bit nanoDAC in SC70

Package

The low power consumption of these parts in normal operation makes them ideally suited to portable battery-operated equipment. The combination of small package and low power makes these nanoDAC devices ideal for level-setting requirements such as generating bias or control voltages in space-constrained and power-sensitive applications.

PRODUCT HIGHLIGHTS

1. Available in a space-saving, 6-lead SC70 package.

2. Low power, single-supply operation. The AD5601/

AD5611/AD5621 operate from a single 2.7 V to 5.5 V supply and with a maximum current consumption of 100 µA, making them ideal for battery-powered applications.

3. The on-chip output buffer amplifier allows the output of

the DAC to swing rail-to-rail with a typical slew rate of

0.5 V/µs.

4. Reference derived from the power supply.

5. High speed serial interface with clock speeds up to

30 MHz. Designed for very low power consumption. The interface powers up only during a write cycle.

6. Power-down capability. When powered down, the DAC

typically consumes 0.2 µA at 3 V. Power-on reset with brownout detection.

www.analog.com

AD5601/AD5611/AD5621

OUTPUT

DAC

POWER-DOWN

CONTROL LOGIC

BUFFER

Figure 1.

RESISTOR NETWORK

OUT

04783-001

Page 2

AD5601/AD5611/AD5621

TABLE OF CONTENTS

Specifications..................................................................................... 3

Timing Characteristics ................................................................ 4

Absolute Maximum Ratings............................................................ 5

ESD Caution.................................................................................. 5

Pin Configuration and Function Descriptions............................. 6

Te r m in o l o g y ...................................................................................... 7

Typical Performance Characteristics ............................................. 8

Theory of Operation ...................................................................... 14

D/A Section ................................................................................. 14

Resistor String............................................................................. 14

Output Amplifier........................................................................ 14

Serial Interface............................................................................ 14

Input Shift Register..................................................................... 14

REVISION HISTORY

3/05—Rev. 0 to Rev. A

Changes to Timing Characteristics................................................ 4

Changes to Absolute Maximum Ratings ....................................... 5

Changes to Full Scale Error Section............................................... 7

Changes to Figure 20...................................................................... 10

Changes to Theory of Operation.................................................. 14

Changes to Power Down Modes................................................... 15

SYNC

Interrupt .......................................................................... 14

Power-On Reset .......................................................................... 15

Power-Down Modes .................................................................. 15

Microprocessor Interfacing....................................................... 16

Applications..................................................................................... 18

Choosing a Reference as Power Supply for the AD5601/AD5611/AD5621

Bipolar Operation Using the AD5601/AD5611/AD5621

Using the AD5601/AD5611/AD5621 with an Opto-Isolated Interface

Power-Supply Bypassing and Grounding ............................... 19

Outline Dimensions....................................................................... 20

Ordering Guide .......................................................................... 20

....................................................... 18

.............................................................. 19

1/05—Revision 0: Initial Version

Rev. A | Page 2 of 20

Page 3

AD5601/AD5611/AD5621

SPECIFICATIONS

VDD = 2.7 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications T

Table 2.

A Grade

1, 2

B Grade2

Parameter Min Typ2 Max Min Typ2 Max Unit Test Conditions/Comments

STATIC PERFORMANCE

AD5601

Resolution 8 Bits Relative Accuracy3 (INL) ±0.5 LSB Differential Nonlinearity

±0.5 LSB Guaranteed monotonic by design

(DNL)

AD5611

Resolution 10 Bits Relative Accuracy3 (INL) ±4 LSB Differential Nonlinearity

±0.5 LSB Guaranteed monotonic by design

(DNL)

AD5621

Resolution 12 Bits Relative Accuracy3 (INL) ±6 LSB Differential Nonlinearity

±0.5 LSB Guaranteed monotonic by design

(DNL) Zero-Code Error * * 0.5 10 mV All 0s loaded to DAC register Full-Scale Error * ±0.5 mV All 1s loaded to DAC register Offset Error * * ±0.063 ±10 mV Gain Error * * ±0.0004 ±0.037 %FSR Zero-Code Error Drift * 5. 0 µV/°C

Gain Temperature Coefficient * 2. 0

OUTPUT CHARACTERISTICS

Output Voltage Range * * Output Voltage Settling

0 V

* * 6 10 µs Code ¼ scale to ¾ scale

Time Slew Rate * 0. 5 V/µs Capacitive Load Stability * 470 pF RL = ∞ * 1000 pF RL = 2 kΩ Output Noise Spectral

* 120

Density Noise * 2 µV

Digital-to-Analog Glitch

* 5 nV-s 1 LSB change around major carry

Impulse Digital Feedthrough * 0.2 nV-s Short-Circuit Current * 15 mA VDD = 3 V/5 V DC Output Impedance * 0.5 Ω

LOGIC INPUTS

Input Current V

, Input High Voltage * 1.8 V VDD = 4.7 V to 5.5 V

INH

* ± 2 µA

* 1.4 V VDD = 2.7 V to 3.6 V V

, Input Low Voltage * 0.8 V VDD = 4.7 V to 5.5 V

INL

* 0.6 V VDD = 2.7 V to 3.6 V Pin Input Capacitance * 3 pF

MIN

ppm

to T

, unless other wise noted.

MAX

FSR/°C

nV/√Hz

DAC code = midscale,1 kHz

DAC code = midscale, 0.1 Hz to 10 kHz bandwidth

Rev. A | Page 3 of 20

Page 4

AD5601/AD5611/AD5621

A Grade

1, 2

B Grade2

Parameter Min Typ2 Max Min Typ2 Max Unit Test Conditions/Comments

POWER REQUIREMENTS

* * 2.7 5.5 V All digital inputs at 0 V or V

IDD (Normal Mode) DAC active and excluding load current

VDD = ±4.5 V to ±5.5 V * * 75 100 µA VIH = VDD and VIL = GND VDD = ±2.7 V to ±3.6 V * * 60 90 µA VIH = VDD and VIL = GND

IDD (All Power-Down Modes) VIH = VDD and VIL = GND

VDD = ±4.5 V to ±5.5 V * 0.5 µA VIH = VDD and VIL = GND VDD = ±2.7 V to ±3.6 V * 0.2 µA VIH = VDD and VIL = GND

POWER EFFICIENCY

OUT/IDD

Asterisk (*) = specifications same as B grade.

Temperature range for A/B grades is –40°C to +125°C, typical at +25°C.

Linearity calculated using a reduced code range: AD5621 from Code 64 to Code 4032; AD5611 from Code 16 to Code 1008; AD5601 from Code 4 to Code 252.

Guaranteed by design and characterization, not production tested.

Total current flowing into all pins.

* 96 % I

= 2 mA and VDD = ±5 V

LOAD

TIMING CHARACTERISTICS

VDD = 2.7 V to 5.5 V; all specifications T

Table 3.

Parameter Limit

All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.

Maximum SCLK frequency is 30 MHz.

33 ns min SCLK cycle time 5 ns min SCLK high time 5 ns min SCLK low time 10 ns min

5 ns min Data setup time

4.5 ns min Data hold time 0 ns min 20 ns min

13 ns min

MIN

to T

, unless otherwise noted. See Figure 2.

MAX

Unit Test Conditions/Comments

SYNC to SCLK falling edge setup time

SCLK falling edge to Minimum

SYNC high time

SYNC rising edge

SYNC rising edge to next SCLK falling edge ignored

SCLK

SYNC

SDIN

D0D1D2D14D15

D15 D14

04783-002

Figure 2. Timing Diagram

Rev. A | Page 4 of 20

Page 5

AD5601/AD5611/AD5621

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 4.

Parameter Rating

VDD to GND −0.3 V to +7.0 V Digital Input Voltage to GND –0.3 V to VDD + 0.3 V V

to GND –0.3 V to VDD + 0.3 V

OUT

Operating Temperature Range

Industrial (A/B Grades) –40°C to +125°C

Storage Temperature Range –65°C to +160°C Maximum Junction Temperature 150°C SC70 Package

θJA Thermal Impedance 433.34°C/W θJC Thermal Impedance 149.47°C/W

Lead Temperature, Soldering

Vapor Phase (60 sec) 215°C Infrared (15 sec) 220°C

ESD 2.0 kV

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Rev. A | Page 5 of 20

Page 6

AD5601/AD5611/AD5621

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

SYNC

SDIN

AD5601/ AD5611/

AD5621

TOP VIEW

(Not to Scale)

OUT

GNDSCLK

04783-003

Figure 3. 6-Lead SC70 Pin Configuration

Table 5. Pin Function Descriptions

Pin No. Mnemonic Function

2 SCLK

SYNC Level-Triggered Control Input (Active Low). This is the frame synchronization signal for the input data. When SYNC

goes low, it enables the input shift register, and data is transferred in on the falling edges of the clocks that follow. The DAC is updated following the 16 rising edge of

SYNC acts as an interrupt and the write sequence is ignored by the DAC.

clock cycle unless SYNC is taken high before this edge, in which case the

Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be transferred at rates up to 30 MHz.

3 SDIN

Serial Data Input. This device has a 16-bit shift register. Data is clocked into the register on the falling edge of the serial clock input.

4 V

Power Supply Input. The AD5601/AD5611/AD5621 can be operated from 2.7 V to 5.5 V. VDD should be decoupled

to GND. 5 GND Ground Reference Point for All Circuitry on the AD5601/AD5611/AD5621. 6 V

OUT

Analog Output Voltage from the DAC. The output amplifier has rail-to-rail operation.

Rev. A | Page 6 of 20

Page 7

AD5601/AD5611/AD5621

TERMINOLOGY

Relative Accuracy

For the DAC, relative accuracy or integral nonlinearity (INL) is a measure of the maximum deviation, in LSBs, from a straight line passing through the endpoints of the DAC transfer function. See Figure 4 to Figure 6 for plots of typical INL vs. code.

Differential Nonlinearity

Differential nonlinearity (DNL) is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ±1 LSB maximum ensures monotonicity. This DAC is guaranteed monotonic by design. See Figure 10 to Figure 12 for plots of typical DNL vs. code.

Zero-Code Error

Zero-code error is a measure of the output error when zero code (0x0000) is loaded to the DAC register. Ideally, the output should be 0 V. The zero-code error is always positive in the AD5601/AD5611/AD5621, because the output of the DAC cannot go below 0 V. Zero-code error is due to a combination of the offset errors in the DAC and output amplifier. Zero-code error is expressed in mV. See Figure 27 for a plot of zero-code error vs. temperature.

Full-Scale Error

Full-scale error is a measure of the output error when full-scale code (0xFFFF) is loaded to the DAC register. Ideally, the output should be V Figure 27 for a plot of full-scale error vs. temperature.

Gain Error

Gain error is a measure of the span error of the DAC. It is the deviation in slope of the DAC transfer characteristic from ideal, expressed as a percent of the full-scale range.

− 1 LSB. Full-scale error is expressed in mV. See

Tot a l U n ad ju s te d E rr o r

Total unadjusted error (TUE) is a measure of the output error taking all the various errors into account. See Figure 7 to Figure 9 for plots of typical TUE vs. code.

Zero-Code Error Drift

Zero-code error drift is a measure of the change in zero-code error with a change in temperature. It is expressed in µV/°C.

Gain Error Drift

Gain error drift is a measure of the change in gain error with changes in temperature. It is expressed in (ppm of full-scale range)/°C.

Digital-to-Analog Glitch Impulse

Digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the DAC register changes state. It is normally specified as the area of the glitch in nV-s and is measured when the digital input code is changed by 1 LSB at the major carry transition (0x2000 to 0x1FFF). See Figure 18.

Digital Feedthrough

Digital feedthrough is a measure of the impulse injected into the analog output of the DAC from the digital inputs of the DAC, but is measured when the DAC output is not updated. It is specified in nV-s and is measured with a full-scale code change on the data bus, that is, from all 0s to all 1s and vice versa.

Rev. A | Page 7 of 20

Page 8

AD5601/AD5611/AD5621

TYPICAL PERFORMANCE CHARACTERISTICS

2.5 VDD = 5V

= 25°C

2.0

1.5

1.0

0.5

–0.5

INL ERROR (LSB)

–1.0

–1.5

–2.0

–2.5

64 464 864 1264 1664 2064 2464 2864 3264 3664

Figure 4. Typical AD5621 INL

1.0

VDD = 5V

= 25°C

0.8

0.6

0.4

0.2

–0.2

INL ERROR (LSB)

–0.4

–0.6

-0.8

–1.0

16 116 216 316 416 516 616 716 816 916

Figure 5. Typical AD5611 INL

0.5 VDD = 5V

= 25°C

0.4

0.3

0.2

0.1

–0.1

INL ERROR (LSB)

–0.2

–0.3

–0.4

–0.5

4 54 104 154 204

Figure 6. Typical AD5601 INL

DAC CODE

04783-004

04783-005

04783-006

2.5 VDD = 5V

= 25°C

2.0

1.5

1.0

0.5

–0.5

TUE ERROR (LSB)

–1.0

–1.5

–2.0

–2.5

64 564 1064 1564 2064 2564 3064 3564

DAC CODE

Figure 7. AD5621 Total Unadjusted Error (TUE)

1.0 VDD = 5V

= 25°C

0.8

0.6

0.4

0.2

–0.2

TUE ERROR (LSB)

–0.4

–0.6

–0.8

–1.0

16 116 216 316 416 516 616 716 816 916

DAC CODE

Figure 8. AD5611 Total Unadjusted Error (TUE)

0.20 VDD = 5V

= 25°C

0.15

0.10

0.05

–0.05

TUE ERROR (LSB)

–0.10

–0.15

–0.20

4 54 104 154 204

DAC CODE

Figure 9. AD5601 Total Unadjusted Error (TUE)

04783-007

04783-008

04783-009

Rev. A | Page 8 of 20

Page 9

AD5601/AD5611/AD5621

= 3V

0.20

0.15

0.10

VDD = 5V

= 25°C

= DV

VIL = GND

= 25°C

VDD = 5V

= DV

VIL = GND

= 25°C

0.05

–0.05

DNL ERROR (LSB)

–0.10

–0.15

–0.20

64 564 1064 1564 2064 2564 3064 3564

DAC CODE

Figure 10. Typical AD5621 DNL

VDD = 5V

= 25°C

–

DNL ERROR (LSB)

–

16 116 216 316 416 516 616 716 816 916

DAC CODE

Figure 11. Typical AD5611 DNL

0.010 VDD = 5V

–0.002

DNL ERROR (LSB)

–0.004

–0.006

–0.008

–0.010

0.008

0.006

0.004

0.002

= 25°C

4 54 104 154 204

DAC CODE

Figure 12. Typical AD5601 DNL

04783-010

04783-011

04783-012

NUMBER OF DEVICES

0.05456

0.05527

0.05599

0.05671

0.05742

0.05814

0.05885

0.06648

0.06710

IDD (mA)

Figure 13. I

Histogram (3 V/5 V)

CH1 = SCLK

CH1 = 5V/DIV CH2 = 1V/DIV TIME BASE = 2µs/DIV

Figure 14. Full-Scale Settling Time

CH1 = SCLK

CH2 = V

OUT

CH1 = 5V/DIV CH2 = 1V/DIV TIME BASE = 2µs/DIV

Figure 15. Half-Scale Settling Time

0.06773

0.06835

CH2 = V

0.06897

0.06960

TA = 25°C V

OUT

TA = 25°C V

0.07022

0.07084

= 5V

0.07147

0.07209

0.07271

0.07334

04783-014

04783-015

04783-013

Rev. A | Page 9 of 20

Page 10

AD5601/AD5611/AD5621

CH1

CH2

CH1

CH2

VDD = 5V T

= 25°C

CH1 1V, CH2 20mV, TIME BASE = 20µs/DIV

Figure 16. Power-On Reset to 0 V

CH1

= 70mV

OUT

04783-016

CH1 5

VDD = 5V T MIDSCALE LOADED

V/DIV

= 25°C

04783-019

Figure 19. 1/f Noise, 0.1 Hz to 10 Hz Bandwidth

VDD = 5V T

= 25°C

CH1

CH2

OUT

VDD = 5V T

= 25°C

OUT

CH1 1V, CH2 5V, TIME BASE = 50µs/DIV

Figure 17. V

vs. V

OUT

2.458

2.456

2.454

2.452

2.450

2.448

2.446

AMPLITUDE (V)

2.444

2.442

2.440

2.438

2.436 0 100 200 300 400 500

SAMPLE NUMBER

TA = 25°C

= 5V

LOAD = 2kΩ AND 220pF CODE 0x2000 TO 0x1FFF 10ns/SAMPLE NUMBER

Figure 18. Digital-to-Analog Glitch Energy

04783-017

04783-018

CH1 5V, CH2 1V, TIME BASE = 2µs/DIV

Figure 20. Exiting Power-Down Mode

140

120

100

(µA)

0 5 10 15 20 25

FULL SCALE

Figure 21. I

1/4 SCALE

ZERO SCALE

FREQUENCY (MHz)

vs. SCLK vs. Code

3/4 SCALE

MIDSCALE

04783-020

04783-021

Rev. A | Page 10 of 20

Page 11

AD5601/AD5611/AD5621

700

VDD = 5V

= 25°C

UNLOADED OUTPUT

600

500

400

300

200

100

ZERO SCALE

OUTPUT NOISE SPECTRAL DENSITY (nV/ Hz)

100 1k 10k 100k

MIDSCALE

FULL SCALE

FREQUENCY (Hz)

Figure 22. Noise Spectral Density

VDD = 5V

VDD = 3V

(mA)

0 2000 4000 6000 8000 10000 12000 14000 16000

DIGITAL INPUT CODE

Figure 23. Supply Current vs. Digital Input Code

0.8 VDD = 5V

= 25°C

0.6

0.4

0.2

(V)

∆

0.0

–0.2

–0.4

–0.6

DAC LOADED WITH ZERO-SCALE CODE

DAC LOADED WITH FULL-SCALE CODE

–15 –10 –5 0 5 10 15

I(mA)

Figure 24. Sink and Source Capability

TA = 25°C

04783-022

04783-023

04783-024

2.50 V

= 5V

2.25

2.00

1.75

1.50

AD5621 MAX INL ERROR

1.25

1.00

0.75

0.50

AD5611 MAX INL ERROR

0.25

0 –0.25 –0.50

AD5611 MIN INL ERROR

–0.75

INL ERROR (LSB)

–1.00 –1.25 –1.50 –1.75 –2.00 –2.25 –2.50

–40 0 40 80 120 160 200

AD5601 MAX INL ERROR

AD5601 MIN INL ERROR

AD5621 MIN INL ERROR

TEMPERATURE (°C)

Figure 25. INL vs. Temperature (5 V)

0.08 VDD = 5V

0.07

DNL ERROR (LSB)

0.06

0.05

0.04

0.03

0.02

0.01

–0.01 –0.02 –0.03 –0.04 –0.05 –0.06 –0.07 –0.08

AD5621 MAX DNL ERROR

AD5611 MAX DNL ERROR

AD5611 MIN DNL ERROR

–40 10 60 110 160

TEMPERATURE (°C)

AD5601 MAX DNL ERROR AD5601 MIN DNL ERROR

AD5621 MIN DNL ERROR

Figure 26. DNL vs. Temperature (5 V)

0.00050

0.00045

0.00040

0.00035

0.00030

0.00025

0.00020

0.00015

0.00010

0.00005

–0.00005 –0.00010

ERROR (LSB)

–0.00015 –0.00020 –0.00025 –0.00030 –0.00035 –0.00040 –0.00045 –0.00050

VDD = 5V

–40 0 40 80 120 160 200

TEMPERATURE (°C)

AD5621 ZERO-CODE ERROR

AD5611 ZERO-CODE ERROR AD5601 ZERO-CODE ERROR

AD5601 FULL-SCALE ERROR

AD5611 FULL-SCALE ERROR

AD5621 FULL-SCALE ERROR

Figure 27. Zero-Code and Full-Scale Error vs. Temperature

04783-025

04783-026

04783-027

Rev. A | Page 11 of 20

Page 12

AD5601/AD5611/AD5621

2.5

2.0

1.5

1.0

0.5

–0.5

–1.0

–1.5

TOTAL UNADJUSTED ERROR (LSB)

–2.0

–2.5

–40 10 60 110 160

AD5611 MAX TUE ERROR

AD5611 MIN TUE ERROR

Figure 28. Total Unadjusted Error (TUE) vs. Temperature (5 V)

1.5

1.4

1.3

1.2

1.1

1.0

0.9

0.8

0.7

0.6

0.5

OFFSET ERROR (mV)

0.4

0.3

0.2

0.1 0

–40 –20 0 20 100 120 140

TEMPERATURE (°C)

Figure 29. Offset Error vs. Temperature (5 V)

–0.002

–0.004

–0.006

–0.008

–0.010

GAIN ERROR (%FSR)

–0.012

–0.014

–0.016

–40 –20 0 20 40 60 80 100 120 140

TEMPERATURE (°C)

Figure 30. Gain Error vs. Temperature (5 V)

AD5621 MAX TUE ERROR

AD5601 MAX TUE ERROR

AD5601 MIN TUE ERROR

AD5621 MIN TUE ERROR

TEMPERATURE (°C)

VDD = 5V

VDD = 3V

40 60 80

VDD = 5V

VDD = 3V

04783-028

04783-029

04783-030

0.10

0.09

0.08 = 5V

0.07

0.06

0.05

(mA)

0.04

0.03

0.02

0.01

–40 –20 0 20 40 60 80 100 120 140

VDD = 3V

TEMPERATURE (°C)

Figure 31. Supply Current vs. Temperature (5 V)

2.5 TA = 25°C

2.0

1.5

AD5621 MAX INL ERROR

1.0

0.5

AD5611 MAX INL ERROR

–0.5

AD5611 MIN INL ERROR

INL ERROR (LSB)

–1.0

–1.5

–2.0

–2.5

2.7 3.2 3.7 4.2 4.7 5.2 5.7 6.2 6.7

AD5621 MIN INL ERROR

SUPPLY VOLTAGE (V)

AD5601 MAX INL ERROR

AD5601 MIN INL ERROR

Figure 32. INL vs. Supply Voltage at 25°C

0.10

0.09

0.08

0.07

0.06

0.05

0.04

0.03

0.02

0.01 0

–0.01 –0.02 –0.03

DNL ERROR (LSB)

–0.04 –0.05 –0.06 –0.07 –0.08 –0.09 –0.10

2.7 3.2 3.7 4.2 4.7 5.2 5.7 6.2 6.7

AD5601 MAX DNL ERROR AD5601 MIN DNL ERROR

AD5611 MAX DNL ERROR

AD5611 MIN DNL ERROR

SUPPLY VOLTAGE (V)

AD5621 MAX DNL ERROR

AD5621 MIN DNL ERROR

Figure 33. DNL vs. Supply Voltage at 25°C

TA = 25°C

04783-031

04783-032

04783-033

Rev. A | Page 12 of 20

Page 13

AD5601/AD5611/AD5621

2.50 TA = 25°C

2.25

2.00

1.75

1.50

1.25

1.00

0.75

0.50

0.25

0 –0.25 –0.50 –0.75 –1.00 –1.25 –1.50 –1.75

TOTAL UNADJUSTED ERROR (LSB)

–2.00 –2.25 –2.50

2.7 3.2 3.7 4.2 4.7 5.2 5.7 6.2 6.7 SUPPLY VOLTAGE (V)

AD5621 MAX TUE

AD5611 MAX TUE AD5601 MAX TUE

AD5601 MIN TUE AD5611 MIN TUE

AD5621 MIN TUE

Figure 34. Total Unadjusted Error (TUE) vs. Supply Voltage at 25°C

0.00025

0.00020

0.00015

0.00010

0.00005

–0.00005

ERROR (LSB)

–0.00010

–0.00015

–0.00020

–0.00025

TA = 25°C

AD5611 ZERO-CODE ERROR

AD5611 FULL-SCALE ERROR

2.7 3.2 3.7 4.2 4.7 5.2 5.7 6.2 6.7

AD5621 ZERO-CODE ERROR

AD5601 ZERO-CODE ERROR

AD5601 FULL-SCALE ERROR

AD5621 FULL-SCALE ERROR

SUPPLY VOLTAGE (V)

Figure 35. Zero-Code and Full-Scale Error vs. Supply Voltage at 25°C

04783-034

04783-035

0.10 TA = 25°C

0.09

0.08

0.07

0.06

0.05

(

0.04

0.03

0.02

0.01

2.7 3.2 3.7 4.2 4.7 5.2 SUPPLY VOLTAGE (V)

Figure 36. Supply Current vs. Supply Voltage at 25°C

450

TA = 25°C

400

350

300

250

(µA)

200

150

100

SCLK/SDIN DECREASING V

SCLK/SDIN INCREASING V

= 5V

LOGIC

= 3V

(V)

Figure 37. SCLK/SDIN vs. Logic Voltage

SCLK/SDIN DECREASING V

= 5V

SCLK/SDIN INCREASING V

= 3V

645321

04783-036

04783-050

Rev. A | Page 13 of 20

Page 14

AD5601/AD5611/AD5621

THEORY OF OPERATION

D/A SECTION

The AD5601/AD5611/AD5621 DACs are fabricated on a CMOS process. The architecture consists of a string DAC followed by an output buffer amplifier. Figure 38 is a block diagram of the DAC architecture.

REF (+)

DAC REGISTER

Figure 38. DAC Architecture

RESISTOR

NETWORK

REF (–)

GND

OUTPUT AMPLIFIER

Because the input coding to the DAC is straight binary, the ideal output voltage is given by

OUT

⎜

⎟

⎝

⎠

⎛

⎞

×=

where D is the decimal equivalent of the binary code that is loaded to the DAC register and n is the bit resolution of the DAC.

RESISTOR STRING

The resistor string structure is shown in Figure 39. It is simply a string of resistors, each of value R. The code loaded to the DAC register determines at which node on the string the voltage is tapped off to be fed into the output amplifier. The voltage is tapped off by closing one of the switches connecting the string to the amplifier. Because it is a string of resistors, it is guaranteed monotonic.

TO OUTPUT AMPLIFIER

OUT

04783-037

OUTPUT AMPLIFIER

The output buffer amplifier is capable of generating rail-to-rail voltages on its output, giving an output range of 0 V to V

. It is capable of driving a load of 2 kΩ in parallel with 1000 pF to GND. The source and sink capabilities of the output amplifier are shown in Figure 24. The slew rate is 0.5 V/µs, with a halfscale settling time of 8 µs with the output loaded.

SERIAL INTERFACE

The AD5601/AD5611/AD5621 have a 3-wire serial interface

SYNC

, SCLK, and SDIN) t hat is compatible with SPI, QSPI,

( and MICROWIRE interface standards as well as most DSPs. See Figure 2 for a timing diagram of a typical write sequence.

The write sequence begins by bringing the

SYNC

line low. Data from the SDIN line is clocked into the 16-bit shift register on the falling edge of SCLK. The serial clock frequency can be as high as 30 MHz, making the AD5601/AD5611/AD5621 compatible with high speed DSPs. On the 16

falling clock edge, the last data bit is clocked in and the programmed function is executed (a change in DAC register contents and/or a change in the mode of operation). At this stage, the

SYNC

line might be kept low or brought high. In either case, it must be brought high for a minimum of 33 ns before the next write sequence so that a falling edge of

Because the than it does when V

SYNC

can initiate the next write sequence.

SYNC

buffer draws more current when VIN = 1.8 V

= 0.8 V,

SYNC

should be idled low between write sequences for even lower power operation of the part, as mentioned previously. However, it must be brought high again just before the next write sequence.

INPUT SHIFT REGISTER

The input shift register is 16 bits wide (see Figure 40). The first two bits are control bits, which control the mode of operation the power is in (normal mode or any one of three power-down modes). For a complete description of the various modes, see the Power-Down Modes section. The next 16 bits are the data bits, which are transferred to the DAC register on the 16 edge of SCLK.

falling

SYNC INTERRUPT

In a normal write sequence, the least 16 falling edges of SCLK and the DAC is updated on the

falling edge. However, if

falling edge, this acts as an interrupt to the write sequence.

The shift register is reset and the write sequence is seen as

04783-038

Figure 39. Resistor String Structure

Rev. A | Page 14 of 20

invalid. Neither an update of the DAC register contents nor a change in the operating mode occurs (see Figure 41).

SYNC

line is kept low for at

SYNC

is brought high before the

Page 15

AD5601/AD5611/AD5621

DB15 (MSB) DB0 (LSB)

PD1 PD0 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

DATA BITS

NORMAL OPERATION

0 1 1

1 kΩ TO GND

100 kΩ TO GND THREE-STATE

POWER-DOWN MODES

04783-039

Figure 40. Input Register Contents

SCLK

SYNC

SDIN

DB15 DB16 DB0DB0

INVALID WRITE SEQUENCE:

SYNC HIGH BEFORE 16

FALLING EDGE

Figure 41.

SYNC

Interrupt Facility

VALID WRITE SEQUENCE, OUTPUT UPDATES

ON THE 16TH FALLING EDGE

04783-040

POWER-ON RESET

The AD5601/AD5611/AD5621 contain a power-on reset circuit that controls the output voltage during power-up. The DAC register is filled with 0s and the output voltage is 0 V. It remains there until a valid write sequence is made to the DAC. This is useful in applications in which it is important to know the state of the DAC’s output while it is in the process of powering up.

POWER-DOWN MODES

The AD5601/AD5611/AD5621 have four separate modes of operation. These modes are software-programmable by setting two bits (DB15 and DB14) in the control register. Table 6 shows how the state of the bits corresponds to the mode of operation of the device.

Table 6. Modes of Operation for the AD5601/AD5611/AD5621

DB15 DB14 Operating Mode

0 0 Normal operation Power-down mode: 0 1 1 kΩ to GND 1 0 100 kΩ to GND 1 1 Three-state

When both bits are set to 0, the part works normally with its normal power consumption of 100 µA maximum at 5 V. However, for the three power-down modes, the supply current falls to typically 0.2 µA at 3 V.

Not only does the supply current fall, but the output stage is also internally switched from the output of the amplifier to a resistor network of known values. This has the advantage that the output impedance of the part is known while the part is in powerdown mode.

There are three different options: the output is connected internally to GND through a 1 kΩ resistor or a 100 kΩ resistor, or the output is left open-circuited (three-state). Figure 42 shows the output stage.

RESISTOR

STRING DAC

Figure 42. Output Stage during Power-Down

AMPLIFIER

POWER-DOWN

CIRCUITRY

RESISTOR NETWORK

OUT

04783-041

The bias generator, output amplifier, resistor string, and other associated linear circuitry are all shut down when power-down mode is activated. However, the contents of the DAC register are unaffected when in power-down. The time to exit powerdown is typically 13 µs for V

= 5 V and 16 µs for VDD = 3 V.

See Figure 20 for a plot.

Rev. A | Page 15 of 20

Page 16

AD5601/AD5611/AD5621

MICROPROCESSOR INTERFACING

AD5601/AD5611/AD5621 to ADSP-2101/ADSP-2103 Interface

Figure 43 shows a serial interface between the AD5601/ AD5611/AD5621 and the ADSP-2101/ADSP-2103. The ADSP-2101/ADSP-2103 should be set up to operate in SPORT transmit alternate framing mode. The ADSP-2101/ADSP-2103 SPORT is programmed through the SPORT control register and should be configured as follows: internal clock operation, active low framing, and 16-bit word length. Transmission is initiated by writing a word to the Tx register after the SPORT is enabled.

AD5601/AD5611/AD5621 to Blackfin® ADSP-BF53X Interface

Figure 45 shows a serial interface between the AD5601/ AD5611/AD5621 and the Blackfin ADSP-BF53x microprocessor. The ADSP-BF53x processor family incorporates two dualchannel synchronous serial ports, SPORT1 and SPORT0, for serial and multiprocessor communications. Using SPORT0 to connect to the AD5601/ AD5611/AD5621, the setup for the interface is as follows: DT0PRI drives the SDIN pin of the AD5601/AD5611/AD5621, while TSCLK0 drives the SCLK of the part. The

is driven from TFS0.

SYNC

ADSP-2101/ ADSP-2103*

TFS

SCLK

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 43. AD5601/AD5611/AD5621 to ADSP-2101/ADSP-2103 Interface

AD5601/AD5611/ AD5621*

SYNC SDIN SCLK

AD5601/AD5611/AD5621 to 68HC11/68L11 Interface

Figure 44 shows a serial interface between the AD5601/ AD5611/AD5621 and the 68HC11/68L11 microcontroller. SCK of the 68HC11/68L11 drives the SCLK of the AD5601/ AD5611/AD5621, while the MOSI output drives the serial data line of the DAC. The

SYNC

signal is derived from a port line (PC7). The setup conditions for correct operation of this interface are as follows: the 68HC11/68L11 should be configured so that its CPOL bit is 0 and its CPHA bit is 1. When data is being transmitted to the DAC, the

SYNC

line is taken low (PC7). When the 68HC11/68L11 are configured as above, data appearing on the MOSI output is valid on the falling edge of SCK. Serial data from the 68HC11/68L11 is transmitted in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. Data is transmitted MSB first. To load data to the AD5601/AD5611/AD5621, PC7 is left low after the first eight bits are transferred and a second serial write operation is performed to the DAC. PC7 is taken high at the end of this procedure.

04783-042

ADSP-BF53x*

DT0PRI

TSCLK0

TFS0

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 45. AD5601/AD5611/AD5621 to Blackfin ADSP-BF53x Interface

AD5601/AD5611/ AD5621*

SDIN SCLK SYNC

AD5601/AD5611/AD5621 to 80C51/80L51 Interface

Figure 46 shows a serial interface between the AD5601/ AD5611/AD5621 and the 80C51/80L51 microcontroller. The setup for the interface is as follows: TxD of the 80C51/80L51 drives SCLK of the AD5601/AD5611/AD5621, while RxD

SYNC

drives the serial data line of the part. The

signal is again derived from a bit programmable pin on the port. In this case, Port Line P3.3 is used. When data is to be transmitted to the AD5601/AD5611/AD5621, P3.3 is taken low. The 80C51/80L51 transmit data only in 8-bit bytes; therefore, only eight falling clock edges occur in the transmit cycle. To load data to the DAC, P3.3 is left low after the first eight bits are transmitted, and a second write cycle is initiated to transmit the second byte of data. P3.3 is taken high following the completion of this cycle. The 80C51/80L51 output the serial data LSB first. The AD5601/AD5611/AD5621 require data with the MSB as the first bit received. The 80C51/80L51 transmit routine should take this into account.

04783-044

68HC11/

68L11*

PC7 SCK

MOSI

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 44. AD5601/AD5611/AD5621 to 68HC11/68L11 Interface

AD5601/AD5611/ AD5621*

SYNC SCLK SDIN

04783-043

Rev. A | Page 16 of 20

*ADDITIONAL PINS OMITTED FOR CLARITY

80C51/80L51*

P3.3

TXD

RXD

Figure 46. AD5601/AD5611/AD5621 to 80C51/80L51 Interface

AD5601/AD5611/ AD5621*

SYNC SCLK SDIN

04783-045

Page 17

AD5601/AD5611/AD5621

AD5601/AD5611/AD5621 to MICROWIRE Interface

Figure 47 shows an interface between the AD5601/AD5611/ AD5621 and any MICROWIRE-compatible device. Serial data is shifted out on the falling edge of the serial clock and is clocked into the AD5601/AD5611/AD5621 on the rising edge of the SK.

MICROWIRE*

CS SK SO

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 47. AD5601/AD5611/AD5621 to MICROWIRE Interface

AD5601/AD5611/ AD5621*

SYNC SCLK SDIN

04783-046

Rev. A | Page 17 of 20

Page 18

AD5601/AD5611/AD5621

APPLICATIONS

CHOOSING A REFERENCE AS POWER SUPPLY FOR THE AD5601/AD5611/AD5621

The AD5601/AD5611/AD5621 come in a tiny SC70 package with less than 100 µA supply current. Because of this, the choice of reference depends on the application requirement. For spacesaving applications, the ADR02 is available in an SC70 package and has excellent drift at 9 ppm/°C (3 ppm/°C in the R-8 package). It also provides very good noise performance at

3.4 µV p-p in the 0.1 Hz to 10 Hz range.

Because the supply current required by the AD5601/AD5611/ AD5621 is extremely low, the parts are ideal for low supply applications. The ADR395 voltage reference is recommended in this case. It requires less than 100 µA of quiescent current and can, therefore, drive multiple DACs in one system, if required. It also provides very good noise performance at 8 µV p-p in the

0.1 Hz to 10 Hz range.

ADR395

BIPOLAR OPERATION USING THE AD5601/AD5611/AD5621

The AD5601/AD5611/AD5621 have been designed for singlesupply operation, but a bipolar output range is also possible using the circuit in Figure 49. The circuit in Figure 49 gives an output voltage range of ±5 V. Rail-to-rail operation at the amplifier output is achievable using an AD820 or OP295 as the output amplifier.

R2 = 10k

Ω

OUT

+5V

AD820/ OP295

–5V

+5V

04783-048

+5V

10µF

0.1µF

Figure 49. Bipolar Operation with the AD5601/AD5611/AD5621

R1 = 10kΩ

AD5601/AD5611/

AD5621

3-WIRE SERIAL

INTERFACE

3-WIRE

SERIAL

INTERFACE

Figure 48. ADR395 as Power Supply to the AD5601/AD5611/AD5621

SYNC

SCLK

SDIN

AD5601/AD5611/

AD5621

OUT

= 0V TO 5V

04783-047

Some recommended precision references for use as supplies to the AD5601/AD5611/AD5621 are listed in Table 7.

Table 7. Precision References for Use with the AD5601/AD5611/AD5621

Part No.

Initial Accuracy (mV max)

Temperature Drift (ppm/°C max)

0.1 Hz to 10 Hz Noise (µV p-p typ)

ADR435 ±2 3 (R-8) 8 ADR425 ±2 3 (R-8) 3.4 ADR02 ±3 3 (R-8) 10 ADR02 ±3 3 (SC70) 10 ADR395 ±5 9 (TSOT-23) 8

The output voltage for any input code can be calculated as follows:

⎡

⎛

×=

⎜

⎢

⎣

⎝

⎞ ⎟

⎠

R2R1D

⎞

⎟

⎠

⎛

⎜ ⎝

where D represents the input code in decimal (0 – 2

With V

= 5 V, R1 = R2 = 10 kΩ:

⎛

⎜

⎝

⎞

−

⎟

⎠

⎤

⎞

⎛

×−

⎟

⎜

⎥

⎠

⎝

⎦

This is an output voltage range of ±5 V with 0x0000 corresponding to a –5 V output, and 0x3FFF corresponding to a +5 V output.

Rev. A | Page 18 of 20

Page 19

AD5601/AD5611/AD5621

USING THE AD5601/AD5611/AD5621 WITH AN OPTO-ISOLATED INTERFACE

In process-control applications in industrial environments, it is often necessary to use an opto-isolated interface to protect and isolate the controlling circuitry from any hazardous commonmode voltages that might occur in the area where the DAC is functioning. Opto-isolators provide isolation in excess of 3 kV. Because the AD5601/AD5611/AD5621 use a 3-wire serial logic interface, they require only three opto-isolators to provide the required isolation (see Figure 50). The power supply to the parts also needs to be isolated. This is done by using a transformer. On the DAC side of the transformer, a 5 V regulator provides the 5 V supply required for the AD5601/AD5611/AD5621.

+5V

POWER

SCLK

SYNC

DATA

Figure 50. AD5601/AD5611/AD5621 with an Opto-Isolated Inter face

REGULATOR

10kΩ

SCLK

SYNC

SDIN

AD5601/ AD5611/

AD5621

GND

10µF

0.1µF

OUT

04783-049

POWER-SUPPLY BYPASSING AND GROUNDING

When accuracy is important in a circuit, it is helpful to carefully consider the power supply and ground return layout on the board. The printed circuit board containing the AD5601/ AD5611/AD5621 should have separate analog and digital sections, each having its own area of the board. If the AD5601/ AD5611/AD5621 are in a system where other devices require an AGND-to-DGND connection, the connection should be made at one point only. This ground point should be as close as possible to the AD5601/AD5611/AD5621.

The power supply to the AD5601/AD5611/AD5621 should be bypassed with 10 µF and 0.1 µF capacitors. The capacitors should be physically as close as possible to the device, with the

0.1 µF capacitor ideally right up against the device. The 10 µF capacitors are the tantalum bead type. It is important that the

0.1 µF capacitor have low effective series resistance (ESR) and effective series inductance (ESI), such as in common ceramic types of capacitors. This 0.1 µF capacitor provides a low impedance path to ground for high frequencies caused by transient currents due to internal logic switching.

The power supply line itself should have as large a trace as possible to provide a low impedance path and reduce glitch effects on the supply line. Clocks and other fast switching digital signals should be shielded from other parts of the board by digital ground. Avoid crossover of digital and analog signals, if possible. When traces cross on opposite sides of the board, ensure that they run at right angles to each other to reduce feedthrough effects through the board. The best board layout technique is the microstrip technique, where the component side of the board is dedicated to the ground plane only and the signal traces are placed on the solder side. However, this is not always possible with a 2-layer board.

Rev. A | Page 19 of 20

Page 20

AD5601/AD5611/AD5621

OUTLINE DIMENSIONS

2.20

2.00

1.80

1.35

1.25

1.15 PIN 1

1.30 BSC

1.00

0.90

0.70

0.10 MAX

Figure 51. 6-Lead Thin Shrink Small Outline Transistor Package [SC70]

ORDERING GUIDE

Temperature

Model

AD5601BKSZ-

500RL7 AD5601BKSZ-REEL71 –40°C to +125°C ±0.5 LSB INL

AD5611AKSZ-

500RL7 AD5611AKSZ-REEL71 –40°C to +125°C ±4.0 LSB INL

AD5621AKSZ-

500RL7 AD5621AKSZ-REEL71 –40°C to +125°C ±6.0 LSB INL

Z = Pb-free part.

Range Description Package Description

–40°C to +125°C ±0.5 LSB INL

–40°C to +125°C ±4.0 LSB INL

–40°C to +125°C ±6.0 LSB INL

0.30

0.15

0.10 COPLANARITY

COMPLIANT TO JEDEC STANDARDS MO-203-AB

2.40

4 5 6

2.10

3 2 1

1.80

0.65 BSC

1.10

0.80

SEATING PLANE

0.40

0.10

0.22

0.08

0.30

0.10

(KS-6)

Dimensions shown in millimeters

6-Lead Thin Shrink Small Outline Transistor Package (SC70)

Package Option Branding

KS-6 D3V

KS-6 D3U

KS-6 D3S

D04783–0–3/05(A)

Rev. A | Page 20 of 20

Datasheet AD5601 Datasheet (Analog Devices)

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

PRODUCT HIGHLIGHTS

SPECIFICATIONS

TIMING CHARACTERISTICS

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TERMINOLOGY

TYPICAL PERFORMANCE CHARACTERISTICS

THEORY OF OPERATION

D/A SECTION

OUTPUT AMPLIFIER

RESISTOR STRING

SERIAL INTERFACE

INPUT SHIFT REGISTER

POWER-DOWN MODES

POWER-ON RESET

MICROPROCESSOR INTERFACING

AD5601/AD5611/AD5621 to ADSP-2101/ADSP-2103 Interface

AD5601/AD5611/AD5621 to Blackfin® ADSP-BF53X Interface

AD5601/AD5611/AD5621 to 68HC11/68L11 Interface

AD5601/AD5611/AD5621 to 80C51/80L51 Interface

APPLICATIONS

BIPOLAR OPERATION USING THE AD5601/AD5611/AD5621

POWER-SUPPLY BYPASSING AND GROUNDING

OUTLINE DIMENSIONS

ORDERING GUIDE